Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the technical problem of poor transmission performance. The manufacturing method comprises the steps that a first conductive layer is formed on a substrate, the substrate is provided with a plurality of first bosses and first grooves surrounding the first bosses, and the first conductive layer is filled in the first grooves and covers the top surfaces of the first bosses; a plurality of cavities are formed in the first conductive layer, and at least part of the cavities are located between the two adjacent first bosses in the first direction; removing part of the first conductive layer to form a plurality of second grooves arranged at intervals, and at least part of the cavity forms a first recess communicated with the second grooves; an initial bit line layer is formed within the second recess, within the first recess, and on the first conductive layer. And opening at least part of the cavities to form the first recesses communicated with the second grooves, thereby reducing the number of the cavities and ensuring the transmission performance of the semiconductor structure. The initial bit line layer fills the second groove and the first recess so as to facilitate isolation of the first conductive layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor structure commonly used in electronic devices such as computers, which includes multiple storage units, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line (WL), one of the source and drain is electrically connected to the bit line (BL), and the other of the source and drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor.

[0003] However, as the size shrinks, the contact plugs connecting the transistors and the bit lines often have voids, and the transmission performance of the semiconductor structure is poor. Summary of the invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, so as to improve the transmission performance of the semiconductor structure.

[0005] According to some embodiments, a first aspect of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: forming a first conductive layer on a substrate, the substrate having a plurality of first bosses disposed at intervals and arranged in an array, and a first groove surrounding the first bosses, the first conductive layer filling the first groove and covering the top surface of the first bosses, the first conductive layer having a plurality of cavities, and at least part of the cavities being located between two first bosses adjacent to each other along a first direction;

[0006] Removing part of the first conductive layer to form a plurality of second grooves arranged at intervals, wherein the second grooves are located above the first bosses, and parts of the top surfaces of two adjacent first bosses along the first direction are exposed in the same second groove, and at least part of the voids form a first depression connected to the second groove;

[0007] An initial bit line layer is formed in the second groove, in the first recess, and on the first conductive layer. The initial bit line layer fills the second groove and the first recess and covers the top surface of the first conductive layer.

[0008] In some possible embodiments, forming an initial bit line layer in the second groove, in the first recess, and on the first conductive layer includes:

[0009] A metal layer is formed on the side wall and bottom wall of the second groove, the surface of the first recess, and the top surface of the first conductive layer, the metal layer in the second groove encloses a third groove, the metal layer in the first recess encloses a second recess, and the second recess is connected to the third groove;

[0010] forming a first barrier layer on a surface of the metal layer away from the substrate, and forming a second conductive layer on a surface of the first barrier layer away from the substrate, wherein the first barrier layer and the second conductive layer completely fill the third groove and the second recess;

[0011] A first protection layer is formed on a surface of the second conductive layer away from the substrate, and the metal layer, the first barrier layer, the second conductive layer, and the first protection layer form the initial bit line layer.

[0012] In some possible embodiments, after forming a metal layer on the sidewall and bottom wall of the second groove, the surface of the first recess, and the top surface of the first conductive layer, the method further includes:

[0013] The metal layer is subjected to rapid thermal treatment, and the metal layer reacts with the first conductive layer to form a metal semiconductor compound layer.

[0014] In some possible embodiments, the material of the first conductive layer includes silicon, the material of the metal layer includes titanium, and the metal semiconductor compound layer is a titanium silicide layer.

[0015] In some possible embodiments, the thickness of the metal layer is 1-5 nm, the metal layer is formed by a chemical vapor deposition process, and the reaction gas of the metal layer includes titanium chloride, hydrogen and ammonia;

[0016] In some possible embodiments, the first barrier layer is a titanium silicon nitride layer.

[0017] In some possible embodiments, the thickness of the first barrier layer is 3-5 nm, the first barrier layer is formed by an atomic layer deposition process, and the reaction gas of the first barrier layer includes dichlorosilane, hydrogen, and ammonia.

[0018] In some possible embodiments, in any three adjacent rows of the first bosses, the first bosses in one row are arranged along the second direction, the first bosses in an adjacent row are staggered, the first bosses in alternate rows are arranged opposite to each other along the first direction, and the second direction intersects with the first direction;

[0019] The removing part of the first conductive layer to form a plurality of second grooves arranged at intervals comprises:

[0020] The first conductive layer is etched with the first bosses as an etching stop layer to form the second grooves, and part of the top surfaces of two adjacent first bosses in alternate rows and the corresponding adjacent first bosses in adjacent rows are exposed in the same second groove.

[0021] In some possible embodiments, after removing part of the first conductive layer to form a plurality of second grooves spaced apart from each other, the method further includes:

[0022] A portion of the surface of the first recess away from the substrate is etched to enlarge the circumferential dimension of the first recess.

[0023] In some possible embodiments, the enlarged first depression is hemispherical or hemispherical.

[0024] In some possible embodiments, after forming an initial bit line layer in the second groove, in the first recess, and on the first conductive layer, the method further includes:

[0025] Etching the initial bit line layer to form a plurality of bit lines that are spaced apart and extend along the first direction, wherein the bit lines are located above a row of the first bosses arranged along the first direction, and grooves are formed between adjacent bit lines;

[0026] The first conductive layer is etched along the trench to expose a portion of the bottom wall of the first recess, the first conductive layer in the first recess forms a contact plug, and a portion of the contact plug has a top surface with the first recess.

[0027] In some possible embodiments, forming the first conductive layer on the substrate includes:

[0028] Providing a substrate having a plurality of active regions arranged in an array;

[0029] Depositing a second protective layer and a second barrier layer in sequence on the substrate, wherein the second protective layer covers the active area, and the substrate, the second protective layer and the second barrier layer form the base;

[0030] Etching the substrate to form the first boss and the first groove in the substrate, wherein the first boss covers the end of the active region, and the ends of two active regions adjacent to each other along the first direction share one first boss;

[0031] forming the first conductive layer on the first boss and in the first groove;

[0032] Alternatively, forming the first conductive layer on the substrate comprises:

[0033] Providing a substrate having a plurality of active regions arranged in an array;

[0034] Depositing a second protective layer, a second barrier layer and a first conductive layer on the substrate in sequence, wherein the second protective layer covers the active area, and the substrate, the second protective layer and the second barrier layer form the base;

[0035] Etching the first conductive layer to form a plurality of second bosses that are spaced apart and arranged in an array, and a fourth groove surrounding the second bosses;

[0036] Etching the substrate along the fourth groove to form the first boss and the first groove in the substrate, wherein the first boss covers the end of the active region, and the ends of two active regions adjacent to each other along the first direction share one first boss;

[0037] A second conductive layer is formed in the first groove and the fourth groove. The second conductive layer fills the first groove and the fourth groove. The second conductive layer and the second boss form the first conductive layer.

[0038] In some possible embodiments, the first groove penetrates the second protection layer and the second barrier layer and extends into the substrate.

[0039] The method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure has at least the following advantages:

[0040] In the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, the substrate has a plurality of first bosses and a first groove surrounding each first boss, a first conductive layer is formed in the first groove and on the first boss, a plurality of voids are formed in the first conductive layer, and at least part of the voids are located between two first bosses adjacent to each other along the first direction. Part of the first conductive layer is removed to form a plurality of second grooves arranged at intervals, the second grooves expose part of the top surface of two first bosses adjacent to each other along the first direction, and at least part of the voids, the exposed voids form a first depression located at the bottom wall of the second groove, and the initial bit line layer is filled in the second groove and the first depression. By opening at least part of the voids and connecting them with the second groove, the number of voids in the first conductive layer is reduced, especially the number of voids in the first conductive layer located between two first bosses adjacent to each other along the first direction is reduced. This part of the first conductive layer subsequently forms a contact plug, and there are fewer or even no voids in the contact plug, thereby improving the transmission performance of the contact plug and ensuring the transmission performance of the semiconductor structure. By filling the second groove and the first recess with the initial bit line layer, the initial bit line layer is in good contact with the first conductive layer, avoiding the existence of a gap, facilitating the isolation of the first conductive layer, and avoiding the mutual diffusion of ions in the initial bit line layer and the first conductive layer, so as to ensure the normal electrical properties of the semiconductor structure.

[0041] According to some embodiments, a second aspect of the present disclosure provides a semiconductor structure, including:

[0042] A substrate, the substrate having a plurality of first bosses disposed at intervals and arranged in an array, and a first groove surrounding the first bosses;

[0043] A contact plug, the contact plug being disposed in the first groove and connected between two adjacent first bosses along a first direction;

[0044] A first conductive line extending along the first direction and integrally formed with the contact plug, wherein a recessed structure is provided at corresponding positions of the first conductive line and the contact plug;

[0045] A second conductive line is disposed on the first conductive line and the contact plug and is filled in the recessed structure.

[0046] In some possible embodiments, the semiconductor structure further includes: a contact layer, wherein the contact layer is disposed between the first conductive line and the second conductive line, and between the contact plug and the second conductive line.

[0047] In some possible embodiments, the semiconductor structure further includes: a first barrier layer, wherein the first barrier layer is disposed between the contact layer and the second conductive line.

[0048] In some possible embodiments, the first conductive line includes polysilicon, the material of the second conductive line includes metal, the material of the contact layer includes titanium silicide, and the material of the first barrier layer includes titanium silicon nitride.

[0049] The semiconductor structure provided by the embodiments of the present disclosure has at least the following advantages:

[0050] The first wire and the contact plug in the semiconductor structure provided by the embodiment of the present disclosure are integrally formed, and a recessed structure is provided at the corresponding position, which can reduce the void 21 in the contact plug, improve the transmission performance of the contact plug, and ensure the transmission performance of the semiconductor structure. The second wire fills the recessed structure, increases the volume of the second wire, and further improves the transmission performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 is a schematic diagram of a semiconductor structure in the related art;

[0052] Figure 2 is a flow chart of a method for manufacturing a semiconductor structure in an embodiment of the present disclosure;

[0053] Figure 3 is a schematic structural diagram of a substrate in an embodiment of the present disclosure;

[0054] Figure 4 is a top view of a substrate in an embodiment of the present disclosure;

[0055] Figure 5 is a schematic diagram of a structure after a first conductive layer is formed in an embodiment of the present disclosure;

[0056] Figure 6 is a schematic diagram of a structure after a mask layer is formed in an embodiment of the present disclosure;

[0057] Figure 7 is a schematic diagram of a structure after a second groove is formed in an embodiment of the present disclosure;

[0058] Figure 8 is a schematic diagram of a structure after a metal layer is formed in one embodiment of the present disclosure;

[0059] Fig. 9 is a schematic diagram of a structure after forming a first barrier layer in an embodiment of the present disclosure;

[0060] Fig.10 is a schematic diagram of a structure after forming a second conductive layer in an embodiment of the present disclosure;

[0061] Fig.11 It is a schematic diagram of the structure after forming the first protective layer in one embodiment of the present disclosure;

[0062] Fig.12 It is a schematic diagram of the structure after the first recess is enlarged in one embodiment of the present disclosure;

[0063] Fig.13 is a schematic diagram of a structure after a metal semiconductor compound layer is formed in one embodiment of the present disclosure;

[0064] Fig.14 is another structural schematic diagram of a substrate in an embodiment of the present disclosure;

[0065] Fig.15 Schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0066] Description of reference numerals:

[0067] 10-base; 11-first boss;

[0068] 12-first groove; 13-substrate;

[0069] 14-active region; 15-second protective layer;

[0070] 16- second barrier layer; 20- first conductive layer;

[0071] 21-hollow; 22-second groove;

[0072] 23-first depression; 24-second depression;

[0073] 25-third groove; 30-initial bit line layer;

[0074] 31-metal layer; 32-metal semiconductor compound layer;

[0075] 33-first barrier layer; 34-second conductive layer;

[0076] 35-first protection layer; 40-bit line;

[0077] 50-Mask layer. DETAILED DESCRIPTION

[0078] The semiconductor structure in the related art has the problem of poor transmission performance. The inventor has found that Figure 1 The substrate 10 has a plurality of first bosses 11 arranged at intervals, and a first groove surrounding the first bosses 11. When forming the first conductive layer 20, as the height of the adjacent first bosses 11 or the film layer thereon increases, the number of voids 21 in the first conductive layer 20 increases. The first conductive layer 20 between two adjacent first bosses 11 along the first direction (the direction in which the bit line 40 extends) is used to form a contact plug for signal transmission between the bit line 40 and the substrate 10. The presence of voids 21 in the first conductive layer 20 in this region will reduce the transmission performance of the semiconductor structure.

[0079] In addition, the bit line 40 is usually a stacked structure, and the bit line 40 is in contact with the first conductive layer 20. There is often a problem that it is difficult to balance contact resistance and blocking isolation between the bit line 40 and the first conductive layer 20, which also affects the transmission performance of the semiconductor structure. Specifically, the film layer in contact with the first conductive layer 20 of the bit line 40 is a titanium layer or a titanium nitride layer, which can form a good ohmic contact with the first conductive layer 20, reducing the contact resistance between the bit line 40 and the first conductive layer 20, but the layer has poor ion blocking performance, and the ions between the bit line 40 and the first conductive layer 20 are easy to diffuse with each other, especially the doped ions in the first conductive layer 20 diffuse into the bit line 40. The film layer in contact with the first conductive layer 20 of the bit line 40 is a titanium silicon nitride layer, which can better block the diffusion of ions, but the contact resistance between this layer and the first conductive layer 20 is large.

[0080] To this end, the embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, by forming a second groove in the first conductive layer, opening the void in the first conductive layer between two first bosses adjacent to each other in the first direction, forming a first depression connected to the second groove, and filling the initial bit line layer in the first depression and the second groove. A contact plug is subsequently formed in the first conductive layer between two first bosses adjacent to each other in the first direction, and there are fewer or even no voids in the contact plug, thereby improving its transmission performance, thereby improving the transmission performance of the semiconductor structure. The initial bit line layer is filled in the first depression, and the initial bit line layer subsequently forms a bit line, and there is no gap between the bit line and the contact plug, which facilitates the isolation of the contact plug, avoids the mutual diffusion of ions between the bit line and the contact plug, ensures that the electrical properties of the bit line and the contact plug are normal, thereby ensuring the transmission performance of the semiconductor structure.

[0081] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0082] See also Figure 2 , the present disclosure provides a method for manufacturing a semiconductor structure, the manufacturing method comprising:

[0083] Step S100: A first conductive layer is formed on a substrate, wherein the substrate has a plurality of first bosses that are spaced apart and arranged in an array, and a first groove surrounding the first bosses, wherein the first conductive layer fills the first groove and covers the top surface of the first bosses, wherein the first conductive layer has a plurality of voids, and at least some of the voids are located between two adjacent first bosses along a first direction.

[0084] See also Figure 3 The substrate 10 has a plurality of first bosses 11 (such as Figure 3The substrate 10 may include a substrate 13, a second protective layer 15 disposed on the substrate 13, and a second barrier layer 16 disposed on the second protective layer 15. The substrate 13 may be made of silicon, germanium, silicon germanium, arsenic germanium, silicon on insulator (SOI) or germanium on insulator (GOI). The second protective layer 15 may be made of silicon oxide to reduce oxidation of the substrate 13. The second barrier layer 16 may be made of silicon nitride or silicon oxynitride, which has a relatively high hardness and is not easy to be pierced.

[0085] like Figure 3 As shown, the first groove 12 penetrates the second barrier layer 16 and the second protective layer 15, and extends to the inside of the substrate 13, that is, the bottom wall of the first groove 12 is located in the substrate 13 to increase the exposed area of ​​the substrate 13. Accordingly, the plurality of first bosses 11 each include a portion of the substrate 13, the second protective layer 15, and the second barrier layer 16 stacked in sequence. The first boss 11 may be a truncated cone, an elliptical cone, or the like.

[0086] For some examples, see Figure 4 In any three adjacent rows of first bosses 11, the first bosses 11 in one row are arranged along the second direction, the first bosses 11 in adjacent rows are staggered, and the first bosses 11 in alternate rows are arranged oppositely along the first direction. The second direction intersects the first direction, for example, is perpendicular to it, so as to increase the arrangement density of the first bosses 11. The first direction can be a vertical direction ( Figure 4 The second direction may be a horizontal direction ( Figure 4 X direction as shown).

[0087] like Figure 4 As shown, the row direction is the second direction, and the multiple first bosses 11 in each row are arranged in sequence along the second direction, and the first bosses 11 in two adjacent rows are staggered. That is, each first boss 11 in one of the two adjacent rows moves a certain distance along the second direction relative to each first boss 11 in the other row, and the moving distance is less than the spacing between two adjacent first bosses 11 along the second direction. The column direction is the first direction, and the first bosses 11 adjacent to each other row form a column, and the number of columns is twice the number of the first bosses 11 in each row.

[0088] See also Figure 3 and Figure 5, the first conductive layer 20 is filled in the first groove 12 and covers the top surface of the first boss 11, and the top surface of the first conductive layer 20 is higher than the top surface of the first boss 11. The material of the first conductive layer 20 can be polysilicon, and there are multiple cavities 21 in the first conductive layer 20, and there are at least some cavities 21 in the first conductive layer 20 between two first bosses 11 adjacent in the first direction. There can be one or more cavities 21 between two first bosses 11 adjacent in the first direction, and a part of the cavity 21 is higher than the first boss 11 in the direction away from the substrate 10.

[0089] Step S200: remove part of the first conductive layer to form a plurality of second grooves spaced apart from each other, wherein the second grooves are located above the first bosses, and parts of the top surfaces of two first bosses adjacent to each other along the first direction are exposed in the same second groove, and at least part of the cavity forms a first depression connected to the second groove.

[0090] See also Figure 6 and Figure 7 , a portion of the first conductive layer 20 located on the side of the first boss 11 away from the substrate 10 is removed to form a plurality of second grooves 22 arranged at intervals in the first conductive layer 20, that is, the second grooves 22 are located above the first boss 11, and the second grooves 22 are not connected and are independent of each other. The second grooves 22 are opposite to the first conductive layer 20 located between two first bosses 11 adjacent to each other along the first direction, and the adjacent portions of the top surfaces of the two first bosses 11 adjacent to each other along the first direction are exposed in the same second groove 22. Taking the first direction as the vertical direction as an example, the adjacent portions of the top surfaces of the two first bosses 11 adjacent to each other above and below form a portion of the bottom wall of the same second groove 22.

[0091] At least part of the cavity 21 is located between two first bosses 11 adjacent to each other in the first direction. When the first conductive layer 20 is removed to form the second groove 22, at least part of the cavity 21 is opened and exposed to form a first recess 23. The first recess 23 is connected to the corresponding second groove 22. Specifically, two first bosses 11 adjacent to each other in the first direction form a group of first bosses 11. The first recess 23 located between the first bosses 11 in the same group is connected to the second groove 22.

[0092] By forming the first conductive layer 20 on the substrate 10 and removing part of the first conductive layer 20, the voids 21 in the first conductive layer 20 are opened. On the one hand, the number of voids 21 in the first conductive layer 20 is reduced to ensure the transmission performance between the subsequently formed bit line and the first conductive layer 20. On the other hand, it is also convenient to isolate the first conductive layer 20 to avoid mutual diffusion of ions between the subsequently formed bit line and the first conductive layer 20, for example, preventing high-concentration doped ions in the first conductive layer 20 from diffusing into the bit line to ensure normal electrical properties of the semiconductor structure.

[0093] Step S300: forming an initial bit line layer in the second groove, in the first recess, and on the first conductive layer, wherein the initial bit line layer fills the second groove and the first recess and covers the top surface of the first conductive layer.

[0094] See also Figures 7 to 11 The initial bit line layer 30 fills the second groove 22 and the first depression 23 and covers the top surface of the first conductive layer 20. The top surface of the initial bit line layer 30 can be a plane. By filling the second groove 22 and the first depression 23 with the initial bit line layer 30, there can be no gap between the initial bit line layer 30 and the first conductive layer 20, so as to ensure that the initial bit line layer 30 and the first conductive layer 20 are in good contact, and there are no or few voids 21 in the transmission path from the initial bit line layer 30 to the substrate 13, so as to ensure the transmission performance of the semiconductor structure.

[0095] In a method for manufacturing a semiconductor structure in a certain embodiment, a substrate 10 has a plurality of first protrusions 11 and a first groove 12 surrounding each first protrusion 11, a first conductive layer 20 is formed in the first groove 12 and on the first protrusion 11, a plurality of cavities 21 are formed in the first conductive layer 20, and at least part of the cavities 21 are located between two first protrusions 11 adjacent to each other in a first direction. Part of the first conductive layer 20 is removed to form a plurality of second grooves 22 arranged at intervals, the second grooves 22 expose part of the top surface of two first protrusions 11 adjacent to each other in the first direction, and at least part of the cavities 21, the exposed cavities 21 form a first recess 23 located at the bottom wall of the second groove 22, and an initial bit line layer 30 is filled in the second groove 22 and the first recess 23. By opening at least part of the cavities 21 and connecting with the second groove 22, the number of cavities 21 in the first conductive layer 20 is reduced, especially the number of cavities 21 in the first conductive layer 20 located between two first protrusions 11 adjacent to each other in the first direction is reduced. This portion of the first conductive layer 20 is subsequently formed into a contact plug, and there are fewer or even no voids 21 in the contact plug, thereby improving the transmission performance of the contact plug and ensuring the transmission performance of the semiconductor structure. The initial bit line layer 30 is used to fill the second groove 22 and the first recess 23, so that the initial bit line layer 30 is in good contact with the first conductive layer 20, avoiding the existence of a gap, facilitating the isolation of the first conductive layer 20, and also avoiding the mutual diffusion of ions in the initial bit line layer 30 and the first conductive layer 20, so as to ensure the normal electrical properties of the semiconductor structure.

[0096] See also Figures 4 to 7 In any three adjacent rows of first bosses 11, the first bosses 11 in one row are arranged along the second direction, the first bosses 11 in adjacent rows are staggered, and the first bosses 11 in alternate rows are arranged opposite to each other along the first direction, a portion of the first conductive layer 20 is removed to form a plurality of second grooves 22 arranged at intervals (step S200), including:

[0097] The first conductive layer 20 is etched with the first bosses 11 as an etching stop layer to form second grooves 22 , and part of the top surfaces of two adjacent first bosses 11 in alternate rows and corresponding adjacent first bosses 11 in adjacent rows are exposed in the same second groove 22 .

[0098] In some possible implementations, a mask layer 50 is formed on the first conductive layer 20, and the mask layer 50 has a preset pattern. The preset pattern includes a plurality of openings arranged at intervals, and the openings are opposite to the area between two first bosses 11 adjacent to each other in alternate rows. The orthographic projections of the openings on the substrate 10 have a partial overlap with the orthographic projections of the corresponding two first bosses 11 adjacent to each other in alternate rows on the substrate 10, and the orthographic projections of the first bosses 11 adjacent to the adjacent rows of the two first bosses 11 on the substrate 10 also have a partial overlap.

[0099] The first conductive layer 20 is etched with the mask layer 50 as a mask and the first boss 11 as an etching stop layer to form a second groove 22. The first conductive layer 20 remaining on the first boss 11 forms a second boss, and the second boss is located within the projection range of the first boss 11. The first groove 12 is still filled with the first conductive layer 20. Two first bosses 11 adjacent to each other in alternate rows and part of the top surface of the first boss 11 adjacent to its adjacent row are exposed in the same second groove 22, so that the circumferential dimension of the second groove 22 is larger, so that the cavity 21 between the two first bosses 11 adjacent to each other in the first direction can be fully exposed. Exemplarily, part of the top surfaces of four first bosses 11 adjacent to each other in the upper, lower, left, and right directions are included in the same second groove 22.

[0100] The mask layer 50 is removed to expose the second boss, that is, to expose the first conductive layer 20 remaining on the first boss 11. The mask layer 50 may be a spin on hard mask (SOH) layer, which may be removed by an etching process.

[0101] See also Figure 7 and Fig.12 In some examples, after removing a portion of the first conductive layer 20 to form a plurality of second grooves 22 spaced apart from each other (step S200), the method further includes: etching a portion of the surface of the first recess 23 away from the substrate 10 to expand the circumferential size of the first recess 23.

[0102] By etching the inner circumferential surface of the first recess 23 close to the second groove 22, the exposed surface area of ​​the first recess 23 can be increased, thereby increasing the contact area between the first recess 23 and the initial bit line layer 30, reducing the contact resistance between the first conductive layer 20 and the initial bit line layer 30, thereby reducing the contact resistance of the contact plug and the bit line formed subsequently, and improving the transmission performance of the semiconductor structure.

[0103] Exemplarily, the enlarged first recess 23 is hemispherical or hemispherical, and the enlarged first recess 23 is in a shape of being larger at the top and smaller at the bottom, so as to facilitate the deposition of a film layer in the first recess 23. When etching a part of the surface of the first recess 23 and etching the first conductive layer 20 to form the second recess 22, both are etching the first conductive layer 20, and the same etching gas can be used. The etching gas can include difluoromethane or tetrafluoromethane, and the flow rate of difluoromethane can be 33sccm, and the flow rate of tetrafluoromethane can be 35sccm.

[0104] See also Figures 7 to 11 In some examples, forming an initial bit line layer 30 in the second groove 22, in the first recess 23, and on the first conductive layer 20 (step S300) includes:

[0105] Step S301: forming a metal layer on the side wall and bottom wall of the second groove, the surface of the first recess, and the top surface of the first conductive layer; the metal layer in the second groove encloses a third groove; the metal layer in the first recess encloses a second recess; and the second recess is connected to the third groove.

[0106] like Figure 7 and Figure 8 As shown, the metal layer 31 covers the sidewalls and bottom wall of the second groove 22, the surface of the first recess 23, and the top surface of the first conductive layer 20 outside the second groove 22. The metal layer 31 is relatively thin, and the metal layer 31 does not fill the first recess 23 and the second recess 22. The metal layer 31 in the first recess 23 encloses the second recess 24, and the metal layer 31 in the second recess 22 encloses the third recess 25, and the second recess 24 is connected to the third recess 25. In some examples, the thickness of the metal layer 31 is 1-5 nm, and the metal layer 31 is formed by a chemical vapor deposition (CVD) process, and the reaction gas of the metal layer 31 includes titanium chloride, hydrogen, and ammonia.

[0107] Step S302: forming a first barrier layer on a surface of the metal layer away from the substrate, and forming a second conductive layer on a surface of the first barrier layer away from the substrate, wherein the first barrier layer and the second conductive layer fill the third groove and the second recess.

[0108] See also Figures 8 to 10The first barrier layer 33 covers the surface of the metal layer 31 on one side away from the substrate 10, and the second conductive layer 34 covers the surface of the first barrier layer 33 on one side away from the substrate 10. The metal layer 31, the first barrier layer 33 and the second conductive layer 34 form a stacked structure. The first barrier layer 33 covers the sidewall and bottom wall of the third groove 25, the surface of the second recess 24, and the top surface of the first barrier layer 33 outside the third groove 25. The first barrier layer 33 in the third groove 25 encloses the fifth groove, and the first barrier layer 33 in the second recess 24 encloses the third recess.

[0109] The second conductive layer 34 fills up the fifth groove and the third depression, and covers the top surface of the first barrier layer 33 outside the fifth groove. The bottom surface of the second conductive layer 34 forms a protrusion that matches the third depression, and the protrusion fills up the third depression, so that the first depression 23 and the second groove 22 are filled with the second conductive layer 34, the first barrier layer 33 and the metal layer 31, so that the thickness of the second conductive layer 34 opposite to the first depression 23 and the second groove 22 is increased, so as to reduce the resistance of the second conductive layer 34.

[0110] In some examples, the first barrier layer 33 is a titanium silicon nitride layer, which has a good barrier effect to reduce or avoid mutual diffusion of ions in the first conductive layer 20 and the second conductive layer 34. The thickness of the first barrier layer 33 is 3-5 nm, and the first barrier layer 33 is formed by an atomic layer deposition (Atomic Layer Deposition, referred to as ALD) process, and the reaction gas of the first barrier layer 33 includes dichlorosilane, hydrogen and ammonia. The second conductive layer 34 can be a tungsten layer, and the second conductive layer 34 is deposited and chemically mechanically polished (CMP) is performed on the second conductive layer 34 to make the top surface of the second conductive layer 34 flat, so as to facilitate the formation of other film layers thereon.

[0111] Step S303: forming a first protection layer on a surface of the second conductive layer away from the substrate, and the metal layer, the first barrier layer, the second conductive layer and the first protection layer form an initial bit line layer.

[0112] See also Fig.11 The first protective layer 35 covers the surface of the second conductive layer 34 away from the substrate 10 to reduce oxidation of the second conductive layer 34. The material of the first protective layer 35 can be silicon nitride or silicon oxynitride. The initial bit line layer 30 is used to form a bit line, which includes a metal layer 31, a first protective layer 35, a second conductive layer 34 and a first barrier layer 33 stacked in sequence.

[0113] See also Fig. 9 and Fig.13In some examples, after forming the metal layer 31 on the sidewalls and bottom wall of the second groove 22, the surface of the first recess 23, and the top surface of the first conductive layer 20 (step S301), the method further includes: performing rapid heat treatment on the metal layer 31, and reacting the metal layer 31 with the first conductive layer 20 to form a metal semiconductor compound layer 32.

[0114] The semiconductor structure after the metal layer 31 is formed is annealed by rapid thermal processing (RTP) so that the metal layer 31 and the first conductive layer 20 in contact react with each other, and the metal layer 31 forms a metal semiconductor compound layer 32. An ohmic contact is formed between the metal semiconductor compound layer 32 and the first conductive layer 20 to reduce the contact resistance between the metal semiconductor compound layer 32 and the first conductive layer 20.

[0115] The material of the first conductive layer 20 includes silicon, the material of the metal layer 31 includes titanium, and the metal semiconductor compound layer 32 includes a titanium silicide layer, for example, a titanium silicide layer. In this configuration, the titanium of the metal layer 31 and the silicon of the first conductive layer 20 are easily reacted at high temperatures, and the contact resistance between the formed titanium silicide layer and the first conductive layer 20 is relatively small, about 300 Kohm.

[0116] In some examples, the step of performing rapid thermal treatment on the metal layer 31 may be performed between the step of forming the first barrier layer and the second conductive layer. For example, after forming the metal layer 31 and the first barrier layer 33, the film layer is annealed for rapid thermal treatment, and the metal layer 31 reacts with the first conductive layer 20 to form the metal semiconductor compound layer 32, and then the second conductive layer 34 is formed. During the rapid thermal treatment, the first barrier layer 33 can also provide protection for the first conductive layer 20 and the metal layer 31 to reduce the impact of the annealing atmosphere on the metal layer 31 and the first conductive layer 20.

[0117] For some examples, see Fig.11 After forming the initial bit line layer 30 in the second groove 22, in the first recess 23, and on the first conductive layer 20 (step S300), the method further includes:

[0118] Step S400: etching the initial bit line layer to form a plurality of bit lines that are spaced apart and extend along a first direction, wherein the bit lines are located above a row of first bosses arranged along the first direction, and grooves are formed between adjacent bit lines.

[0119] The initial bit line layer 30 is etched to form a groove penetrating the initial bit line layer 30, the groove exposes the first conductive layer 20, and the remaining initial bit line layer 30 is isolated to form a plurality of bit lines, and the plurality of bit lines all extend along the first direction. Each bit line is located directly above a row of first bosses 11 arranged along the first direction, and in two adjacent first bosses 11 along the first direction, a portion of the top surface of each first boss 11 is exposed in the grooves on both sides of the corresponding bit line.

[0120] Step S500: etching the first conductive layer along the trench to expose a portion of the bottom wall of the first recess, forming a contact plug in the first conductive layer in the first recess, and a portion of the contact plug has a first recess on its top surface.

[0121] The first conductive layer 20 exposed in the groove is etched until the substrate 10 is etched. The remaining portion of the first conductive layer 20 on the first boss 11, and the orthographic projection of the portion of the first conductive layer 20 on the first boss 11 is located within the range of the top surface of the first boss 11, that is, along the first direction, the length of the first conductive layer 20 of the first boss 11 is less than the length of the first boss 11. The first conductive layer 20 located in the first groove 12 forms a contact plug, that is, the first conductive layer 20 between two adjacent first bosses 11 along the first direction forms a contact plug, the two end surfaces of the contact plug are respectively connected to the side walls of the two first bosses 11, the top surface of the contact plug is connected to the bottom surface of the bit line, and the bottom surface of the contact plug is connected to the substrate 10.

[0122] The top surface of some contact plugs has a first recess 23, that is, the bottom surface of some bit lines matches the top surface of the contact plugs. On the one hand, the contact area between the contact plugs and the bit lines is increased, the contact resistance between the contact plugs and the bit lines is reduced, and the transmission performance between the contact plugs and the bit lines is ensured; on the other hand, the voids 21 inside the contact plugs are reduced, which facilitates the isolation of the contact plugs and avoids the mutual diffusion of ions in the contact plugs and the bit lines.

[0123] In some possible examples, forming a first conductive layer 20 on a substrate 10 (step S100) includes:

[0124] A substrate 13 is provided, and the substrate 13 has a plurality of active regions 14 arranged in an array.

[0125] A second protective layer 15 and a second barrier layer 16 are sequentially deposited on the substrate 13 , the second protective layer 15 covers the active region 14 , and the substrate 13 , the second protective layer 15 and the second barrier layer 16 form a base 10 .

[0126] The substrate 10 is etched to form a first boss 11 and a first groove 12 in the substrate 10 . The first boss 11 covers the end of the active region 14 , and the ends of two active regions 14 adjacent to each other along the first direction share one first boss 11 .

[0127] A first conductive layer 20 is formed on the first protrusion 11 and in the first groove 12 .

[0128] The multiple active regions 14 in the substrate 13 may be isolated from each other by a shallow trench isolation structure (STI for short). The shallow trench isolation structure may be formed simultaneously with the second protective layer 15. Fig.14 After forming a shallow trench in the substrate 13, an insulating material, such as silicon oxide, is deposited in the shallow trench and on the top surface of the active area 14. The insulating material in the shallow trench forms a shallow trench isolation structure, and the insulating material on the active area 14 and the shallow trench isolation structure forms a second protective layer 15. The second barrier layer 16 covers the second protective layer 15, and its material can be silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0129] The substrate 10 is etched to form a first boss 11 and a first groove 12. Both ends of the active area 14 are covered with the first boss 11, and the ends of two active areas 14 adjacent to each other along the first direction are covered with the same first boss 11. Along the first direction, the first bosses 11 and active areas 14 in the same column are alternately arranged in sequence and have a partial overlapping area to correspond to a bit line. A first conductive layer 20 is deposited in the first groove 12 and on the first boss 11, and the first conductive layer 20 fills the first groove 12 and covers the top surface of the first boss 11, that is, the first conductive layer 20 is formed in one step.

[0130] In some other possible examples, forming the first conductive layer 20 on the substrate 10 (step S100) includes:

[0131] A substrate 13 is provided, and the substrate 13 has a plurality of active regions 14 arranged in an array.

[0132] A second protective layer 15 , a second barrier layer 16 and a first conductive layer are sequentially deposited on the substrate 13 . The second protective layer 15 covers the active region 14 . The substrate 13 , the second protective layer 15 and the second barrier layer 16 form a base 10 .

[0133] The first conductive layer is etched to form a plurality of second bosses that are spaced apart and arranged in an array, and a fourth groove surrounding the second bosses.

[0134] The substrate 10 is etched along the fourth groove to form a first boss 11 and a first groove 12 in the substrate 10 . The first boss 11 covers the end of the active area 14 , and the ends of two active areas 14 adjacent to each other along the first direction share one first boss 11 .

[0135] A second conductive layer is formed in the first groove 12 and the fourth groove. The second conductive layer fills the first groove 12 and the fourth groove. The second conductive layer and the second boss form a first conductive layer 20 .

[0136] The formation of the active region 14, the second protective layer 15, and the second barrier layer 16 can refer to the previous example, and will not be described in detail here. After the second barrier layer 16 is formed, a first conductive layer is formed on the second barrier layer 16. The first conductive layer and the substrate 10 thereunder are etched to form a second boss and a fourth groove in the first conductive layer, and a first boss 11 and a first groove 12 are formed in the substrate 10, wherein the first boss 11 corresponds to the second boss, and the first groove 12 corresponds to and is connected to the fourth groove.

[0137] The second conductive layer is deposited in the first groove 12 and the fourth groove, and the second conductive layer fills the first groove 12 and the fourth groove. The second conductive layer and the second boss form a first conductive layer 20. The second conductive layer is made of the same material as the first conductive layer, so that the second conductive layer and the second boss are integrated to reduce interlayer separation.

[0138] In the above example, the first groove 12 penetrates the second protection layer 15 and the second barrier layer 16 and extends into the substrate 13, that is, the bottom wall of the first groove 12 is located in the substrate 13, so as to increase the exposed area of ​​the active region 14, thereby increasing the contact area between the active region 14 and the first conductive layer 20. For example, the second barrier layer 16, the second protection layer 15 and the substrate 13 are etched to form the first groove 12.

[0139] The present disclosure also provides a semiconductor structure. Fig.15 The semiconductor structure includes a substrate 10, a contact plug, a first conductive line and a second conductive line. The substrate 10 has a plurality of first bosses 11 arranged at intervals and in an array, and a first groove 12 surrounding the first bosses 11.

[0140] Exemplarily, the base 10 includes a substrate 13, a second protective layer 15 disposed on the substrate 13, and a second barrier layer 16 disposed on the second protective layer 15. The material of the substrate 13 may be silicon, germanium, silicon germanium, arsenic germanium, silicon on insulator, or germanium on insulator. The material of the second protective layer 15 may be silicon oxide to reduce oxidation of the substrate 13. The material of the second barrier layer 16 may be silicon nitride or silicon oxynitride, which has a relatively high hardness and is not easy to be etched through.

[0141] Among the plurality of first bosses 11, in any three adjacent rows of first bosses 11, the first bosses 11 in one row are arranged along the second direction, the first bosses 11 in adjacent rows are staggered, and the first bosses 11 in alternate rows are arranged relatively along the first direction. The second direction intersects with the first direction, for example, is perpendicular, so as to increase the arrangement density of the first bosses 11. The first direction may be a vertical direction, and the second direction may be a horizontal direction, that is, the first direction is a column direction, and the second direction is a row direction.

[0142] There are multiple contact plugs, all of which are arranged in the first groove 12, and the multiple contact plugs are arranged at intervals. A contact plug is connected between two adjacent first bosses 11 along the first direction, so that the contact plugs and the first bosses 11 are alternately arranged in sequence along the first direction. The top surface of the contact plug can be flush with the top surface of the first boss 11, so that the height of the contact plug is small, reducing the cavity 21 in the contact plug.

[0143] The first wire extends along the first direction and is integrally formed with the contact plug. The first wire and the contact plug are made of the same material, for example, polysilicon. The first wire and the contact plug are alternately arranged and aligned in sequence along the first direction, and the top surface of the first wire is higher than the top surface of the contact plug.

[0144] A recessed structure is provided at the position corresponding to the first conductive line and the contact plug. In some examples, the recessed structure includes a first recess 23 provided on the top surface of a portion of the contact plug, and a gap in the first conductive line. The first recess 23 is formed by opening the cavity 21 in the contact plug, and the first recess 23 is a portion of the surface of the cavity 21. The gap runs through the first conductive line, divides the first conductive line into multiple sections along the first direction, and exposes the first recess 23, that is, the first conductive line is segmented and continuous along the first direction, so that the gap can fully expose the first recess 23.

[0145] Exemplarily, each section of the first conductive line is disposed on a corresponding first boss 11, and along the first direction, the gap between two adjacent sections of the first conductive line exposes the contact plug, and exposes the end portions of two adjacent first bosses 11 along the first direction that are close to each other. That is, along the first direction, both ends of each section of the first conductive line are located in the corresponding first boss 11. The first conductive line and the contact plug are formed by depositing the first conductive layer 20, etching the first conductive layer 20 to form a recessed structure, and etching and separating the remaining first conductive layer 20.

[0146] The second conductive line is disposed on the first conductive line and the contact plug and filled in the recessed structure to increase the volume of the second conductive line. The second conductive line is formed by depositing a second conductive layer 34 and separately etching the second conductive layer 34 .

[0147] In order to reduce the contact resistance with the first wire, the semiconductor structure further includes a contact layer disposed between the first wire and the second wire, and between the contact plug and the second wire. The contact layer and the contact plug have the same element so that an ohmic contact is formed between the contact layer and the contact plug, thereby reducing the contact resistance between the contact layer and the contact plug. For example, the material of the contact plug is polysilicon, and the material of the contact layer is titanium silicide.

[0148] In order to prevent the second conductive line from diffusing into the film layer below it, in some examples, the semiconductor structure further includes a first barrier layer disposed between the contact layer and the second conductive line. The first barrier layer 33 is used to reduce or prevent the mutual diffusion of ions between the second conductive line and the contact plug to ensure that the electrical properties of the contact plug and the second conductive line are normal.

[0149] The first barrier layer 33 and the contact layer have the same elements, for example, the material of the contact layer includes titanium silicide, and the material of the first barrier layer 33 includes titanium silicon nitride. With such a configuration, on the one hand, the first barrier layer 33 can play a better barrier role, and on the other hand, the contact resistance between the first barrier layer 33 and the contact layer is smaller than the contact resistance between the first barrier layer 33 and the first wire, thereby improving the transmission performance of the semiconductor structure.

[0150] It can be understood that the contact layer conformally covers the surface of the recessed structure, the first barrier layer 33 conformally covers the surface of the contact layer, the second wire conformally covers the surface of the first barrier layer 33, and the top surface of the second wire is a plane, that is, the stacked contact layer, the first barrier layer 33 and the second wire fill the recessed structure. The material of the second wire may include metal, such as tungsten.

[0151] In summary, the first wire and the contact plug in the semiconductor structure in the embodiment of the present disclosure are integrally formed, and a recessed structure is provided at the corresponding position, which can reduce the void 21 in the contact plug, improve the transmission performance of the contact plug, and ensure the transmission performance of the semiconductor structure. The second wire fills the recessed structure, which increases the volume of the second wire, thereby improving the transmission performance of the semiconductor structure.

[0152] In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referenced to each other. The description of reference terms such as "one implementation", "some implementations", "illustrative implementations", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the implementation or example are included in at least one implementation or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same implementation or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more implementations or examples in a suitable manner.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: A first conductive layer is formed on a substrate, wherein the substrate has a plurality of first bosses that are spaced apart and arranged in an array, and a first groove surrounding the first bosses, the first conductive layer fills the first groove and covers the top surface of the first bosses, the first conductive layer has a plurality of cavities, and at least part of the cavities are located between two first bosses that are adjacent to each other along a first direction; Removing part of the first conductive layer to form a plurality of second grooves arranged at intervals, wherein the second grooves are located above the first bosses, and parts of the top surfaces of two adjacent first bosses along the first direction are exposed in the same second groove, and at least part of the voids form a first depression connected to the second groove; An initial bit line layer is formed in the second groove, in the first recess, and on the first conductive layer. The initial bit line layer fills the second groove and the first recess and covers the top surface of the first conductive layer.

2. The method according to claim 1, characterized in that: Forming an initial bit line layer in the second groove, in the first recess, and on the first conductive layer, comprising: A metal layer is formed on the side wall and bottom wall of the second groove, the surface of the first recess, and the top surface of the first conductive layer, the metal layer in the second groove encloses a third groove, the metal layer in the first recess encloses a second recess, and the second recess is connected to the third groove; forming a first barrier layer on a surface of the metal layer away from the substrate, and forming a second conductive layer on a surface of the first barrier layer away from the substrate, wherein the first barrier layer and the second conductive layer completely fill the third groove and the second recess; A first protection layer is formed on a surface of the second conductive layer away from the substrate, and the metal layer, the first barrier layer, the second conductive layer, and the first protection layer form the initial bit line layer.

3. The method according to claim 2, characterized in that: After forming a metal layer on the sidewall and bottom wall of the second groove, the surface of the first recess, and the top surface of the first conductive layer, the method further includes: The metal layer is subjected to rapid thermal treatment, and the metal layer reacts with the first conductive layer to form a metal semiconductor compound layer.

4. The method according to claim 3, characterized in that: The material of the first conductive layer includes silicon, the material of the metal layer includes titanium, and the metal semiconductor compound layer is a titanium silicide layer.

5. The method according to claim 4, characterized in that: The thickness of the metal layer is 1-5 nm. The metal layer is formed by a chemical vapor deposition process. The reaction gas of the metal layer includes titanium chloride, hydrogen and ammonia.

6. The method according to claim 3, characterized in that: The first barrier layer is a titanium silicon nitride layer.

7. The manufacturing method according to claim 6, characterized in that: The thickness of the first barrier layer is 3-5 nm. The first barrier layer is formed by an atomic layer deposition process. The reaction gas of the first barrier layer includes dichlorosilane, hydrogen and ammonia.

8. The production method according to any one of claims 1 to 7, characterized in that: In any three adjacent rows of the first bosses, the first bosses in one row are arranged along the second direction, the first bosses in adjacent rows are staggered, the first bosses in alternate rows are arranged opposite to each other along the first direction, and the second direction intersects with the first direction; The removing part of the first conductive layer to form a plurality of second grooves arranged at intervals comprises: The first conductive layer is etched with the first bosses as an etching stop layer to form the second grooves, and part of the top surfaces of two adjacent first bosses in alternate rows and the corresponding adjacent first bosses in adjacent rows are exposed in the same second groove.

9. The production method according to any one of claims 1 to 7, characterized in that: After removing part of the first conductive layer to form a plurality of second grooves spaced apart from each other, the method further includes: A portion of the surface of the first recess away from the substrate is etched to enlarge the circumferential dimension of the first recess.

10. The manufacturing method according to claim 9, characterized in that: The enlarged first depression is hemispherical or hemispherical.

11. The production method according to any one of claims 1 to 7, characterized in that: After forming an initial bit line layer in the second groove, in the first recess, and on the first conductive layer, the method further includes: Etching the initial bit line layer to form a plurality of bit lines that are spaced apart and extend along the first direction, wherein the bit lines are located above a row of the first bosses arranged along the first direction, and grooves are formed between adjacent bit lines; The first conductive layer is etched along the trench to expose a portion of the bottom wall of the first recess, the first conductive layer in the first recess forms a contact plug, and a portion of the contact plug has a top surface with the first recess.

12. The production method according to any one of claims 1 to 7, characterized in that: The first conductive layer is formed on the substrate, comprising: Providing a substrate having a plurality of active regions arranged in an array; Depositing a second protective layer and a second barrier layer in sequence on the substrate, wherein the second protective layer covers the active area, and the substrate, the second protective layer and the second barrier layer form the base; Etching the substrate to form the first boss and the first groove in the substrate, wherein the first boss covers the end of the active region, and the ends of two active regions adjacent to each other along the first direction share one first boss; forming the first conductive layer on the first boss and in the first groove; Alternatively, forming the first conductive layer on the substrate comprises: Providing a substrate having a plurality of active regions arranged in an array; Depositing a second protective layer, a second barrier layer and a first conductive layer on the substrate in sequence, wherein the second protective layer covers the active area, and the substrate, the second protective layer and the second barrier layer form the base; Etching the first conductive layer to form a plurality of second bosses that are spaced apart and arranged in an array, and a fourth groove surrounding the second bosses; Etching the substrate along the fourth groove to form the first boss and the first groove in the substrate, wherein the first boss covers the end of the active region, and the ends of two active regions adjacent to each other along the first direction share one first boss; A second conductive layer is formed in the first groove and the fourth groove. The second conductive layer fills the first groove and the fourth groove. The second conductive layer and the second boss form the first conductive layer.

13. The manufacturing method according to claim 12, characterized in that: The first groove penetrates the second protection layer and the second barrier layer and extends into the substrate.

14. A semiconductor structure, characterized in that: The semiconductor structure comprises: A substrate, the substrate having a plurality of first bosses disposed at intervals and arranged in an array, and a first groove surrounding the first bosses; A contact plug, the contact plug being disposed in the first groove and connected between two adjacent first bosses along a first direction; A first conductive line extending along the first direction and integrally formed with the contact plug, wherein a recessed structure is provided at corresponding positions of the first conductive line and the contact plug; A second conductive line is disposed on the first conductive line and the contact plug and is filled in the recessed structure.

15. The semiconductor structure according to claim 14, characterized in that: The semiconductor structure further includes a contact layer disposed between the first conductive line and the second conductive line, and between the contact plug and the second conductive line.

16. The semiconductor structure according to claim 15, characterized in that The semiconductor structure further includes a first barrier layer disposed between the contact layer and the second conductive line.

17. The semiconductor structure according to any one of claims 14 to 16, characterized in that: The first conductive line includes polysilicon, the second conductive line includes metal, the contact layer includes titanium silicide, and the first barrier layer includes titanium silicon nitride.

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