Semiconductor structure

Abstract

The embodiment of the invention relates to a semiconductor structure. Comprising a substrate in which an active region extending along a first direction is formed; a fuse gate located on a top surface of an end portion of the active region and extending in a second direction intersecting with the first direction; wherein the end part of the active region is provided with a plurality of first lug bosses, and the top surfaces of the first lug bosses at the same end part of the active region are in contact with the bottom surface of the same fuse grid. The contact area of edge contact between the fuse gate and the end part of the active region is increased, the success rate of edge breakdown of the fuse gate when an anti-fuse structure unit in the semiconductor structure is started is improved, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure. Background Art

[0002] A typical memory chip adopts a redundant design to obtain a chip with storage capacity that meets the demand. The redundant design is realized by an antifuse structure unit. When the antifuse structure unit is activated, it is necessary to break down the gate oxide layer in the fuse gate included in the antifuse structure unit to achieve conduction between the fuse gate and the bottom silicon substrate. Whether the gate oxide layer in the fuse gate can be successfully broken down plays an important role in the function of the antifuse structure unit. When the antifuse structure unit is activated, there is a certain proportion of un-blow issues, which affects the performance of the antifuse structure unit. How to reduce the occurrence of un-blow issues has become an urgent problem to be solved. Summary of the invention

[0003] The disclosed embodiments provide a semiconductor structure that can optimize the unblown problem that occurs when an anti-fuse structure unit is activated, thereby achieving the purpose of improving the performance of the anti-fuse structure unit.

[0004] The present disclosure provides a semiconductor structure, comprising:

[0005] A substrate having an active region extending along a first direction;

[0006] a fuse gate, located on a top surface of an end portion of the active region and extending along a second direction intersecting the first direction;

[0007] The end of the active region has a plurality of first protrusions, and the top surface of each first protrusion at the same end of the active region contacts the bottom surface of the same fuse gate.

[0008] In one embodiment, the fuse gate comprises:

[0009] A first extending portion extending along a second direction;

[0010] A plurality of second protrusions, contacting the first extension portion and extending along a third direction intersecting the second direction, wherein a bottom surface of each second protrusion contacts a top surface of the active region;

[0011] A first distance between a first side surface of the second protrusion facing away from the first extension portion and the central axis of the active region is smaller than a second distance between a second side surface of the first protrusion close to the central axis and the central axis.

[0012] In one embodiment, an edge of an orthographic projection of the second protrusion on the active region coincides with an edge of the active region.

[0013] In one embodiment, the shape of the second protrusion is the same as the shape of the first protrusion.

[0014] In one embodiment, any active region is in contact with at least two fuse gates that are spaced apart from each other.

[0015] In one embodiment, the width of the fuse gate remains unchanged, and the direction of the width is perpendicular to the second direction.

[0016] In one embodiment, the active region includes a doped region, and a bottom surface of the fuse gate contacts a top surface of the doped region.

[0017] In one embodiment, the active region includes an end portion and a middle portion, and the semiconductor structure further includes:

[0018] The access gate is located on the top surface of the middle portion and extends along the second direction.

[0019] In one embodiment, the fuse gate comprises:

[0020] A fuse gate dielectric layer in contact with a top surface of an end portion of the active region;

[0021] The fuse gate structure layer is located on the top surface of the fuse gate dielectric layer, and the orthographic projection of the fuse gate structure layer on the fuse gate dielectric layer coincides with the fuse gate dielectric layer.

[0022] In the above-mentioned semiconductor structure, the end of the active area has multiple first protrusions, and the top surface of each first protrusion at the same end of the active area is in contact with the bottom surface of the same fuse gate. Compared with the end of the active area having 0 or 1 first protrusions, the number of first protrusions in contact with the fuse gate in the active area is increased, that is, the contact area of ​​the edge contact between the fuse gate and the end of the active area is increased, which improves the success rate of the fuse gate edge breakdown when the anti-fuse structure unit in the semiconductor structure is started, thereby improving the performance of the semiconductor structure.

[0023] The present disclosure also provides a semiconductor structure, comprising:

[0024] A substrate having an active region extending along a first direction;

[0025] a fuse gate, located on a top surface of the active region and extending along a second direction intersecting the first direction;

[0026] The fuse gate includes:

[0027] A first extending portion extending along a second direction;

[0028] A plurality of second protrusions are in contact with the first extension and extend along a third direction intersecting the second direction, and a bottom surface of each second protrusion is in contact with a top surface of the active region.

[0029] In the above-mentioned semiconductor structure, the fuse gate includes a plurality of second protrusions extending along a third direction intersecting with the second direction, and the bottom surface of each second protrusion is in contact with the top surface of the active area. In a horizontal plane parallel to the substrate, the arrangement of the second protrusions enables a multi-line contact between the fuse gate and the active area. Compared with a single-line contact between the fuse gate and the active area, the length of the edge contact between the fuse gate and the active area is increased, thereby improving the success rate of the fuse gate edge breakdown when the anti-fuse structure unit in the semiconductor structure is started, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 is a schematic top view of a semiconductor structure in one embodiment;

[0032] Figure 2 is a schematic top view of a semiconductor structure in another embodiment;

[0033] Figure 3 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure along the BB direction in a corresponding embodiment;

[0034] Figure 4 is a schematic top view of a semiconductor structure in yet another embodiment;

[0035] Figure 5 for Figure 4 A cross-sectional schematic diagram of a semiconductor structure along the BB direction in a corresponding embodiment;

[0036] Figure 6 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0037] Figure 7 is a schematic top view of a semiconductor structure after an active region is formed in one embodiment;

[0038] Figure 8 for Figure 7 A schematic cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0039] Fig. 9 for Figure 7 A schematic top view of a semiconductor structure after a fuse gate is formed in a corresponding embodiment;

[0040] Fig.10 for Fig. 9 A schematic cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0041] Fig.11 for Fig. 9 A schematic top view of a semiconductor structure after source and drain regions are formed in a corresponding embodiment;

[0042] Fig.12 for Fig.11 A schematic cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0043] Fig.13 is a schematic top view of a semiconductor structure after an active region is formed in another embodiment;

[0044] Fig.14 for Fig.13 A schematic cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0045] Fig.15 for Fig.13 A schematic top view of a semiconductor structure after a fuse gate is formed in a corresponding embodiment;

[0046] Fig.16 for Fig.15 A schematic cross-sectional view of the corresponding semiconductor structure along the BB direction;

[0047] Fig.17 for Fig.15 A schematic top view of a semiconductor structure after source and drain regions are formed in a corresponding embodiment;

[0048] Fig.18 for Fig.17 A schematic cross-sectional view of the corresponding semiconductor structure along direction BB.

[0049] Description of reference numerals:

[0050] 102, substrate; 104, fuse gate; 106, access gate; 202, active area; 204, first protrusion; 206, first extension; 208, second protrusion; 210, shallow trench isolation structure; 212, fuse gate dielectric layer; 214, fuse gate structure layer; 216, first doped region; 218, source and drain region; 220, access gate dielectric layer; 222, access gate structure layer. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the embodiments of the present application, the embodiments of the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the embodiments of the present application are given in the drawings. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the embodiments of the present application. The terms used herein in the specification of the embodiments of the present application are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0053] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the embodiments of the present application.

[0054] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first raised portion may be referred to as a second raised portion, and similarly, a second raised portion may be referred to as a first raised portion. Both the first raised portion and the second raised portion are raised portions, but they are not the same raised portion.

[0055] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of the present application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0056] In the present disclosure, the upper surface of the substrate is the surface of the substrate close to the word line groove opening, the lower surface of the substrate is the surface of the substrate close to the word line groove opening, and the upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For the structure or layer located in the substrate, the two surfaces in the vertical direction close to the upper surface of the substrate are the upper surface / top surface / top / top surface, and the surface away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom surface. For the structure or layer located on the substrate, on the contrary, the two surfaces close to the upper surface of the substrate are the lower surface / bottom surface / bottom / bottom surface, and the surface away from the upper surface of the substrate is the upper surface / top surface / top / top surface. For the structure, groove, hole or layer in the semiconductor structure, the surface in the horizontal direction is the sidewall / side of the structure, groove, hole or layer.

[0057] The anti-fuse structure unit as a redundant design includes two gate structures, namely, a fuse gate and an access gate. The access gate plays the role of controlling the switch, and the fuse gate is the key to whether the anti-fuse structure unit including the fuse gate is turned on. The different breakdown positions of the gate oxide layer in the fuse gate make the on-resistance of the anti-fuse gate structure unit different when it is working. The larger the on-resistance, the more likely it is that the problem of not being able to accurately identify whether the anti-fuse structure unit is turned on, that is, the occurrence of an un-blow issue, how to obtain a small on-resistance has become an urgent problem to be solved.

[0058] Figure 1 FIG. 1 is a schematic top view of a semiconductor structure in an embodiment. Figure 1 As shown, in this embodiment, a semiconductor structure is provided, including: a substrate 102 and a fuse gate 104, wherein an active area 202 extending along a first direction is formed in the substrate 102; the fuse gate 104 is located on the top surface of the end of the active area 202 and extends along a second direction intersecting the first direction; wherein the end of the active area 202 has a plurality of first protrusions 204, and the top surface of each first protrusion 204 at the same end of the active area 202 contacts the bottom surface of the same fuse gate 104.

[0059] The constituent material of the substrate 102 includes, but is not limited to, undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the substrate 102 is selected from single crystal silicon. For example, the first direction is perpendicular to the second direction, the first direction is, for example, the Y direction, and the second direction is, for example, the X direction.

[0060] The active area 202 is divided into a first end, a middle part and a second end along the first direction Y, that is, the active area 202 has an end with multiple first protrusions 204, including one or two of the first end and the second end that are in contact with the fuse gate 104, wherein one end of the middle part is in contact with the first end, the other end of the middle part is in contact with the second end, the first end and the second end are not in contact, the fuse gate 104 is located on the top surface of the first end and / or the top surface of the second end, and the same fuse gate 104 cannot be in contact with the top surface of the first end and the top surface of the second end at the same time. The end of the first end and the second end that contacts the fuse gate 104 has a plurality of first protrusions 204, that is, when only one of the first end and the second end contacts the fuse gate 104, the end that contacts the fuse gate 104 has a plurality of first protrusions 204; the end that does not contact the fuse gate 104 may have a plurality of first protrusions 204, or may not have a first protrusion 204, and the present disclosure does not limit this. When the first end and the second end contact different fuse gates 104 at the same time, both the first end and the second end have a plurality of first protrusions 204. Figure 1 The first end and the second end are in contact with different fuse gates 104 at the same time for exemplary description. Here, the multiple means greater than or equal to 2. On the plane parallel to the top surface of the substrate 102, the sum of the contact areas between the edge of the first protrusion 204 and the fuse gate 104 is the edge contact area between the fuse gate 104 and the active area 202. The first protrusion 204 is provided to increase the contact area of ​​the edge contact between the fuse gate 104 and the active area 202, reduce the probability of center break down of the fuse gate 104, that is, increase the probability of edge breakdown of the fuse gate 104, reduce the on-resistance of the fuse gate 104 when the semiconductor structure is working, improve the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure, reduce the occurrence of un-fuse abnormality, and improve the working performance of the semiconductor structure.

[0061] In the above-mentioned semiconductor structure, the end of the active area 202 has multiple first protrusions, and the top surface of each first protrusion 204 at the same end of the active area 202 contacts the bottom surface of the same fuse gate 104. Compared with the case where the end of the active area 202 has 0 or 1 first protrusion 204, the number of first protrusions 204 in contact with the fuse gate 104 in the active area 202 is increased, that is, the contact area of ​​the edge contact between the fuse gate 104 and the end of the active area 202 is increased, thereby improving the success rate of edge breakdown of the fuse gate 104 when starting the anti-fuse structure unit in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0062] In some embodiments, the top surface of the first protrusion 204 is in full contact with the bottom surface of the fuse gate 104. Compared with the case where the end of the active region 202 has a first protrusion 204 and part of the top surface of the first protrusion 204 is in contact with the bottom surface of the fuse gate 104, the length of the edge contact between the fuse gate 104 and the active region 202 is increased, and the success rate of the edge breakdown of the fuse gate when the anti-fuse structure unit in the semiconductor structure is started is further increased, the on-resistance of the fuse gate 104 when the semiconductor structure is working is reduced, the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure is improved, the occurrence of the un-fuse abnormality is reduced, and the performance of the semiconductor structure is improved. Compared with a case where the end of the active area 202 has a first protrusion 204 and the top surface of the first protrusion 204 is in contact with the entire bottom surface of the fuse gate 104, or the end of the active area 202 has no first protrusion 204, the length of the edge contact between the fuse gate 104 and the active area 202 remains unchanged, so that the contact area of ​​the edge contact between the fuse gate 104 and the active area 202 is increased by setting the first protrusion 204, while the length of the edge contact between the fuse gate 104 and the active area 202 is not affected, thereby maximizing the success rate of edge breakdown of the fuse gate 104, and allowing the first protrusion 204 to maximally reduce the on-resistance of the fuse gate 104 when the semiconductor structure is working, thereby improving the performance of the semiconductor structure.

[0063] In some other embodiments, a portion of the top surface of the first protrusion 204 contacts the bottom surface of the fuse gate 104. Compared with the case where the end of the active region 202 has a first protrusion 204 and a portion of the top surface of the first protrusion 204 contacts the bottom surface of the fuse gate 104, the length of the edge contact between the fuse gate 104 and the active region 202 is increased, and the success rate of the edge breakdown of the fuse gate when the anti-fuse structure unit in the semiconductor structure is started is further increased, the on-resistance of the fuse gate 104 when the semiconductor structure is working is reduced, the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

[0064] In some embodiments, the shape of the orthographic projection of the first protrusion 204 on the substrate 102 includes, but is not limited to, one or more of a parallelogram, a wave, an arc, or a triangle. For example, the parallelogram includes a rectangle and a square.

[0065] In some embodiments, the first end and the second end have different numbers of first protrusions 204 .

[0066] In other embodiments, the ends (first end and second end) of the active region 202 have the same number of first protrusions 204. Exemplarily, the orthographic projections of the first protrusions 204 at the ends of the active region 202 on the substrate 102 have the same shape, so that the preparation process of the active region 202 is simple.

[0067] In some embodiments, in the connection direction of the first protrusions 204 , the distances between adjacent first protrusions 204 are the same, so that the preparation process of the active region 202 is simple.

[0068] Figure 2 2 is a top view schematic diagram of a semiconductor structure in another embodiment. In one embodiment, the fuse gate 104 includes: a first extension portion 206 and a plurality of second protrusions 208; the first extension portion 206 extends along the second direction X, the second protrusions 208 are in contact with the first extension portion 206, and extend along a third direction intersecting the second direction X, and the bottom surface of each second protrusion 208 is in contact with the top surface of the end of the active area 202; illustratively, the third direction Y' is parallel to the first direction Y, and in other embodiments, the third direction Y' intersects with both the first direction Y and the second direction X. The third direction Y', the first direction Y and the second direction X are in the same plane, a first distance D1 between a first side surface of the second protrusion 208 away from the first extension portion 206 and the central axis AA of the active region 202 is smaller than a second distance D2 between a second side surface of the first protrusion 204 close to the central axis AA and the central axis; the central axis AA is a straight line passing through the midline point of the active region 202 in a direction perpendicular to the first direction Y, therefore, the orthographic projection of the side surface of the second protrusion 208 not in contact with the first extension portion 206 on the substrate 102 is located on the top surface of the active region 202, Among them, on a plane parallel to the surface of the substrate, the total length L of the edge contact between the fuse gate 104 and the active area 202 is W1+L1-L2, the first width W1 is the width of the active area 202 in the second direction X, the first length L1 is the perimeter of the projection figure of the orthographic projection of the second protrusion 208 on the active area 202, the second length L2 is the length of the orthographic projection of the side of the second protrusion 208 in contact with the first extension portion 206 on the substrate 102, and the second length L2 is a part of the first length L1, that is, L1>L2, therefore, the total length L is greater than the first width W1.

[0069] In the process of forming the fuse gate 104, on a plane parallel to the surface of the substrate 102, the gate dielectric layer at the edge of the fuse gate 104 is more susceptible to plasma bombardment than the gate dielectric layer at other positions. Therefore, the quality of the gate dielectric layer at the edge of the fuse gate 104 is worse than that of the gate dielectric layer at other positions of the fuse gate 104, and it is more likely to be broken down. By setting the second protrusion 208, the edge contact between the fuse gate 104 and the active area 202 is changed from a straight line contact to a multi-line contact, thereby increasing the total length of the edge contact between the fuse gate 104 and the active area 202, that is, the total length of the edge contact between the fuse gate 104 and the active area 202 is increased from less than or equal to the first width W1 to greater than the first width W1, further increasing the success rate of the edge breakdown of the fuse gate 104, reducing the on-resistance of the fuse gate 104 when the semiconductor structure is working, improving the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure, and improving the performance of the semiconductor structure.

[0070] In some embodiments, the top surface of the same end of the active region 202 contacts the bottom surfaces of several second protrusions 208 at the same time. Specifically, the top surface of the first end and / or the top surface of the second end contacts the bottom surface of at least one second protrusion 208.

[0071] In some embodiments, a top surface of at least one end of the active region 202 contacts a bottom surface of the second protrusion 208 .

[0072] In one embodiment, the edge of the orthographic projection of the second protrusion 208 on the active area 202 coincides with the edge of the active area 202. In other embodiments, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is located in the area surrounded by the edge of the active area 202. When the distance between the projection of the second protrusion 208 on the substrate 102 and the central axis AA remains unchanged, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is set to be located in the area surrounded by the edge of the active area 202, so as to further increase the total length of the edge contact between the fuse gate 104 and the active area 202, further increase the success rate of the edge breakdown of the fuse gate 104, and further improve the performance of the semiconductor structure.

[0073] In one embodiment, the shape of the second protrusion 208 is the same as that of the first protrusion 204 , that is, the shape of the orthographic projection of the second protrusion 208 on the substrate 102 is the same as that of the orthographic projection of the first protrusion 204 on the substrate 102 .

[0074] In one embodiment, any active region 202 is in contact with at least two spaced-apart fuse gates 104 at the same time, that is, a first end and a second end of the active region 202 are in contact with the spaced-apart fuse gates 104 respectively.

[0075] like Figure 1 As shown, in one embodiment, the width of the fuse gate 104 remains unchanged, and the direction of the width is perpendicular to the second direction X, that is, the fuse gate 104 does not include the second protrusion 208 .

[0076] like Figure 2 As shown, in one embodiment, the substrate 102 includes a shallow trench isolation structure 210, and the shallow trench isolation structure 210 isolates a plurality of active regions 202 arranged at intervals in the substrate 102, and the fuse gate 104 is in contact with the top surfaces of the ends of the plurality of active regions 202 at the same time. Exemplarily, the fuse gate 104 includes a plurality of fuse sub-gates arranged in sequence and in contact with each other, and at least one fuse sub-gate includes a second protrusion 208. Specifically, the fuse sub-gates correspond to the active regions 202 one by one, that is, the number of fuse sub-gates in the fuse gate 104 is equal to the number of active regions 202 in contact with the fuse gate 104 at the same time, the bottom surface of the fuse sub-gate is in contact with the top surface of the end of the corresponding active region 202, and at least one fuse sub-gate includes a second protrusion 208 whose bottom surface is in contact with the top surface of the active region 202. In some embodiments, the fuse sub-gate includes a plurality of second protrusions 208 contacting the top surface of the same end of the same active region 202 .

[0077] Figure 3 for Figure 2 A cross-sectional schematic diagram of a semiconductor structure along the BB direction in a corresponding embodiment is shown in FIG. Figure 2 , Figure 3 As shown, in one embodiment, the active region 202 includes ends (a first end, a second end) and a middle portion, and the semiconductor structure further includes: a plurality of access gates 106, the access gates 106 are located on the top surface of the middle portion of the active region 202, and extend along the second direction X. It can be understood that the access gates 106 are spaced apart from the fuse gates 104. Exemplarily, the top surface of the middle portion of the same active region 202 is in contact with the bottom surface of more than or equal to one access gate 106 at the same time, that is, at least one storage transistor is formed in the same active region 202.

[0078] like Figure 3As shown, in one embodiment, the fuse gate 104 includes: a fuse gate dielectric layer 212 and a fuse gate structure layer 214, the fuse gate dielectric layer 212 is in contact with the top surface of the end of the active area 202; the fuse gate structure layer 214 is located on the top surface of the fuse gate dielectric layer 214, and the orthographic projection of the fuse gate structure layer 214 on the fuse gate dielectric layer 212 coincides with the fuse gate dielectric layer 212, that is, the fuse gate structure layer 214 and the fuse gate dielectric layer 212 have the same shape.

[0079] Exemplarily, the constituent materials of the fuse gate dielectric layer 212 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0080] Exemplarily, the constituent materials of the fuse gate structure layer 214 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0081] Continue to refer Figure 3 In one embodiment, the semiconductor structure further includes: a first doped region 216, located in the active region 202, having a first conductivity type, at least a portion of the top surface of the first doped region 216 is in contact with the bottom surface of the fuse gate 104, wherein the active region 202 has a second conductivity type, and the second conductivity type is a conductivity type different from the first conductivity type. For example, the first conductivity type may be P-type and the second conductivity type may be N-type, or the first conductivity type may be N-type and the second conductivity type may be P-type. Exemplarily, the top surface of the first doped region 216 facing away from the access gate 106 is in contact with the bottom surface of the fuse gate 104.

[0082] It is clear that when the constituent material of the fuse gate dielectric layer 212 remains unchanged, when the semiconductor structure includes the first doping region 216, the first thickness of the fuse gate dielectric layer 212 is greater than the second thickness of the fuse gate dielectric layer 212 when the semiconductor structure does not include the first doping region 216, and the direction of the thickness is from the bottom surface of the substrate 102 away from the fuse gate 104 to the top surface of the substrate 102 forming the fuse gate 104.

[0083] In one embodiment, the semiconductor structure further includes: source and drain regions 218, which are located in the active region 202 on both sides of the access gate 106 and have the first conductivity type. The source and drain regions 218 can be used as source regions or drain regions. The source region, the drain region and the access gate 106 constitute an access transistor. In some embodiments, on a plane parallel to the top surface of the substrate 102, a side of the source and drain regions 218 facing away from the access gate 106 is in contact with the first doped region 216, and an orthographic projection of the access gate 106 on the substrate 102 is in contact with an orthographic projection of the source and drain regions 218 on the substrate 102. In other embodiments, the source and drain regions 218 are located in the active region 202 between the access gate 106 and an adjacent access gate 106 and / or in the active region between the access gate 106 and the fuse gate 104; on a plane parallel to the top surface of the substrate 102, one side of the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102, and the other side of the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102 or is in contact with the orthographic projection of the fuse gate 104 on the substrate 102.

[0084] like Figure 3 As shown, in one embodiment, the access gate 106 includes: an access gate dielectric layer 220 and an access gate structure layer 222, the access gate dielectric layer 220 is in contact with the top surface of the middle part of the active area 202; the access gate structure layer 222 is located on the top surface of the access gate dielectric layer 220, and the orthographic projection of the access gate structure layer 222 on the access gate dielectric layer 220 coincides with the access gate dielectric layer 220, that is, the access gate structure layer 222 and the access gate dielectric layer 220 have the same shape.

[0085] Exemplarily, the constituent materials of the access gate dielectric layer 220 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Exemplarily, the constituent materials of the access gate dielectric layer 220 and the constituent materials of the fuse gate dielectric layer 212 are the same or different.

[0086] Exemplarily, the constituent material of the access gate structure layer 222 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). Exemplarily, the constituent material of the access gate structure layer 222 is the same as or different from the constituent material of the fuse gate structure layer 214.

[0087] Figure 4 FIG. 1 is a schematic top view of a semiconductor structure in another embodiment. Figure 4As shown, in this embodiment, a semiconductor structure is provided, including: a substrate 102 and a fuse gate 104, wherein an active region 202 extending along a first direction Y is formed in the substrate 102; the fuse gate 104 is located on the top surface of the active region 202 and extends along a second direction X intersecting the first direction Y; the fuse gate 104 includes: a first extension portion 206 and a plurality of second protrusions 208, wherein the first extension portion 206 extends along the second direction X; the second protrusions 208 contact the first extension portion 206 and extend along a third direction Y' intersecting the second direction X, wherein the bottom surface of each second protrusion 208 contacts the top surface of the active region 202. In this embodiment, the first direction Y, the second direction X, and the third direction Y' are defined as described above and are not defined herein. The orthographic projection of the side surface of the second protrusion 208 that is not in contact with the first extension portion 206 on the substrate 102 is located on the top surface of the active area 202, wherein, on a plane parallel to the surface of the substrate 102, the total length L of the edge contact between the fuse gate 104 and the active area 202 is W1+L1-L2, the first width W1 is the width of the active area 202 in the second direction X, the first length L1 is the perimeter of the projection figure of the orthographic projection of the second protrusion 208 on the active area 202, the second length L2 is the length of the orthographic projection of the side surface of the second protrusion 208 in contact with the first extension portion 206 on the substrate 102, and the second length L2 is a part of the first length L1, that is, L1>L2, therefore, the total length L is greater than the first width W1.

[0088] In the process of forming the fuse gate 104, on a plane parallel to the surface of the substrate 102, the gate dielectric layer at the edge position of the fuse gate 104 is more susceptible to plasma bombardment than the gate dielectric layer at other positions. Therefore, the quality of the gate dielectric layer at the edge position of the fuse gate 104 is worse than that of the gate dielectric layer at other positions of the fuse gate 104, and it is more likely to be broken down. By setting the second protrusion 208, the edge contact between the fuse gate 104 and the active area 202 is changed from a straight line contact to a multi-line contact, and the total length of the edge contact between the fuse gate 104 and the active area 202 is increased, that is, the total length of the edge contact between the fuse gate 104 and the active area 202 is increased from less than or equal to the first width W1 to a length L greater than the first width W1, thereby increasing the success rate of the edge breakdown of the fuse gate 104, reducing the on-resistance of the fuse gate 104 when the semiconductor structure is working, improving the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure, and improving the performance of the semiconductor structure.

[0089] In the above semiconductor structure, the fuse gate 104 includes a plurality of second protrusions 208 extending along a third direction Y' intersecting the second direction X, and the bottom surface of each second protrusion 208 contacts the top surface of the active area 202. On a plane parallel to the substrate 102, the second protrusions 208 are arranged so that there is a multi-line contact between the fuse gate 104 and the active area 202. Compared with the single-line contact between the fuse gate 104 and the active area 202, the length of the edge contact between the fuse gate 104 and the active area 202 is increased, thereby improving the success rate of the edge breakdown of the fuse gate 104 when the anti-fuse structure unit in the semiconductor structure is started, thereby improving the performance of the semiconductor structure.

[0090] The active region 202 is divided into a first end, a middle portion, and a second end along the first direction Y. In some embodiments, the top surface of the same end of the active region 202 that contacts the fuse gate 104 contacts the bottom surfaces of several second protrusions 208 at the same time. Specifically, the top surface of the first end and / or the top surface of the second end contacts the bottom surface of at least one second protrusion 208.

[0091] In one embodiment, the edge of the orthographic projection of the second protrusion 208 on the active area 202 coincides with the edge of the active area 202. In other embodiments, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is located in the area surrounded by the edge of the active area 202. When the distance between the projection of the second protrusion 208 on the substrate 102 and the central axis AA remains unchanged, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is set to be located in the area surrounded by the edge of the active area 202, so as to further increase the total length of the edge contact between the fuse gate 104 and the active area 202, further increase the success rate of the edge breakdown of the fuse gate 104, and further improve the performance of the semiconductor structure, wherein the central axis AA is a straight line passing through the center point of the active area 202 in the direction perpendicular to the first direction Y.

[0092] In one embodiment, the shape of the orthographic projection of the second protrusion 208 on the substrate 102 includes, but is not limited to, one or more of a parallelogram, a wave, an arc, or a triangle. For example, the parallelogram includes a rectangle and a square.

[0093] In one embodiment, any active region 202 is in contact with at least two spaced-apart fuse gates 104 at the same time, that is, a first end and a second end of the active region 202 are in contact with the spaced-apart fuse gates 104 respectively.

[0094] In one embodiment, the end of the active region 202 has no first protrusion or has one first protrusion.

[0095] In other embodiments, there are multiple first protrusions at at least one end of the active area 202. This arrangement can increase the contact area of ​​the edge contact between the fuse gate 104 and the end of the active area 202, further improve the success rate of edge breakdown of the fuse gate 104 when starting the anti-fuse structure unit in the semiconductor structure, and improve the performance of the semiconductor structure.

[0096] like Figure 4 As shown, in one embodiment, the substrate 102 includes a shallow trench isolation structure 210, and the shallow trench isolation structure 210 isolates a plurality of active regions 202 arranged at intervals in the substrate 102, and the fuse gate 104 is in contact with the top surfaces of the ends of the plurality of active regions 202 at the same time. Exemplarily, the fuse gate 104 includes a plurality of fuse sub-gates arranged in sequence and in contact with each other, and specifically, the fuse sub-gates correspond to the active regions 202 one by one, that is, the number of fuse sub-gates in the fuse gate 104 is equal to the number of active regions 202 in contact with the fuse gate 104 at the same time, the bottom surface of the fuse sub-gate is in contact with the top surface of the end of the corresponding active region 202, and the fuse sub-gates each include a plurality of second protrusions 208 in contact with the top surface of the same end of the same active region 202, and the number of the second protrusions 208 in each fuse sub-gate is the same or different.

[0097] Figure 5 for Figure 4 A cross-sectional schematic diagram of a semiconductor structure along the BB direction in a corresponding embodiment is shown in FIG. Figure 4 , Figure 5 As shown, in one embodiment, the active region 202 includes ends (a first end, a second end) and a middle portion, and the semiconductor structure further includes: a plurality of access gates 106, the access gates 106 are located on the top surface of the middle portion of the active region 202, and extend along the second direction X. It can be understood that the access gates 106 are spaced apart from the fuse gates 104. Exemplarily, the top surface of the middle portion of the same active region 202 is in contact with the bottom surface of more than or equal to one access gate 106 at the same time, that is, at least one storage transistor is formed in the same active region 202.

[0098] like Figure 5 As shown, in one embodiment, the fuse gate 104 includes: a fuse gate dielectric layer 212 and a fuse gate structure layer 214, the fuse gate dielectric layer 212 is in contact with the top surface of the end of the active area 202; the fuse gate structure layer 214 is located on the top surface of the fuse gate dielectric layer 214, and the orthographic projection of the fuse gate structure layer 214 on the fuse gate dielectric layer 212 coincides with the fuse gate dielectric layer 212, that is, the fuse gate structure layer 214 and the fuse gate dielectric layer 212 have the same shape.

[0099] Exemplarily, the constituent materials of the fuse gate dielectric layer 212 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3).

[0100] Exemplarily, the constituent materials of the fuse gate structure layer 214 include, but are not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi).

[0101] like Figure 5 As shown, in one embodiment, the semiconductor structure further includes: source and drain regions 218, which are located in the active region 202 on both sides of the access gate 106 and have a first conductivity type, and the source and drain regions 218 can be used as source regions or drain regions, and the source region, the drain region and the access gate 106 constitute an access transistor, wherein the active region 202 has a second conductivity type, and the second conductivity type is a different conductivity type from the first conductivity type. For example, the first conductivity type can be P-type and the second conductivity type can be N-type, or the first conductivity type can be N-type and the second conductivity type can be P-type. In some embodiments, the source and drain regions 218 are located in the active region 202 between the access gate 106 and an adjacent access gate 106 and / or in the active region 202 between the access gate 106 and an adjacent fuse gate 104. On a plane parallel to the top surface of the substrate 102, one side of the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102, and the other side of the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102 or is in contact with the orthographic projection of the fuse gate 104 on the substrate 102.

[0102] In some other embodiments, the semiconductor structure further includes: a first doped region 216, located in the active region 202, having a first conductivity type, and at least a portion of the top surface of the first doped region 216 is in contact with the bottom surface of the fuse gate 104. Exemplarily, the top surface of the first doped region 216 facing away from the access gate 106 is in contact with the bottom surface of the fuse gate 104. On a plane parallel to the top surface of the substrate 102, a side of the source and drain region 218 facing away from the access gate 106 is in contact with the first doped region 216, and the orthographic projection of the access gate 106 on the substrate 102 is in contact with the orthographic projection of the source and drain region 218 on the substrate 102.

[0103] like Figure 5 As shown, in one embodiment, the access gate 106 includes: an access gate dielectric layer 220 and an access gate structure layer 222, the access gate dielectric layer 220 is in contact with the top surface of the middle part of the active area 202; the access gate structure layer 222 is located on the top surface of the access gate dielectric layer 220, and the orthographic projection of the access gate structure layer 222 on the access gate dielectric layer 220 coincides with the access gate dielectric layer 220, that is, the access gate structure layer 222 and the access gate dielectric layer 220 have the same shape.

[0104] Exemplarily, the constituent materials of the access gate dielectric layer 220 include, but are not limited to, silicon oxide (e.g., silicon dioxide), silicon nitride (silicon oxynitride), nitride (e.g., silicon nitride), metal oxide (e.g., Al2O3), metal oxynitride (e.g., AlON), metal silicide, high-k dielectric material (dielectric constant greater than 3.9), low-k dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), ultra-low-k dielectric material (dielectric constant less than 2.5), ferroelectric material, anti-ferroelectric material, carbide (silicon carbide), or a combination thereof. Exemplarily, the high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). Exemplarily, the constituent materials of the access gate dielectric layer 220 and the constituent materials of the fuse gate dielectric layer 212 are the same or different.

[0105] Exemplarily, the constituent material of the access gate structure layer 222 includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Exemplarily, the metal may be tungsten (W), nickel (Ni), copper (Cu), aluminum (Al), molybdenum (Mo), ruthenium (Ru), tantalum (Ta), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes tungsten silicon (WSi). Exemplarily, the constituent material of the access gate structure layer 222 is the same as or different from the constituent material of the fuse gate structure layer 214.

[0106] Figure 6 FIG. 1 is a schematic diagram of a process for preparing a semiconductor structure in an embodiment. Figure 6 As shown, in this embodiment, a method for preparing a semiconductor structure is provided, comprising:

[0107] S102, providing a substrate, in which an active region extending along a first direction is formed.

[0108] S104, forming a fuse gate on the top surface of the end of the active region.

[0109] Figure 7 is a schematic top view of a semiconductor structure after an active region is formed in one embodiment, Figure 8 for Figure 7 The corresponding cross-sectional diagram of the semiconductor structure along the BB direction, Fig. 9 for Figure 7 A schematic top view of a semiconductor structure after a fuse gate is formed in a corresponding embodiment, Fig.10 for Fig. 9 The corresponding schematic cross-sectional view of the semiconductor structure along the BB direction is shown in FIG. Figure 7-Figure 10 As shown, step S102-step S104 specifically include: providing a substrate 102, and forming an active area 202 extending along a first direction in the substrate 102, wherein a plurality of first protrusions 204 are formed at the end of the active area 202, and a fuse gate 104 extending along a second direction is formed on the top surface of the end of the active area 202, the second direction intersects with the first direction, and the top surface of each first protrusion 204 at the same end of the active area 202 contacts the bottom surface of the same fuse gate 104.

[0110] The constituent material of the substrate 102 includes, but is not limited to, undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the constituent material of the substrate 102 is selected from single crystal silicon. For example, the first direction is perpendicular to the second direction, the first direction is, for example, the Y direction, and the second direction is, for example, the X direction.

[0111] The active area 202 is divided into a first end, a middle part and a second end along the first direction Y, that is, the active area 202 has an end with multiple first protrusions 204, including one or two of the first end and the second end that are in contact with the fuse gate 104, wherein one end of the middle part is in contact with the first end, the other end of the middle part is in contact with the second end, the first end and the second end are not in contact, the fuse gate 104 is located on the top surface of the first end and / or the top surface of the second end, and the same fuse gate 104 cannot be in contact with the top surface of the first end and the top surface of the second end at the same time. The end portion of the first end portion and the second end portion that contacts the fuse gate 104 has a plurality of first protrusions 204, that is, when only one of the first end portion and the second end portion contacts the fuse gate 104, the end portion that contacts the fuse gate 104 has a plurality of first protrusions 204; the end portion that does not contact the fuse gate 104 may have a plurality of first protrusions 204 or may not have a first protrusion 204, and the present disclosure does not impose any restrictions on this. When the first end portion and the second end portion contact different fuse gates 104 at the same time, both the first end portion and the second end portion have a plurality of first protrusions 204. The multiple here means greater than or equal to 2. On a plane parallel to the top surface of the substrate 102, the sum of the contact areas between the edge of the first protrusion 204 and the fuse gate 104 is the edge contact area between the fuse gate 104 and the active area 202. By setting the first protrusion 204, the contact area of ​​the edge contact between the fuse gate 104 and the active area 202 is increased, and the probability of center break down of the fuse gate 104 is reduced, that is, the probability of edge breakdown of the fuse gate 104 is increased, the on-resistance of the fuse gate 104 when the semiconductor structure is working is reduced, the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure is improved, the occurrence of unblown abnormalities is reduced, and the working performance of the semiconductor structure is improved.

[0112] In the preparation method of the above-mentioned semiconductor structure, a plurality of first protrusions 204 are formed at the end of the active area 202, and the top surface of each first protrusion 204 at the same end of the active area 202 contacts the bottom surface of the same fuse gate 104. Compared with the case where the end of the active area 202 has 0 or 1 first protrusion 204, the number of first protrusions 204 in contact with the fuse gate 104 in the active area 202 is increased, that is, the contact area of ​​the edge contact between the fuse gate 104 and the end of the active area 202 is increased, thereby improving the success rate of edge breakdown of the fuse gate 104 when starting the anti-fuse structure unit in the semiconductor structure, thereby improving the performance of the semiconductor structure.

[0113] The top surface of the first protrusion 204 is in full contact with the bottom surface of the fuse gate 104. Compared with the case where the end of the active area 202 has a first protrusion 204 and part of the top surface of the first protrusion 204 is in contact with the bottom surface of the fuse gate 104, the length of the edge contact between the fuse gate 104 and the active area 202 is increased, and the success rate of the edge breakdown of the fuse gate when the anti-fuse structure unit in the semiconductor structure is started is further increased, and the on-resistance of the fuse gate 104 when the semiconductor structure is working is reduced, and the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure is improved, and the occurrence of the un-fuse abnormality is reduced, and the performance of the semiconductor structure is improved. Compared with a case where the end of the active area 202 has a first protrusion 204 and the top surface of the first protrusion 204 is in contact with the entire bottom surface of the fuse gate 104, or the end of the active area 202 has no first protrusion 204, the length of the edge contact between the fuse gate 104 and the active area 202 remains unchanged, so that the contact area of ​​the edge contact between the fuse gate 104 and the active area 202 is increased by setting the first protrusion 204, while the length of the edge contact between the fuse gate 104 and the active area 202 is not affected, thereby maximizing the success rate of edge breakdown of the fuse gate 104, and allowing the first protrusion 204 to maximally reduce the on-resistance of the fuse gate 104 when the semiconductor structure is working, thereby improving the performance of the semiconductor structure.

[0114] In some other embodiments, a portion of the top surface of the first protrusion 204 contacts the bottom surface of the fuse gate 104. Compared with the case where the end of the active region 202 has a first protrusion 204 and a portion of the top surface of the first protrusion 204 contacts the bottom surface of the fuse gate 104, the length of the edge contact between the fuse gate 104 and the active region 202 is increased, and the success rate of the edge breakdown of the fuse gate when the anti-fuse structure unit in the semiconductor structure is started is further increased, the on-resistance of the fuse gate 104 when the semiconductor structure is working is reduced, the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure is improved, and the performance of the semiconductor structure is improved.

[0115] In some embodiments, the shape of the orthographic projection of the first protrusion 204 on the substrate 102 includes, but is not limited to, one or more of a parallelogram, a wave, an arc, or a triangle. For example, the parallelogram includes a rectangle and a square.

[0116] In some embodiments, the first end and the second end have different numbers of first protrusions 204 .

[0117] In other embodiments, the ends (first end and second end) of the active region 202 have the same number of first protrusions 204. Exemplarily, the orthographic projections of the first protrusions 204 at the ends of the active region 202 on the substrate 102 have the same shape, so that the preparation process of the active region 202 is simple.

[0118] In some embodiments, in the connection direction of the first protrusions 204 , the distances between adjacent first protrusions 204 are the same, so that the preparation process of the active region 202 is simple.

[0119] like Figure 7 , Figure 8 As shown, in one embodiment, the substrate 102 includes a shallow trench isolation structure 210 , which isolates a plurality of active regions 202 arranged at intervals in the substrate 102 , and the fuse gate 104 contacts the top surfaces of the ends of the plurality of active regions 202 at the same time.

[0120] like Figure 7 , Figure 8 As shown, in one embodiment, before forming the fuse gate 104 on the top surface of the end of the active region 202, it also includes: forming a first doped region 216 having a first conductivity type in the active region 102, wherein the active region 202 has a second conductivity type, and the second conductivity type is a conductivity type different from the first conductivity type. For example, the first conductivity type can be P-type and the second conductivity type can be N-type, or the first conductivity type can be N-type and the second conductivity type can be P-type. Exemplarily, at least a portion of the top surface of the first doped region 216 contacts the bottom surface of the fuse gate 104.

[0121] like Fig.10 As shown, in one embodiment, forming a fuse gate 104 on the top surface at the end of the active area 202 includes: forming a fuse gate dielectric layer 212 on the top surface at the end of the active area 202; forming a fuse gate structure layer 214 on the top surface of the fuse gate dielectric layer 212, wherein the orthographic projection of the fuse gate structure layer 214 on the fuse gate dielectric layer 212 coincides with the fuse gate dielectric layer 212, that is, the fuse gate structure layer 214 and the fuse gate dielectric layer 212 have the same shape.

[0122] It is clear that, when the constituent material of the fuse gate dielectric layer 212 remains unchanged, when the semiconductor structure includes the first doping region 216, the first thickness of the fuse gate dielectric layer 212 is greater than the second thickness of the fuse gate dielectric layer 212 when the semiconductor structure does not include the first doping region 216, and the direction of the thickness is from the bottom surface of the substrate 102 away from the fuse gate 104 to the top surface of the substrate 102 forming the fuse gate 104.

[0123] like Fig. 9 , Fig.10 As shown, in one embodiment, the active region 202 includes an end portion (a first end portion, a second end portion) and a middle portion, and a fuse gate 104 is formed on a top surface of the end portion of the active region 202, including:

[0124] A plurality of access gates 106 are formed on the top surface of the middle portion of the active region 202, and the access gates 106 extend along the second direction X. It can be understood that the access gates 106 are spaced apart from the fuse gates 104. Exemplarily, the top surface of the middle portion of the same active region 202 is in contact with the bottom surfaces of more than or equal to one access gate 106 at the same time, that is, at least one storage transistor is formed in the same active region 202.

[0125] like Fig.10 As shown, in one embodiment, the access gate 106 includes: an access gate dielectric layer 220 and an access gate structure layer 222, the access gate dielectric layer 220 is in contact with the top surface of the middle part of the active area 202; the access gate structure layer 222 is located on the top surface of the access gate dielectric layer 220, and the orthographic projection of the access gate structure layer 222 on the access gate dielectric layer 220 coincides with the access gate dielectric layer 220, that is, the access gate structure layer 222 and the access gate dielectric layer 220 have the same shape.

[0126] In some embodiments, a fuse gate dielectric layer 212 is formed on the top surface of the end of the active area 202, including: forming an access gate dielectric layer 220 on the top surface of the middle part of the active area 202, and the access gate dielectric layer 220 is spaced apart from the fuse gate dielectric layer 212; forming a fuse gate structure layer 214 on the top surface of the fuse gate dielectric layer 212, including: forming an access gate structure layer 222 on the top surface of the access gate dielectric layer 220.

[0127] like Fig. 9 , Fig.10 As shown, in one embodiment, the fuse gate 104 extends along the second direction X, the width of the fuse gate 104 remains unchanged, and the direction of the width is perpendicular to the second direction X, that is, the fuse gate 104 does not include the second protrusion 208 .

[0128] Fig.11 for Fig. 9 A schematic top view of a semiconductor structure after source and drain regions are formed in a corresponding embodiment, Fig.12 for Fig.11 The corresponding schematic cross-sectional view of the semiconductor structure along the BB direction is shown in FIG. Fig.11 , Fig.12 As shown, in one embodiment, after forming the fuse gate 104 on the top surface of the end of the active region 202, the method further includes: forming source and drain regions 218 having a first conductivity type in the active region 202 on both sides of the access gate 106. The source and drain regions 218 can be used as source regions or drain regions, and the source region, the drain region and the access gate 106 constitute an access transistor.

[0129] like Fig.12 As shown, in an embodiment in which a first doped region 216 is formed in the active region 202, on a plane parallel to the top surface of the substrate 102, the side of the source / drain region 218 facing away from the access gate 106 is in contact with the first doped region 216, and the orthographic projection of the access gate 106 on the substrate 102 is in contact with the orthographic projection of the source / drain region 218 on the substrate 102.

[0130] In some other embodiments, the semiconductor structure does not include the first doped region 216, and the source / drain region 218 is located in the active region 202 between the access gate 106 and the adjacent access gate 106 and / or in the active region 202 between the access gate 106 and the fuse gate 104; on a plane parallel to the top surface of the substrate 102, one side of the orthographic projection of the source / drain region 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102, and the other side of the orthographic projection of the source / drain region 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102 or is in contact with the orthographic projection of the fuse gate 104 on the substrate 102.

[0131] like Figure 2As shown, in one embodiment, the fuse gate 104 includes: a first extension portion 206 and a plurality of second protrusions 208; forming the fuse gate 104 on the top surface of the end of the active area 202 includes: forming the fuse gate 104 including the first extension portion 206 and the plurality of second protrusions 208 contacting each other at the end of the active area 202, wherein the first extension portion 206 extends along the second direction X, the second protrusions 208 extend along the third direction intersecting the second direction X, and the bottom surface of each second protrusion 208 contacts the top surface of the end of the active area 202; illustratively, the third direction Y' is parallel to the first direction Y, and in other embodiments, the third direction Y' intersects with both the first direction Y and the second direction X. The third direction Y', the first direction Y and the second direction X are in the same plane, a first distance D1 between a first side surface of the second protrusion 208 away from the first extension portion 206 and the central axis AA of the active region 202 is smaller than a second distance D2 between a second side surface of the first protrusion 204 close to the central axis AA and the central axis; the central axis AA is a straight line passing through the midline point of the active region 202 in a direction perpendicular to the first direction Y, therefore, the orthographic projection of the side surface of the second protrusion 208 not in contact with the first extension portion 206 on the substrate 102 is located on the top surface of the active region 202, Among them, on a plane parallel to the surface of the substrate, the total length L of the edge contact between the fuse gate 104 and the active area 202 is W1+L1-L2, the first width W1 is the width of the active area 202 in the second direction X, the first length L1 is the perimeter of the projection figure of the orthographic projection of the second protrusion 208 on the active area 202, the second length L2 is the length of the orthographic projection of the side of the second protrusion 208 in contact with the first extension portion 206 on the substrate 102, and the second length L2 is a part of the first length L1, that is, L1>L2, therefore, the total length L is greater than the first width W1.

[0132] In the process of forming the fuse gate 104, on a plane parallel to the surface of the substrate 102, the gate dielectric layer at the edge of the fuse gate 104 is more susceptible to plasma bombardment than the gate dielectric layer at other positions. Therefore, the quality of the gate dielectric layer at the edge of the fuse gate 104 is worse than that of the gate dielectric layer at other positions of the fuse gate 104, and it is more likely to be broken down. By setting the second protrusion 208, the edge contact between the fuse gate 104 and the active area 202 is changed from a straight line contact to a multi-line contact, thereby increasing the total length of the edge contact between the fuse gate 104 and the active area 202, that is, the total length of the edge contact between the fuse gate 104 and the active area 202 is increased from less than or equal to the first width W1 to greater than the first width W1, further increasing the success rate of the edge breakdown of the fuse gate 104, reducing the on-resistance of the fuse gate 104 when the semiconductor structure is working, improving the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure, and improving the performance of the semiconductor structure.

[0133] In some embodiments, the top surface of the same end of the active region 202 contacts the bottom surfaces of several second protrusions 208 at the same time. Specifically, the top surface of the first end and / or the top surface of the second end contacts the bottom surface of at least one second protrusion 208.

[0134] In some embodiments, a top surface of at least one end of the active region 202 contacts a bottom surface of the second protrusion 208 .

[0135] In one embodiment, the edge of the orthographic projection of the second protrusion 208 on the active area 202 coincides with the edge of the active area 202. In other embodiments, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is located in the area surrounded by the edge of the active area 202. When the distance between the projection of the second protrusion 208 on the substrate 102 and the central axis AA remains unchanged, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is set to be located in the area surrounded by the edge of the active area 202, so as to further increase the total length of the edge contact between the fuse gate 104 and the active area 202, further increase the success rate of the edge breakdown of the fuse gate 104, and further improve the performance of the semiconductor structure.

[0136] In one embodiment, the shape of the second protrusion 208 is the same as that of the first protrusion 204 , that is, the shape of the orthographic projection of the second protrusion 208 on the substrate 102 is the same as that of the orthographic projection of the first protrusion 204 on the substrate 102 .

[0137] In one embodiment, any active region 202 is in contact with at least two spaced-apart fuse gates 104 at the same time, that is, a first end and a second end of the active region 202 are in contact with the spaced-apart fuse gates 104 respectively.

[0138] like Figure 2 As shown, in some embodiments, the fuse gate 104 includes a plurality of fuse sub-gates arranged in sequence and in contact with each other, and at least one fuse sub-gate includes a second protrusion 208. Specifically, the fuse sub-gates correspond to the active regions 202 one by one, that is, the number of fuse sub-gates in the fuse gate 104 is equal to the number of active regions 202 that are in contact with the fuse gate 104 at the same time, the bottom surface of the fuse sub-gate is in contact with the top surface of the end of the corresponding active region 202, and at least one fuse sub-gate includes a second protrusion 208 whose bottom surface is in contact with the top surface of the active region 202. In some embodiments, the fuse sub-gate includes a plurality of second protrusions 208 that are in contact with the top surface of the same end of the same active region 202.

[0139] Fig.13FIG. 1 is a schematic top view of a semiconductor structure after an active region is formed in another embodiment. Fig.14 for Fig.13 The corresponding cross-sectional diagram of the semiconductor structure along the BB direction, Fig.15 for Fig.13 A schematic top view of a semiconductor structure after a fuse gate is formed in a corresponding embodiment, Fig.16 for Fig.15 The corresponding schematic cross-sectional view of the semiconductor structure along the BB direction is shown in FIG. Figure 13-Figure 16 As shown, in some embodiments, step S102-step S104 specifically include: providing a substrate 102, and forming an active area 202 extending along a first direction in the substrate 102; forming a fuse gate 104 including a first extension portion 206 and a plurality of second protrusions 208 contacting each other on a top surface of an end portion of the active area 202, wherein the first extension portion 206 extends along a second direction X, the second protrusions 208 extend along a third direction intersecting the second direction X, and the bottom surface of each second protrusion 208 contacts the top surface of the end portion of the active area 202; illustratively, the third direction Y' is parallel to the first direction Y, and in other embodiments, the third direction Y' intersects with both the first direction Y and the second direction X. The third direction Y', the first direction Y and the second direction X are in the same plane, a first distance D1 between a first side surface of the second protrusion 208 away from the first extension portion 206 and the central axis AA of the active region 202 is smaller than a second distance D2 between a second side surface of the first protrusion 204 close to the central axis AA and the central axis; the central axis AA is a straight line passing through the midline point of the active region 202 in a direction perpendicular to the first direction Y, therefore, the orthographic projection of the side surface of the second protrusion 208 not in contact with the first extension portion 206 on the substrate 102 is located on the top surface of the active region 202, Among them, on a plane parallel to the surface of the substrate, the total length L of the edge contact between the fuse gate 104 and the active area 202 is W1+L1-L2, the first width W1 is the width of the active area 202 in the second direction X, the first length L1 is the perimeter of the projection figure of the orthographic projection of the second protrusion 208 on the active area 202, the second length L2 is the length of the orthographic projection of the side of the second protrusion 208 in contact with the first extension portion 206 on the substrate 102, and the second length L2 is a part of the first length L1, that is, L1>L2, therefore, the total length L is greater than the first width W1.

[0140] In the process of forming the fuse gate 104, on a plane parallel to the surface of the substrate 102, the gate dielectric layer at the edge position of the fuse gate 104 is more susceptible to plasma bombardment than the gate dielectric layer at other positions. Therefore, the quality of the gate dielectric layer at the edge position of the fuse gate 104 is worse than that of the gate dielectric layer at other positions of the fuse gate 104, and it is more likely to be broken down. By setting the second protrusion 208, the edge contact between the fuse gate 104 and the active area 202 is changed from a straight line contact to a multi-line contact, and the total length of the edge contact between the fuse gate 104 and the active area 202 is increased, that is, the total length of the edge contact between the fuse gate 104 and the active area 202 is increased from less than or equal to the first width W1 to a length L greater than the first width W1, thereby increasing the success rate of the edge breakdown of the fuse gate 104, reducing the on-resistance of the fuse gate 104 when the semiconductor structure is working, improving the accuracy of identifying the conduction of the anti-fuse structure unit in the semiconductor structure, and improving the performance of the semiconductor structure.

[0141] In the method for preparing the semiconductor structure, the formed fuse gate 104 includes a plurality of second protrusions 208 extending along a third direction Y' intersecting the second direction X, and the bottom surface of each second protrusion 208 contacts the top surface of the active area 202. On a plane parallel to the substrate 102, the second protrusions 208 are arranged so that there is a multi-line contact between the fuse gate 104 and the active area 202. Compared with the single-line contact between the fuse gate 104 and the active area 202, the length of the edge contact between the fuse gate 104 and the active area 202 is increased, thereby improving the success rate of the edge breakdown of the fuse gate 104 when the anti-fuse structure unit in the semiconductor structure is started, thereby improving the performance of the semiconductor structure.

[0142] like Fig.13 As shown, in one embodiment, the end of the active region 202 has no first protrusion 204 or has one first protrusion 204 .

[0143] like Fig.13 As shown, in other embodiments, there are multiple first protrusions 204 at least one end of the active area 202. This arrangement can increase the contact area of ​​the edge contact between the fuse gate 104 and the end of the active area 202, further improve the success rate of edge breakdown of the fuse gate 104 when starting the anti-fuse structure unit in the semiconductor structure, and improve the performance of the semiconductor structure.

[0144] The active region 202 is divided into a first end, a middle portion, and a second end along the first direction Y. In some embodiments, the top surface of the same end of the active region 202 that contacts the fuse gate 104 contacts the bottom surfaces of several second protrusions 208 at the same time. Specifically, the top surface of the first end and / or the top surface of the second end contacts the bottom surface of at least one second protrusion 208.

[0145] The active region 202 is divided into a first end, a middle portion, and a second end along the first direction Y. In some embodiments, the top surface of the same end of the active region 202 that contacts the fuse gate 104 contacts the bottom surfaces of several second protrusions 208 at the same time. Specifically, the top surface of the first end and / or the top surface of the second end contacts the bottom surface of at least one second protrusion 208.

[0146] In one embodiment, the edge of the orthographic projection of the second protrusion 208 on the active area 202 coincides with the edge of the active area 202. In other embodiments, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is located in the area surrounded by the edge of the active area 202. When the distance between the projection of the second protrusion 208 on the substrate 102 and the central axis AA remains unchanged, the edge of the orthographic projection of the second protrusion 208 on the active area 202 is set to be located in the area surrounded by the edge of the active area 202, so as to further increase the total length of the edge contact between the fuse gate 104 and the active area 202, further increase the success rate of the edge breakdown of the fuse gate 104, and further improve the performance of the semiconductor structure, wherein the central axis AA is a straight line passing through the center point of the active area 202 in the direction perpendicular to the first direction Y.

[0147] In one embodiment, the shape of the orthographic projection of the second protrusion 208 on the substrate 102 includes, but is not limited to, one or more of a parallelogram, a wave, an arc, or a triangle. For example, the parallelogram includes a rectangle and a square.

[0148] In one embodiment, any active region 202 is in contact with at least two spaced-apart fuse gates 104 at the same time, that is, a first end and a second end of the active region 202 are in contact with the spaced-apart fuse gates 104 respectively.

[0149] like Fig.13 , Fig.15As shown, in one embodiment, the substrate 102 includes a shallow trench isolation structure 210, and the shallow trench isolation structure 210 isolates a plurality of active regions 202 arranged at intervals in the substrate 102, and the fuse gate 104 is in contact with the top surfaces of the ends of the plurality of active regions 202 at the same time. Exemplarily, the fuse gate 104 includes a plurality of fuse sub-gates arranged in sequence and in contact with each other, and specifically, the fuse sub-gates correspond to the active regions 202 one by one, that is, the number of fuse sub-gates in the fuse gate 104 is equal to the number of active regions 202 in contact with the fuse gate 104 at the same time, the bottom surface of the fuse sub-gate is in contact with the top surface of the end of the corresponding active region 202, and the fuse sub-gates each include a plurality of second protrusions 208 in contact with the top surface of the same end of the same active region 202, and the number of the second protrusions 208 in each fuse sub-gate is the same or different.

[0150] like Fig.15 , Fig.16 As shown, in one embodiment, the active region 202 includes an end portion (a first end portion, a second end portion) and a middle portion, and a fuse gate 104 is formed on a top surface of the end portion of the active region 202, including:

[0151] A plurality of access gates 106 are formed on the top surface of the middle portion of the active region 202, and the access gates 106 extend along the second direction X. It can be understood that the access gates 106 are spaced apart from the fuse gates 104. Exemplarily, the top surface of the middle portion of the same active region 202 is in contact with the bottom surfaces of more than or equal to one access gate 106 at the same time, that is, at least one storage transistor is formed in the same active region 202.

[0152] like Fig.16 As shown, in one embodiment, forming a fuse gate 104 on the top surface at the end of the active area 202 includes: forming a fuse gate dielectric layer 212 on the top surface at the end of the active area 202; forming a fuse gate structure layer 214 on the top surface of the fuse gate dielectric layer 212, wherein the orthographic projection of the fuse gate structure layer 214 on the fuse gate dielectric layer 212 coincides with the fuse gate dielectric layer 212, that is, the fuse gate structure layer 214 and the fuse gate dielectric layer 212 have the same shape.

[0153] Fig.17 for Fig.15 A schematic top view of a semiconductor structure after source and drain regions are formed in a corresponding embodiment, Fig.18 for Fig.17 The corresponding schematic cross-sectional view of the semiconductor structure along the BB direction is shown in FIG. Fig.17 , Fig.18As shown, in one embodiment, after forming the fuse gate 104 on the top surface of the end of the active region 202, the method further includes: forming source and drain regions 218 having a first conductivity type in the active region 202 on both sides of the access gate 106. The source and drain regions 218 can be used as source regions or drain regions, and the source region, the drain region and the access gate 106 constitute an access transistor.

[0154] like Fig.18 As shown, in some embodiments, the source and drain regions 218 are located in the active region 202 between the access gate 106 and the adjacent access gate 106 and / or in the active region 202 between the access gate 106 and the fuse gate 104; on a plane parallel to the top surface of the substrate 102, one side of the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102, and the other side opposite to the orthographic projection of the source and drain regions 218 on the substrate 102 is in contact with the orthographic projection of the access gate 106 on the substrate 102 or is in contact with the orthographic projection of the fuse gate 104 on the substrate 102.

[0155] It should be understood that although Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 6 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0156] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0157] The above-mentioned embodiments only express several implementation methods of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, wherein an active region extending along a first direction is formed in the substrate; a fuse gate, located on a top surface of an end portion of the active region and extending along a second direction intersecting the first direction; The end of the active region has a plurality of first protrusions, and the top surface of each of the first protrusions at the same end of the active region contacts the bottom surface of the same fuse gate.

2. The semiconductor structure according to claim 1, characterized in that: The fuse gate comprises: A first extending portion extending along the second direction; a plurality of second protrusions, contacting the first extension portion and extending along a third direction intersecting the second direction, wherein a bottom surface of each of the second protrusions is in contact with a top surface of the active region; A first distance between a first side surface of the second protrusion facing away from the first extension portion and the central axis of the active region is smaller than a second distance between a second side surface of the first protrusion close to the central axis and the central axis.

3. The semiconductor structure according to claim 2, characterized in that: An edge of an orthographic projection of the second protrusion on the active region coincides with an edge of the active region.

4. The semiconductor structure according to claim 2, characterized in that: The shape of the second protrusion is the same as that of the first protrusion.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that: Any of the active regions is in contact with at least two of the fuse gates that are spaced apart from each other.

6. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The width of the fuse gate remains unchanged, and a direction of the width is perpendicular to the second direction.

7. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The active region includes a doped region, and a bottom surface of the fuse gate contacts a top surface of the doped region.

8. The semiconductor structure according to any one of claims 1 to 4, characterized in that: The active region includes an end portion and a middle portion, and the semiconductor structure further includes: The access gate is located on the top surface of the middle portion and extends along the second direction.

9. The semiconductor structure according to claim 1, characterized in that: The fuse gate comprises: a fuse gate dielectric layer, contacting a top surface of an end portion of the active region; The fuse gate structure layer is located on the top surface of the fuse gate dielectric layer, and the orthographic projection of the fuse gate structure layer on the fuse gate dielectric layer coincides with the fuse gate dielectric layer.

10. A semiconductor structure, characterized in that: include: a substrate, wherein an active region extending along a first direction is formed in the substrate; a fuse gate, located on a top surface of the active region and extending along a second direction intersecting the first direction; The fuse gate comprises: A first extending portion extending along the second direction; A plurality of second protrusions are in contact with the first extension portion and extend along a third direction intersecting the second direction, and a bottom surface of each of the second protrusions is in contact with a top surface of the active region.

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