Manufacturing method of flash memory device and flash memory device

Abstract

The invention discloses a manufacturing method of a flash memory device and the flash memory device, and the method comprises the steps: providing a substrate, and forming a gate structure and a peripheral resistance region on the substrate; the top surface of the gate structure is higher than the top surface of the peripheral resistance region; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the peripheral resistance region; performing CMP processing on the interlayer dielectric layer, and stopping on the top surface of the gate structure; etching the gate structure to form a groove; filling a metal layer in the groove; a metal plug is formed on the metal layer. The purpose of reducing the Gate resistance of the flash memory device is achieved through the metal layer without being limited by the line width of the gate structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing a flash memory device and a flash memory device. Background Art

[0002] Traditional ETOX (Erase Through Oxide) flash uses Co-Salicide (Co-Salicide is a term used in semiconductor manufacturing processes, where "Co" refers to metal cobalt and "Salicide" is the abbreviation of "Self-Aligned Silicide") to reduce the resistance on the gate. As the cell size gradually decreases, the gate also becomes smaller. The smaller the gate, the lower the quality of the salicide formed, making it unsuitable for cell-related processes below 45nm. With ion implantation, as more and more gates are connected in common, the resistance will be too large, causing the effective voltage to drop, greatly reducing the device efficiency. How to effectively reduce the gate resistance is a bottleneck in the continuous reduction of ETOX flash. Summary of the invention

[0003] The object of the present invention is to provide a method for manufacturing a flash memory device and a flash memory device, so as to effectively solve the problem of excessively high gate resistance of the flash memory device.

[0004] In order to solve the above problems, the present invention is implemented by the following technical solutions:

[0005] A method for manufacturing a flash memory device includes: providing a substrate, and forming a gate structure and a peripheral resistance region on the substrate. The top surface of the gate structure is higher than the top surface of the peripheral resistance region.

[0006] An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the gate structure and the peripheral resistance area. The interlayer dielectric layer is subjected to CMP treatment, and the treatment stops on the top surface of the gate structure. The gate structure is etched to form a trench. A metal layer is filled in the trench, and a metal plug is formed on the metal layer.

[0007] Optionally, the gate structure includes: a coupling oxide layer, a floating gate layer, an ONO structure and a control gate layer formed in sequence on the substrate.

[0008] Optionally, the interlayer dielectric layer is an oxide layer.

[0009] Optionally, the material of the interlayer dielectric layer is SiO2.

[0010] Optionally, the material of the metal layer is tungsten.

[0011] Optionally, the step of filling the metal layer in the trench includes: forming a metal layer on the trench and the interlayer dielectric layer; and performing CMP treatment on the metal layer, stopping on the interlayer dielectric layer.

[0012] Optionally, before forming the metal plug on the metal layer, the method further includes: removing the interlayer dielectric layer; and forming a cobalt silicide layer on the top surface of the peripheral resistance region.

[0013] Optionally, the step of forming a metal plug on the metal layer includes:

[0014] depositing an interlayer insulating layer on the metal layer and the cobalt silicide layer,

[0015] Disposing a metal insertion plug mask on the interlayer insulating layer;

[0016] Etching the interlayer insulating layer to form a metal plug hole;

[0017] Filling the metal insertion plug hole with metal;

[0018] The interlayer insulating layer is removed to form the metal plug.

[0019] On the other hand, the present invention also provides a flash memory device, comprising: a substrate, a gate structure and a peripheral resistance region formed on the substrate, the top surface of the gate structure being higher than the top surface of the peripheral resistance region; a metal layer formed on the gate structure and a cobalt silicide layer formed on the top surface of the peripheral resistance region; and a plurality of metal plugs formed on the metal layer and the cobalt silicide layer, respectively.

[0020] Optionally, the gate structure includes: a coupling oxide layer, a floating gate layer, an ONO structure and a control gate layer stacked in sequence from bottom to top; and the material of the metal layer is tungsten.

[0021] Compared with the prior art, the present invention has at least the following technical effects:

[0022] The present invention utilizes the height difference between the gate structure and the peripheral resistance area, uses the interlayer dielectric layer and the CMP planarization process to form a metal layer on the top layer of the gate structure. Through the arrangement of the metal layer (conductive layer), the metal layer is a good conductor and can reduce the gate resistance without affecting the area of ​​the flash memory device. The problem of excessive array gate resistance of the advanced process ETOX Flash is effectively solved.

[0023] The present invention enables the formation of the metal layer to no longer rely on the line width of the gate structure, that is, it is not limited by the line width of the gate structure. The existing conductive layer is Co-Salicide, while the conductive layer of the present invention uses a metal layer, and can be prepared from relatively cheap metal tungsten, further reducing the cost of the device.

[0024] The present invention does not need to introduce too many other complex circuits, which is beneficial to reducing the size of the flash memory device, that is, it is beneficial to reducing the chip area, thereby reducing the cost.

[0025] The present invention does not need to add an additional mask, further reducing the manufacturing cost of the device and improving the manufacturing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1a to Figure 1f A structural cross-sectional view of a manufacturing process of a flash memory device provided by an embodiment of the present invention;

[0027] Figure 2 A schematic flow chart of a method for manufacturing a flash memory device provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following is a further detailed description of the manufacturing method of the flash memory device and the flash memory device proposed in the present invention in combination with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structure, proportion, size, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any modification of the structure, change in the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0029] As described in the background art, as the size of cells (memory units) gradually decreases, the existing manufacturing process of flash memory devices still has the problem of being unable to effectively reduce the gate resistance.

[0030] Currently, ETOX flash on the market, such as those with cell sizes of 65nm / 55nm / 45nm, uses Si and Co to form Co-Salicide to achieve the purpose of reducing Gate resistance, which specifically refers to the resistance between CT (metal plug) and ArrayGate (control gate). That is, in the prior art, Co-Salicide is formed between the top surface of the control gate and the metal plug to reduce the Array Gate resistance.

[0031] It is understandable that Co-Salicide specifically refers to the process of using a metal called cobalt to form self-aligned silicide. In this process, cobalt reacts with silicon to form cobalt silicide (CoSi or CoSi2). This silicide can effectively reduce the contact resistance between the source and drain of the transistor, and can also reduce the resistance of the gate. This is very critical to improving the performance of integrated circuits. In short, the Co-Salicide process is a technology used to improve the performance of integrated circuits. It reduces resistance by forming a layer of cobalt silicide in key areas of the transistor, thereby improving overall electrical performance.

[0032] However, as the process size / cell size continues to shrink, the gate line width of processes below 45nm is too small, resulting in a small contact area, which is not conducive to the formation of Co-Salicide. Therefore, it is difficult to form a certain thickness of Co-Salicide to achieve the purpose of reducing the resistance between CT and Array Gate.

[0033] Furthermore, in order to solve the above problem, it is conceivable to use ion implantation to reduce the resistance between the CT and the array gate.

[0034] However, for traditional ETOX flash, 8 / 16 / 32 common gates are generally used to implement page control, so as to save the area of ​​the flash memory device.

[0035] It is understandable that the "page" type usually refers to the concept of "page". Page is one of the basic units of data storage in flash memory. In flash memory, data is read and programmed (written) in units of pages, while erase operations are usually performed in larger units, called "blocks".

[0036] The efficiency of reducing the resistance between CT and Gate by connecting multiple Gates together and using ion implantation is relatively poor.

[0037] Generally, the Co-Salicide method can reduce the Gate resistance to single digits, while the resistance formed by ion implantation is generally 10-20 times greater than that achieved by the Co-Salicide method. That is, the problem of reducing the resistance by ion implantation is that the efficiency is poor, and even if ion implantation is used, the resistance of the injected Gate resistor is much higher than that of the Co-Salicide method. It can be seen that the ion implantation method cannot effectively solve the problem of excessively high Gate resistance, and it will also increase losses, complicate the circuit, and affect the area of ​​the flash memory device.

[0038] In view of this, the present invention provides a method for manufacturing a flash memory device, which forms a metal layer on the top of the gate structure to reduce the gate resistance without affecting the area of ​​the flash memory device.

[0039] Combination Figure 1a to Figure 1f as well as Figure 2 As shown, this embodiment provides a method for manufacturing a flash memory device, including: step S101, providing a substrate 100, and forming a gate structure 200 and a peripheral resistance region 300 on the substrate 100. The top surface of the gate structure 200 is higher than the top surface of the peripheral resistance region 300.

[0040] Step S102 , forming an interlayer dielectric layer 400 on the substrate 100 , wherein the interlayer dielectric layer 400 covers the gate structure 200 and the peripheral resistance region 300 .

[0041] Step S103 , performing CMP (chemical mechanical polishing) on ​​the interlayer dielectric layer 400 , stopping on the top surface of the gate structure 200 .

[0042] Step S104 , etching the gate structure 200 to form a trench 401 .

[0043] Step S105 , filling the groove 401 with a metal layer 500 , and forming a metal insertion plug 700 on the metal layer 500 .

[0044] In this embodiment, by utilizing the height difference between the gate structure and the peripheral resistance area, using the interlayer dielectric layer and the CMP planarization process, a metal layer is formed on the top layer of the gate structure. By setting the metal layer (conductive layer), the metal layer is a good conductor and can reduce the gate resistance without affecting the area of ​​the flash memory device. This effectively solves the problem of excessive array gate resistance of the advanced process ETOX Flash.

[0045] In this embodiment, the formation of the metal layer is no longer dependent on the line width of the gate structure. The existing conductive layer is Co-Salicide, while the conductive layer of the present invention uses a metal layer, and can be made of relatively cheap metal tungsten, further reducing the device cost.

[0046] This embodiment does not need to introduce too many other complex circuits, which is beneficial to reducing the size of the flash memory device, that is, it is beneficial to reducing the chip area, thereby reducing costs.

[0047] This embodiment does not require the addition of an additional mask, thereby further reducing the manufacturing cost of the device and improving the manufacturing efficiency.

[0048] Please continue to refer to Figure 1a As shown, in this embodiment, the gate structure 200 includes: a coupling oxide layer (not shown), a floating gate layer (Floating Gate, FG) 201, an ONO structure 202 and a control gate layer (Control Gate, CG) 203 formed in sequence on the substrate 100.

[0049] In this embodiment or some other embodiments, the ONO structure 202 is formed by stacking an oxide layer, a silicon nitride layer, and an oxide layer from bottom to top.

[0050] It can be understood that, in this embodiment, the process of forming the gate structure 200 is the same as that in the prior art, and will not be described in detail herein.

[0051] Please continue to refer to Figure 1b As shown, in this embodiment, the interlayer dielectric layer 400 is an oxide layer.

[0052] Preferably, the material of the interlayer dielectric layer 400 is SiO 2 , which is cheap and helps to reduce the manufacturing cost.

[0053] Please continue to refer to Figure 1d As shown, in this embodiment, the control gate in the gate structure 200 is etched to form a trench 401. The depth of the trench 401 is relatively shallow, and the depth can be determined according to the value of the resistance to be reduced.

[0054] Please continue to refer to Figure 1e As shown, in this embodiment, the material of the metal layer is tungsten, which is a low-cost conductor, thereby further reducing the cost.

[0055] The step of filling the metal layer 500 in the trench 401 includes: forming a metal layer 500 on the trench 401 and the interlayer dielectric layer 400; and performing CMP treatment on the metal layer 500, stopping on the interlayer dielectric layer 400. Thus, the trench 500 can be filled.

[0056] Please continue to refer to Figure 1f As shown, in this embodiment, it can be understood that before forming the metal plug 700 on the metal layer 500, the process further includes: removing the interlayer dielectric layer 400; and forming a cobalt silicide layer (Co-Salicide) 600 on the top surface of the peripheral resistor region 300. The process of forming Co-Salicide is the same as that in the prior art, and will not be described in detail here.

[0057] Optionally, the step of forming the metal plug 700 on the metal layer 500 includes: depositing an interlayer insulating layer (not shown) on the metal layer 500 and the cobalt silicide layer 600, and setting a metal plug mask (not shown) on the interlayer insulating layer; etching the interlayer insulating layer to form a metal plug hole (not shown); filling the metal plug hole with metal; and removing the interlayer insulating layer to form the metal plug 700.

[0058] It can be understood that in this embodiment, the structures of the gate structure 200 and the peripheral resistance region 300, in addition to the structures mentioned in the text, also have various protective wall layers and other structures that are the same as those in the prior art and will not be described in detail herein.

[0059] On the other hand, the present invention also provides a flash memory device, comprising: a substrate 100, a gate structure 200 and a peripheral resistance region 300 formed on the substrate 100, wherein the top surface of the gate structure 200 is higher than the top surface of the peripheral resistance region 300; a metal layer 500 formed on the gate structure 200 and a cobalt silicide layer 600 formed on the top surface of the peripheral resistance region 300; and a plurality of metal plugs 700 formed on the metal layer 500 and the cobalt silicide layer 600, respectively.

[0060] In this embodiment, the gate structure 200 includes: a coupling oxide layer, a floating gate layer 201, an ONO structure 202 and a control gate layer 203 stacked in sequence from bottom to top; the material of the metal layer 500 is tungsten.

[0061] It can be seen that this structure is completely consistent with the traditional ETOX Flash architecture. It uses the height difference between the cell and the peripheral circuit and two CMP processes to achieve self-aligned metal layer filling, thereby effectively reducing the Gate resistance.

[0062] In summary, the present invention describes a highly cost-effective solution that is easy to implement in advanced ETOX flash, which can effectively solve the problem that the gate line width of advanced processes is too small and the Co-Salicide process cannot be used, without increasing the mask and increasing the production cost. It realizes the filling of self-aligned metal tungsten W to reduce the gate resistance of the cell, so that the chip area is further reduced and the cost is further reduced.

[0063] Furthermore, in the context of this document, unless otherwise indicated, the term "layer" encompasses both singular and plural forms. As used herein, layers in which semiconductor devices, components, or parts are formed or processed according to patterns formed in an overlying hard mask may also be collectively referred to as target layers. The target layer here may be a portion of the semiconductor substrate described above. The target layer may be formed of a metal, a semiconductor, and / or an insulator. In the target layer, a portion of an integrated circuit device, such as a memory or a microprocessor, may be formed. Although the "processing" through the hard mask is described as etching for a preferred embodiment to transfer the hard mask pattern into the target layer, it will be appreciated by those skilled in the art that processing in other embodiments may include, for example, oxidation, nitridation, selective deposition, doping, etc. through the hard mask.

[0064] As used herein, the term "trimming" refers to cleaning up the roughness of a layer or reducing the feature width of a layer in a lateral direction. The term may be used interchangeably with "shrinking."

[0065] In the above description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0066] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0067] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0068] Spatial relationship terms such as "under...", "below...", "below...", "below...", "above...", "above...", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then, the element or feature described as "under other elements" or "under it" or "under it" will be oriented to be "on" other elements or features. Therefore, the exemplary terms "under..." and "under..." may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms of "one", "an" and "said / the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0069] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for manufacturing a flash memory device, characterized in that: include: Providing a substrate, forming a gate structure and a peripheral resistance region on the substrate; The top surface of the gate structure is higher than the top surface of the peripheral resistance region; forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the gate structure and the peripheral resistance region; Performing CMP treatment on the interlayer dielectric layer, stopping on the top surface of the gate structure; Etching the gate structure to form a trench; Filling a metal layer in the groove; A metal plug is formed on the metal layer.

2. The method for manufacturing a flash memory device according to claim 1, wherein: The gate structure comprises: A coupling oxide layer, a floating gate layer, an ONO structure and a control gate layer are sequentially formed on the substrate.

3. The method for manufacturing a flash memory device according to claim 1, wherein: The interlayer dielectric layer is an oxide layer.

4. The method for manufacturing a flash memory device according to claim 1, wherein: The material of the interlayer dielectric layer is SiO2.

5. The method for manufacturing a flash memory device according to claim 1, wherein: The material of the metal layer is tungsten.

6. The method for manufacturing a flash memory device according to claim 1, wherein: The step of filling the metal layer in the groove comprises: forming a metal layer on the trench and the interlayer dielectric layer; The metal layer is subjected to CMP treatment, and the treatment stops on the interlayer dielectric layer.

7. The method for manufacturing a flash memory device according to claim 1, wherein: Before forming the metal plug on the metal layer, the method further includes: removing the interlayer dielectric layer; A cobalt silicide layer is formed on the top surface of the peripheral resistance region.

8. The method for manufacturing a flash memory device according to claim 1, wherein: The step of forming a metal plug on the metal layer comprises: depositing an interlayer insulating layer on the metal layer and the cobalt silicide layer, Disposing a metal insertion plug mask on the interlayer insulating layer; Etching the interlayer insulating layer to form a metal plug hole; Filling the metal insertion plug hole with metal; The interlayer insulating layer is removed to form the metal plug.

9. A flash memory device, characterized in that: include: A substrate, a gate structure and a peripheral resistance region formed on the substrate, wherein a top surface of the gate structure is higher than a top surface of the peripheral resistance region; a metal layer formed on the gate structure and a cobalt silicide layer formed on a top surface of the peripheral resistance region; A plurality of metal plugs are formed on the metal layer and the cobalt silicide layer respectively.

10. The flash memory device according to claim 9, wherein: The gate structure comprises: a coupling oxide layer, a floating gate layer, an ONO structure and a control gate layer stacked in sequence from bottom to top; the material of the metal layer is tungsten.

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