Memory and preparation method thereof

Abstract

The invention provides a memory and a preparation method thereof. The memory comprises a plurality of memory units, a plurality of first adhesion layers and address lines. Each storage unit comprises a top electrode, and the multiple storage units are arranged in rows at intervals in the first direction. The multiple first adhesion layers are connected with the multiple top electrodes in a one-to-one correspondence mode and cover the corresponding top electrodes. The address lines are located on the sides, away from the storage units, of the first adhesion layers, and the address lines extend in the first direction and are connected with one row of the first adhesion layers. The first adhesion layers cover the top electrodes, and the plurality of first adhesion layers are connected with the plurality of top electrodes in a one-to-one correspondence manner, so that the first adhesion layers not only can increase the adhesiveness between the address lines and the top electrodes, but also can reduce the loss of the top electrodes in the preparation process, thereby improving the thickness uniformity of the top electrodes.

Description

Technical Field

[0001] The present application generally relates to the field of semiconductors, and more particularly, to a memory and a method for manufacturing the same. Background Art

[0002] Semiconductor memory is the foundation of information technology. As a candidate for the next generation of non-volatile semiconductor memory, Phase Change Random Access Memory (PCRAM) has received widespread attention due to its advantages such as high-speed reading, high erasable times, non-volatility, small component size, low power consumption, and resistance to strong vibration and radiation.

[0003] In the current three-dimensional phase change memory process, the top electrode is easily lost during the preparation process, which affects its uniformity. Summary of the invention

[0004] The purpose of the present application is to provide a memory and a method for preparing the same, aiming to improve the thickness uniformity of the top electrode.

[0005] In a first aspect, the present application provides a memory, comprising:

[0006] A plurality of memory cells are arranged in rows along a first direction, each memory cell comprising a top electrode;

[0007] A plurality of first adhesion layers corresponding to the plurality of top electrodes one by one and covering the corresponding top electrodes;

[0008] The address line is located at a side of the first adhesive layer away from the storage unit. The address line extends along the first direction and connects a row of the first adhesive layer.

[0009] In some embodiments, the method further includes: a second adhesive layer located between the address line and the first adhesive layer, wherein the second adhesive layer extends along the first direction and connects a row of the first adhesive layers.

[0010] In some embodiments, the second adhesive layer comprises the same material as the first adhesive layer.

[0011] In some embodiments, the plurality of second adhesive layers are connected to the plurality of address lines in a one-to-one correspondence.

[0012] In some embodiments, the orthographic projection of the first adhesive layer on the address line is within the range of the orthographic projection of the second adhesive layer on the address line.

[0013] In some embodiments, the sum of the thickness of the first adhesion layer and the second adhesion layer is 4.5 nm to 5.5 nm.

[0014] In some embodiments, a material of the first adhesion layer includes at least one of tungsten silicon nitride, titanium silicon nitride, titanium nitride, or tungsten nitride.

[0015] In a second aspect, the present application provides a method for preparing a memory, comprising:

[0016] forming a storage stack including a top electrode, a first initial adhesion layer covering the top electrode, and a patterned mask layer located on the first initial adhesion layer;

[0017] removing the patterned mask layer;

[0018] An address line is formed on a side of the first initial adhesion layer away from the memory stack.

[0019] In some embodiments, the step of removing the patterned mask layer includes: removing the patterned mask layer using a chemical mechanical polishing process;

[0020] In the chemical mechanical polishing process, a polishing rate of the first initial adhesion layer is lower than a polishing rate of the patterned mask layer.

[0021] In some embodiments, it also includes:

[0022] Before forming the address line, a second initial adhesion layer is formed on a side of the first initial adhesion layer away from the memory stack.

[0023] The present application provides a memory and a preparation method thereof, wherein the memory comprises a plurality of memory cells, a plurality of first adhesion layers and an address line. The memory cell comprises a top electrode, and the plurality of memory cells are arranged in a row along a first direction. The plurality of first adhesion layers are connected to the plurality of top electrodes one by one and cover the corresponding top electrodes. The address line is located on a side of the first adhesion layer away from the memory cell, and the address line extends along the first direction and connects a row of the first adhesion layers. Since the first adhesion layer covers the top electrode, and the plurality of first adhesion layers are connected to the plurality of top electrodes one by one, the first adhesion layer can not only increase the adhesion between the address line and the top electrode, but also reduce the loss of the top electrode during the preparation process, thereby improving the thickness uniformity of the top electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0025] Figure 1 is a schematic diagram of a three-dimensional structure of a memory provided in some embodiments of the present application;

[0026] Figure 2 yes Figure 1A schematic diagram of the cross-sectional structure of the memory in the YZ direction is shown;

[0027] Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the memory in the XZ direction is shown;

[0028] Figure 4 is a schematic flow chart of a method for preparing a memory provided in some embodiments of the present application;

[0029] Figures 5 to 10 is a schematic diagram of the structure of the memory provided in some embodiments of the present application during the preparation process;

[0030] Fig.11 It is a schematic diagram of the structure of the storage system provided in some embodiments of the present application. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0032] It should be understood that although the terms first, second, etc. may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the present application.

[0033] It should be understood that when a component is said to be "on" or "connected" another component, it can be directly on or connected to another component, or there may be an intervening component. Other words used to describe the relationship between components should be interpreted in a similar manner.

[0034] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness that is less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, an interconnect layer may include one or more second conductive layers and a contact layer and one or more dielectric layers.

[0035] It should be noted that the illustrations provided in the embodiments of the present application are only used to illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.

[0036] This article uses Cartesian coordinates to represent directions, where "X" represents the first direction, "Y" represents the second direction, and "Z" represents the third direction. The first direction, the second direction, and the third direction intersect with each other, that is, X, Y, and Z intersect with each other, for example, they may be perpendicular to each other, or at a certain angle.

[0037] Memories may include magnetic hard disks, random access memories (RAM), read-only memories (ROM), dynamic random access memories (DRAM), synchronous dynamic random access memories (SDRAM), ferroelectric RAM (FeRAM), magnetic random access memories (MRAM), resistive random access memories (RRAM), flash memories, phase change memories (PCM), selector only memories (SOM), and others. Memories may be volatile or non-volatile. Non-volatile memory cells can maintain their stored logic states for long periods of time in the absence of an external power source. Volatile memory cells lose their stored states over time when power is lost, and usually need to be periodically refreshed by an external power source.

[0038] For ease of understanding, the memory in the embodiments of the present application is described by taking a phase change memory and a selector-only memory as examples.

[0039] See also Figure 1 to Figure 3 , Figure 1 is a schematic diagram of a three-dimensional structure of a memory provided in some embodiments of the present application, Figure 2 yes Figure 1 The schematic diagram of the cross-sectional structure of the memory in the YZ direction is shown. Figure 3 yes Figure 1 The cross-sectional structure diagram of the memory in the XZ direction is shown.

[0040] The memory 100 includes: a plurality of memory cells 10, a plurality of first adhesive layers 20 and an address line 30. The memory cells 10 include top electrodes 11, and the plurality of memory cells 10 are arranged in rows along a first direction X; the plurality of first adhesive layers 20 are connected to the plurality of top electrodes 11 one by one and cover the corresponding top electrodes 11; the address line 30 is located on a side of the first adhesive layer 20 away from the memory cells 10, and the address line 30 extends along the first direction X and connects a row of the first adhesive layers 20.

[0041] Since the first adhesion layer 20 covers the top electrode 11, and multiple first adhesion layers 20 are connected to multiple top electrodes 11 one by one, the first adhesion layer 20 can not only increase the adhesion between the address line 30 and the top electrode 11, but also reduce the loss of the top electrode 11 during the preparation process, thereby improving the thickness uniformity of the top electrode 11.

[0042] The following is a detailed description with reference to the accompanying drawings.

[0043] Since the multiple first adhesion layers 20 cover the upper surfaces of the multiple top electrodes 11 one by one, the top electrode 11 can be protected by the first adhesion layer 20 during the preparation process (such as including etching process and chemical mechanical polishing process), so the thickness uniformity of the top electrode 11 can be improved, which is beneficial to its subsequent etching process and improves its electrical performance (for example, reducing leakage of the address line 30, increasing the read and write window, etc.).

[0044] Under the protection of the first adhesion layer 20, the thickness difference of the top electrode 11 between different wafers (or memory 100) can be controlled within 1.5nm, thereby reducing the electrical impact on the memory 100. Under the protection of the first adhesion layer 20, the thickness difference of the top electrode 11 between different memory blocks in a wafer can be controlled within 1nm, thereby reducing the impact on the subsequent etching process of the wafer. In some embodiments, the thickness of the top electrode 11 in the memory 100 is 13nm to 14nm, for example, 13.5nm.

[0045] The plurality of memory cells 10 may be arranged in rows along the first direction X and in columns along the second direction Y, i.e., they are distributed in an array along the first direction X and the second direction Y. Since the first adhesive layer 20 is connected to the memory cells 10 in a one-to-one correspondence, the first adhesive layer 20 is also distributed in an array along the first direction X and the second direction Y, and the plurality of first adhesive layers 20 arranged along the first direction X is called a row. In some embodiments, the orthographic projection of the first adhesive layer 20 on the address line 30 is located within the range of the address line 30, i.e., the upper surface of the first adhesive layer 20 is in contact with the address line 30.

[0046] The memory 100 may include at least one of a phase change memory and a select only memory.

[0047] In some embodiments, the memory 100 is a select-only memory, and each memory cell 10 may include a bottom electrode, a top electrode 11 , and a gate layer located between the bottom electrode and the top electrode 11 .

[0048] In some embodiments, Figure 2 As shown, the memory 100 is a phase change memory, and each memory cell 10 may include a bottom electrode 12, a middle electrode 13, a top electrode 11, a selection layer 14 located between the bottom electrode 12 and the middle electrode 13, and a phase change layer 15 located between the middle electrode 13 and the top electrode 11.

[0049] The memory 100 may further include another address line 40, one of the two address lines being a bit line and the other being a word line. For example, the word line is connected to the top electrode 11, and the bit line is connected to the bottom electrode 12. The word line and the bit line may be skewed and perpendicular, and a plurality of memory cells 10 are connected between the word line and the bit line and are located at the intersection of the word line and the bit line.

[0050] Each of the top electrode 11, the middle electrode 13 and the bottom electrode 12 may include amorphous carbon or other conductive materials. The gating layer 14 may include ZnxTey, GexTey, NbxOy, SixAsy, AsxTey, etc. The phase change layer 15 may include materials such as chalcogenide-based materials, which contain any of the four elements of Group VIA, oxygen (O), sulfur (S), selenium (Se) and tellurium (Te). The phase change layer 15 is, for example, a compound of a chalcogenide element and a more electropositive element or free radical, a combination of a chalcogenide and other materials (such as a transition metal), and a chalcogenide alloy.

[0051] In some embodiments, the material of the first adhesion layer 20 includes at least one of tungsten silicon nitride (WSiN), titanium silicon nitride (TiSiN), titanium nitride (TiN) or tungsten nitride (WN). The first adhesion layer 20 may also be made of other metal nitrides.

[0052] The first adhesive layer 20 can reduce the separation of the address line 30 and the film layer below it, and the resistance of the first adhesive layer 20 will be reduced when the memory cell 10 is selected, and the resistance is relatively high when it is not selected, so that the leakage current can be reduced.

[0053] In some embodiments, the memory cell 10 may further include a first buffer layer 151 and a second buffer layer 152, wherein the first buffer layer 151 is located between the intermediate electrode 13 and the phase change layer 15, and the second buffer layer 152 is located between the phase change layer 15 and the top electrode 11, and the first buffer layer 151 and the second buffer layer 152 may improve the heating uniformity of the phase change layer 15. Exemplary materials of the first buffer layer 151 and the second buffer layer 152 are tungsten.

[0054] The memory 100 may further include a dielectric layer 50 located between adjacent memory cells 10 , and the dielectric layer 50 may include a spin on dielectric (SOD) layer.

[0055] In some embodiments, the memory 100 further includes a second adhesive layer 60 located between the address line 30 and the first adhesive layer 20, and the second adhesive layer 60 extends along the first direction X and connects a row of the first adhesive layer 20. Therefore, the second adhesive layer 60 and the address line 30 both extend along the first direction X and both connect a row of the first adhesive layer 20, so the second adhesive layer 60 can increase the adhesion of the address line 30 to the underlying film layer.

[0056] Exemplarily, the plurality of second adhesive layers 60 are connected to the plurality of address lines 30 in a one-to-one correspondence. Specifically, the second adhesive layer 60 may be arranged to overlap with the address lines 30.

[0057] like Figure 3 As shown, the second adhesive layer 60 is not only bonded between the address line 30 and the first adhesive layer 20, but also bonded between the address line 30 and the dielectric layer 50, thereby increasing the adhesion area of ​​the address line 30 and further reducing the separation of the address line 30 from the underlying film layer.

[0058] In some embodiments, the second adhesion layer 60 and the first adhesion layer 20 include the same material, that is, the second adhesion layer 60 also includes at least one of tungsten silicon nitride (WSiN), titanium silicon nitride (TiSiN), titanium nitride (TiN) or tungsten nitride (WN), so that the second adhesion layer 60 can be better combined with the first adhesion layer 20. Since the material characteristics of the first adhesion layer 20 and the second adhesion layer 60 are similar to those of the address line 30 (tungsten), the etching process for forming the address line 30 and the adhesion layer is also more friendly.

[0059] In some embodiments, the orthographic projection of the first adhesive layer 20 on the address line 30 is within the range of the orthographic projection of the second adhesive layer 60 on the address line 30, thereby maximizing the contact area between the two and increasing the bonding force.

[0060] In some embodiments, the sum of the thickness of the first adhesion layer 20 and the second adhesion layer 60 is 4.5nm to 5.5nm, for example, 5nm. This thickness range enables the total thickness of the adhesion layer (including the first adhesion layer 20 and the second adhesion layer 60) in the memory 100 to meet the requirements of adhesion and electrical properties at the same time. In addition, even if the first adhesion layer 20 is lost as a sacrificial layer in the process of protecting the top electrode 11, the thickness of the second adhesion layer 60 can be adjusted in time so that the thickness of the entire adhesion layer meets the requirements. In addition, the thickness of the address line 30 can be 49nm to 59nm, which is much larger than the total thickness of the adhesion layer, so the thickness uniformity of the adhesion layer has little effect on the thickness uniformity of the address line 30.

[0061] It can be understood that “thickness” refers to the dimension of the film layer along the third direction Z. For example, the third direction Z may be perpendicular to the first direction X and the second direction Y.

[0062] like Figure 2 As shown, the memory 100 may further include a third adhesive layer 70 located between the gate layer 14 and the bit line, and the third adhesive layer 70 extends along the second direction Y. The second adhesive layer 60 may reduce the separation of the bit line from the upper film layer.

[0063] The memory 100 may further include a sidewall protection layer 80 located on the sidewall of the memory cell 10, and the sidewall protection layer 80 may protect the memory cell 10 from damage or oxidation during the preparation process of the memory 100. Since the first adhesion layer 20 may be formed together with the memory cell 10 to protect the top electrode 11, the sidewall protection layer 80 is also located on the sidewall of the first adhesion layer 20. Since the second adhesion layer 60 may be formed together with the address line 30, the second adhesion layer 60 may cover the end of the sidewall protection layer 80.

[0064] In the memory 100 provided in the embodiment of the present application, multiple first adhesion layers 20 cover the upper surfaces of multiple top electrodes 11 one by one, so the first adhesion layer 20 can be prepared together with the top electrode 11, so the top electrode 11 can be protected by the first adhesion layer 20 during the entire preparation process of the memory 100, thereby improving the thickness uniformity of the top electrode 11.

[0065] See also Figure 4 , Figure 4 1 is a flow chart of a method for preparing a memory provided in some embodiments of the present application, comprising:

[0066] Step S1: forming a storage stack including a top electrode, a first initial adhesion layer covering the top electrode, and a patterned mask layer located on the first initial adhesion layer;

[0067] Step S2: removing the patterned mask layer;

[0068] Step S3: forming an address line on a side of the first initial adhesion layer away from the memory stack.

[0069] In the preparation method of the memory, since the first initial adhesion layer covering the top electrode is added before removing the patterned mask layer, the loss of the top electrode during the removal process can be reduced, thereby improving the thickness uniformity of the top electrode. In addition, after removing the patterned mask layer, the address line is formed, and the first initial adhesion layer serves as an adhesion layer between the top electrode and the address line, thereby reducing the separation of the address line and the top electrode.

[0070] Please also see Figures 5 to 10 , Figures 5 to 10 is a schematic diagram of the structure of the memory provided in some embodiments of the present application during the preparation process. The preparation method of the memory can be used to prepare the memory 100 in the above embodiment, so it can be combined with reference to Figure 1 to Figure 3 The method for preparing the memory includes the following steps S1 to S3.

[0071] Step S1: forming a storage stack 10a including a top electrode 11, a first initial adhesion layer 20a covering the top electrode 11, and a patterned mask layer 90a located on the first initial adhesion layer 20a. Figure 5 to Figure 7 .

[0072] like Figure 5 As shown, a substrate 101 is provided, and an initial storage stack 10b is formed on the substrate 101. For example, a bottom electrode 12, a gating layer 14, an intermediate electrode 13, a phase change layer 15 and a top electrode 11 are stacked in sequence on the substrate 101; a first adhesion material layer 20b and a mask layer 90b (for example, silicon nitride) are formed in sequence on the initial storage stack 10b.

[0073] Can be formed by deposition process Figure 5 For each film layer in the film, the deposition process includes but is not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), atomic layer deposition (Atom Layer Deposition, ALD), physical vapor deposition (Physical Vapor Deposition, PVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), any other suitable deposition process or any combination thereof.

[0074] It should be understood that the position order of the gate layer 14 and the phase change layer 15 can be exchanged, and the storage stack 10a composed of different materials can be formed according to the type of the memory 100, and the present application is not limited to this. For example, the storage stack 10a can only include the bottom electrode 12, the gate layer 14, and the middle electrode 13.

[0075] The substrate 101 may be a semiconductor substrate, for example, silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI) or germanium on insulator (GOI). The materials of the bottom electrode 12, the middle electrode 13 and the top electrode 11 may be the same, and may include carbon; the material of the gate layer 14 may include Zn x Te y ,Ge x Te y , Nb x O y 、Si x As y 、As x Te y The material of the phase change layer 15 may include, for example, a chalcogenide-based material including any one of four elements of Group VIA, oxygen (O), sulfur (S), selenium (Se), and tellurium (Te).

[0076] like Figure 6 As shown, the mask layer 90b, the first adhesion material layer 20b and the initial storage stack 10b are etched (eg, dry etched) to form a self-aligned patterned mask layer 90a, a first initial adhesion layer 20a and a storage stack 10a.

[0077] Before forming the initial memory stack 10b, the memory manufacturing method may further include: Figure 5 As shown, a metal layer 40a (eg, tungsten) and a third initial adhesion layer 70a (eg, tungsten silicon nitride) are formed on the substrate 101; Figure 6 As shown, during the process of etching the initial memory stack 10 b , the metal layer 40 a is etched together to form another address line 40 and a third adhesive layer 70 .

[0078] The preparation method of the memory may further include: 1) Figure 6 As shown, a sidewall protection layer 80 may also be formed on the sidewall of the storage stack 10a; 2) as shown in FIG. Figure 7 As shown, an insulating layer (eg, insulating material such as silicon oxide) is formed on the periphery of the memory stack 10a to separate different memory blocks, and a dielectric layer 50, such as a spin-on dielectric layer (Spin On Dielectric, SOD), is formed between and above the memory cells 10.

[0079] Step S2: removing the patterned mask layer 90a. For details, please refer to Figure 8-Figure 9 .

[0080] Specific examples, such as Figure 8 As shown, a chemical mechanical polishing (CMP) process may be first used to pattern the portion of the dielectric layer 50 above the mask layer 90a. Fig. 9 As shown, another chemical mechanical polishing process is used to remove the patterned mask layer 90a. In this chemical mechanical polishing process, the polishing rate of the first initial adhesion layer 20a is lower than the polishing rate of the patterned mask layer 90a, so that the first initial adhesion layer 20a can be used as a CMP stop layer to better protect the top electrode 11 from being affected by the CMP.

[0081] In some embodiments, the selectivity of the patterned mask layer 90a to the first initial adhesion layer 20a is greater than 150, which can reduce the loss of the first initial adhesion layer 20a as a sacrificial layer or a stop layer of the CMP process. Since a portion of the first initial adhesion layer 20a can be sacrificed as a sacrificial layer, the CMP process has a relatively low requirement for the selectivity. In other words, compared to the case where there is no first initial adhesion layer 20a, in order to protect the top electrode 11 from loss as much as possible, a larger selectivity of the patterned mask layer 90a to the top electrode 11 is required in the CMP process. Therefore, the selectivity of the patterned mask layer 90a to the first initial adhesion layer 20a in the embodiment of the present application can be less than the selectivity of the patterned mask layer 90a to the top electrode 11, and the requirement for the selectivity is lower.

[0082] Step S3: forming an address line 30 on the side of the first initial adhesion layer 20a away from the storage stack 10a. Figure 3 and Fig.10 , Fig.10 yes Figure 3 Schematic diagram of the cross-sectional structure of the memory in the YZ direction.

[0083] The method for manufacturing the memory may further include: before forming the address line 30, forming a second initial adhesion layer 60a on a side of the first initial adhesion layer 20a away from the memory stack 10a, wherein the second initial adhesion layer 60a may increase the adhesion between the address line 30 and the memory stack 10a. In addition, if the first initial adhesion layer 20a is damaged during the CMP process of the patterned mask layer 90a, adding the second initial adhesion layer 60a may improve the thickness uniformity of the entire adhesion layer, thereby also improving the thickness uniformity of the address line 30.

[0084] The step of forming the address line 30 and the second adhesive layer 60 may include: 1) depositing a conductive layer 30a on a side of the second initial adhesive layer 60a away from the memory stack 10a; 2) etching the conductive layer 30a, the second initial adhesive layer 60a, the first initial adhesive layer 20a and the memory stack 10a to form the address line 30 and the second adhesive layer 60 extending along the first direction X, and a plurality of first adhesive layers 20 and a plurality of memory cells 10 connected to the plurality of first adhesive layers 20 in a one-to-one correspondence (see Figure 2 This etching process etches the memory stack 10a extending along the second direction Y into a plurality of memory cells 10, etches the conductive layer 30a into a plurality of address lines 30, and etches the second initial adhesion layer 60a into a plurality of second adhesion layers 60, but the etching gases corresponding to each film layer may be different.

[0085] Among them, the address line 30, the second adhesion layer 60, the first adhesion layer 20 and the storage unit 10 are self-aligned and etched, the first adhesion layer 20 and the storage unit 10 (or the top electrode 11) are deposited together and formed together through two etching processes, and the second adhesion layer 60 and the address line 30 are deposited and etched together.

[0086] The preparation method of the memory may also include: Figure 2 As shown, a first buffer layer 151 is formed between the intermediate electrode 13 and the phase change layer 15 ; and a second buffer layer 152 is formed between the phase change layer 15 and the top electrode 11 .

[0087] The method for preparing the memory may further include: Figure 2 On the basis of the above, a sidewall protection layer is formed on the sidewall of the memory cell.

[0088] The method for preparing a memory provided in an embodiment of the present application includes the above steps S1 to S3 . The first adhesion layer 20 and the top electrode 11 are formed by sequential deposition and sequential etching, so the top electrode 11 can be protected from damage, thereby improving the performance of the memory 100 .

[0089] See also Fig.11 , Fig.11 1 is a schematic diagram of a storage system provided in some embodiments of the present application. The storage system may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, an augmented reality (AR), a virtual reality (VR) device, or any other suitable electronic device having a storage device. Fig.11As shown in , the storage system 200 may include a host 210 and a memory system 220, the memory system 220 having one or more memories 221 and a controller 222, the memory 221 may be the memory in any of the above embodiments. The host 210 may be a processor of an electronic device (e.g., a central processing unit or a system on a chip (e.g., an application processor). The host 210 may be configured to send data to the memory 221 or obtain data from the memory 221.

[0090] In some embodiments, the controller 222 is coupled to the memory 221 and the host 210, and is configured to control the memory 221. The controller 222 can manage data stored in the memory 221 and communicate with the host 210. In some embodiments, the controller 222 is designed to operate in a low duty cycle environment, such as a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 222 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded Multi Media Card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0091] The controller 222 may be configured to control the operation of the memory 221, such as read, erase, and program operations. The controller 222 may also be configured to manage various functions regarding data stored or to be stored in the memory 221, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 222 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 221. The controller 222 may also perform any other suitable functions, such as formatting the memory 221. The controller 222 may communicate with an external device (e.g., the host 210) according to a specific communication protocol. For example, the controller 222 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0092] Each memory 221 may include a memory cell array 2211 and a peripheral circuit 2212 , which may be integrated on the same or different dies, allowing a wider bus and a higher operating speed.

[0093] The peripheral circuit 2212 may include any suitable digital, analog and / or mixed signal circuits for facilitating the operation of the memory device. For example, the peripheral circuit may include control logic, data buffers, decoders (decoders may also be referred to as decoders), drivers, and read / write circuits. When the control logic receives a read / write operation command and address data, under the action of the control logic, the decoder may apply the corresponding voltage generated by the driver to the corresponding word line (Word Line, WL) and bit line (Bit Line, BL) based on the decoded address to implement a data read operation or write operation, and perform data interaction with the outside through the data buffer. Exemplarily, after receiving the read operation or write operation command and address data, the control logic may determine the selected word line and the selected bit line corresponding to the selected memory cell in a plurality of memory cells under the action of the decoder. Exemplarily, the memory cell may be controlled by a row decoder and a column decoder. Specifically: the row decoder may receive a row address from the memory controller and activate the appropriate word line based on the received row address. The column decoder may receive a column address from the memory controller and activate the appropriate bit line, and may activate the memory cell at the intersection of the word line and the bit line.

[0094] The memory cell array 2211 may include at least one memory block, each memory block may include a plurality of memory cell layers stacked along the Z-axis direction, and each memory cell layer may include a plurality of memory cells. It should be understood that a memory cell may be located at the intersection of two address lines, and this intersection may be referred to as the address of the memory cell; other memory cells connected to the common conductor may be referred to as unselected memory cells.

[0095] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A memory, characterized in that: include: A plurality of memory cells are arranged in rows along a first direction, each memory cell comprising a top electrode; A plurality of first adhesion layers corresponding to the plurality of top electrodes one by one and covering the corresponding top electrodes; The address line is located at a side of the first adhesive layer away from the storage unit. The address line extends along the first direction and connects a row of the first adhesive layer.

2. The memory according to claim 1, characterized in that: Also includes: A second adhesive layer is located between the address line and the first adhesive layer, and the second adhesive layer extends along the first direction and connects a row of the first adhesive layers.

3. The memory according to claim 2, characterized in that: The second adhesive layer comprises the same material as the first adhesive layer.

4. The memory according to claim 2, characterized in that: The plurality of second adhesive layers are connected to the plurality of address lines in a one-to-one correspondence.

5. The memory according to claim 2, characterized in that: The orthographic projection of the first adhesive layer on the address line is located within the range of the orthographic projection of the second adhesive layer on the address line.

6. The memory according to claim 2, characterized in that: The sum of the thickness of the first adhesion layer and the second adhesion layer is 4.5 nm to 5.5 nm.

7. The memory according to claim 1, characterized in that: The material of the first adhesion layer includes at least one of tungsten silicon nitride, titanium silicon nitride, titanium nitride or tungsten nitride.

8. A method for preparing a memory, characterized in that: include: forming a storage stack including a top electrode, a first initial adhesion layer covering the top electrode, and a patterned mask layer located on the first initial adhesion layer; removing the patterned mask layer; An address line is formed on a side of the first initial adhesion layer away from the memory stack.

9. The method for preparing a memory according to claim 8, characterized in that: The step of removing the patterned mask layer comprises: removing the patterned mask layer by a chemical mechanical polishing process; In the chemical mechanical polishing process, a polishing rate of the first initial adhesion layer is lower than a polishing rate of the patterned mask layer.

10. The method for preparing a memory according to claim 8, characterized in that: Also includes: Before forming the address line, a second initial adhesion layer is formed on a side of the first initial adhesion layer away from the memory stack.

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