Manufacturing method of split-gate trench Schottky contact super barrier rectifier and device structure of split-gate trench Schottky contact super barrier rectifier

Abstract

The invention discloses a manufacturing method of a split gate trench Schottky contact super barrier rectifier and a device structure thereof. The method mainly comprises the following steps: covering a mask layer on the surface of a polycrystalline silicon covering layer; forming a through groove in the mask layer; etching the polycrystalline silicon covering layer and the gate dielectric thin layer below the mask layer through groove; deep injection of second conductive type impurities is carried out, so that the second conductive type impurities are injected into the lightly doped first conductive type drift region through the formed through groove part and are blocked at the part covering the mask layer; the device structure comprises a lower electrode layer, a heavily doped first conductive type substrate layer, a lightly doped first conductive type drift layer, a trench gate dielectric layer, a polycrystalline silicon filling layer, a gate dielectric thin layer, a polycrystalline silicon covering layer, a second conductive type body region and an upper electrode layer. Under the condition that the good forward characteristic of the Schottky contact super-barrier rectifier is maintained, the barrier capacitance of the device is reduced, and the device has better reverse recovery performance.

Description

Technical Field

[0001] The invention relates to the technical field of power semiconductor devices, in particular to a manufacturing method of a split-gate trench Schottky contact super-barrier rectifier and a device structure thereof. Background Art

[0002] Medium and low voltage power semiconductor diodes are widely used in power supplies and power converters. Schottky barrier diodes (SBDs) have the characteristics of low forward voltage and fast reverse recovery, and are usually used as rectifier devices. However, their specific on-resistance and forward voltage will increase sharply with the increase of breakdown voltage. Similar to the concept of PN junction pinching off the electric field in junction barrier Schottky (JBS), such as Figure 1 As shown in Figure 1, the trench MOS barrier Schottky diode (TMBS) uses a deep MOS trench to pinch off the electric field. This not only reduces the electric field on the mesa surface, but also changes the electric field distribution in the drift layer, reducing the lateral depletion caused by the PN junction in the JBS. Therefore, it has lower reverse leakage current, higher breakdown voltage, and smaller forward voltage. However, TMBS still faces the image force barrier reduction effect and reliability issues caused by direct Schottky contact. In addition, the junction capacitance of TMBS is still large.

[0003] Schottky contact super barrier rectifier (SSBR) has been proven to have simple manufacturing process, low forward voltage, low reverse leakage current and excellent high temperature reliability. However, the breakdown voltage of existing SSBR is only tens of volts. And because SSBR is a majority carrier device, increasing the breakdown voltage will cause its forward conduction characteristics to deteriorate rapidly. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a split-gate trench Schottky contact super-barrier rectifier, comprising the following steps:

[0005] 1) Covering a lightly doped first conductivity type drift region on a heavily doped first conductivity type substrate.

[0006] 2) Forming a trench on the lightly doped first conductivity type drift region.

[0007] 3) Covering the trench formed in step 2) with a dielectric layer to form a U-shaped trench gate dielectric layer.

[0008] 4) depositing polysilicon, heavily doping the polysilicon, and then performing reverse etching to remove excess polysilicon outside the U-shaped trench gate dielectric layer formed in step 4) to form a polysilicon filling layer.

[0009] 5) Performing thermal oxidation growth on the surface of the super-barrier rectifier sample formed in step 4) to form a gate dielectric thin layer, and then forming a polysilicon capping layer on the gate dielectric thin layer by deposition. The polysilicon capping layer is heavily doped.

[0010] 6) Covering the surface of the polysilicon cover layer with a mask layer II, forming a through groove in the mask layer II, and etching the polysilicon cover layer and the gate dielectric thin layer below the through groove in the mask layer II.

[0011] 7) Perform deep implantation of second conductivity type impurities, so that the second conductivity type impurities are implanted into the lightly doped first conductivity type drift region through the through groove formed in step 7, and are blocked by the covering mask layer. Remove the mask layer.

[0012] 8) Forming a second conductivity type body region.

[0013] 9) Depositing a metal layer to form an upper electrode layer, and making the upper electrode layer form a Schottky contact with the second conductive type body region, and the upper electrode layer form an ohmic contact with the polysilicon cover layer.

[0014] 10) Depositing a lower electrode layer on the lower surface of the heavily doped first conductive type substrate and forming an ohmic contact.

[0015] Furthermore, the process of covering the lightly doped first conductivity type drift region includes epitaxial growth.

[0016] Further, the step of forming a trench on the lightly doped first conductivity type drift region includes:

[0017] 1) Covering the lightly doped first conductivity type drift region with a mask layer I.

[0018] 2) Forming a through groove in the mask layer.

[0019] 3) Etching the lightly doped first conductivity type drift region below the through groove of the mask layer, so that a trench is formed on the lightly doped first conductivity type drift region.

[0020] 4) The mask layer I is removed.

[0021] Furthermore, the polysilicon filling layer is located in the U-shaped trench gate dielectric layer.

[0022] Further, the method of forming the second conductivity type body region includes rapid thermal processing.

[0023] Furthermore, the second conductive type body region is not connected to the U-shaped trench gate dielectric layer. The second conductive type body region and the U-shaped trench gate dielectric layer are spaced apart.

[0024] The split-gate trench Schottky contact super-barrier rectifier formed based on the manufacturing method comprises a lower electrode layer, a heavily doped first conductive type substrate layer, a lightly doped first conductive type drift layer, a U-shaped trench gate dielectric layer, a polysilicon filling layer, a gate dielectric thin layer, a polysilicon capping layer, a second conductive type body region and an upper electrode layer.

[0025] The heavily doped first conductive type substrate layer covers the lower electrode layer. The lightly doped first conductive type drift layer covers the heavily doped first conductive type substrate layer.

[0026] The trench gate dielectric layer is a U-shaped groove, covering a portion of the surface of the lightly doped first conductivity type drift layer. The polysilicon filling layer is filled in the trench gate dielectric layer.

[0027] The gate dielectric thin layer completely covers the polysilicon filling layer and the trench gate dielectric layer, and covers a portion of the surface of the lightly doped first conductivity type drift layer.

[0028] The gate dielectric thin layer also covers a portion of the surface of the second conductive type body region.

[0029] The polysilicon capping layer covers the gate dielectric thin layer.

[0030] The second conductive type body region covers a portion of the surface of the lightly doped first conductive type drift layer.

[0031] The second conductive type body region is not connected to the U-shaped trench gate dielectric layer.

[0032] The second conductive type body region is spaced apart from the U-shaped trench gate dielectric layer.

[0033] The upper electrode layer covers the polysilicon cover layer and covers a portion of the surface of the second conductive type body region.

[0034] An ohmic contact is formed between the upper electrode layer and the polysilicon cover layer, and a Schottky contact is formed between the upper electrode layer and the second conductive type body region.

[0035] Furthermore, the lightly doped first conductivity type drift layer, the gate dielectric thin layer, the polysilicon capping layer, the second conductivity type body region, and the upper electrode layer together form a Schottky contact super-barrier rectifier structure.

[0036] Furthermore, the trench gate dielectric layer, the polysilicon filling layer, the gate dielectric thin layer, and the polysilicon covering layer together form a split gate trench structure.

[0037] Furthermore, the gate dielectric thin layer is used as a gate dielectric material in a Schottky contact super-barrier rectifier structure.

[0038] The gate dielectric thin layer is used as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer from the polysilicon covering layer so that the polysilicon filling layer and the polysilicon covering layer are not in contact.

[0039] The technical effect of the present invention is unquestionable. The present invention introduces a newly added split gate structure by growing a thin layer of gate dielectric. While maintaining the good forward characteristics of SSBR, the barrier capacitance of the device is reduced, and it has better reverse recovery performance. At the same time, the thin layer of gate dielectric makes it unnecessary to contact the narrow polysilicon in the groove with the anode metal during the manufacturing process of the device, which reduces the minimum line width requirement and effectively reduces the process complexity and difficulty. The split gate will not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a schematic diagram of an existing trench gate MOS Schottky barrier rectifier;

[0041] Figure 2-Figure 7 is a schematic cross-sectional view corresponding to the method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to an embodiment of the present invention;

[0042] Figure 8 Schematic diagram of the cross-sectional structure of the split-gate trench Schottky contact super-barrier rectifier according to an embodiment of the present invention;

[0043] Fig. 9 Comparison of junction capacitance of different technologies;

[0044] In the figure: a lower electrode layer 10, a heavily doped first conductivity type substrate layer 20, a lightly doped first conductivity type drift layer 30, a mask layer 31, a mask layer 32, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon cap layer 70, a second conductivity type body region 80 and an upper electrode layer 90. DETAILED DESCRIPTION

[0045] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0046] Embodiment 1:

[0047] See also Figure 2-Figure 9 , a method for manufacturing a split-gate trench Schottky contact super-barrier rectifier, comprising the following steps:

[0048] 1) Covering the lightly doped first conductivity type drift region 30 on the heavily doped first conductivity type substrate 20 .

[0049] 2) Forming a trench on the lightly doped first conductivity type drift region 30 .

[0050] 3) A dielectric layer is formed in the trench formed in step 2) to form a U-shaped trench gate dielectric layer 40 .

[0051] 4) Polysilicon is deposited and heavily doped, and then reverse etching is performed to remove excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3 to form a polysilicon filling layer 50 .

[0052] 5) Perform thermal oxidation growth on the surface of the super-barrier rectifier sample formed in step 4) to form a gate dielectric thin layer 60, and then form a polysilicon capping layer 70 by deposition on the gate dielectric thin layer 60. The polysilicon capping layer 70 is heavily doped.

[0053] 6) Cover the surface of the polysilicon cover layer 70 with a mask layer II32. Form a through groove in the mask layer II32. Etch the polysilicon cover layer 70 and the gate dielectric thin layer 60 below the through groove of the mask layer II32.

[0054] 7) Perform deep implantation of second conductivity type impurities, so that the second conductivity type impurities are implanted into the lightly doped first conductivity type drift region 30 through the through groove formed in step 6, and are blocked by the covering mask layer II32. Remove the mask layer II32.

[0055] 8) Forming a second conductivity type body region 80 .

[0056] 9) Depositing a metal layer to form an upper electrode layer 90 , and making the upper electrode layer 90 form a Schottky contact with the second conductive type body region 80 , and the upper electrode layer 90 form an ohmic contact with the polysilicon cap layer 70 .

[0057] 10) Depositing a lower electrode layer 10 on the lower surface of the heavily doped first conductive type substrate 20 to form an ohmic contact.

[0058] The process of covering the lightly doped first conductivity type drift region 30 includes epitaxial growth.

[0059] The step of forming a trench on the lightly doped first conductivity type drift region 30 includes:

[0060] s1) Covering the lightly doped first conductivity type drift region 30 with a mask layer I31.

[0061] s2) forming a through groove in the mask layer 131.

[0062] s3) etching the lightly doped first conductivity type drift region 30 below the through groove of the mask layer I31, so that a trench is formed on the lightly doped first conductivity type drift region 30.

[0063] s4) removing the mask layer I31.

[0064] The polysilicon filling layer 50 is located in the U-shaped trench gate dielectric layer 40 .

[0065] The method of forming the second conductivity type body region 80 includes rapid thermal processing.

[0066] The second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40. The second conductive type body region 80 and the U-shaped trench gate dielectric layer 40 are spaced apart from each other.

[0067] Embodiment 2:

[0068] The split-gate trench Schottky contact superbarrier rectifier formed based on the manufacturing method described in Example 1 includes a lower electrode layer 10, a heavily doped first conductive type substrate layer 20, a lightly doped first conductive type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon capping layer 70, a second conductive type body region 80 and an upper electrode layer 90.

[0069] The heavily doped first conductive type substrate layer 20 covers the lower electrode layer 10. The lightly doped first conductive type drift layer 30 covers the heavily doped first conductive type substrate layer 20.

[0070] The trench gate dielectric layer 40 is a U-shaped groove, covering a portion of the surface of the lightly doped first conductivity type drift layer 30. The polysilicon filling layer 50 is filled in the trench gate dielectric layer 40.

[0071] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40 , and covers a portion of the surface of the lightly doped first conductivity type drift layer 30 .

[0072] The gate dielectric thin layer 60 also covers a portion of the surface of the second conductive type body region 80 .

[0073] The polysilicon capping layer 70 covers the gate dielectric thin layer 60 .

[0074] The second conductivity type body region 80 covers a portion of the surface of the lightly doped first conductivity type drift layer 30 .

[0075] The second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40 .

[0076] The second conductive type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40 .

[0077] The upper electrode layer 90 covers the polysilicon capping layer 70 and covers a portion of the surface of the second conductivity type body region 80 .

[0078] An ohmic contact is formed between the upper electrode layer 90 and the polysilicon cap layer 70. A Schottky contact is formed between the upper electrode layer 90 and the second conductive type body region 80.

[0079] The lightly doped first conductivity type drift layer 30 , the gate dielectric thin layer 60 , the polysilicon cap layer 70 , the second conductivity type body region 80 , and the upper electrode layer 90 together form a Schottky contact super-barrier rectifier structure.

[0080] The trench gate dielectric layer 40 , the polysilicon filling layer 50 , the gate dielectric thin layer 60 , and the polysilicon capping layer 70 together form a split gate trench structure.

[0081] The gate dielectric thin layer 60 is used as a gate dielectric material in the Schottky contact super-barrier rectifier structure.

[0082] The gate dielectric thin layer 60 is used as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer 50 from the polysilicon capping layer 70 so that the polysilicon filling layer 50 and the polysilicon capping layer 70 are not in contact with each other.

[0083] Embodiment 3:

[0084] A method for manufacturing a split-gate trench Schottky contact super-barrier rectifier comprises the following steps:

[0085] 1) Covering the lightly doped first conductivity type drift region 30 on the heavily doped first conductivity type substrate 20 .

[0086] 2) Forming a trench on the lightly doped first conductivity type drift region 30 .

[0087] 3) A dielectric layer is formed in the trench formed in step 2) to form a U-shaped trench gate dielectric layer 40 .

[0088] 4) Polysilicon is deposited and heavily doped, and then reverse etching is performed to remove excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3 to form a polysilicon filling layer 50 .

[0089] 5) Perform thermal oxidation growth on the surface of the super-barrier rectifier sample formed in step 4) to form a gate dielectric thin layer 60, and then form a polysilicon capping layer 70 by deposition on the gate dielectric thin layer 60. The polysilicon capping layer 70 is heavily doped.

[0090] 6) Cover the surface of the polysilicon cover layer 70 with a mask layer II32. Form a through groove in the mask layer II32. Etch the polysilicon cover layer 70 and the gate dielectric thin layer 60 below the through groove of the mask layer II32.

[0091] 7) Perform deep implantation of second conductivity type impurities, so that the second conductivity type impurities are implanted into the lightly doped first conductivity type drift region 30 through the through groove formed in step 6) and are blocked by the covering mask layer II32. Remove the mask layer II32.

[0092] 8) Forming a second conductivity type body region 80 .

[0093] 9) Depositing a metal layer to form an upper electrode layer 90 , and making the upper electrode layer 90 form a Schottky contact with the second conductive type body region 80 , and the upper electrode layer 90 form an ohmic contact with the polysilicon cap layer 70 .

[0094] 10) Depositing a lower electrode layer 10 on the lower surface of the heavily doped first conductive type substrate 20 to form an ohmic contact.

[0095] Embodiment 4:

[0096] A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, the technical content of which is the same as that of Example 3, and further, the process of covering the lightly doped first conductivity type drift region 30 includes epitaxial growth.

[0097] Embodiment 5:

[0098] A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, the technical content of which is the same as any one of Embodiments 3-4, and further, the step of forming a trench on the lightly doped first conductive type drift region 30 comprises:

[0099] 1) Covering the lightly doped first conductivity type drift region 30 with a mask layer I31 .

[0100] 2) A through groove is formed in the mask layer 131.

[0101] 3) Etching the lightly doped first conductivity type drift region 30 below the through groove of the mask layer I31 , so that a trench is formed on the lightly doped first conductivity type drift region 30 .

[0102] 4) Remove the mask layer I31.

[0103] Embodiment 6:

[0104] A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, the technical content of which is the same as any one of Embodiments 3-5, and further, the polysilicon filling layer 50 is located in the U-shaped trench gate dielectric layer 40.

[0105] Embodiment 7:

[0106] A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, the technical content of which is the same as any one of embodiments 3-6, and further, a method for forming a second conductive type body region 80 includes rapid thermal processing.

[0107] Embodiment 8:

[0108] A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, the technical content is the same as any one of embodiments 3-7, further, the second conductivity type body region 80 is not connected to the U-shaped trench gate dielectric layer 40. The second conductivity type body region 80 and the U-shaped trench gate dielectric layer 40 are spaced apart.

[0109] Embodiment 9:

[0110] The split-gate trench Schottky contact superbarrier rectifier formed based on the manufacturing method described in any one of Examples 3-8 includes a lower electrode layer 10, a heavily doped first conductive type substrate layer 20, a lightly doped first conductive type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon capping layer 70, a second conductive type body region 80 and an upper electrode layer 90.

[0111] The heavily doped first conductive type substrate layer 20 covers the lower electrode layer 10. The lightly doped first conductive type drift layer 30 covers the heavily doped first conductive type substrate layer 20.

[0112] The trench gate dielectric layer 40 is a U-shaped groove, covering a portion of the surface of the lightly doped first conductivity type drift layer 30. The polysilicon filling layer 50 is filled in the trench gate dielectric layer 40.

[0113] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40 , and covers a portion of the surface of the lightly doped first conductivity type drift layer 30 .

[0114] The gate dielectric thin layer 60 also covers a portion of the surface of the second conductive type body region 80 .

[0115] The polysilicon capping layer 70 covers the gate dielectric thin layer 60 .

[0116] The second conductivity type body region 80 covers a portion of the surface of the lightly doped first conductivity type drift layer 30 .

[0117] The second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40 .

[0118] The second conductive type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40 .

[0119] The upper electrode layer 90 covers the polysilicon capping layer 70 and covers a portion of the surface of the second conductivity type body region 80 .

[0120] An ohmic contact is formed between the upper electrode layer 90 and the polysilicon cap layer 70. A Schottky contact is formed between the upper electrode layer 90 and the second conductive type body region 80.

[0121] Embodiment 10:

[0122] The split-gate trench Schottky contact superbarrier rectifier formed by the manufacturing method described in any one of Examples 3-8 has the same technical content as Example 9. Furthermore, the lightly doped first conductive type drift layer 30, the gate dielectric thin layer 60, the polysilicon capping layer 70, the second conductive type body region 80, and the upper electrode layer 90 together form a Schottky contact superbarrier rectifier structure.

[0123] Embodiment 11:

[0124] The split-gate trench Schottky contact superbarrier rectifier formed based on the manufacturing method described in any one of Examples 3-8 has the same technical content as any one of Examples 9-10. Furthermore, the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon covering layer 70 together form a split gate trench structure.

[0125] Embodiment 12:

[0126] The split-gate trench Schottky contact superbarrier rectifier formed by the manufacturing method described in any one of Examples 3-8 has the same technical content as any one of Examples 9-11. Furthermore, the gate dielectric thin layer 60 is used as a gate dielectric material in the Schottky contact superbarrier rectifier structure.

[0127] The gate dielectric thin layer 60 is used as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer 50 from the polysilicon capping layer 70 so that the polysilicon filling layer 50 and the polysilicon capping layer 70 are not in contact with each other.

[0128] Embodiment 13:

[0129] A method for manufacturing a split-gate trench Schottky contact super-barrier rectifier comprises the following main steps:

[0130] 1) If Figure 2 As shown, a lightly doped first conductivity type drift region 30 is covered on a heavily doped first conductivity type substrate 20; the covering is preferably carried out by epitaxial growth;

[0131] 2) If Figure 3 As shown, a mask layer I31 is covered on the lightly doped first conductive type drift region 30; a through groove is formed in the mask layer I31; the lightly doped first conductive type drift region 30 below the through groove of the mask layer I31 is etched, so that a groove is formed on the lightly doped first conductive type drift region 30, and then the mask layer I31 is removed;

[0132] 3) If Figure 4 As shown, the trench formed in step 2 is covered with a dielectric layer to form a U-shaped trench gate dielectric layer 40;

[0133] 4) If Figure 5 As shown, polysilicon is deposited, and the polysilicon is heavily doped, and then reverse etching is performed to remove the excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3, and finally a polysilicon filling layer 50 is formed; the polysilicon filling layer 50 is located in the U-shaped trench gate dielectric layer 40;

[0134] 5) performing thermal oxidation growth on the surface of the sample formed in step 4 to form a gate dielectric thin layer 60, and then forming a polysilicon capping layer 70 on the gate dielectric thin layer 60 by deposition; and heavily doping the polysilicon capping layer 70;

[0135] 6) If Figure 6 As shown, a mask layer II32 is covered on the surface of the polysilicon cover layer 70; a through groove is formed in the mask layer II32; and the polysilicon cover layer 70 and the gate dielectric thin layer 60 below the through groove of the mask layer II32 are etched;

[0136] 7) Selecting appropriate implantation energy to deeply implant the second conductive type impurities, so that the second conductive type impurities are partially implanted into the lightly doped first conductive type drift region 30 in the through groove formed in step 6, and are partially blocked by the covering mask layer II32; removing the mask layer II32;

[0137] 8) If Figure 7 As shown, the second conductive type body region 80 is formed by rapid thermal processing; the second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the second conductive type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40;

[0138] 9) depositing a metal layer to form an upper electrode layer 90; and making the upper electrode layer 90 form a Schottky contact with the second conductive type body region 80, and making the upper electrode layer 90 form an ohmic contact with the polysilicon cover layer 70;

[0139] 10) Depositing a lower electrode layer 10 on the lower surface of the heavily doped first conductive type substrate 20 to form an ohmic contact.

[0140] like Figure 8As shown, the embodiment of the present invention introduces a newly added split gate structure by growing a thin layer of gate dielectric on the basis of a conventional trench structure. While maintaining the good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and it has better reverse recovery performance. At the same time, the thin layer of gate dielectric makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal during the manufacturing process of the device, which reduces the minimum line width requirement and effectively reduces the process complexity and difficulty. The split gate will not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device.

[0141] Embodiment 14:

[0142] The device structure of the split-gate trench Schottky contact super-barrier rectifier formed by the manufacturing method of the split-gate trench Schottky contact super-barrier rectifier given in Example 13 includes a lower electrode layer 10, a heavily doped first conductive type substrate layer 20, a lightly doped first conductive type drift layer 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon cap layer 70, a second conductive type body region 80 and an upper electrode layer 90;

[0143] The heavily doped first conductive type substrate layer 20 covers the lower electrode layer 10; the lightly doped first conductive type drift layer 30 covers the heavily doped first conductive type substrate layer 20;

[0144] The trench gate dielectric layer 40 is a U-shaped groove, covering a portion of the surface of the lightly doped first conductivity type drift layer 30; the polysilicon filling layer 50 is filled in the trench gate dielectric layer 40;

[0145] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40, covers a portion of the surface of the lightly doped first conductivity type drift layer 30, and also covers a portion of the surface of the second conductivity type body region 80; the polysilicon capping layer 70 covers the gate dielectric thin layer 60;

[0146] The second conductive type body region 80 covers a portion of the surface of the lightly doped first conductive type drift layer 30; the second conductive type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the second conductive type body region 80 is spaced apart from the U-shaped trench gate dielectric layer 40;

[0147] The upper electrode layer 90 covers the polysilicon cover layer 70 and covers part of the surface of the second conductive type body region 80; an ohmic contact is formed between the upper electrode layer 90 and the polysilicon cover layer 70; and a Schottky contact is formed between the upper electrode layer 90 and the second conductive type body region 80;

[0148] The lightly doped first conductivity type drift layer 30, the gate dielectric thin layer 60, the polysilicon cap layer 70, the second conductivity type body region 80, and the upper electrode layer 90 together form a Schottky contact super barrier rectifier structure; the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon cap layer 70 together form a split gate trench structure;

[0149] The gate dielectric thin layer 60 is used as a gate dielectric material in the Schottky contact superbarrier rectifier structure and as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer 50 from the polysilicon covering layer 70 so that the polysilicon filling layer 50 and the polysilicon covering layer 70 are not in contact.

[0150] The materials of the heavily doped first conductive type substrate layer 20 and the lightly doped first conductive type drift layer 30 are preferably silicon and silicon carbide; the materials of the polysilicon filling layer 50 and the polysilicon covering layer 70 are preferably polysilicon; the materials of the trench gate dielectric layer 40 and the gate dielectric thin layer 60 are preferably silicon dioxide, silicon oxynitride or hafnium oxide.

[0151] like Figure 8 As shown, the embodiment of the present invention introduces a newly added split gate structure by growing a thin layer of gate dielectric on the basis of a conventional trench structure. While maintaining the good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and it has better reverse recovery performance. At the same time, the thin layer of gate dielectric makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal during the manufacturing process of the device, which reduces the minimum line width requirement and effectively reduces the process complexity and difficulty. The split gate will not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device.

[0152] Embodiment 15:

[0153] The first conductivity type is selected as N type and the second conductivity type is selected as P type. This embodiment discloses a method for manufacturing a split-gate trench Schottky contact super-barrier rectifier and a device structure thereof.

[0154] A method for manufacturing a split-gate trench Schottky contact super-barrier rectifier comprises the following main steps:

[0155] 1) If Figure 2 As shown, a lightly doped N-type drift region 30 is epitaxially grown on a heavily doped N-type substrate 20; the materials of the heavily doped N-type substrate 20 and the lightly doped N-type drift region 30 are selected to be silicon; the thickness of the lightly doped N-type drift region 30 is about 10 microns;

[0156] 2) If Figure 3As shown, a mask layer I31 is covered on the lightly doped N-type drift region 30; a through groove is formed in the mask layer I31; the lightly doped N-type drift region 30 below the through groove of the mask layer I31 is etched, so that a groove is formed on the lightly doped N-type drift region 30, and then the mask layer I31 is removed; the depth of the groove is about 4 microns and the width is about 1.5 microns;

[0157] 3) If Figure 4 As shown, an oxide layer is grown by thermal oxidation in the trench formed in step 2, and the thickness of the oxide layer is about 0.5 microns; a U-shaped trench gate dielectric layer 40 is formed;

[0158] 4) If Figure 5 As shown, polysilicon is deposited, and the polysilicon is heavily doped, and then reverse etching is performed to remove the excess polysilicon outside the U-shaped trench gate dielectric layer 40 formed in step 3, and finally a polysilicon filling layer 50 is formed; the polysilicon filling layer 50 is located in the U-shaped trench gate dielectric layer 40;

[0159] 5) performing thermal oxidation growth on the surface of the sample formed in step 4 to form a gate dielectric thin layer 60 with a thickness of about 5 nanometers, and then forming a polysilicon cap layer 70 with a thickness of about 0.4 micrometers on the gate dielectric thin layer 60 by deposition; and heavily doping the polysilicon cap layer 70;

[0160] 6) If Figure 6 As shown, a mask layer II32 is covered on the surface of the polysilicon cover layer 70; a through groove is formed in the mask layer II32; and the polysilicon cover layer 70 and the gate dielectric thin layer 60 below the through groove of the mask layer II32 are etched;

[0161] 7) Selecting appropriate implantation energy to perform deep implantation of P-type impurities, so that the P-type impurities are partially implanted into the lightly doped N-type drift region 30 in the through groove formed in step 6, and are blocked in the covering mask layer II32; removing the mask layer II32;

[0162] 8) If Figure 7 As shown, a P-type body region 80 is formed by rapid thermal processing; the P-type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the P-type body region 80 and the U-shaped trench gate dielectric layer 40 are spaced apart;

[0163] 9) depositing a metal layer to form an upper electrode layer 90; and forming a Schottky contact between the upper electrode layer 90 and the P-type body region 80, and forming an ohmic contact between the upper electrode layer 90 and the polysilicon cap layer 70; the metal deposited on the upper electrode layer 90 is selected from Pt, PtNi, Ti or TiN;

[0164] 10) Depositing a lower electrode layer 10 on the lower surface of the heavily doped N-type substrate 20 to form an ohmic contact.

[0165] According to the above manufacturing method, a split-gate trench Schottky contact super-barrier rectifier is formed, comprising a lower electrode layer 10, a heavily doped N-type substrate 20, a lightly doped N-type drift region 30, a U-shaped trench gate dielectric layer 40, a polysilicon filling layer 50, a gate dielectric thin layer 60, a polysilicon cap layer 70, a P-type body region 80 and an upper electrode layer 90;

[0166] The heavily doped N-type substrate 20 covers the lower electrode layer 10 ; the lightly doped N-type drift region 30 covers the heavily doped N-type substrate 20 ;

[0167] The trench gate dielectric layer 40 is a U-shaped groove, covering a portion of the surface of the lightly doped N-type drift region 30; the polysilicon filling layer 50 is filled in the trench gate dielectric layer 40;

[0168] The gate dielectric thin layer 60 completely covers the polysilicon filling layer 50 and the trench gate dielectric layer 40, covers a portion of the surface of the lightly doped N-type drift region 30, and also covers a portion of the surface of the P-type body region 80; the polysilicon capping layer 70 covers the gate dielectric thin layer 60;

[0169] The P-type body region 80 covers a portion of the surface of the lightly doped first conductive type drift layer 30; the P-type body region 80 is not connected to the U-shaped trench gate dielectric layer 40; the P-type body region 80 and the U-shaped trench gate dielectric layer 40 are spaced apart;

[0170] The upper electrode layer 90 covers the polysilicon cover layer 70 and covers a part of the surface of the P-type body region 80; an ohmic contact is formed between the upper electrode layer 90 and the polysilicon cover layer 70; and a Schottky contact is formed between the upper electrode layer 90 and the P-type body region 80;

[0171] The lightly doped N-type drift region 30, the gate dielectric thin layer 60, the polysilicon capping layer 70, the P-type body region 80, and the upper electrode layer 90 together form a Schottky contact super-barrier rectifier structure; the trench gate dielectric layer 40, the polysilicon filling layer 50, the gate dielectric thin layer 60, and the polysilicon capping layer 70 together form a split-gate trench structure;

[0172] The gate dielectric thin layer 60 is used as a gate dielectric material in the Schottky contact superbarrier rectifier structure and as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer 50 from the polysilicon covering layer 70 so that the polysilicon filling layer 50 and the polysilicon covering layer 70 are not in contact.

[0173] The embodiment of the present invention introduces a newly added split gate structure by growing a thin layer of gate dielectric on the basis of a conventional trench structure. While maintaining the good forward characteristics of the SSBR, the barrier capacitance of the device is reduced, and the reverse recovery performance is better. At the same time, the thin layer of gate dielectric makes it unnecessary to connect the narrow polysilicon in the trench to the anode metal during the manufacturing process of the device, which reduces the minimum line width requirement and effectively reduces the process complexity and difficulty. The split gate will not affect the optimization of the electric field distribution in the device by the trench structure, and can effectively improve the breakdown voltage of the device. Fig. 9 The figure shows the comparison of the junction capacitance between the conventional trench gate MOS structure and the split gate structure of the present invention. It can be seen that the split gate structure of the present invention can reduce the rectifier barrier capacitance, thereby improving the reverse recovery characteristics of the device.

Claims

1. A method for manufacturing a split-gate trench Schottky contact superbarrier rectifier, characterized in that: The following steps are involved: 1) Covering a lightly doped first conductivity type drift region (30) on a heavily doped first conductivity type substrate (20). 2) forming a trench on the lightly doped first conductivity type drift region (30). 3) Covering the trench formed in step 2) with a dielectric layer to form a U-shaped trench gate dielectric layer (40); 4) depositing polysilicon, heavily doping the polysilicon, and then performing reverse etching to remove excess polysilicon outside the U-shaped trench gate dielectric layer (40) formed in step 3), thereby forming a polysilicon filling layer (50); 5) performing thermal oxidation growth on the surface of the super-barrier rectifier sample formed in step 4) to form a gate dielectric thin layer (60), and then forming a polysilicon capping layer (70) on the gate dielectric thin layer (60) by deposition; and heavily doping the polysilicon capping layer (70); 6) Covering the surface of the polysilicon cover layer (70) with a mask layer II (32); forming a through groove in the mask layer II (32); etching the polysilicon cover layer (70) and the gate dielectric thin layer (60) below the through groove of the mask layer II (32); 7) performing deep implantation of second conductive type impurities, so that the second conductive type impurities are implanted into the lightly doped first conductive type drift region (30) through the through groove formed in step 6) and are blocked by the covering mask layer II (32); removing the mask layer II (32); 8) forming a second conductivity type body region (80); 9) depositing a metal layer to form an upper electrode layer (90), and making the upper electrode layer (90) form a Schottky contact with the second conductive type body region (80), and the upper electrode layer (90) form an ohmic contact with the polysilicon cover layer (70); 10) Depositing a lower electrode layer (10) on the lower surface of the heavily doped first conductive type substrate (20) and forming an ohmic contact.

2. The method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to claim 1, characterized in that: The process of covering the lightly doped first conductivity type drift region (30) includes epitaxial growth.

3. The method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to claim 1, characterized in that: The step of forming a trench on the lightly doped first conductivity type drift region (30) comprises: 1) covering the lightly doped first conductivity type drift region (30) with a mask layer I (31); 2) forming a through groove in the mask layer I (31); 3) etching the lightly doped first conductivity type drift region (30) below the through groove of the mask layer I (31), so that a groove is formed on the lightly doped first conductivity type drift region (30); 4) Remove the mask layer I (31).

4. The method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to claim 1, characterized in that: The polysilicon filling layer (50) is located in the U-shaped trench gate dielectric layer (40).

5. The method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to claim 1, characterized in that: The method of forming the second conductivity type body region (80) includes rapid thermal processing.

6. The method for manufacturing a split-gate trench Schottky contact superbarrier rectifier according to claim 1, characterized in that: The second conductive type body region (80) is not connected to the U-shaped groove gate dielectric layer (40); the second conductive type body region (80) and the U-shaped groove gate dielectric layer (40) are distributed at intervals.

7. A split-gate trench Schottky contact superbarrier rectifier formed by the manufacturing method according to any one of claims 1 to 6, characterized in that: It comprises a lower electrode layer (10), a heavily doped first conductive type substrate layer (20), a lightly doped first conductive type drift layer (30), a U-shaped trench gate dielectric layer (40), a polysilicon filling layer (50), a gate dielectric thin layer (60), a polysilicon capping layer (70), a second conductive type body region (80) and an upper electrode layer (90); The heavily doped first conductive type substrate layer (20) covers the lower electrode layer (10); the lightly doped first conductive type drift layer (30) covers the heavily doped first conductive type substrate layer (20); The trench gate dielectric layer (40) is a U-shaped groove, covering a portion of the surface of the lightly doped first conductive type drift layer (30); the polysilicon filling layer (50) is filled in the trench gate dielectric layer (40); The gate dielectric thin layer (60) completely covers the polysilicon filling layer (50) and the trench gate dielectric layer (40), and covers a portion of the surface of the lightly doped first conductive type drift layer (30); The gate dielectric thin layer (60) also covers a portion of the surface of the second conductive type body region (80); The polysilicon cover layer (70) covers the gate dielectric thin layer (60); The second conductive type body region (80) covers a portion of the surface of the lightly doped first conductive type drift layer (30); The second conductive type body region (80) is not connected to the U-shaped trench gate dielectric layer (40); The second conductive type body region (80) and the U-shaped groove gate dielectric layer (40) are spaced apart and distributed; The upper electrode layer (90) covers the polysilicon cover layer (70) and covers a portion of the surface of the second conductive type body region (80); An ohmic contact is formed between the upper electrode layer (90) and the polysilicon cover layer (70); and a Schottky contact is formed between the upper electrode layer (90) and the second conductive type body region (80).

8. The split-gate trench Schottky contact superbarrier rectifier according to claim 7, characterized in that: The lightly doped first conductive type drift layer (30), the gate dielectric thin layer (60), the polysilicon cover layer (70), the second conductive type body region (80), and the upper electrode layer (90) together form a Schottky contact super-barrier rectifier structure.

9. The split-gate trench Schottky contact superbarrier rectifier according to claim 7, characterized in that: The trench gate dielectric layer (40), the polysilicon filling layer (50), the gate dielectric thin layer (60) and the polysilicon covering layer (70) together form a split gate trench structure.

10. The split-gate trench Schottky contact superbarrier rectifier according to claim 9, characterized in that: The gate dielectric thin layer (60) is used as a gate dielectric material in a Schottky contact super-barrier rectifier structure; The gate dielectric thin layer (60) is used as an isolation dielectric material in the split gate trench structure to isolate the polysilicon filling layer (50) from the polysilicon covering layer (70), so that the polysilicon filling layer (50) and the polysilicon covering layer (70) are not in contact.

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