Semiconductor device and manufacturing method

Abstract

The invention provides a semiconductor device and a manufacturing method, and relates to the technical field of semiconductors. According to the semiconductor manufacturing method provided by the invention, the inclined field plate can be formed on the semiconductor device, so that the electric field distribution of the single-stage field plate is improved, and the electric field change of the semiconductor device at the field plate is more uniform. In addition, the inclined field plate is formed based on the load effect of plasma etching, so that the grooves with the depth continuously changing are formed through the windows with the sizes continuously changing, and the grooves are communicated to form the inclined grooves to prepare the inclined field plate. Therefore, the inclined field plate in the semiconductor device can be formed based on a single preparation process, the inclined field plate does not need to be formed by repeating specific preparation steps, and the preparation difficulty of the inclined field plate is reduced. In addition, the grooves with different depths are communicated, so that the bottom surfaces of the inclined grooves are more coherent, and the coherence of the inclined field plate is guaranteed.

Description

Technical Field

[0001] This application relates to semiconductor technology, specifically to a semiconductor device and its manufacturing method. Background Technology

[0002] In semiconductor devices, a field plate is a structure used to optimize the electric field distribution, typically applied in laterally diffused metal-oxide-semiconductor (LDMOS) devices. The main function of the field plate is to reduce the electric field strength in the drain region by increasing the area of ​​the electric field distribution, thereby improving the device's breakdown voltage (BV) and breakdown voltage, while simultaneously reducing the on-resistance (RDson), thus enhancing the device's performance and reliability.

[0003] In traditional LDMOS devices, the field plate is typically a single-stage parallel field plate. The electric field variation of this field plate is non-uniform, especially with spikes at the field plate edges. Therefore, optimizing the electric field variation of the field plate is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a semiconductor device and manufacturing method, in which a tilted field plate is formed in the semiconductor device, thereby reducing the peak electric field on the semiconductor surface and optimizing the electric field formed by the field plate.

[0005] In a first aspect, this application provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate, the substrate including a plurality of semiconductor structures; forming a patterned photoresist layer on the substrate, wherein the patterned photoresist layer includes a plurality of window regions distributed along a target direction and a plurality of blocking regions, the blocking regions being used to isolate adjacent window regions, and the opening width of at least a portion of the continuous window regions gradually changing along the target direction; performing a plasma etching process using the patterned photoresist layer as a mask to form trenches at positions corresponding to the window regions in the substrate, wherein a separation structure of the trenches is formed at positions corresponding to the blocking regions in the substrate, and the etching depth of the trenches is positively correlated with the opening width of the corresponding window; removing the photoresist layer; removing the separation structure between the trenches to form a field plate groove, wherein the field plate groove includes an inclined bottom surface corresponding to at least a portion of the continuous window regions; and forming an inclined field plate of a semiconductor structure on the inclined bottom surface of the field plate groove.

[0006] In a second aspect, this application provides a semiconductor device formed based on the manufacturing method described in the first aspect.

[0007] The semiconductor manufacturing method provided in this application can form tilted field plates on semiconductor devices, thereby improving the electric field distribution of a single-level field plate and making the electric field change at the field plate of the semiconductor device more uniform. Furthermore, the tilted field plate of this application is formed based on the loading effect of plasma etching, thereby forming grooves of continuously varying depths through windows of continuously varying sizes, and connecting these grooves to form tilted grooves to fabricate the tilted field plate. Thus, the tilted field plate in the semiconductor device can be formed based on a single fabrication process without repeating specific fabrication steps, reducing the fabrication difficulty of the tilted field plate. In addition, this application makes the bottom surface of the tilted grooves more continuous by connecting grooves of different depths, thereby ensuring the continuity of the tilted field plate. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 This is a schematic diagram of the structure of a semiconductor device with an inclined field plate provided in some embodiments of this application.

[0010] Figure 2 This is an exemplary flowchart of a method for manufacturing a semiconductor device provided in some embodiments of this application.

[0011] Figure 3 This is a schematic diagram of the structure of a semiconductor device to be formed into an inclined field plate, provided in some embodiments of this application.

[0012] Figure 4 This is a schematic diagram of the structure of a semiconductor device coated with a photoresist layer provided in some embodiments of this application.

[0013] Figure 5 This is a schematic diagram of the structure of a semiconductor device including multiple trenches provided in some embodiments of this application.

[0014] Figure 6 This is a schematic diagram of the structure of a semiconductor device with a field plate groove provided in some embodiments of this application.

[0015] Figure 7 This is a schematic diagram of the structure of a semiconductor device after field plate material is deposited in a field plate groove according to some embodiments of this application.

[0016] Figure 8 This is a schematic diagram of the structure of a semiconductor device after filling with a dielectric, provided in some embodiments of this application.

[0017] Figure 9 This is a schematic diagram of the structure of a photoresist layer provided in some embodiments of this application.

[0018] Among them, 100 is a semiconductor device; 110 is a P-type substrate; 120 is an N-type drift layer; 130 is a P-well; 140 is a control gate; 150 is an isolation gate; 160 is a tilted field plate; 170 is an interlayer dielectric; 171 is a trench; 172 is a separation structure; 173 is a field plate groove; 174 is a second deposition layer; 180 is a patterned photoresist layer; 181 is a window region; 182 is a blocking region; 190 is a first deposition layer; 191 is a sidewall deposition structure; and 192 is a substrate deposition structure. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0021] In this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0022] Exemplary semiconductor devices: To illustrate semiconductor devices with tilted field plates, this application uses an LDMOS structure as an example to explain semiconductor devices with tilted field plates. Figure 1 Semiconductor devices typically include multiple LDMOS structures, which can be isolated from each other by isolation trenches. Figure 1The semiconductor device shown may contain only one LDMOS structure. The arrangement of LDMOS structures in semiconductor devices can be found in related technologies and will not be elaborated here.

[0023] like Figure 1 As shown, the semiconductor device 100 may include a P-type substrate 110 (P-Sub), an N-type drift layer 120 (N-drift), a P-well 130 (P-Well), a control gate 140 (Poly Gate), an isolation gate 150, a tilted field plate 160, and an interlayer dielectric 170. The specific functions of the P-type substrate 110, N-type drift layer 120, P-well 130, control gate 140, and isolation gate 150 in the LDMOS structure can be found in related technologies and will not be elaborated upon here.

[0024] The interlayer dielectric 170 may include a dielectric reflecting the semiconductor structure (transistor layer) and metal layer of the semiconductor device 100. A tilted field plate 160 may be formed in the interlayer dielectric 170 and disposed at an angle. The tilted field plate 160 is generally located away from the surface of the semiconductor structure in the stacking direction of the semiconductor device, away from the control gate 140.

[0025] Therefore, based on the aforementioned inclined field plate 160, a high electric field peak will not be formed on the semiconductor surface at the edge of the field plate, thus making the electric field change more uniform.

[0026] In some embodiments, the inclined field plate 160 provided in this application is formed based on a groove structure (referred to as a field plate groove) with an inclined bottom surface, and a portion of the field plate material (such as metal material, polycrystalline silicon, etc.) will also be retained on the sidewall of the field plate groove.

[0027] In addition to the aforementioned structure, the semiconductor device 100 may also include metal leads connected to the metal layer. Specifically, the control gate 140 and the tilted field plate 160 in the semiconductor device 100 are both provided with metal leads.

[0028] As a result, an inclined field plate is formed on the aforementioned semiconductor device, thereby improving the electric field distribution of the single-level field plate and making the electric field change of the semiconductor device at the field plate more uniform.

[0029] To form the aforementioned semiconductor device with an inclined field plate, this application also provides a method for fabricating the semiconductor device, which is described below in conjunction with... Figures 2-8 The manufacturing process of semiconductor devices is explained.

[0030] Exemplary manufacturing method of semiconductor devices: Figure 2 This is an exemplary flowchart of a method for manufacturing a semiconductor device provided in some embodiments of this application.

[0031] like Figure 2 As shown, Figure 1 The method for manufacturing the semiconductor device shown, P200, may include the following steps: S210, Provide a substrate.

[0032] S220, A patterned photoresist layer is formed on the substrate.

[0033] S230. Perform a plasma etching process using a patterned photoresist layer as a mask to form trenches in the substrate at positions corresponding to the window region.

[0034] S240, Remove the photoresist layer.

[0035] S250, Remove the separation structure between each groove to form a groove in the field plate.

[0036] S260, An inclined field plate with a semiconductor structure is formed on the inclined bottom surface of the field plate groove.

[0037] The following will combine Figures 3-8 The steps in P200 above will be explained.

[0038] The substrate in S210 mentioned above can refer to Figure 3 The semiconductor device shown is to be formed into an inclined field plate.

[0039] Considering that the tilted field plate is often disposed in the interlayer medium, the aforementioned substrate in S210 can refer to the doped substrate that has formed the semiconductor structure and the interlayer medium between the transistor and the first metal layer. That is, the substrate includes multiple semiconductor structures.

[0040] Taking the LDMOS structure as an example, such as Figure 3 As shown, the semiconductor device 100 to be formed into an inclined field plate may include a P-type substrate 110, an N-type drift layer 120, a P-well 130, a control gate 140, an isolation gate 150, and an interlayer dielectric 170. Among these, Figure 3 The semiconductor device 100 includes a P-type substrate 110, an N-type drift layer 120, a P-well 130, a control gate 140, an isolation gate 150, and... Figure 1 Consistent with the above.

[0041] Considering the subsequent preparation process, it can be used as Figure 3 The upper surface of the interlayer medium 170 serves as the stop layer for chemical mechanical polishing. Figure 3 The thickness of the interlayer medium 170 in the middle and Figure 1 The thickness of the interlayer medium 170 is the same within the allowable tolerance range.

[0042] The aforementioned S220 can be used for Figure 3 The semiconductor device shown is processed to form an inclined field plate, thereby forming... Figure 4 The semiconductor device shown is coated with a photoresist layer.

[0043] like Figure 4 As shown, a patterned photoresist layer 180 can be formed above the aforementioned interlayer dielectric 170. Considering that this application requires the formation of multiple trenches with varying depths, the patterned photoresist layer 180 has multiple window regions 181 and multiple blocking regions 182 distributed along the target direction (the horizontal direction in the figure), and the opening width of at least some of the continuous window regions 181 gradually changes along the target direction.

[0044] In subsequent steps, the aforementioned patterned photoresist layer 180 is used as a mask layer (also called a photomask) for the plasma etching process. The aforementioned window region 181 can refer to the area in the patterned photoresist layer 180 where the photoresist has been removed, exposing the interlayer dielectric 170 to the etching environment, while the blocking region 182 can refer to the area in the patterned photoresist layer 180 where the photoresist is retained, preventing the interlayer dielectric 170 from being exposed to the etching environment. That is, in the subsequent plasma etching process, the area of ​​the interlayer dielectric 170 corresponding to the window region 181 will be etched by the plasma etching process to form trenches, while the area corresponding to the blocking region 182 will be retained.

[0045] Considering the loading effect of plasma etching, the etching rate is related to the pattern size and density, and the etching rate is slower in small window patterns. Specifically, given that the opening width of at least some consecutive window regions 181 in the aforementioned plurality of window regions 181 gradually changes along the target direction, after subsequent plasma etching, these consecutive window regions 181 with gradually changing opening widths along the target direction will form multiple trenches with gradually changing etching depths along the target direction, and the depth change of the trenches is positively correlated with the change in opening width. After forming multiple trenches with varying depths, connecting the trenches can form a groove with an inclined bottom surface, thereby forming an inclined field plate, as detailed in the following description.

[0046] In some embodiments, the aforementioned patterned photoresist layer 180 can be formed based on a photoresist photolithography process. That is, a photoresist layer can first be formed on a substrate (i.e., above the aforementioned interlayer medium 170). Then, an optical etching process is performed on the photoresist layer based on an etching pattern of multiple window regions to form a patterned photoresist layer.

[0047] As an example only, the aforementioned patterned photoresist layer 180 can be implemented based on the following steps: Photoresist Coating: First, a layer of photoresist is uniformly coated onto the substrate (i.e., above the interlayer dielectric). This step can be achieved using spin coating technology, allowing the photoresist to uniformly cover the entire substrate surface.

[0048] Soft baking: After coating the photoresist, a soft bake is required to remove the solvent from the photoresist and allow it to cure. This step helps improve the adhesion and stability of the photoresist.

[0049] Exposure: A patterned photomask (i.e., an etched pattern of multiple window areas) is placed over a silicon wafer coated with photoresist, and ultraviolet light is used to illuminate the photoresist. The ultraviolet light penetrates the photomask, causing chemical changes in certain areas beneath it, thus forming the pattern.

[0050] Development: After exposure, the photoresist needs to undergo development. The developer dissolves the unexposed portions of the photoresist, thus forming the desired pattern. The developed patterned photoresist clearly reflects the design on the photomask.

[0051] Hard bake: After development, hard bake is usually performed to further cure the photoresist and enhance its mechanical strength and durability.

[0052] The aforementioned process can be used to form the patterned photoresist layer 180. For details regarding the specific distribution of the window regions 181 within the patterned photoresist layer 180, please refer to [link / reference needed]. Figure 9 The details and related descriptions will not be elaborated here.

[0053] The aforementioned S230 can be used for Figure 4 The semiconductor device with the photoresist layer shown is processed to form... Figure 5 The semiconductor device shown contains multiple trenches.

[0054] As mentioned above, due to the loading effect of the plasma etching process, during S230, for the same etching time, a window region with a larger aperture width will form a trench 171 with a greater etching depth. That is, the etching depth of the trench 171 is positively correlated with the aperture width of the corresponding window. The larger the aperture width of the corresponding window region 181, the greater the etching depth of the trench 171.

[0055] Meanwhile, considering that the window region 181 is separated by the blocking region 182, a separation structure 172 will be formed between the two trenches 171 to separate each trench 171. That is, a separation structure 172 will be formed between the trenches 171 at the position in the substrate (the upper surface of the interlayer dielectric 170) corresponding to the blocking region 182.

[0056] Considering that the aforementioned patterned photoresist layer 180 has multiple consecutive window regions 181 with opening widths gradually changing along the target direction, the etching depth of the consecutive trenches 171 formed in S230 for these consecutive window regions 181 will also gradually change along the target direction. Therefore, when the separation structure 172 between these trenches 171 is removed, an inclined bottom surface is formed, which serves as the bottom surface for the subsequent fabrication of the inclined field plate.

[0057] The aforementioned S240 can be used for Figure 5 The semiconductor device shown, containing multiple trenches, is processed to remove... Figure 5 The patterned photoresist layer 180 is described in the figure. The stripping process and results of the patterned photoresist layer 180 can be found in relevant technologies and will not be described in detail here.

[0058] The aforementioned S250 can remove the patterned photoresist layer 180° after processing. Figure 5 The semiconductor device shown is processed to obtain Figure 6 The semiconductor device shown has a field plate groove.

[0059] In some embodiments, the aforementioned S250 can be implemented using a wet etching process. Specifically, the aforementioned trenches 171 and the separation structures 172 between the trenches 171 can be exposed to a wet etching environment (such as an acidic environment) and thus etched. The separation structures 172 between the trenches 171 are etched away, thereby opening up the trenches 171 to form field plate recesses 173, thereby obtaining a semiconductor device with field plate recesses 173.

[0060] Specifically, during the wet etching process of S250, the separation structure 172 between the trenches 171 is laterally etched away by the wet etching environment, thereby connecting the various trenches 171 to form the field plate groove 173. In order to ensure that the separation structure 172 is etched, the wet etching process often has redundancy, which means that the wet etching environment often further etches the sidewalls and bottom surface of the field plate groove 173, thereby achieving a smoothing treatment of the bottom surface of the field plate groove 173, so that the inclined bottom surface of the field plate groove 173 can be approximated as a gradual change.

[0061] In addition, in order to ensure that the separation structure 172 between each trench 171 is etched synchronously, the width of the separation structure 172 is often the same. Therefore, the width of the blocking area 182 of the aforementioned patterned photoresist layer 180 can also be the same, so that the width of the separation structure 172 is the same.

[0062] In some embodiments, considering that the interlayer medium 170 is generally formed of silicon oxide, when performing the aforementioned S250, an acidic environment can generally be used as a wet etching environment to etch the separation structure 172 of the interlayer medium 170.

[0063] Furthermore, considering the integrity of the surface of the interlayer medium 170, when performing the aforementioned S250, a protective layer can be formed in other areas that do not require etching (i.e., the upper surface of the interlayer medium 170 outside of the trench 171 and the separation structure 172), and then the trench 171 and the separation structure 172 are exposed to the wet etching environment, so as to protect the integrity of the upper surface of the interlayer medium 170 through the protective layer.

[0064] It should be noted that during the etching process of the separation structure 172, the bottom surface of the trench 171 will also be etched to a certain extent. Therefore, when designing the process parameters of S220 and S240, it is necessary to consider the total etching amount of the two processes and allocate it reasonably to obtain the field plate groove 173 that meets the requirements.

[0065] For example, the process parameters and wet etching amount of S240 can generally be determined based on the width of the separation structure 172 and the lateral etching rate of the wet etching process. The etching amount and process parameters of the aforementioned S220 plasma etching can be deduced based on the wet etching amount of the trench and the depth requirement of the field plate groove 173.

[0066] Thus, the field plate groove 173 formed based on the above process has an inclined bottom surface corresponding to the multiple continuous window regions 181 that gradually change along the target direction, thereby enabling the deposition process to form an inclined field plate.

[0067] That is, the aforementioned S260 can be used for Figure 6 The field plate groove 173 shown is subjected to deposition treatment to form Figure 1 The semiconductor device shown.

[0068] Therefore, the tilted field plate of this application is formed based on the loading effect of plasma etching, thereby forming grooves with continuously varying depths through windows of continuously varying sizes, and connecting these grooves to form tilted grooves to fabricate the tilted field plate. Thus, the tilted field plate in a semiconductor device can be formed based on a single fabrication process without repeating specific fabrication steps, reducing the fabrication difficulty of the tilted field plate. Furthermore, this application makes the bottom surface of the tilted grooves more continuous by connecting grooves of different depths, thereby ensuring the continuity of the tilted field plate.

[0069] Considering that the area of ​​the aforementioned inclined field plate 160 to be filled is presented as a field plate groove 173, in the formation Figure 1 In the process of creating the semiconductor device shown, the field plate material can be filled first, and then the missing interlayer dielectric 170 at the field plate groove 173 can be filled to form... Figure 1 The semiconductor device shown.

[0070] That is based on Figure 6In the subsequent fabrication process of the semiconductor device with field plate grooves shown, field plate material can be deposited first to obtain... Figure 7 The image shows a semiconductor device after field plate material has been deposited within a field plate groove. Specifically, a first deposition process can be performed based on the field plate material of the tilted field plate to form a first deposition layer. The field plate material of the tilted field plate is typically a metallic material (such as copper) or polycrystalline silicon.

[0071] like Figure 7 As shown, the first deposition layer 190 can refer to the deposition layer formed on the semiconductor structure (i.e., the interlayer dielectric 170 with field plate groove 173) after performing the first deposition process. Specifically, the first deposition layer 190 may include an inclined field plate 160 deposited on the inclined bottom surface of the field plate groove 173, a sidewall deposition structure 191 deposited on the groove sidewall of the field plate groove 173, and a substrate deposition structure 192 deposited on the substrate surface (i.e., the upper surface of the interlayer dielectric 170 where the field plate groove 173 is not formed).

[0072] After forming the aforementioned inclined field plate 160, the missing medium in the aforementioned field plate groove 173 can be filled. That is, it can be used for... Figure 7 The semiconductor device shown undergoes a second deposition process to form a second deposition layer, thereby forming... Figure 8 The semiconductor device shown is filled with a dielectric material.

[0073] like Figure 8 As shown, the second deposition layer 174 can refer to the deposition layer formed after performing the second deposition process. This second deposition layer 174 generally uses the same material as the aforementioned interlayer medium 170 (generally silicon oxide) to fill the medium missing in the field plate groove 173. In specific implementation, the second deposition process can be achieved by directly depositing silicon oxide, or by depositing silicon material and then oxidizing it.

[0074] After the formation of the second deposition layer 174, a chemical mechanical polishing (CMP) process can be performed. Specifically, the substrate surface below the second deposition layer 174 (i.e., the upper surface of the interlayer dielectric 170 before the formation of the field plate groove 173) can be used as a stop layer for CMP to remove the second deposition layer 174 outside the field plate groove 173, resulting in... Figure 1 The semiconductor device shown.

[0075] Furthermore, considering that a protective layer may be provided on the upper surface of the interlayer medium 170 where the field plate groove 173 is not formed in the aforementioned S250, the aforementioned chemical mechanical polishing process may also use the upper surface of the interlayer medium 170 where the field plate groove 173 is not formed under the protective layer as a stop layer.

[0076] Exemplary patterned photoresist layer: To further illustrate the patterned photoresist layer provided in this application, this application... Figure 9 A schematic diagram of the structure of a graphic photoresist layer from a top-down view is also provided.

[0077] like Figure 9 As shown, the patterned photoresist layer 180 forms multiple window regions 181 and multiple blocking regions 182 distributed along the target direction within the etching range. As mentioned above, the window regions 181 do not retain photoresist, but trenches are formed on the substrate through the window regions 181 during subsequent plasma etching. The blocking regions 182 retain photoresist, and protect the substrate surface during subsequent plasma etching, forming a separation structure between the trenches.

[0078] As mentioned above, considering that each of the discrete structures needs to be etched away in the subsequent wet etching process, the widths of the aforementioned discrete structures are basically the same, and the widths of the corresponding blocking regions 182 are also the same. Preferably, for the LDMOS structure, the width of the blocking region 182 ranges from 0.09 μm to 0.3 μm.

[0079] In order to achieve a gradual change in the opening width of at least a portion of the continuous window regions in the multiple window regions 181 along the target direction, the opening width of the multiple continuous window regions varies at equal intervals along the target direction in combination with the loading effect of plasma etching.

[0080] For example, Figure 9 In the diagram, the rightmost window region has the smallest size, and its opening width is denoted as x. The difference in opening width between adjacent window regions is... Then, along the leftward direction in the diagram, the opening width of the window region can be analyzed as x + (n-1). Where n reflects the number of window regions from right to left.

[0081] Therefore, based on the aforementioned multiple window regions with varying equidistant spacing, the etching depth of the resulting trenches generally varies accordingly, thus forming field plate grooves with inclined bottom surfaces. The specific correspondence can be calculated experimentally, and this application will not elaborate on it.

[0082] In specific implementation, when the semiconductor structure is configured as a laterally diffused metal-oxide-semiconductor, the minimum opening width (i.e., the aforementioned x) of multiple window regions ranges from 0.09 μm to 0.18 μm, and the change in opening width between adjacent window regions (i.e., the aforementioned x) The width range is 0.005μm to 0.02μm.

[0083] It should be noted that the aforementioned Figures 1-9This mainly involves a tilted field plate 160 that is away from the surface of the semiconductor structure in the stacking direction of the semiconductor device, along a direction away from the control gate 140, while other types of tilted field plates can be adaptively adjusted based on the size design of different window areas.

[0084] Specifically, in an actual semiconductor structure, the tilt of the tilted field plate 160 can be adjusted according to actual needs. That is, as mentioned above... Figure 1 The field plate slopes upwards from left to right in the diagram. In actual fabrication, the slope direction of the field plate can be the same as... Figure 1 Similarly, it can also tilt downwards from left to right, or it can tilt in segments (such as tilting downwards from left to right first, and then tilting upwards from left to right, forming a tilted field plate similar to the shape of a √).

[0085] The tilted field plate 160 with other tilt directions and tilt methods mentioned above can also be processed based on the fabrication method provided in this application. Specifically, its tilt condition (such as tilting upward or downward) can be analyzed, the tilted field plate can be segmented, and a corresponding patterned photoresist layer can be designed based on its segmentation results.

[0086] Based on the aforementioned two tilting scenarios—upward tilting from left to right and downward tilting from left to right—the corresponding field plates can form patterns in two ranges within the patterned photoresist layer. Specifically, a first range of window areas and / or a second range of window areas are formed based on the tilting of the tilted field plates, wherein the tilting of the tilted field plates formed in the first range of window areas differs from that formed in the second range of window areas.

[0087] Specifically, if the opening width of the window area in the first range increases along the target direction, then the corresponding portion of the inclined field plate in the first range will tilt downwards from left to right. If the opening width of the window area in the second range decreases along the target direction, then the corresponding portion of the inclined field plate in the second range will tilt upwards from left to right.

[0088] For cases where the tilting direction is first from left to right upward and then from left to right downward, a first range of window areas and a second range of window areas can be formed sequentially from left to right in the patterned photoresist layer, so that the corresponding tilted field plate will generally first approach the surface of the semiconductor structure and then move away from the surface of the semiconductor structure.

[0089] Unexpected technical effects: In summary, the semiconductor device and manufacturing method provided in this application have the following unexpected effects: ①This application forms an inclined field plate on a semiconductor device (such as an LDMOS structure), thereby achieving more continuous control of the surface electric field through the inclined field plate, reducing the occurrence of peak electric fields, and improving the device's withstand voltage.

[0090] ② This application cleverly utilizes the loading effect of plasma etching, where the etching rate is related to the pattern size and density, and the etching rate is slower in small window patterns. By designing a layout with gradient window sizes, a tilted field plate can be formed in a single plasma etching and wet etching process, reducing the frequent use of photomasks and process steps in the manufacturing of tilted field plates, thereby lowering manufacturing costs.

[0091] ③ This application optimizes the layout based on actual process requirements. Specifically, by setting blocking areas of equal width, the separation structures between trenches are etched simultaneously. By using window areas with varying equidistant spacing, the continuous variation of trench etching depth is controlled to ensure the continuity of the inclined field plate.

[0092] ④ The photoresist layout provided in this application has the ability to expand design capabilities. In addition to unidirectional tilted field plates, multidirectional tilted field plates and combinations of tilted field plates and horizontal field plates can also be formed by adjusting the corresponding window width, which has strong adaptability.

[0093] ⑤ Although this application mainly relates to the fabrication of tilted field plates in interlayer dielectrics, its principle can also be applied to other semiconductor structures, and other tilted grooves / field plates can be fabricated through adaptive adjustments.

[0094] The embodiments disclosed above are merely illustrative of this application. The embodiments do not exhaustively describe all details, nor do they limit this application to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to better understand and utilize this application. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The manufacturing method includes: A substrate is provided, the substrate comprising a plurality of semiconductor structures; A patterned photoresist layer is formed on the substrate, wherein the patterned photoresist layer includes a plurality of window regions distributed along a target direction and a plurality of blocking regions, the blocking regions being used to isolate adjacent window regions, and the opening width of at least a portion of the continuous window regions gradually changes along the target direction. A plasma etching process is performed using the patterned photoresist layer as a mask to form trenches in the substrate at positions corresponding to the window region. Separation structures of the trenches are formed in the substrate at positions corresponding to the blocking region. The etching depth of the trenches is positively correlated with the opening width of the corresponding window. Remove the photoresist layer; Remove the separation structure between the various grooves to form a field plate groove, wherein the field plate groove includes an inclined bottom surface corresponding to the at least part of the continuous window area; An inclined field plate of the semiconductor structure is formed on the inclined bottom surface of the field plate groove.

2. The manufacturing method according to claim 1, characterized in that, The opening widths of the multiple window regions vary equidistantly along the target direction.

3. The manufacturing method according to claim 2, characterized in that, The semiconductor structure is configured as a laterally diffused metal-oxide semiconductor, and the minimum opening width of the plurality of window regions ranges from 0.09 μm to 0.18 μm, while the width variation of the opening width between adjacent window regions ranges from 0.005 μm to 0.02 μm.

4. The manufacturing method according to claim 2, characterized in that, The width of the blocking areas is the same.

5. The manufacturing method according to claim 4, characterized in that, The width of the blocking area ranges from 0.09μm to 0.3μm.

6. The manufacturing method according to claim 1, characterized in that, The patterned photoresist layer forms a first range of window regions and / or a second range of window regions based on the tilt of the tilted field plate, wherein the tilt of the tilted field plate formed by the first range of window regions is different from the tilt of the tilted field plate formed by the second range of window regions. The opening width of the window area within the first range increases along the target direction, and the opening width of the window area within the second range decreases along the target direction.

7. The manufacturing method according to claim 1, characterized in that, The inclined field plate forming the semiconductor structure on the inclined bottom surface of the field plate groove includes: A first deposition process is performed on the field plate material based on the inclined field plate to form a first deposition layer, wherein the first deposition layer includes an inclined field plate deposited on the inclined bottom surface of the field plate groove, a sidewall deposition structure deposited on the groove sidewall of the field plate groove, and a substrate deposition structure deposited on the substrate surface. Fill the groove in the field plate.

8. The manufacturing method according to claim 7, characterized in that, The filling of the groove in the field plate includes: A second deposition process is performed to form a second deposition layer; A chemical mechanical polishing process is performed on the substrate surface below the second deposited layer as a stop layer to remove the second deposited layer outside the field plate groove.

9. The manufacturing method according to claim 1, characterized in that, The process of forming a patterned photoresist layer on the substrate includes: A photoresist layer is formed on the substrate; An optical etching process is performed on the photoresist layer based on the etching pattern of the multiple window regions to form the patterned photoresist layer.

10. A semiconductor device, characterized in that, The semiconductor device is formed based on the manufacturing method according to any one of claims 1 to 9.

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