Gallium nitride semiconductor power device and manufacturing method thereof

Abstract

The present invention discloses a gallium nitride semiconductor power device and a manufacturing method thereof, the manufacturing method comprising the following steps: a. providing a substrate, and growing a passivation layer on the substrate; b. preparing an ohmic metal layer; c. preparing a dielectric stack; d. forming a first gate field plate region; f. forming a gate region; g. preparing a first gate field plate, a second gate field plate and a gate; h. preparing an interlayer dielectric layer; i. preparing a source. The present invention also provides a gallium nitride semiconductor power device. The present invention forms a gate region and a gate field plate region by manufacturing a dielectric stack on the passivation layer, and then etches the dielectric stack according to the positions of the gate and the gate field plate, and then manufactures the gate and the gate field plate in the gate region and the gate field plate region respectively, which not only simplifies the manufacturing process, but also reduces the manufacturing cost. The semiconductor power device manufactured by the present invention has the characteristics of small size and good product quality.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a gallium nitride semiconductor power device and a manufacturing method thereof. Background Art

[0002] Gallium nitride is a wide bandgap semiconductor material with the advantages of high efficiency, high frequency, and low energy consumption. It has broad application prospects in the field of power electronic devices. Compared with traditional silicon power electronic devices, gallium nitride power electronic devices have higher operating frequencies and lower energy losses, and can complete the same power conversion tasks in a shorter time, thereby improving energy utilization efficiency. Therefore, in recent years, gallium nitride power electronic devices have become a research hotspot in the field of electronic power.

[0003] In the process of manufacturing the gate and gate field plate of existing gallium nitride power devices, dielectric layers and gates / gate field plates are usually alternated, that is, a dielectric layer is first made, and then a gate is made on the dielectric layer, and then another dielectric layer is made, and then a gate field plate is made on the dielectric layer, until the gate field plate is completed. The existing manufacturing method has problems such as complex process, high cost, and large size of the power device, which affects its performance to a certain extent. Therefore, how to simplify the existing preparation process of gallium nitride power devices, reduce costs, and produce small-sized gallium nitride power devices has become an urgent problem to be solved. Summary of the invention

[0004] The present invention provides a method for manufacturing a gallium nitride semiconductor power device, which is used to solve the problems of complex process, high cost and large size of the manufactured device in the existing gallium nitride semiconductor power device manufacturing process.

[0005] To achieve the purpose of the present invention, the present invention provides a method for manufacturing a gallium nitride semiconductor power device, the method comprising the following steps:

[0006] a. providing a substrate, wherein the substrate is a gallium nitride substrate, and growing a passivation layer on the substrate;

[0007] b. Preparing an ohmic metal layer: forming an ohmic metal layer at a source position on the passivation layer;

[0008] c. Preparing a dielectric stack: forming a dielectric stack on the passivation layer and the ohmic metal layer, the dielectric stack comprising a first dielectric layer, a first etch stop layer, a second dielectric layer, a second etch stop layer and a third dielectric layer stacked from top to bottom;

[0009] d. Forming a first gate field plate region: forming a first gate field plate region on the first dielectric layer;

[0010] e. Forming a second gate field plate region: forming a second gate field plate region on the second dielectric layer;

[0011] f. Forming a gate region: forming a gate region on the third dielectric layer;

[0012] g. Preparing a first gate field plate, a second gate field plate and a gate: forming a first gate field plate, a second gate field plate and a gate in a first gate field plate region, a second gate field plate region and a gate region respectively;

[0013] h. Preparing an interlayer dielectric layer: forming an interlayer dielectric layer on the upper surface of the first gate field plate, the second gate field plate, the gate, and the third dielectric layer from the gate region to the source region;

[0014] i. Prepare the source electrode: make a source contact hole at the source position on the interlayer dielectric layer and the third dielectric layer, and form a source electrode in the contact hole, wherein the source electrode is electrically connected to the ohmic metal layer.

[0015] Furthermore, in step c, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, and the materials of the first etch stop layer and the second etch stop layer are both aluminum nitride.

[0016] In step d, the step of forming a first gate field plate region on the first dielectric layer includes:

[0017] forming a first photoresist layer on the first dielectric layer at the first gate field plate position, etching the first dielectric layer at positions other than the first gate field plate, and removing the first etching stopper layer at positions other than the first gate field plate;

[0018] The first photoresist layer is then removed to form the first gate field plate region.

[0019] In step e, the step of forming a second gate field plate region on the second dielectric layer includes:

[0020] Forming a second photoresist layer on the second dielectric layer in the first gate field plate region and the second gate field plate position, etching the second dielectric layer at positions other than the second gate field plate, and removing the second etching stop layer at positions other than the second gate field plate;

[0021] The second photoresist layer is then removed to form a second gate field plate region.

[0022] In step f, the step of forming a gate region on the third dielectric layer includes:

[0023] Forming a third photoresist layer at a non-gate position, and etching the third dielectric layer at a gate position to form a gate region;

[0024] The third photoresist layer is then removed.

[0025] The steps of step g include:

[0026] A metal layer is deposited on the upper surface of the third dielectric layer from the first gate field plate region, the second gate field plate region, the gate region and the source region, and metal etching is performed on the first gate field plate region, the second gate field plate region and the region outside the gate region to form a first gate field plate, a second gate field plate and a gate.

[0027] The steps of step i include:

[0028] The interlayer dielectric layer and the third dielectric layer at the source position are etched respectively, a source contact hole is made at the source position, and a source is formed in the contact hole.

[0029] The present invention also provides a gallium nitride semiconductor power device, which comprises a gallium nitride substrate, a passivation layer, a dielectric stack and an interlayer dielectric layer which are stacked in sequence, wherein the dielectric stack comprises a first dielectric layer, a first etch barrier layer, a second dielectric layer, a second etch barrier layer and a third dielectric layer which are stacked from top to bottom, a first gate field plate is provided between the first dielectric layer and the interlayer dielectric layer, a second gate field plate is provided between the second dielectric layer and the interlayer dielectric layer, a gate is provided between the passivation layer and the interlayer dielectric layer, an ohmic metal layer which is isolated from the gate is provided between the third dielectric layer and the passivation layer, and a source electrode which is electrically connected to the ohmic metal layer is provided in the interlayer dielectric layer and the third dielectric layer.

[0030] Furthermore, the first gate field plate and the second gate field plate are arranged on a side of the gate away from the source, and the second gate field plate and the first gate field plate are stepped field plates extending upward step by step toward the side away from the source, and the second gate field plate is connected to the first gate field plate and the gate respectively.

[0031] Further, the first gate field plate has a rectangular cross section, an upper surface and a side portion thereof are respectively connected to a portion of the interlayer dielectric layer, and a lower surface thereof is connected to an upper surface of the first dielectric layer;

[0032] The second gate field plate has a rectangular cross section, an upper surface and a side portion close to the source electrode are respectively connected to a portion of the interlayer dielectric layer, a lower surface is connected to a portion of the upper surface of the second dielectric layer, and another side portion is respectively connected to a side portion of the first dielectric layer and a side portion of the first etching stop layer;

[0033] The cross-section of the gate is "T"-shaped, the upper surface of its horizontal part and a side close to the source are respectively connected to a portion of the interlayer dielectric layer, the lower surface of its horizontal part is connected to a portion of the upper surface of the third dielectric layer, the other side of its horizontal part is respectively connected to the side of the second dielectric layer and the side of the second etching stop layer, and the vertical part passes through the third dielectric layer and is connected to the passivation layer.

[0034] The beneficial effects of the present invention are:

[0035] In the manufacturing process of the gallium nitride semiconductor power device of the present invention, a dielectric stack is manufactured on the passivation layer, and then the dielectric stack is etched according to the positions of the gate and the gate field plate to form a gate region and a gate field plate region, and then the gate and the gate field plate are manufactured in the gate region and the gate field plate region respectively, which not only simplifies the manufacturing process but also reduces the manufacturing cost.

[0036] On the other hand, when preparing the gate and the gate field plate, the dielectric stack is etched while the dielectric stack from the gate area to the source area is etched. After the gate and the gate field plate are completed, the source contact hole is immediately made, so that there are only interlayer dielectric layers and the third dielectric layer around the source contact hole. Not only is the structure simple, but the quality of the made source contact hole is also better.

[0037] In addition, since the first gate field plate and the second gate field plate are arranged on the side of the gate away from the source, the distance (Lgs) between the gate and the source can be reduced, the device volume can be reduced, and the electric field distribution between the gate and the source can be optimized. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flow chart of the method of embodiment 1 of the present invention.

[0039] Figure 2 It is a cross-sectional view of the structure obtained after executing step S10 in Example 1 of the present invention.

[0040] Figure 3 It is a cross-sectional view of the structure obtained after executing step S20 in Example 1 of the present invention.

[0041] Figure 4 It is a cross-sectional view of the structure obtained after executing step S30 in Example 1 of the present invention.

[0042] Figure 5 It is a cross-sectional view of the structure obtained after executing step S41 in Example 1 of the present invention.

[0043] Figure 6 It is a cross-sectional view of the structure obtained after executing step S42 in Example 1 of the present invention.

[0044] Figure 7It is a cross-sectional view of the structure obtained after executing step S43 in Example 1 of the present invention.

[0045] Figure 8 It is a cross-sectional view of the structure obtained after executing step S51 in Example 1 of the present invention.

[0046] Fig. 9 It is a cross-sectional view of the structure obtained after executing step S52 in Example 1 of the present invention.

[0047] Fig.10 It is a cross-sectional view of the structure obtained after executing step S53 in Example 1 of the present invention.

[0048] Fig.11 It is a cross-sectional view of the structure obtained after executing step S61 in Example 1 of the present invention.

[0049] Fig.12 It is a cross-sectional view of the structure obtained after executing step S62 in Example 1 of the present invention.

[0050] Fig.13 It is a cross-sectional view of the structure obtained after executing step S63 in Example 1 of the present invention.

[0051] Fig.14 It is a cross-sectional view of the structure obtained after executing step S70 in Example 1 of the present invention.

[0052] Fig.15 It is a cross-sectional view of the structure obtained after executing step S80 in Example 1 of the present invention.

[0053] Fig.16 It is a cross-sectional view of a structure obtained by forming a source contact hole in step S90 according to embodiment 1 of the present invention.

[0054] Fig.17 It is a cross-sectional view of the structure obtained after executing step S90 in embodiment 1 of the present invention.

[0055] Fig.18 It is a structural diagram of embodiment 2 of the present invention.

[0056] In the figure, 10, substrate, 20, passivation layer, 30, ohmic metal layer, 40, dielectric stack, 41, first dielectric layer, 42, first etch stop layer, 43, second dielectric layer, 44, second etch stop layer, 45, third dielectric layer, 46, first photoresist layer, 47, second photoresist layer, 48, third photoresist layer, 50, first gate field plate, 60, second gate field plate, 70, gate, 80, interlayer dielectric layer, 90, source. DETAILED DESCRIPTION

[0057] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0058] Example 1

[0059] See also Figure 1 The gallium nitride semiconductor power device prepared in this embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.

[0060] Specifically, Figure 1 As shown, the manufacturing method of the gallium nitride semiconductor power device of this embodiment includes the following steps:

[0061] S10 , providing a substrate 10 , and growing a passivation layer 20 on the substrate 10 .

[0062] In this step, if Figure 2 As shown, the substrate 10 is a gallium nitride substrate, and a passivation layer 20 is deposited on the substrate 10 by metal organic chemical vapor deposition (MOCVD) or plasma enhanced chemical vapor deposition (PECVD). The passivation layer 20 is made of silicon nitride or silicon dioxide material, which serves as a gate insulator to prevent gate leakage current.

[0063] S20 , preparing an ohmic metal layer 30 .

[0064] In this step, if Figure 3 As shown, an ohmic metal layer 30 is formed at the source position on the passivation layer 20. The ohmic metal layer 30 is formed at the source position on the passivation layer 20 by metal deposition. The material of the ohmic metal layer 30 can be titanium, aluminum, titanium nitride alloy, etc., which is used to be electrically connected to the source 90.

[0065] S30 , preparing a dielectric stack 40 .

[0066] In this step, if Figure 4 As shown, a dielectric stack 40 is formed on the passivation layer 20 and the ohmic metal layer 30 to define electrodes and achieve electrical separation. The dielectric stack 40 can be deposited on the passivation layer 20 and the ohmic metal layer 30 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The dielectric stack 40 includes multiple dielectric layers and an etching barrier layer provided between two adjacent dielectric layers. By providing the etching barrier layer, it can be ensured that the etching of the upper dielectric layer does not affect the lower dielectric layer, thereby ensuring the thickness uniformity of the same dielectric layer. The thickness of each dielectric layer and the etching barrier layer can be set according to actual needs. Figure 4 In the illustrated embodiment, the dielectric stack 40 includes a first dielectric layer 41, a first etch stop layer 42, a second dielectric layer 43, a second etch stop layer 44, and a third dielectric layer 45 stacked from top to bottom. Specifically, the materials of the first dielectric layer 41, the second dielectric layer 43, and the third dielectric layer 45 are one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride, and aluminum oxide. In this embodiment, the materials of the first dielectric layer 41, the second dielectric layer 43, and the third dielectric layer 45 are silicon nitride. The materials of the first etch stop layer 42 and the second etch stop layer 44 are aluminum nitride, which are used to ensure the uniformity of the thickness of the second dielectric layer 43 and the third dielectric layer 45, respectively.

[0067] S40 , forming a first gate field plate region.

[0068] In this step, if Figure 5 , Figure 6 and Figure 7 As shown, a first gate field plate region is formed on the first dielectric layer 41 , and the first gate field plate region is arranged on a side of the gate region away from the source region.

[0069] Specifically, the step includes:

[0070] S41, forming a first photoresist layer.

[0071] like Figure 5 As shown, in order to retain the first dielectric layer 41 located in the first gate field plate region, a first photoresist layer 46 may be filled at the first gate field plate position so that the first photoresist layer 46 covers the surface of the first dielectric layer 41 located in the first gate field plate region.

[0072] S42 , etching the first dielectric layer 41 and the first etching stop layer 42 .

[0073] like Figure 6 As shown, the first dielectric layer 41 in the non-first gate field plate region is etched, and after the first dielectric layer 41 is etched, the first etch barrier layer 42 in the non-first gate field plate region is etched, and the surface of the first dielectric layer 41 in the first gate field plate region is covered by the first photoresist layer 46, and thus is retained. The first dielectric layer 41 may be etched by a dry etching method or a wet etching method, and the first etch barrier layer 42 may be etched by the same method as that of the first dielectric layer 41, and only the etching conditions are changed to simplify the process and improve the etching efficiency.

[0074] S43 , removing the first photoresist layer 46 .

[0075] like Figure 7As shown, after etching the first dielectric layer 41 and the first etching stop layer 42 in the non-first gate field plate region, the first photoresist layer 46 is removed to form the first gate field plate region. The first photoresist layer 46 can be removed by dry etching or wet etching.

[0076] S50 , forming a second gate field plate region.

[0077] In this step, if Figure 8 , Fig. 9 and Fig.10 As shown, a second gate field plate region is formed on the second dielectric layer 43 , and the second gate field plate region is arranged on a side of the first gate field plate region away from the source region.

[0078] Specifically, the step includes:

[0079] S51 , forming a second photoresist layer 47 .

[0080] like Figure 8 As shown, in order to retain the second dielectric layer 43 and the first gate field plate region located in the second gate field plate region, a second photoresist layer 47 can be filled on the second dielectric layer 43 at the second gate field plate position and the first gate field plate region, so that the second photoresist layer 47 covers the surface of the first dielectric layer 41 located in the first gate field plate region and the surface of the second dielectric layer 43 located in the second gate field plate region.

[0081] S52 , etching the second dielectric layer 43 and the second etching stop layer 44 .

[0082] like Fig. 9 As shown, the second dielectric layer 43 in the non-second gate field plate region is etched, and after the second dielectric layer 43 is etched, the second etching stop layer 44 in the non-second gate field plate region is etched. Since the surface of the second dielectric layer 43 in the first gate field plate region and the surface of the second dielectric layer 43 in the second gate field plate region are covered by the second photoresist layer 47, they are retained. The etching of the second dielectric layer 43 can be performed by a dry etching method or a wet etching method, and the etching of the second etching stop layer 44 can be performed by the same method as that of etching the second dielectric layer 43, and only the etching conditions are changed to simplify the process and improve the etching efficiency.

[0083] S53 , removing the second photoresist layer 47 .

[0084] like Fig.10 As shown, after etching the second dielectric layer 43 and the second etching stop layer 44, the second photoresist layer 47 is removed to form a second gate field plate region. The second photoresist layer 47 can be removed by dry etching or wet etching.

[0085] S60 , forming a gate region.

[0086] In this step, if Fig.11 , Fig.12 and Fig.13 As shown, a gate region is formed on the third dielectric layer 45 .

[0087] Specifically, the step includes:

[0088] S61 , forming a third photoresist layer 48 .

[0089] like Fig.11 As shown, in order to etch the third dielectric layer 45 at the gate position, a third photoresist layer 48 may be formed at the non-gate position to reserve the dielectric layer at the non-gate position.

[0090] S62 , etching the third dielectric layer 45 .

[0091] like Fig.12 As shown, the third dielectric layer 45 at the gate position is etched to form a gate region. The etching of the third dielectric layer 45 can be performed by dry etching or wet etching.

[0092] S63 , removing the third photoresist layer 48 .

[0093] like Fig.13 As shown, after etching the third dielectric layer 45, the third photoresist layer 48 is removed to expose the first gate field plate region, the second gate field plate region, the gate region and the third dielectric layer 45 between the gate and the source. The third photoresist layer 48 can be removed by dry etching or wet etching.

[0094] S70 , preparing a first gate field plate 50 , a second gate field plate 60 and a gate 70 .

[0095] In this step, if Fig.14As shown, a first gate field plate, a second gate field plate and a gate are formed in the first gate field plate region, the second gate field plate region and the gate region, respectively. Specifically, a metal layer is deposited on the surface of the first dielectric layer 41 in the first gate field plate region, the second dielectric layer 43 in the second gate field plate region, the third dielectric layer 45 in the gate region and the third dielectric layer 45 between the gate and the source, and the metal layer in the first gate field plate region, the second gate field plate region and the region outside the gate region is subjected to metal etching to form a first gate field plate 50, a second gate field plate 60 and a gate 70. In this embodiment, the first gate field plate 50 and the second gate field plate 60 are arranged on the side of the gate 70 away from the source 90, and the second gate field plate 60 and the first gate field plate 50 are step-type field plates extending upward step by step toward the side away from the source 90, and the second gate field plate 60 is connected to the first gate field plate 50 and the gate 70, respectively. The materials of the first gate field plate 50, the second gate field plate 60 and the gate 70 include but are not limited to Al, Ti, and TiN.

[0096] S80 , preparing an interlayer dielectric layer 80 .

[0097] In this step, if Fig.15 As shown, an interlayer dielectric layer 80 is formed on the upper surface of the first gate field plate 50, the second gate field plate 60, the gate 70 and the third dielectric layer 45 from the gate region to the source region. The interlayer dielectric layer 80 can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition.

[0098] S90 , preparing a source electrode 90 .

[0099] In this step, if Fig.16 , Fig.17 As shown, a source contact hole is made at the source position on the interlayer dielectric layer 80 and the third dielectric layer 45, and a source 90 is formed in the contact hole, and the source 90 is electrically connected to the ohmic metal layer 30. Specifically, the interlayer dielectric layer 80 and the third dielectric layer 45 at the source position are etched respectively, a source contact hole is made at the source position, and a source 90 is formed in the contact hole. The interlayer dielectric layer 80 and the third dielectric layer 45 at the source position are removed by dry etching or wet etching. The source 90 can be made by metal evaporation such as magnetron sputtering, electron beam evaporation, thermal evaporation, etc.

[0100] In the manufacturing process of the gallium nitride semiconductor power device of this embodiment, a dielectric stack 40 is first manufactured on the passivation layer 20, and then the first dielectric layer 41 is etched according to the position of the first gate field plate 50, the second dielectric layer 43 is etched according to the position of the second gate field plate 60, and the third dielectric layer 45 is etched according to the position of the gate 70, and the first gate field plate 50, the second gate field plate 60 and the gate 70 are arranged at the first gate field plate position, the second gate field plate position and the gate position, respectively, which not only simplifies the manufacturing process of the gate and the gate field plate, but also reduces the manufacturing cost.

[0101] On the other hand, when preparing the first gate field plate 50, the second gate field plate 60 and the gate 70, while etching the dielectric stack 40, the dielectric stack from the gate area to the source area is also etched synchronously. After the first gate field plate 50, the second gate field plate 60 and the gate 70 are completed, the source contact hole is immediately made, so that there are only the interlayer dielectric layer 80 and the third dielectric layer 45 around the source contact hole. Not only is the structure simple, but the quality of the made source contact hole is also better.

[0102] In addition, since the first gate field plate 50 and the second gate field plate 60 are arranged on the side of the gate away from the source, and no gate field plate is arranged between the gate 70 and the source 90, the distance between the gate and the source can be reduced, the device volume can be reduced, and the electric field distribution between the gate and the source can be optimized.

[0103] Example 2

[0104] like Fig.18 As shown, the gallium nitride semiconductor power device of this embodiment includes a gallium nitride substrate 10, a passivation layer 20, a dielectric stack 40 and an interlayer dielectric layer 80 which are stacked in sequence, an ohmic metal layer 30 and a gate 70 are provided between the passivation layer 20 and the dielectric stack 40, and a gate field plate and a source 90 are provided between the dielectric stack 40 and the interlayer dielectric layer 80. The gallium nitride semiconductor power device prepared in this embodiment is a D-type gallium nitride high electron mobility transistor, which can be used as a high-power application device such as a switching device or an amplifier device.

[0105] like Fig.18 As shown, the substrate 10 is a gallium nitride substrate, and a passivation layer 20 is provided on the upper surface of the substrate 10. The passivation layer 20 serves as a gate insulator to prevent gate leakage current. An ohmic metal layer 30 is formed at the source position on the passivation layer 20 for electrical connection with the source 90. The cross section of the ohmic metal layer 30 is "T" shaped, the lower surface of the horizontal part thereof is connected to the upper surface of the passivation layer 20, and the vertical part thereof is provided in the passivation layer 20.

[0106] like Fig.18As shown, a dielectric stack 40 is provided on the passivation layer 20 and the ohmic metal layer 30 to define the electrodes and realize electrical separation. The dielectric stack 40 includes a plurality of dielectric layers and an etching barrier layer provided between two adjacent dielectric layers. By providing the etching barrier layer, the thickness uniformity of the dielectric layer under the etching barrier layer can be ensured. The thickness of each dielectric layer and the etching barrier layer can be set according to actual needs. A gate 70 and a gate field plate are provided on the dielectric stack 40, an interlayer dielectric layer 80 is provided on the gate 70 and the gate field plate, and a source 90 is provided on the interlayer dielectric layer 80, and the source is electrically connected to the ohmic metal layer 30.

[0107] Specifically, Fig.18 In the illustrated embodiment, the dielectric stack 40 includes a first dielectric layer 41, a first etch stop layer 42, a second dielectric layer 43, a second etch stop layer 44, and a third dielectric layer 45 stacked from top to bottom. The gate field plate includes a first gate field plate 50 and a second gate field plate 60. The first gate field plate 50 is disposed on the first dielectric layer 41 on the side of the gate region away from the source region. The cross section of the first gate field plate 50 is rectangular, and its lower surface covers the upper surface of the first dielectric layer 41. The second gate field plate 60 is located on the second dielectric layer 43 on the side of the gate region away from the source region, and is connected to the first gate field plate 50. The cross section of the second gate field plate 60 is rectangular, and its lower surface covers a portion of the upper surface of the second dielectric layer 43, and its side away from the source 90 is connected to the side of the first dielectric layer 41 and the side of the first etch stop layer 42. The gate 70 is located on the third dielectric layer 45, which is connected to the second gate field plate 60 and is spaced apart from the ohmic metal layer 30. The cross-section of the gate 70 is "T"-shaped, with the lower surface of its horizontal portion connected to the upper surface of a portion of the third dielectric layer 45, and the side of its horizontal portion away from the source 90 connected to the side of the second dielectric layer 43 and the side of the second etching stop layer 44 respectively, and its vertical portion passes through the third dielectric layer 45 and is connected to the passivation layer 20.

[0108] The materials of the first dielectric layer 41, the second dielectric layer 43 and the third dielectric layer 45 are silicon nitride, and the materials of the first etching stop layer 42 and the second etching stop layer 44 are both aluminum nitride. Since the etching conditions of silicon nitride and aluminum nitride are different, the thickness uniformity of the underlying aluminum nitride layer can be better guaranteed when etching silicon nitride. Similarly, the thickness uniformity of the underlying silicon nitride layer can be better guaranteed when etching aluminum nitride.

[0109] like Fig.18As shown, an interlayer dielectric layer 80 is provided on the gate field plate and the gate 70, and the interlayer dielectric layer 80 covers the upper surface of the first gate field plate 50 and a side portion close to the source, covers the upper surface of the second gate field plate 60 and a side portion close to the source, covers the upper surface of the horizontal portion of the gate 70 and a side portion close to the source, and covers a portion of the upper surface of the third dielectric layer 45. A source contact hole is provided at the source position of the third dielectric layer 45, and the source contact hole penetrates from the upper surface of the interlayer dielectric layer 80 to the lower surface of the third dielectric layer 45. A source 90 is provided in the source contact hole, and is electrically connected to the ohmic metal layer 30. The cross section of the source 90 is "T" shaped, and the lower surface of its horizontal portion is connected to the upper surface of a portion of the interlayer dielectric layer 80, and its vertical portion is provided in the source contact hole, so that the vertical portion of the source 90 passes through the interlayer dielectric layer 80 and the third dielectric layer 45 in sequence and is connected to the ohmic metal layer 30.

[0110] like Fig.18 As shown, the first gate field plate 50 and the second gate field plate 60 of this embodiment are arranged on the side of the gate region away from the source region, and no gate field plate is arranged on the side of the gate region and the source region. Therefore, the distance between the gate and the source can be reduced, the device volume can be reduced, and the electric field distribution between the gate and the source can be optimized. On the other hand, since there are only the interlayer dielectric layer 80 and the third dielectric layer 45 around the source contact hole, the structure around the source contact hole is simple, and the quality of the prepared source contact hole is better.

[0111] Although the present invention is disclosed through the above embodiments, the protection scope of the present invention is not limited thereto. Without departing from the concept of the present invention, any deformation, replacement, etc. made to the above components shall fall within the scope of the claims of the present invention.

Claims

1. A method for manufacturing a gallium nitride semiconductor power device, characterized in that: The method comprises the following steps: a. providing a substrate, wherein the substrate is a gallium nitride substrate, and growing a passivation layer on the substrate; b. Preparing an ohmic metal layer: forming an ohmic metal layer at a source position on the passivation layer; c. Preparing a dielectric stack: forming a dielectric stack on the passivation layer and the ohmic metal layer, the dielectric stack comprising a first dielectric layer, a first etch stop layer, a second dielectric layer, a second etch stop layer and a third dielectric layer stacked from top to bottom; d. Forming a first gate field plate region: forming a first gate field plate region on the first dielectric layer; e. Forming a second gate field plate region: forming a second gate field plate region on the second dielectric layer; f. Forming a gate region: forming a gate region on the third dielectric layer; g. Preparing a first gate field plate, a second gate field plate and a gate: forming a first gate field plate, a second gate field plate and a gate in a first gate field plate region, a second gate field plate region and a gate region respectively; h. Preparing an interlayer dielectric layer: forming an interlayer dielectric layer on the upper surface of the first gate field plate, the second gate field plate, the gate, and the third dielectric layer from the gate region to the source region; i. Prepare the source electrode: make a source contact hole at the source position on the interlayer dielectric layer and the third dielectric layer, and form a source electrode in the contact hole, wherein the source electrode is electrically connected to the ohmic metal layer; In step d, the step of forming a first gate field plate region on the first dielectric layer includes: forming a first photoresist layer on the first dielectric layer at the first gate field plate position, etching the first dielectric layer at positions other than the first gate field plate, and removing the first etching stopper layer at positions other than the first gate field plate; Then removing the first photoresist layer to form the first gate field plate region; In step e, the step of forming a second gate field plate region on the second dielectric layer includes: Forming a second photoresist layer on the second dielectric layer in the first gate field plate region and the second gate field plate position, etching the second dielectric layer at positions other than the second gate field plate, and removing the second etching stop layer at positions other than the second gate field plate; Then removing the second photoresist layer to form a second gate field plate region; In step f, the step of forming a gate region on the third dielectric layer includes: Forming a third photoresist layer at a non-gate position, and etching the third dielectric layer at a gate position to form a gate region; The third photoresist layer is then removed.

2. The method for manufacturing a gallium nitride semiconductor power device according to claim 1, characterized in that: In step c, the materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are one or a combination of two or more of silicon nitride, silicon oxide, aluminum nitride and aluminum oxide, and the materials of the first etch stop layer and the second etch stop layer are both aluminum nitride.

3. The method for manufacturing a gallium nitride semiconductor power device according to claim 1, wherein: The steps of step g include: A metal layer is deposited on the upper surface of the third dielectric layer from the first gate field plate region, the second gate field plate region, the gate region and the source region, and metal etching is performed on the first gate field plate region, the second gate field plate region and the region outside the gate region to form a first gate field plate, a second gate field plate and a gate.

4. The method for manufacturing a gallium nitride semiconductor power device according to claim 1, wherein: The steps of step i include: The interlayer dielectric layer and the third dielectric layer at the source position are etched respectively, a source contact hole is made at the source position, and a source is formed in the contact hole.

5. A gallium nitride semiconductor power device prepared by the method according to any one of claims 1 to 4, characterized in that: The power device comprises a gallium nitride substrate, a passivation layer, a dielectric stack and an interlayer dielectric layer which are stacked in sequence, wherein the dielectric stack comprises a first dielectric layer, a first etch barrier layer, a second dielectric layer, a second etch barrier layer and a third dielectric layer which are stacked from top to bottom, a first gate field plate is arranged between the first dielectric layer and the interlayer dielectric layer, a second gate field plate is arranged between the second dielectric layer and the interlayer dielectric layer, a gate is arranged between the passivation layer and the interlayer dielectric layer, an ohmic metal layer which is isolated from the gate is arranged between the third dielectric layer and the passivation layer, and a source electrode which is electrically connected to the ohmic metal layer is arranged in the interlayer dielectric layer and the third dielectric layer.

6. The gallium nitride semiconductor power device according to claim 5, characterized in that: The first gate field plate and the second gate field plate are arranged on a side of the gate away from the source, and the second gate field plate and the first gate field plate are step-type field plates extending upward step by step toward the side away from the source, and the second gate field plate is connected to the first gate field plate and the gate respectively.

7. The gallium nitride semiconductor power device according to claim 6, characterized in that: The first gate field plate has a rectangular cross section, an upper surface and a side portion thereof are respectively connected to a portion of the interlayer dielectric layer, and a lower surface thereof is connected to an upper surface of the first dielectric layer; The second gate field plate has a rectangular cross section, an upper surface and a side portion close to the source electrode are respectively connected to a portion of the interlayer dielectric layer, a lower surface is connected to a portion of the upper surface of the second dielectric layer, and another side portion is respectively connected to a side portion of the first dielectric layer and a side portion of the first etching stop layer; The cross section of the gate is "T"-shaped, the upper surface of its horizontal part and a side close to the source are respectively connected to a portion of the interlayer dielectric layer, the lower surface of its horizontal part is connected to a portion of the upper surface of the third dielectric layer, the other side of its horizontal part is respectively connected to the side of the second dielectric layer and the side of the second etching stop layer, and the vertical part passes through the third dielectric layer and is connected to the passivation layer.

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