Manufacturing method of high-voltage planar silicon controlled rectifier

Abstract

The invention provides a manufacturing method of a high-voltage planar silicon controlled rectifier, which is characterized in that extended junctions surround the peripheral edge of a front P-type base region, the diameters of the extended junctions are different, and the extended junctions are gradually reduced along the direction far away from the front P-type base region, so that the doping concentration can be continuously and linearly decreased towards the edge direction along the front P-type base region; meanwhile, the doping concentration is gradually reduced, so that the junction depth is gradually reduced, the main junction electric field can be effectively improved, the size of the terminal is further reduced, and the chip area is reduced; and the composite passive film is formed on the front surface of the silicon wafer, so that an external electric field can be shielded, surface breakdown is avoided, reverse voltage resistance is improved, the silicon controlled rectifier is not easy to crack, and the performance of a silicon controlled rectifier product is more excellent.

Description

Technical Field

[0001] The invention belongs to the field of microelectronic technology, and in particular relates to a method for manufacturing a high-voltage planar thyristor. Background Art

[0002] Thyristor is a P1N1P2N2 four-layer three-terminal structure element with three PN junctions and three electrodes to the outside. It has the characteristics of small size, simple structure, high efficiency and long life, and can be used in controlled rectification, AC voltage regulation, protection, contactless electronic switch, inverter and frequency conversion fields, etc. At present, the high-voltage thyristor products produced need to meet the high-quality requirements of withstand voltage exceeding 1200V and leakage current less than 1uA. Therefore, it is necessary to optimize the terminal design and surface passivation protection of high-voltage thyristor products. Except for a few leading companies in China, the remaining manufacturers of existing high-voltage thyristor products basically use the table process for terminal surface protection, that is, a groove with a depth of more than 50um is corroded on the surface of the silicon wafer material, and the groove is filled with glass, but the total thickness of the silicon wafer is generally not more than 260um. The thermal expansion coefficient of glass is inconsistent with that of silicon. Therefore, the silicon wafer protected by the table glass is very easy to break, and the glass passivation process requires manual or electrophoretic coating of glass. The purity of glass is difficult to control. If there is external pollution, the leakage of thyristor will increase significantly. For this reason, a terminal structure of a planar conventional field plate divider ring with a floating potential ring is proposed. The potential ring can make the space charge area on the top surface of the semiconductor wider. This structure is the most frequently used terminal structure for planar thyristor products at this stage. Its advantages include that the silicon wafer will not bend during the process, the silicon wafer breakage rate during the process is low, the chip surface is flat, and the appearance is good. However, the disadvantage is that the terminal of the PN junction occupies more area, so the chip area required for products of the same specification will be larger. Therefore, the optimization of product junction terminals and surface passivation technology have always been the main topics of high-voltage thyristor products. Summary of the invention

[0003] In view of the above problems, the present invention provides a method for manufacturing a high-voltage planar thyristor, which can not only greatly reduce the fragmentation rate and leakage, but also reduce the size of the terminal and improve the utilization rate.

[0004] The present invention adopts the following technical scheme, a method for manufacturing a high-voltage planar thyristor, comprising the following steps:

[0005] S1. Select N-type single crystal silicon material and process it into silicon wafers, and then thermally generate an oxide layer on the surface of the silicon wafers;

[0006] S2, etching the front and back isolation patterns on the silicon wafer by a photolithography machine, and then removing the oxide layer on the area to be processed by hydrofluoric acid;

[0007] S3, coating the front and back surfaces of the silicon wafer with a boron source, and then performing high-temperature diffusion to penetrate the P-type layer on the front and back surfaces of the silicon wafer to form an isolation island;

[0008] S4, respectively etching the P-type region patterns on the front and back areas to be fabricated of the silicon wafer, then coating the surface of the P-type region patterns with a boron source and placing it in a high-temperature diffusion furnace for treatment, so that the boron source diffuses into the silicon wafer located in the P-type region patterns to form a front P-type base region and a back P-type base region, thereby forming a main junction of the thyristor;

[0009] S5. Photolithography is performed on the front side of the silicon wafer according to the pattern to form an extended junction around the edges of the front P-type base region, wherein the extended junction is formed by a number of extended circles evenly distributed around the edges of the front P-type base region, and high-temperature annealing and diffusion treatment is performed after boron ions are implanted into the extended circle, wherein the diameter of the extended circle gradually decreases as it moves away from the front P-type base region;

[0010] S6, etching an N+ emitter region on the surface of the front P-type base region and the back P-type base region, and etching a gate N+ region on the surface of the front P-type base region;

[0011] S7, rinsing the oxide layer on the surface of the silicon wafer, and depositing a polysilicon film, a silicon dioxide film, a silicon oxide film, and a silicon nitride film on the front side of the silicon wafer from bottom to top in order to form a composite passivation film;

[0012] S8, etching a metal contact area on the front side of the silicon wafer, and corroding the composite passivation film of the metal contact area, depositing an aluminum layer on the metal contact area and the back side of the silicon wafer respectively, photolithography a reverse pattern on the metal contact area using a photolithography machine, and corroding the aluminum layer outside the pattern, thereby forming the gate and T1 pole of the thyristor, and an isolation oxide layer is deposited on the metal contact area between the gate and T1 pole;

[0013] S9, continuing to deposit a titanium-nickel-silver alloy layer on the aluminum layer on the reverse side of the silicon wafer, thereby forming a T2 pole of the thyristor;

[0014] S10, performing low temperature treatment on the aluminum layer so that the aluminum layer forms a metal ohmic contact with the silicon wafer, and finally forming a thyristor chip.

[0015] Furthermore, the silicon wafer is made of N-type single crystal silicon material with a resistivity of 50 ohm centimeters and a thickness of 225 um;

[0016] Further, in step S5, the front P-type base region is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the expansion circle surrounds the edges of the front P-type base region in an annular direction, the diameter of the expansion circle close to the front P-type base region is larger than the diameter of the expansion circle away from the front P-type base region, and as the diameter of the expansion circle gradually decreases, the spacing between adjacent expansion circles in the same annular direction gradually increases;

[0017] Furthermore, in step S7, the following steps are also included:

[0018] S7.1, using LPCVD equipment, and setting the temperature at 650°C to 680°C, under the pressure condition of 280mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the LPCVD equipment for reaction, so as to deposit a polycrystalline silicon film with a thickness of 600nm to 700nm on the front side of the silicon wafer;

[0019] S7.2, depositing a silicon dioxide film with a thickness of 400nm to 500nm on the polysilicon film, and performing annealing after the deposition is completed;

[0020] S7.3, using a PECVD device, and setting the temperature at 300°C to 400°C, under a pressure of 180 mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the PECVD device for reaction, so as to deposit a silicon oxide film with a thickness of 200nm to 300nm on the silicon dioxide film;

[0021] S7.4, replacing the reaction gas in the PECVD device, that is, introducing 100cc to 150cc of silane and 50cc to 100cc of ammonia into the PECVD device for reaction to deposit a silicon nitride film with a thickness of 600nm to 700nm on the silicon oxide film;

[0022] Furthermore, in the step S8, the thickness of the aluminum layer on the metal contact area is 4um to 6um; the thickness of the aluminum layer on the back of the silicon wafer is 1um to 2um;

[0023] Furthermore, in the titanium-nickel-silver alloy layer, the thickness of titanium is 100nm-200nm, the thickness of nickel is 300nm-400nm, and the thickness of silver is 1000nm-1200nm.

[0024] The beneficial effects of the present invention are that an extended junction is arranged around the edges of the front P-type base region, the diameters of the extended circles are of different sizes, and gradually decrease as they are away from the front P-type base region, so that the doping concentration can be continuously and linearly decreased along the front P-type base region toward the edge, and at the same time, the doping concentration gradually decreases so that the junction depth is also gradually reduced, which can effectively improve the main junction electric field, thereby reducing the size of the terminal and the chip area; and a composite passivation film is formed on the front side of the silicon wafer, which can shield the external electric field, avoid surface breakdown, improve the reverse withstand voltage, and is not easy to crack, so that the performance of the thyristor product is more superior. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1It is a cross-sectional structural diagram of a chip produced by the present invention;

[0026] Figure 2 It is a schematic diagram of the structure of the composite passivation film in the present invention;

[0027] Figure 3 It is a distribution diagram of the expansion circle in the present invention;

[0028] Figure 4 It is a breakdown simulation curve diagram of the present invention. DETAILED DESCRIPTION

[0029] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0030] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0031] like Figure 1 to Figure 3 As shown, a method for manufacturing a high-voltage planar thyristor in the present invention comprises the following steps:

[0032] S1, select N-type single crystal silicon material to be processed into silicon wafer, and then thermally grow (i.e., by hydrogen-oxygen synthesis) an oxide layer with a thickness of 1.6um on the surface of silicon wafer 1; wherein, according to the high withstand voltage requirement of 1200V, silicon wafer 1 adopts N-type single crystal silicon material with a resistivity of 50 ohm centimeters and a thickness of 225um;

[0033] S2, etching the front and back isolation patterns on the silicon wafer 1 by a photolithography machine, and then removing the oxide layer on the area to be processed by hydrofluoric acid;

[0034] S3, coating the front and back surfaces of the silicon wafer 1 with a boron source, and then performing high-temperature diffusion in a high-temperature diffusion furnace to diffuse through the P-type layers on the front and back surfaces of the silicon wafer 1 to form an isolation island 2;

[0035] S4, respectively etching the P-type region patterns on the front and back areas to be fabricated of the silicon wafer 1, then coating the surface of the P-type region patterns with a boron source and placing it in a high-temperature diffusion furnace for treatment, so that the boron source diffuses into the silicon wafer 1 located in the P-type region patterns to form a front P-type base region 3 and a back P-type base region 4, thereby forming a main junction of the thyristor;

[0036] S5. Photolithography is performed on the front side of the silicon wafer 1 according to the photolithography pattern to form an extended junction 5 around the edges of the front P-type base region 3, which can form a continuous decreasing distribution of impurities from the main junction to the edge direction; the front P-type base region 3 is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the extended junction 5 is formed by a number of extended circles 14 uniformly distributed around the edges of the front P-type base region 3, and the extended circles 14 surround the edges of the front P-type base region 3 in an annular direction. After boron ions are injected into the extended circles 14, high-temperature annealing and diffusion treatment are performed, wherein the diameter of the extended circle gradually decreases as it moves away from the front P-type base region 3, that is, the diameter of the extended circle close to the front P-type base region 3 is larger than the diameter of the extended circle away from the front P-type base region 3, and as the diameter of the extended circle gradually decreases, the spacing between adjacent extended circles in the same annular direction gradually increases, that is, Figure 3 As shown, the spacing between adjacent extended circles in each vertical column becomes larger;

[0037] Specifically, after injecting boron ions into the expansion circle and performing high-temperature annealing diffusion treatment, a ring-shaped junction terminal expansion structure surrounding the front P-type base region 3 can be formed. The doping concentration of the ring-shaped junction terminal expansion structure continuously decreases along the front P-type base region 3 toward the edge, and then high-temperature diffusion is performed to achieve impurity redistribution; that is, through high-temperature diffusion, the ions in the expansion circle diffuse laterally so that the various expansion circle areas are interconnected, which is equivalent to different doping concentrations, thereby achieving the effect of lateral variable doping, and then forming a junction terminal expansion structure surrounding the edge of the front P-type base region 3. Because the diameter of the expansion circle and the spacing between the expansion circles change regularly, the doping concentration continuously and linearly decreases along the front P-type base region 3 toward the edge, and the reduction in doping concentration causes the junction depth to gradually decrease.

[0038] In summary, the use of annular junction terminal expansion technology and lateral variable doping technology, that is, the use of an annular decreasing circle design structure, can greatly reduce the size of the terminal and improve the utilization of the terminal size compared to the existing planar thyristor with a floating potential ring structure as the terminal; and the lateral variable doping and boron ion doping injection of expansion circles of different diameters will result in different impurity concentrations and junction depths in the doped area after annealing. This phenomenon is used to form a P-type area with varying doping concentrations and junction depths in the lateral direction, which can effectively improve the main junction electric field, reduce the chip area, and increase the voltage resistance ratio of the terminal.

[0039] S6, etching an N+ emitter region 6 on the surface of the front P-type base region 3 and the back P-type base region 4, and etching a gate N+ region 13 on the surface of the front P-type base region 3, the N+ emitter region 6 and the gate N+ region 13 on the surface of the front P-type base region 3 are arranged adjacently and spaced apart;

[0040] S7, cleaning the oxide layer on the surface of the silicon wafer 1, and depositing a polysilicon film (SIPOS), a silicon dioxide film (LTO), a silicon oxide film (TEOS), and a silicon nitride film (SiN) on the front side of the silicon wafer 1 from bottom to top in order to form a composite passivation film 12;

[0041] Polycrystalline silicon film (SIPOS) is a semi-insulating passivation film, which is equivalent to having the advantages of both insulating film and "conductive" film. Polycrystalline silicon film (SIPOS) itself is electrically neutral, which can eliminate the charge accumulation caused by surface induction, no ohmic current flows, does not change the space charge of the junction, and does not have hot carrier storage effect. The density of the recombination center generated between the polycrystalline silicon film (SIPOS) and the thyristor substrate is low, which is conducive to reducing PN junction leakage;

[0042] Specifically, in step S7, the following steps are also included:

[0043] S7.1, using LPCVD equipment, and setting the temperature at 650°C to 680°C, under the pressure condition of 280mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the LPCVD equipment for reaction, so as to deposit a polycrystalline silicon film with a thickness of 600nm on the front side of the silicon wafer 1;

[0044] S7.2, depositing a 400 nm thick silicon dioxide film on the polysilicon film, and performing annealing after the deposition to eliminate stress and densify the film;

[0045] S7.3, using a PECVD device, and setting the temperature at 300°C to 400°C, under a pressure of 180 mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the PECVD device for reaction to deposit a 200nm thick silicon oxide film on the silicon dioxide film;

[0046] S7.4, replacing the reaction gas in the PECVD device, that is, introducing 100cc to 150cc of silane and 50cc to 100cc of ammonia into the PECVD device for reaction to deposit a 600nm thick silicon nitride film on the silicon oxide film;

[0047] According to the above, a multilayer composite passivation film of SIPOS+LTO+TEOS+SIN is finally formed on the front side of the silicon wafer 1. According to the characteristics of the film layer, there is no high-energy barrier at the interface between the polycrystalline silicon film (SIPOS) and the silicon material, and there are high-density traps in the film. When the surface of the silicon wafer 1 is contaminated by ions, it will be captured by the traps in the polycrystalline silicon film (SIPOS) to form a space charge region. This space charge region has a shielding effect on the external electric field, and hot carriers cannot stay in the polycrystalline silicon film (SIPOS) for a long time. Therefore, the carriers injected into the passivation film will not have a storage effect due to the avalanche breakdown of the PN junction; at the same time, it can alleviate the influence of the electric field caused by the ions that have been contaminated on the surface of the silicon wafer 1 on the silicon surface; and the polycrystalline silicon film (SIPOS) is electrically neutral, and no electric field concentration will be formed on the surface, thereby avoiding surface breakdown and improving the reverse withstand voltage.

[0048] Silicon nitride film (SiN) has a dense structure, low pinhole density, good chemical stability, and a large dielectric constant. It has a very high barrier ability to sodium ions and water vapor, which can reduce the contamination of polysilicon film (SIPOS) by the outside world, and can reduce the stress of silicon nitride film (SiN), making the structure of silicon nitride film (SiN) more stable and not easy to crack. It also improves the corrosion resistance of silicon nitride film (SiN), and can operate stably in relatively harsh environments;

[0049] S8, etching a metal contact area 7 on the front side of the silicon wafer 1, and corroding the composite passivation film of the metal contact area 7, depositing aluminum layers on the metal contact area 7 and the back side of the silicon wafer 1, respectively, the thickness of the aluminum layer on the metal contact area 7 is 4um; the thickness of the aluminum layer on the back side of the silicon wafer 1 is 1um; using a photolithography machine to photoetch a reverse pattern on the metal contact area 7, and corroding the aluminum layer outside the pattern, thereby forming the gate 8 and T1 pole 9 of the thyristor, and an isolation oxide layer 11 is deposited on the metal contact area 7 between the gate 8 and the T1 pole 9;

[0050] S9, a titanium-nickel-silver alloy layer is continuously deposited on the aluminum layer on the reverse side of the silicon wafer 1, thereby forming a T2 pole 10 of the thyristor; wherein, in the titanium-nickel-silver alloy layer, the thickness of titanium is 100 nm, the thickness of nickel is 300 nm, and the thickness of silver is 1000 nm;

[0051] S10, performing low temperature treatment on the aluminum layer so that the aluminum layer forms a metal ohmic contact with the silicon wafer 1, and finally forming a thyristor chip.

[0052] Compared with the planar structured thyristors currently on the market, the planar thyristors produced by the present invention can meet the high withstand voltage requirement of more than 1200V, and the effective terminal length is only 220um; the design structure of the present invention reduces the size of the terminal, improves the utilization of the terminal size, and reduces the cost. At the same time, the passivation structure of the multi-layer composite passivation film is adopted, which reduces the leakage of the thyristor product and improves the withstand voltage of the product, and greatly improves the ability of the product to resist external harmful impurities, effectively improving the reliability of the thyristor product.

[0053] After the present invention optimizes the terminal design and the surface passivation protection, the simulated breakdown voltage can reach more than 1400V. Figure 4 The present invention can reduce the chip area to a large extent, increase the voltage resistance ratio of the terminal, and use a multi-layer composite passivation film to reduce the leakage of the thyristor product while increasing the voltage resistance of the product, and improve the product's ability to resist external harmful impurities, effectively improving the reliability of the thyristor product.

[0054] As shown in Table 1 below, the thyristor device obtained according to the manufacturing steps of the present invention has been tested, and the conclusion can be drawn through the test parameters: the withstand voltage exceeds 1200V and the leakage current is less than 1uA.

[0055] symbol Test conditions Test value unit Off-state repetitive peak voltage VDRM IDRM=1uA 1257 V Repetitive peak reverse voltage VRRM IRRM=1uA 1345 V Off-state repetitive peak current IDRM VDRM=1200V 89 n A Repetitive peak reverse current IRRM VRRM=1200V 193 n A

[0056] Table 1

[0057] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0058] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for manufacturing a high voltage planar thyristor, characterized in that: The following steps are involved: S1. Select N-type single crystal silicon material and process it into silicon wafers, and then thermally generate an oxide layer on the surface of the silicon wafers; S2, etching the front and back isolation patterns on the silicon wafer by a photolithography machine, and then removing the oxide layer on the area to be processed by hydrofluoric acid; S3, coating the front and back surfaces of the silicon wafer with a boron source, and then performing high-temperature diffusion to penetrate the P-type layer on the front and back surfaces of the silicon wafer to form an isolation island; S4, respectively etching the P-type region patterns on the front and back areas to be fabricated of the silicon wafer, then coating the surface of the P-type region patterns with a boron source and placing it in a high-temperature diffusion furnace for treatment, so that the boron source diffuses into the silicon wafer located in the P-type region patterns to form a front P-type base region and a back P-type base region, thereby forming a main junction of the thyristor; S5. Photolithography is performed on the front side of the silicon wafer according to the pattern to form an extended junction around the edges of the front P-type base region, wherein the extended junction is formed by a number of extended circles evenly distributed around the edges of the front P-type base region, and high-temperature annealing and diffusion treatment is performed after boron ions are implanted into the extended circle, wherein the diameter of the extended circle gradually decreases as it moves away from the front P-type base region; S6, etching an N+ emitter region on the surface of the front P-type base region and the back P-type base region, and etching a gate N+ region on the surface of the front P-type base region; S7, rinsing the oxide layer on the surface of the silicon wafer, and depositing a polysilicon film, a silicon dioxide film, a silicon oxide film, and a silicon nitride film on the front side of the silicon wafer from bottom to top in order to form a composite passivation film; S8, etching a metal contact area on the front side of the silicon wafer, and corroding the composite passivation film of the metal contact area, depositing an aluminum layer on the metal contact area and the back side of the silicon wafer respectively, photolithography a reverse pattern on the metal contact area using a photolithography machine, and corroding the aluminum layer outside the pattern, thereby forming the gate and T1 pole of the thyristor, and an isolation oxide layer is deposited on the metal contact area between the gate and T1 pole; S9, continuing to deposit a titanium-nickel-silver alloy layer on the aluminum layer on the reverse side of the silicon wafer, thereby forming a T2 pole of the thyristor; S10, performing low temperature treatment on the aluminum layer so that the aluminum layer forms a metal ohmic contact with the silicon wafer, and finally forming a thyristor chip.

2. The method for manufacturing a high voltage planar thyristor according to claim 1, characterized in that: The silicon wafer is made of N-type single crystal silicon material with a resistivity of 50 ohm-cm and a thickness of 225um.

3. The method for manufacturing a high voltage planar thyristor according to claim 1, characterized in that: In step S5, the front P-type base region is a regular quadrilateral, and the four corners of the regular quadrilateral are rounded; the expansion circle surrounds the edges of the front P-type base region in an annular direction, the diameter of the expansion circle close to the front P-type base region is larger than the diameter of the expansion circle away from the front P-type base region, and as the diameter of the expansion circle gradually decreases, the distance between adjacent expansion circles in the same annular direction gradually increases.

4. The method for manufacturing a high voltage planar thyristor according to claim 1, characterized in that: In step S7, the following steps are also included: S7.1, using LPCVD equipment, and setting the temperature at 650°C to 680°C, under the pressure condition of 280mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the LPCVD equipment for reaction, so as to deposit a polycrystalline silicon film with a thickness of 600nm to 700nm on the front side of the silicon wafer; S7.2, depositing a silicon dioxide film with a thickness of 400nm to 500nm on the polysilicon film, and performing annealing after the deposition is completed; S7.3, using a PECVD device, and setting the temperature at 300°C to 400°C, under a pressure of 180 mtoor, then introducing 150cc to 300cc of silane and 50cc to 100cc of laughing gas into the PECVD device for reaction, so as to deposit a silicon oxide film with a thickness of 200nm to 300nm on the silicon dioxide film; S7.

4. Replace the reaction gas in the PECVD equipment, that is, introduce 100cc to 150cc of silane and 50cc to 100cc of ammonia into the PECVD equipment for reaction to deposit a silicon nitride film with a thickness of 600nm to 700nm on the silicon oxide film.

5. The method for manufacturing a high voltage planar thyristor according to claim 1, characterized in that: In the step S8, the thickness of the aluminum layer on the metal contact area is 4um to 6um; the thickness of the aluminum layer on the back side of the silicon wafer is 1um to 2um.

6. The method for manufacturing a high voltage planar thyristor according to claim 1, characterized in that: In the titanium-nickel-silver alloy layer, the thickness of titanium is 100nm-200nm, the thickness of nickel is 300nm-400nm, and the thickness of silver is 1000nm-1200nm.

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