Groove type silicon carbide field effect transistor and preparation method thereof

Abstract

The invention discloses a groove type silicon carbide field effect transistor and a preparation method, and relates to the technical field of semiconductors. For a trench gate SiC MOSFET device, a highly doped P + region is formed through injection on the inner surface of one side of two trench regions which are close to each other, ohmic contact is formed at the top of the P + region to realize grounding processing, and a depletion layer generated by the P + region and a Drift layer is utilized to expand and wrap a gate oxide layer at a corner at the bottom of a trench, so that the trench gate SiC MOSFET device is formed. Therefore, the trench gate oxide layer of the trench type device is protected, and early breakdown caused by electric field concentration is avoided. And the P + region formed by the adjacent groove regions reduces the area use of the P + region as much as possible, so that the performance of the device is improved to a certain extent, and the cost of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a trench silicon carbide field effect transistor and a preparation method thereof. Background Art

[0002] Voltage-controlled SiC MOSFET switching devices have great prospects in high voltage, high temperature, high frequency, high radiation and other application fields due to the advantages of the physical properties of SiC materials and the switching performance advantages of MOSFET unipolar devices. Currently, most of the devices used on a large scale in the market are planar gate SiC MOSFET devices. Planar gate devices have simpler process and more stable structural characteristics. The disadvantage is that the device area is relatively large, so the switching loss and cost will be higher.

[0003] Since the chip area of ​​trench gate SiC MOSFET can be made smaller, the conduction loss, switching loss and cost of the device are more advantageous, which also makes trench gate SiC MOSFET regarded as the future product development direction by various chip manufacturers. However, the field concentration of the gate oxide layer at the bottom corner of the trench during the use of trench gate SiC MOSFET has always been the biggest safety hazard of the device. Due to the curvature effect of the bottom corner of the trench, coupled with the poor quality of the gate oxide layer, it is easy to cause premature breakdown failure at this location. In order to protect the gate oxide layer at the bottom corner of the trench, the trench gate SiCMOSFET devices currently on the market need to sacrifice a large part of the area to specially design the P+ region, and protect the gate oxide layer through the depletion layer generated by the P+ region and the Drift layer. Therefore, if the gate oxide layer at the bottom corner of the trench of the trench gate SiC MOSFET can be protected while reducing the use of the P+ region area, the performance and cost of the device will be improved. Summary of the invention

[0004] The present invention is directed to a trench gate SiC MOSFET device, and a highly doped P+ region is formed by implanting on the inner surface of one side of two trench regions with a close distance, and an ohmic contact is formed on the top of the P+ region to achieve grounding treatment, and the depletion layer generated by the P+ region and the Drift layer is used to expand and wrap the gate oxide layer at the bottom corner of the trench, thereby protecting the trench gate oxide layer of the trench device and avoiding electric field concentration and thus early breakdown. In addition, the P+ region formed by the adjacent trench region also reduces the area usage of the P+ region as much as possible, thereby improving device performance to a certain extent and reducing device cost.

[0005] The technical solution of the present invention is: A method for preparing a trench silicon carbide field effect transistor comprises the following steps: S100, forming a SiC Drift layer on the top surface of the SiC Sub layer by epitaxial deposition; S200, forming a P-body region and a NP region in the SiC Drift layer in sequence; S300, etching downwards on the top surface of the SiC Drift layer to form a plurality of groove regions spaced apart from each other; S400: P+ region is formed between adjacent trench regions by two opposite oblique Al ion implantations with a doping concentration of 5E18-3E19cm -2 ; S500, forming an oxide layer on one side of the trench region, forming a gate oxide layer on the other side, and filling the space between the oxide layer and the gate oxide layer with a Poly layer; S600, forming an isolation dielectric layer and an ohmic contact alloy layer in sequence on the top of the NP region; S700, forming a front electrode metal layer on the top of the device by sputtering Ti and AlCu metals.

[0006] Specifically, in step S100, the doping concentration of the SiC Sub layer is 1E19-5E19cm -2 , SiC Drift layer doping concentration is 5E15-3E16cm -2 .

[0007] Specifically, the depth of the P-body region in step S200 is 0.8um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0008] Specifically, in step S200, the depth of the NP region is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .

[0009] Specifically, in step S300 , the bottom depth of the groove region is 1 um-2.4 um.

[0010] Specifically, in step S400, the depth of the P+ region is 1.2um-3um, and the doping concentration is 5E18-3E19cm -2 .

[0011] Specifically, in step S500 , the thickness of the gate oxide layer is 40 nm-80 nm.

[0012] Specifically, in step S700 , the thickness of the Ti metal is 0.1 um-0.6 um, and the thickness of the AlCu metal is 2 um-5 um.

[0013] A trench silicon carbide field effect transistor comprises a SiC Sub layer, a SiCDrift layer, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The SiC Drift layer is provided with: P-body regions are provided, each extending downward from the top surface of the SiC Drift layer and arranged at intervals; NP regions, provided with a plurality of them, extending downward from the top surface of the P-body region respectively; There are several P+ regions, each extending downward from the top surface of the SiC Drift layer between the adjacent P-body regions, with a cross-section of a L-shaped structure, whose bottom surface is lower than the bottom surface of the P-body region, and the doping concentration is 5E18-3E19cm -2 ; Oxide layers, provided with a plurality of layers, respectively arranged on the sides of the P+ region; A gate oxide layer, having an L-shaped cross section, with sides connected to the P-body region and the NP region respectively, and a bottom extending toward the oxide layer and connected to the P+ region and the oxide layer respectively; A Poly layer, disposed between the gate oxide layer and the oxide layer; The isolation dielectric layer is located between the plurality of ohmic contact alloy layers, and its bottom surface is respectively connected to the NP region, the gate oxide layer, the Poly layer and the oxide layer.

[0014] Specifically, the bottom surface of the gate oxide layer is higher than the bottom surface of the P+ region.

[0015] The present invention is directed to a trench gate SiC MOSFET device, and a highly doped P+ region is formed by implanting on the inner surface of one side of two trench regions with a close distance, and an ohmic contact is formed on the top of the P+ region to achieve grounding treatment, and the depletion layer generated by the P+ region and the Drift layer is used to expand and wrap the gate oxide layer at the bottom corner of the trench, thereby protecting the trench gate oxide layer of the trench device and avoiding electric field concentration and thus early breakdown. In addition, the P+ region formed by the adjacent trench region also reduces the area usage of the P+ region as much as possible, thereby improving device performance to a certain extent and reducing device cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of a trench gate SiC MOSFET of the present invention; Figure 2 is a structural schematic diagram of step S100 of the present invention; Figure 3 is a schematic structural diagram of step S200 of the present invention; Figure 4 is a schematic structural diagram of step S300 of the present invention; Figure 5 is a schematic structural diagram of step S400 of the present invention; Figure 6is a schematic structural diagram of step S500 of the present invention; Figure 7 is a schematic diagram of the structure of step S600 of the present invention; Figure 8 is a schematic diagram of the structure of step S700 of the present invention; Fig. 9 is a structural schematic diagram of step S800 of the present invention; Fig.10 is a structural schematic diagram of step S900 of the present invention; Fig.11 is a structural schematic diagram of step S1000 of the present invention; Fig.12 is a structural schematic diagram of step S1100 of the present invention; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-body region, 4 is NP region, 5 is P+ region, 6 is oxide layer, 7 is gate oxide layer, 8 is Poly layer, 9 is isolation dielectric layer, 10 is ohmic contact alloy layer, and 11 is front electrode metal layer. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] In the description of the present invention, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific position, be constructed and operated in a specific position, and therefore cannot be understood as limiting the present invention. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0019] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0020] A trench silicon carbide field effect transistor comprises the following steps: S100, forming a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition; The doping concentration of SiC Sub layer 1 in step S100 is 1E19-5E19cm -2 , the doping concentration of SiC Drift layer 2 is 5E15-3E16cm -2 .

[0021] S200, forming a plurality of P-body regions 3 spaced apart on the top surface of the SiC Drift layer 2 by Al ion implantation; The depth of the P-body region 3 in step S200 is 0.8um-2um, and the doping concentration is 1E17-3E18cm -2 .

[0022] S300, forming an NP region 4 on the top surface of the P-body region 3 by N ion implantation; The depth of NP region 4 in step S300 is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .

[0023] S400, etching downwards on the top surface of the SiC Drift layer 2 to form a plurality of groove regions; The bottom depth of the trench region in step S400 is 1 um-2.4 um.

[0024] S500, forming a P+ region 5 between two adjacent trench regions by two opposite oblique Al ion implantations; The depth of the P+ region 5 in step S500 is 1.2um-3um, and the doping concentration is 5E18-3E19cm -2 .

[0025] S600, forming an oxide layer 6 on the side wall of the trench region close to the P+ region 5 by oxide deposition; S700, forming a gate oxide layer 7 connected to the oxide layer 6 on the other side of the trench region by high temperature dry oxygen oxidation; The thickness of the gate oxide layer 7 in step S700 is 40 nm-80 nm.

[0026] S800, forming a Poly layer 8 on the surface of the gate oxide layer 7 by depositing polysilicon; S900, forming an isolation dielectric layer 9 on the top surfaces of the NP region 4, the oxide layer 6, the gate oxide layer 7 and the Poly layer 8 by oxide deposition; S1000, forming an ohmic contact alloy layer 10 on the top surfaces of the NP region 4, the P+ region 5 and the oxide layer 6 by sputtering or depositing Ni metal and then thermally annealing; The Ni metal thickness in step S1000 is 0.3um-1um.

[0027] S1100, forming a front electrode metal layer 11 on the top of the device by sputtering Ti and AlCu metals; In step S1100 , the thickness of the Ti metal is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.

[0028] A trench silicon carbide field effect transistor comprises a SiC Sub layer 1, a SiCDrift layer 2, an ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top; The SiC Drift layer 2 is provided with: P-body regions 3 are provided, each extending downward from the top surface of the SiC Drift layer 2 and arranged at intervals; A plurality of NP regions 4 are provided, each extending downward from the top surface of the P-body region 3; There are several P+ regions 5, each extending downward from the top surface of the SiC Drift layer 2 between the adjacent P-body regions 3, with a cross-section of a L-shaped structure, whose bottom surface is lower than the bottom surface of the P-body region 3, and the doping concentration is 5E18-3E19cm -2 ; Oxide layers 6, provided with a plurality of layers, respectively arranged at the sides of the P+ region 5; The gate oxide layer 7 has an L-shaped cross section, the sides of which are respectively connected to the P-body region 3 and the NP region 4, and the bottom of which extends toward the oxide layer 6 and is respectively connected to the P+ region 5 and the oxide layer 6; the bottom surface of the gate oxide layer 7 is higher than the bottom surface of the P+ region 5; A Poly layer 8, disposed between the gate oxide layer 7 and the oxide layer 6; The isolation dielectric layer 9 is located between the plurality of ohmic contact alloy layers 10, and its bottom surface is connected to the NP region 4, the gate oxide layer 7, the Poly layer 8 and the oxide layer 6 respectively.

[0029] Although the trench gate SiC MOSFET can be made smaller in area due to its structural characteristics, thereby achieving performance and cost advantages, the curvature effect of the bottom corner of the trench of the trench gate SiC MOSFET and the quality problem of the gate oxide layer formed by direct growth of thermal oxidation cause the device to easily fail prematurely at the gate oxide layer position at the bottom corner of the trench during use, affecting the safe use of the entire system. Figure 1In the trench gate SiC MOSFET device shown, a highly doped P+ region 5 is formed by implanting on the inner surface of one side of two trench regions with a close distance, and the depletion layer represented by the dotted line generated by the P+ region 5 and the Drift layer is extended to wrap the gate oxide layer at the bottom corner of the trench, thereby avoiding the problem of electric field concentration here, thereby protecting the trench gate oxide layer, and at the same time forming an ohmic contact at the top of the P+ region to achieve grounding treatment, further improving the protection effect of the P+ region. The P+ region formed by the adjacent trench region also reduces the area usage of the P+ region, thereby further reducing the area of ​​the entire device, thereby improving the device performance to a certain extent and reducing the device cost.

Claims

1. A method for preparing a trench silicon carbide field effect transistor, characterized in that: The steps include: S100, forming a SiC Drift layer (2) on the top surface of the SiC Sub layer (1) by epitaxial deposition; S200, forming a P-body region (3) and a NP region (4) in the SiC Drift layer (2); S300, etching downwards on the top surface of the SiC Drift layer (2) to form a plurality of groove regions arranged at intervals; S400, a P+ region (5) is formed between adjacent trench regions by two opposite oblique Al ion implantations, with a doping concentration of 5E18-3E19cm -2 ; S500, forming an oxide layer (6) on one side of the trench region, forming a gate oxide layer (7) on the other side, and filling the space between the oxide layer (6) and the gate oxide layer (7) with a Poly layer (8); S600, forming an isolation dielectric layer (9) and an ohmic contact alloy layer (10) in sequence on the top of the NP region (4); S700, forming a front electrode metal layer (11) on the top of the device by sputtering Ti and AlCu metals.

2. A method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S100, the doping concentration of the SiC Sub layer (1) is 1E19-5E19cm -2 , the doping concentration of SiC Drift layer (2) is 5E15-3E16cm -2 .

3. A method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: The depth of the P-body region (3) in step S200 is 0.8um-2um, and the doping concentration is 1E17-3E18cm -2 .

4. A method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S200, the depth of the NP region (4) is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .

5. The method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S300 , the bottom depth of the trench region is 1 um-2.4 um.

6. A method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S400, the depth of the P+ region (5) is 1.2um-3um, and the doping concentration is 5E18-3E19cm -2 .

7. The method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S500, the thickness of the gate oxide layer (7) is 40nm-80nm.

8. The method for preparing a trench silicon carbide field effect transistor according to claim 1, characterized in that: In step S700 , the thickness of the Ti metal is 0.1 um-0.6 um, and the thickness of the AlCu metal is 2 um-5 um.

9. A trench silicon carbide field effect transistor, prepared by the method for preparing a trench silicon carbide field effect transistor according to any one of claims 1 to 8, characterized in that: It comprises a SiC Sub layer (1), a SiCDrift layer (2), an ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with: A plurality of P-body regions (3) are provided, each extending downward from the top surface of the SiC Drift layer (2) and arranged at intervals; A plurality of NP regions (4) are provided, each extending downward from the top surface of the P-body region (3); The P+ region (5) is provided with a plurality of P+ regions (5) extending downward from the top surface of the SiC Drift layer (2) between adjacent P-body regions (3), and having a cross-sectional shape with a bottom surface lower than the bottom surface of the P-body region (3), and a doping concentration of 5E18-3E19cm -2 ; A plurality of oxide layers (6) are provided, each of which is arranged on the side of the P+ region (5); A gate oxide layer (7) having an L-shaped cross section, with its sides respectively connected to the P-body region (3) and the NP region (4), and its bottom extending toward the oxide layer (6) and respectively connected to the P+ region (5) and the oxide layer (6); A Poly layer (8) disposed between the gate oxide layer (7) and the oxide layer (6); The isolation dielectric layer (9) is located between the plurality of ohmic contact alloy layers (10), and its bottom surface is respectively connected to the NP region (4), the gate oxide layer (7), the Poly layer (8) and the oxide layer (6).

10. The trench silicon carbide field effect transistor according to claim 9, characterized in that: The bottom surface of the gate oxide layer (7) is higher than the bottom surface of the P+ region (5).

Images