Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The preparation method of the semiconductor device comprises the following steps: providing a substrate, wherein the substrate comprises a high-voltage device region and a low-voltage device region; a first grid electrode and a second grid electrode are formed on the substrate, the first grid electrode is located in the high-voltage device area, and the second grid electrode is located in the low-voltage device area; forming a first side wall layer on the side wall of the first grid electrode; and forming a second side wall layer on the side wall of the first side wall layer and the side wall of the second grid respectively. Therefore, the thickness of the side wall structure of the high-voltage device can be larger than that of the side wall structure of the low-voltage device, the low-voltage device can improve current, the high-voltage device can improve withstand voltage, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] In non-standard logic processes of integrated circuits, high voltage (HV) components and low voltage (LV) components are often integrated together, that is, integrated and manufactured in the same semiconductor device. The different performance requirements of high voltage components and low voltage components lead to large differences in device structure requirements. Using standard logic processes often limits the performance of high voltage components. High voltage components require thicker sidewalls due to high voltage requirements; low voltage components require smaller sidewalls due to device speed requirements. However, the sidewall thicknesses of high voltage components and low voltage components of existing semiconductor devices are equal, resulting in poor performance of semiconductor devices. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same to address at least one of the above problems.

[0004] In order to achieve at least one of the above objectives, in a first aspect, the present application provides a method for preparing a semiconductor device, the method for preparing a semiconductor device comprising:

[0005] Providing a substrate, the substrate comprising a high voltage device region and a low voltage device region;

[0006] forming a first gate and a second gate on the substrate, wherein the first gate is located in the high-voltage device region, and the second gate is located in the low-voltage device region;

[0007] forming a first spacer layer on the sidewall of the first gate;

[0008] A second spacer layer is formed on the sidewall of the first spacer layer and the sidewall of the second gate respectively.

[0009] In one embodiment, the step of forming a first gate and a second gate on the substrate, wherein the first gate is located in the high voltage device region and the second gate is located in the low voltage device region, comprises:

[0010] forming a gate material layer on the substrate;

[0011] forming a sacrificial material layer on the gate material layer in the high voltage device region;

[0012] The gate material layer and the sacrificial material layer are etched to form the first gate and the second gate; wherein a sacrificial layer is formed on a surface of the first gate.

[0013] In one embodiment, the step of forming a first gate and a second gate on the substrate, wherein the first gate is located in the high voltage device region and the second gate is located in the low voltage device region, comprises:

[0014] forming a gate material layer on the substrate;

[0015] Etching the gate material layer to form the first gate and the second gate;

[0016] A sacrificial layer is formed on the surface of the second gate.

[0017] In one embodiment, the step of forming a first spacer layer on the sidewall of the first gate includes:

[0018] Forming a first spacer material layer on the substrate; wherein the first spacer material layer covers the surface of the substrate, the surface of the sacrificial layer and the surface of the second gate, and the material of the first spacer material layer is the same as that of the sacrificial material layer;

[0019] The first spacer material layer and the sacrificial layer are etched to form the first spacer layer.

[0020] In one embodiment, the step of performing etching on the first spacer material layer and the sacrificial layer to form a first spacer layer includes:

[0021] Performing a first etching on the first spacer material layer to expose the top surface of the sacrificial layer;

[0022] The sacrificial layer and the remaining first spacer material layer are etched for the second time to form the first spacer layer.

[0023] In one embodiment, the step of forming a second spacer layer on the sidewall of the first spacer layer and the sidewall of the second gate respectively includes:

[0024] Forming a second spacer material layer on the substrate; wherein the second spacer material layer covers the surface of the substrate, the surface of the first gate, the surface of the first spacer layer and the surface of the second gate;

[0025] The second spacer material layer is etched to form the second spacer layer.

[0026] The method for preparing a semiconductor device provided in an embodiment of the present application first forms a first spacer layer on the side wall of the first gate, and then forms a second spacer layer on the side wall of the first spacer layer and the side wall of the second gate. In this way, the first spacer layer and the second spacer layer together constitute the sidewall structure of the high-voltage device, and the second spacer layer constitutes the sidewall structure of the low-voltage device. In this way, the thickness of the sidewall structure of the high-voltage device can be greater than the thickness of the sidewall structure of the low-voltage device, which is beneficial for the low-voltage device to increase the current and the high-voltage device to increase the withstand voltage, thereby improving the performance of the semiconductor device.

[0027] In a second aspect, an embodiment of the present application further provides a semiconductor device, the semiconductor device comprising:

[0028] A substrate, including a high voltage device region and a low voltage device region;

[0029] A first gate is disposed on the substrate and located in the high voltage device region;

[0030] A second gate is disposed on the substrate and located in the low voltage device region;

[0031] A first spacer layer, disposed around a side wall of the first gate;

[0032] A second spacer layer is provided around the sidewalls of the first spacer layer and the second gate.

[0033] In one embodiment, the material of the first spacer layer is the same as the material of the second spacer layer.

[0034] In one embodiment, along a thickness direction perpendicular to the substrate, the first spacer layer has a first thickness, and the second spacer layer has a second thickness;

[0035] The first thickness is not greater than the second thickness.

[0036] In one embodiment, along a thickness direction perpendicular to the substrate, the first spacer has a first thickness, and the second spacer has a second thickness;

[0037] The ratio of the first thickness to the second thickness is between 0.2-1.

[0038] The semiconductor device provided by the embodiment of the present application is provided with a first spacer layer and a second spacer layer on the side wall of the first gate, and a second spacer layer on the side wall of the second gate. In this way, the first spacer layer and the second spacer layer together constitute the sidewall structure of the high-voltage device, and the second spacer layer constitutes the sidewall structure of the low-voltage device. In this way, the thickness of the sidewall structure of the high-voltage device can be greater than the thickness of the sidewall structure of the low-voltage device, which is beneficial to increase the current of the low-voltage device and increase the withstand voltage of the high-voltage device, thereby improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic flow chart of a method for preparing a semiconductor device provided in one embodiment of the present application.

[0041] Figure 2 for Figure 1 A schematic diagram of a process flow of S200 in the preparation method shown.

[0042] Figure 3 for Figure 1 A schematic diagram of a process of S300 in the preparation method shown.

[0043] Figure 4 for Figure 1 A schematic diagram of a process of S400 in the preparation method shown.

[0044] Figure 5-Figure 11 for Figure 1 Schematic diagram of the device structure during the preparation method shown.

[0045] Fig.12 A schematic diagram of the structure of a semiconductor device provided in one embodiment of the present application.

[0046] Description of reference numerals:

[0047] 1. semiconductor device; 10. substrate; 10a. high-voltage device region; 10b. low-voltage device region; 11. high-voltage well region; 12. low-voltage well region; 13. first doped region; 14. second doped region; 15. first source region; 16. first drain region; 17. second source region; 18. second drain region; 20. first gate; 21. first gate oxide layer; 22. first gate dielectric layer; 30. second gate; 31. second gate oxide layer; 32. second gate dielectric layer; 40. first sidewall layer; 50. second sidewall layer; 60. sacrificial layer; 71. gate material layer; 711. gate oxide material layer; 712. gate dielectric material layer; 72. sacrificial material layer; 73. first sidewall material layer; 74. second sidewall material layer. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0050] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0052] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the application, so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the zones shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the application.

[0054] First, refer to Figure 1 As shown, an embodiment of the present application provides a method for preparing a semiconductor device, and the method for preparing a semiconductor device includes:

[0055] S100: providing a substrate 10, wherein the substrate 10 includes a high voltage device region 10a and a low voltage device region 10b.

[0056] In one example, combining Fig.12 As shown, S100 includes the following steps:

[0057] S101: Provide a semiconductor substrate. In one example, the material of the semiconductor substrate may be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), or other materials known to those skilled in the art.

[0058] S102: forming a shallow trench isolation structure on a semiconductor substrate and performing surface planarization.

[0059] Specifically, a first photolithography barrier layer is formed on the surface of the semiconductor substrate, and after the first photolithography barrier layer is photolithographically formed into a window region, the semiconductor substrate is etched to form a groove. The formed groove is filled with an insulating dielectric to form a shallow trench isolation structure (STI). In the embodiment of the present application, the formed shallow trench isolation structure is also subjected to chemical mechanical polishing (CMP) to achieve planarization of the surface of the semiconductor substrate.

[0060] S103: Perform ion implantation on the semiconductor substrate to form a high-voltage well region 11 and a low-voltage well region 12. The high-voltage well region 11 is located in the high-voltage device region 10a, and the low-voltage well region 12 is located in the low-voltage device region 10b.

[0061] S104 : performing ion implantation in the high-voltage well region 11 to form two first doping regions 13 , and performing ion implantation in the low-voltage well region 12 to form two second doping regions 14 .

[0062] S200 : forming a first gate 20 and a second gate 30 on a substrate 10 , wherein the first gate 20 is located in a high-voltage device region 10 a , and the second gate 30 is located in a low-voltage device region 10 b .

[0063] S300 : forming a first spacer layer 40 on the sidewall of the first gate 20 .

[0064] S400 : forming a second spacer layer 50 on the sidewalls of the first spacer layer 40 and the sidewalls of the second gate 30 .

[0065] In the method for preparing a semiconductor device provided in the embodiment of the present application, a first spacer layer 40 is first formed on the side wall of the first gate 20, and then a second spacer layer 50 is formed on the side wall of the first spacer layer 40 and the side wall of the second gate 30. In this way, the first spacer layer 40 and the second spacer layer 50 together constitute the sidewall structure of the high-voltage device, and the second spacer layer 50 constitutes the sidewall structure of the low-voltage device. In this way, the thickness of the sidewall structure of the high-voltage device can be greater than the thickness of the sidewall structure of the low-voltage device, which is beneficial for the low-voltage device to increase the current and the high-voltage device to increase the withstand voltage, thereby improving the performance of the semiconductor device 1.

[0066] In one embodiment, referring to Figure 2 , and combined with Figure 5 and Figure 6 As shown, S200 includes the following steps:

[0067] S210: forming a gate material layer 71 on the substrate 10. Exemplarily, the gate material layer 71 includes a gate oxide material layer 711 and a gate dielectric material layer 712, the gate oxide material layer 711 may be made of silicon dioxide, and the gate dielectric material layer 712 may be made of polysilicon or a metal material, such as a high-K (dielectric constant) metal material.

[0068] Specifically, a gate oxide material layer 711 is first formed on the surface of the substrate 10, and then a gate dielectric material layer 712 is formed on the surface of the gate oxide material layer 711. The gate oxide material layer 711 can be formed by dry oxygen oxidation, high temperature oxidation, wet oxygen oxidation, etc. The gate dielectric material layer 712 can be formed by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD).

[0069] S220: forming a sacrificial material layer 72 on the gate material layer 71 of the high voltage device region 10a. Exemplarily, the sacrificial material layer 72 may be made of silicon dioxide, and the sacrificial material layer 72 may be formed by dry oxygen oxidation, high temperature oxidation or wet oxygen oxidation.

[0070] In an example, S220 specifically includes the following steps:

[0071] S221 : forming a first mask layer on the surface of the gate material layer 71 , and exposing the surface of the gate material layer 71 in the high-voltage device region 10 a .

[0072] S222 : forming a sacrificial material layer 72 on the exposed surface of the gate material layer 71 and on the surface of the first mask layer.

[0073] S223: removing the first mask layer and the sacrificial material layer 72 located on the surface of the first mask layer.

[0074] Furthermore, after the sacrificial material layer 72 of the high voltage device region 10a is formed, the following steps are performed:

[0075] S230: etching the gate material layer 71 and the sacrificial material layer 72 to form the first gate 20 and the second gate 30. A sacrificial layer 60 is formed on the surface of the first gate 20. Specifically, a second photolithography barrier layer is formed on the surface of the gate material layer 71 and the sacrificial material layer 72, and the gate material layer 71 and the sacrificial material layer 72 are etched after the second photolithography barrier layer is photolithographically formed into a window region.

[0076] In one embodiment, S200 includes the following steps:

[0077] S210: forming a gate material layer 71 on the substrate 10. The preparation process of the gate material layer 71 in this embodiment is the same as that of the gate material layer 71 in the previous embodiment, and will not be described again.

[0078] S220: etching the gate material layer 71 to form the first gate 20 and the second gate 30. Specifically, a second photolithography barrier layer is formed on the surface of the gate material layer 71, and the gate material layer 71 is etched after the second photolithography barrier layer is photolithographically formed into a window region.

[0079] S230 : forming a sacrificial layer 60 on the surface of the second gate 30 . Specifically, forming a sacrificial material layer 72 on the surface of the substrate 10 , and etching the sacrificial material layer 72 to form the sacrificial layer 60 .

[0080] In one embodiment, referring to Figure 3 As shown, S300 includes the following steps:

[0081] S310: forming a first spacer material layer 73 on the substrate 10. The first spacer material layer 73 covers the surface of the substrate 10, the surface of the sacrificial layer 60 and the surface of the second gate 30, and the material of the first spacer material layer 73 is the same as that of the sacrificial material layer 72. Exemplarily, the material of the first spacer material layer 73 may be silicon dioxide, and further, the first spacer material layer 73 may be formed by dry oxygen oxidation, high temperature oxidation or wet oxygen oxidation.

[0082] S320: etching the first spacer material layer 73 and the sacrificial layer 60 to form the first spacer layer 40. Specifically, the first spacer material layer 73 and the sacrificial layer 60 may be etched by a dry process or a wet process.

[0083] In one embodiment, S320 includes the following steps:

[0084] S321: Perform a first etching on the first spacer material layer 73 to expose the top surface of the sacrificial layer 60. Figure 8 As shown, after the first etching is completed, part of the surface of the substrate 10, the surface of the second gate 30 and the surface of the sacrificial layer 60 are exposed, and the first spacer material layer 73 remains on the side walls of the first gate 20 and the sacrificial layer 60, and the first spacer material layer 73 remains on the side walls of the second gate 30.

[0085] S322: Perform a second etching on the sacrificial layer 60 and the remaining first spacer material layer 73 to form a first spacer layer 40. Fig. 9 As shown, after the second etching is completed, the first spacer material layer 73 on the side wall of the second gate 30 is removed, the sacrificial layer 60 on the top surface of the first gate 20 is removed, and a portion of the first spacer material layer 73 remains on the side wall of the first gate 20 to form the first spacer layer 40.

[0086] In one embodiment, referring to Figure 4 , and combined with Fig.10 and Fig.11 As shown, S400 includes the following steps:

[0087] S410 : forming a second spacer material layer 74 on the substrate 10 . The second spacer material layer 74 covers the surface of the substrate 10 , the surface of the first gate 20 , the surface of the first spacer layer 40 and the surface of the second gate 30 .

[0088] In the embodiment of the present application, the material of the second side wall material layer 74 is the same as that of the first side wall material layer 73. The material of the second side wall material layer 74 can be silicon dioxide. The second side wall material layer 74 can be formed by dry oxygen oxidation, high temperature oxidation or wet oxygen oxidation.

[0089] S420: etching the second spacer material layer 74 to form the second spacer material layer 50. Specifically, the second spacer material layer 74 may be etched by a dry process or a wet process.

[0090] In the embodiment of the present application, the first sidewall layer 40 and the second sidewall layer 50 together constitute the sidewall structure of the high-voltage device, and the second sidewall layer 50 constitutes the sidewall structure of the low-voltage device. The preparation method provided in the embodiment of the present application is equivalent to forming the sidewall structure of the high-voltage device through two manufacturing processes, and simultaneously forming the sidewall structure of the low-voltage device in the second manufacturing process. In this way, on the one hand, the high-voltage device and the low-voltage device form sidewall structures of different thicknesses respectively, so that the low-voltage device has a larger current and the high-voltage device has a higher withstand voltage, thereby improving the performance of the semiconductor device 1; on the other hand, the manufacturing process of the sidewall structure is simple, which is conducive to reducing the manufacturing cost of the device.

[0091] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the accompanying drawings may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a portion of the steps or stages in other steps.

[0092] Second, refer to Fig.12 As shown, an embodiment of the present application further provides a semiconductor device 1 , which includes: a substrate 10 , a first gate 20 , a second gate 30 , a first spacer 40 and a second spacer 50 .

[0093] Specifically, the substrate 10 includes a high voltage device region 10a and a low voltage device region 10b. The first gate 20 is disposed on the substrate 10 and is located in the high voltage device region 10a. The second gate 30 is disposed on the substrate 10 and is located in the low voltage device region 10b. The first spacer layer 40 is disposed around the sidewall of the first gate 20. The sidewalls of the first spacer layer 40 and the sidewalls of the second gate 30 are both surrounded by a second spacer layer 50.

[0094] It is understood that the material of the substrate 10 can be single crystal silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low temperature polysilicon (LTPS), etc., or other materials known to those skilled in the art. The first gate 20 includes a first gate oxide layer 21 and a first gate dielectric layer 22 stacked, and the second gate 30 includes a second gate oxide layer 31 and a second gate dielectric layer 32 stacked.

[0095] It should be noted that the sidewall structure can prevent the source and drain from being penetrated due to the larger dose of source and drain being implanted too close to the channel when the source and drain regions are subsequently formed, thereby causing device failure and reduced yield.

[0096] The semiconductor device 1 provided in the embodiment of the present application is provided with a first spacer layer 40 and a second spacer layer 50 on the side wall of the first gate 20, and a second spacer layer 50 on the side wall of the second gate 30. In this way, the first spacer layer 40 and the second spacer layer 50 together constitute the sidewall structure of the high-voltage device, and the second spacer layer 50 constitutes the sidewall structure of the low-voltage device. In this way, the thickness of the sidewall structure of the high-voltage device can be greater than the thickness of the sidewall structure of the low-voltage device, which is beneficial for the low-voltage device to increase the current and the high-voltage device to increase the withstand voltage, thereby improving the performance of the semiconductor device 1, and at the same time, the size of the semiconductor device 1 can be reduced, the chip area can be saved, and it is beneficial to manufacture a higher density chip.

[0097] In one embodiment, the material of the first spacer layer 40 is the same as the material of the second spacer layer 50. Exemplarily, the material of the first spacer layer 40 and the material of the second spacer layer 50 can be silicon dioxide.

[0098] In this way, on the one hand, the material of the sidewall structure of the high-voltage device can be made consistent, making the performance of the high-voltage device more stable; on the other hand, when manufacturing the sidewall structure of the high-voltage device, the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0099] In one embodiment, referring to Fig.11 As shown, along the thickness direction perpendicular to the substrate 10, the first spacer layer 40 has a first thickness L1, and the second spacer layer 50 has a second thickness L2. The first thickness L1 is not greater than the second thickness L2.

[0100] In this way, the thickness difference between the low-voltage device sidewall structure and the high-voltage device sidewall structure can be kept within a reasonable range, which is beneficial to improving the performance of the semiconductor device 1 .

[0101] In one embodiment, along the thickness direction perpendicular to the substrate 10, the first spacer has a first thickness L1, and the second spacer 50 has a second thickness L2. The ratio of the first thickness L1 to the second thickness L2 is between 0.2 and 1. Exemplarily, the ratio may be 0.2, 0.3, 0.5, 0.6, 0.8, 0.9 or 1.

[0102] By making the ratio of the first thickness L1 to the second thickness L2 within the above range, the thickness difference between the low-voltage device sidewall structure and the high-voltage device sidewall structure can be within a reasonable range, which is beneficial to improving the performance of the semiconductor device 1 .

[0103] It should be noted that, refer to Fig.12As shown, the semiconductor device 1 further includes a high-voltage well region 11, a low-voltage well region 12, a first doping region 13, a second doping region 14, a first source region 15, a first drain region 16, a second source region 17, and a second drain region 18. The high-voltage well region 11 is located in the substrate 10 of the high-voltage device region 10a, and the low-voltage well region 12 is located in the substrate 10 of the low-voltage device region 10b. Two first doping regions 13 are arranged at intervals in the high-voltage well region 11, and the first source region 15 and the first drain region 16 are arranged in the two first doping regions 13, respectively. Two second doping regions 14 are arranged at intervals in the low-voltage well region 12, and the second source region 17 and the second drain region 18 are arranged in the two second doping regions 14, respectively. In addition, a shallow trench isolation structure (not shown) is also arranged between the high-voltage well region 11 and the low-voltage well region 12.

[0104] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising a high voltage device region and a low voltage device region; forming a first gate and a second gate on the substrate, wherein the first gate is located in the high-voltage device region, and the second gate is located in the low-voltage device region; forming a first spacer layer on the sidewall of the first gate; A second spacer layer is formed on the sidewall of the first spacer layer and the sidewall of the second gate respectively.

2. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a first gate and a second gate on the substrate, wherein the first gate is located in the high-voltage device region and the second gate is located in the low-voltage device region, comprises: forming a gate material layer on the substrate; forming a sacrificial material layer on the gate material layer in the high voltage device region; The gate material layer and the sacrificial material layer are etched to form the first gate and the second gate; wherein a sacrificial layer is formed on a surface of the first gate.

3. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming a first gate and a second gate on the substrate, wherein the first gate is located in the high-voltage device region and the second gate is located in the low-voltage device region, comprises: forming a gate material layer on the substrate; Etching the gate material layer to form the first gate and the second gate; A sacrificial layer is formed on the surface of the second gate.

4. The method for preparing a semiconductor device according to claim 2 or 3, characterized in that: The step of forming a first spacer layer on the sidewall of the first gate includes: Forming a first spacer material layer on the substrate; wherein the first spacer material layer covers the surface of the substrate, the surface of the sacrificial layer and the surface of the second gate, and the material of the first spacer material layer is the same as that of the sacrificial material layer; The first spacer material layer and the sacrificial layer are etched to form the first spacer layer.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: The step of engraving the first spacer material layer and the sacrificial layer to form a first spacer layer includes: Performing a first etching on the first spacer material layer to expose the top surface of the sacrificial layer; The sacrificial layer and the remaining first spacer material layer are etched for the second time to form the first spacer layer.

6. The method for preparing a semiconductor device according to claim 1, wherein: The step of forming a second spacer layer on the sidewall of the first spacer layer and the sidewall of the second gate respectively comprises: Forming a second spacer material layer on the substrate; wherein the second spacer material layer covers the surface of the substrate, the surface of the first gate, the surface of the first spacer layer and the surface of the second gate; The second spacer material layer is etched to form the second spacer layer.

7. A semiconductor device, characterized in that: include: A substrate, including a high voltage device region and a low voltage device region; A first gate is disposed on the substrate and located in the high voltage device region; A second gate is disposed on the substrate and located in the low voltage device region; A first spacer layer, disposed around a side wall of the first gate; as well as A second spacer layer is provided around the sidewalls of the first spacer layer and the second gate.

8. The semiconductor device according to claim 7, characterized in that The material of the first sidewall layer is the same as that of the second sidewall layer.

9. The semiconductor device according to claim 7, characterized in that Along a thickness direction perpendicular to the substrate, the first spacer layer has a first thickness, and the second spacer layer has a second thickness; The first thickness is not greater than the second thickness.

10. The semiconductor device according to claim 7, wherein: Along a thickness direction perpendicular to the substrate, the first spacer has a first thickness, and the second spacer has a second thickness; The ratio of the first thickness to the second thickness is between 0.2-1.

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