Heterojunction solar cell structure, preparation method and cell

Abstract

The invention discloses a heterojunction solar cell structure and a preparation method thereof. The cell structure is characterized in that a silicon dioxide film layer, a first hydrogenated intrinsic amorphous silicon layer, an n-type H-doped amorphous silicon thin film layer and an n-type H-doped nano silicon thin film layer are sequentially laminated on one side of an N-type monocrystalline silicon substrate; a second hydrogenated intrinsic amorphous silicon layer, a p-type H-doped amorphous silicon thin film layer and a p-type H-doped nano silicon thin film layer are sequentially laminated on the other side of the N-type monocrystalline silicon substrate; a seed conductive layer, a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially arranged on the n / p type H-doped nano silicon thin film layer, the seed conductive layer and the main conductive layer are made of indium tin oxide, and the conductive buffer layer is made of copper-doped indium tin oxide; by improving the internal structure of the cell, the interface contact between the film layer and the doping layer can be optimized, the carrier recombination is reduced, and the photoelectric conversion efficiency of the cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of heterojunction solar cells, and in particular to a heterojunction solar cell structure, a preparation method and a cell. Background Art

[0002] Heterojunction solar cells. It is a highly efficient solar cell technology that optimizes light absorption and carrier separation efficiency by forming a heterojunction between different semiconductor materials, thereby improving the conversion efficiency of solar cells.

[0003] The common heterojunction solar cell structure mainly deposits the intrinsic amorphous silicon layer and the doped layer on both sides of the single crystal silicon substrate film layer. Although it can improve the conversion efficiency to a certain extent, it is limited by its preparation method, interface characteristics and light absorption and projection ability, so its conversion efficiency is still not high. In addition, the traditional heterojunction solar cell structure and preparation method may still bring some unavoidable problems, such as: when depositing the intrinsic amorphous silicon layer and the doped layer, high-energy particle bombardment may cause surface damage to the N-type single crystal silicon substrate, increase interface defects, reduce open circuit voltage and photoelectric conversion efficiency, and the defect state density at the interface between the intrinsic amorphous silicon layer and the crystalline silicon is high, which is easy to cause carrier recombination and reduce battery performance.

[0004] It can be seen that how to improve the internal structure of heterojunction solar cells to improve the conversion efficiency of the cells has become a technical problem that needs to be urgently solved by those skilled in the art. Summary of the invention

[0005] The present invention provides a heterojunction solar cell structure, a preparation method and a cell to solve the problem of how to improve the internal structure of a heterojunction solar cell to avoid damage to a doping layer film and to improve the photoelectric conversion efficiency of the cell.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a heterojunction solar cell structure, comprising:

[0007] N-type single crystal silicon substrate, silicon dioxide film layer, first hydrogenated intrinsic amorphous silicon layer, second hydrogenated intrinsic amorphous silicon layer, n-type H-doped amorphous silicon thin film layer, p-type H-doped amorphous silicon thin film layer, n-type H-doped nano-silicon thin film layer, p-type H-doped nano-silicon thin film layer, seed conductive layer, main conductive layer, conductive buffer layer and metal electrode layer;

[0008] The silicon dioxide film layer is disposed on one side of the N-type single crystal silicon substrate, and the first hydrogenated intrinsic amorphous silicon layer is disposed on the other side;

[0009] The p-type H-doped amorphous silicon thin film layer is provided on a side of the first hydrogenated intrinsic amorphous silicon layer away from the N-type single crystal silicon substrate, and the p-type H-doped nano-silicon thin film layer is provided on a side of the p-type H-doped amorphous silicon thin film layer away from the first hydrogenated intrinsic amorphous silicon layer;

[0010] The second hydrogenated intrinsic amorphous silicon layer is provided on a side of the silicon dioxide film layer away from the N-type single crystal silicon substrate, and an n-type H-doped amorphous silicon thin film layer is provided on a side of the second hydrogenated intrinsic amorphous silicon layer away from the silicon dioxide film layer;

[0011] The n-type H-doped nano-silicon thin film layer is disposed on a side of the n-type H-doped amorphous silicon thin film layer away from the second hydrogenated intrinsic amorphous silicon layer;

[0012] Wherein, a seed conductive layer, a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially deposited on the n-type H-doped nano-silicon thin film layer and the p-type H-doped nano-silicon thin film layer respectively.

[0013] Furthermore, the seed conductive layer and the main conductive layer are both made of indium tin oxide, wherein:

[0014] The thickness of the seed conductive layer is 20-50 nm, and the thickness of the main conductive layer is 40-150 nm.

[0015] Furthermore, the conductive buffer layer is made of indium tin oxide doped with 1 wt % copper, and has a thickness of 10-20 nm.

[0016] Furthermore, the n-type H-doped amorphous silicon thin film layer and the p-type H-doped amorphous silicon thin film layer are seed layers, wherein:

[0017] The thickness of the n-type H-doped amorphous silicon thin film layer is 1-2 nm, and the thickness of the p-type H-doped amorphous silicon thin film layer is 3-5 nm.

[0018] Furthermore, the p-type H-doped nano-silicon thin film layer is used as a hole transport layer and has a thickness of 5-7 nm.

[0019] Another embodiment of the present invention provides a method for preparing a heterojunction solar cell, which is applied to the above-mentioned heterojunction solar cell structure, comprising:

[0020] Texturing, cleaning and etching of N-type single crystal silicon substrate;

[0021] Prepare a layer of intrinsic amorphous silicon layer on the front and back of the N-type single crystal silicon substrate respectively, and deposit a layer of silicon dioxide passivation layer between the front of the N-type single crystal silicon substrate and the bottom of the intrinsic amorphous silicon layer through a deposition cycle;

[0022] Depositing an n-type H-doped amorphous silicon thin film layer and an n-type H-doped nano-silicon thin film layer in sequence on the intrinsic amorphous silicon layer on the front side;

[0023] Depositing a p-type H-doped amorphous silicon thin film layer and a p-type H-doped nano-silicon thin film layer in sequence on the intrinsic amorphous silicon layer on the back side;

[0024] A seed conductive layer is deposited on the top surface of the n-type H-doped nano-silicon film layer and the bottom surface of the p-type H-doped nano-silicon film layer respectively by a target deposition method, and a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially deposited on the seed conductive layer.

[0025] Further, the step of depositing a silicon dioxide passivation layer between the front surface of the N-type single crystal silicon substrate and the bottom surface of the intrinsic amorphous silicon layer through a deposition cycle comprises:

[0026] In the first deposition process, SiCl2, argon and ozone are introduced into the front surface of the N-type single crystal silicon substrate in sequence by an atomic vapor deposition method, and then argon is introduced after heating;

[0027] The first deposition process is repeatedly performed in a cycle until the corresponding silicon dioxide passivation layer is obtained.

[0028] Furthermore, the n-type H-doped nano-silicon thin film layer is prepared by introducing silane, hydrogen and phosphine onto the n-type H-doped amorphous silicon thin film layer through a high-frequency chemical vapor deposition method.

[0029] Furthermore, the target deposition method is used to deposit a seed conductive layer on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer, and a main conductive layer and a conductive buffer layer are sequentially deposited on the seed conductive layer, including:

[0030] Depositing a layer of indium tin oxide film as a seed conductive layer on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer respectively through a target process;

[0031] A layer of indium tin oxide film is plated on the seed conductive layer as a main conductive layer by physical vapor deposition;

[0032] A layer of indium tin oxide doped with 1 wt % copper is deposited on the main conductive layer as a conductive buffer layer.

[0033] Yet another embodiment of the present invention provides a heterojunction solar cell, comprising the above heterojunction solar cell structure.

[0034] Compared with the prior art, the embodiments of the present invention have the following advantages:

[0035] (1) The present invention adopts a composite film layer of silicon dioxide and hydrogenated intrinsic amorphous silicon film layer for passivation, thereby improving the passivation efficiency and reducing the passivation cost. The use of silicon dioxide film layer as a base can solve the problem of damage to the intrinsic amorphous silicon film layer. In addition, the intrinsic amorphous silicon film layer also optimizes the interface contact between the silicon dioxide film layer and the doped film layer, reduces carrier recombination, and improves the photoelectric conversion efficiency of the battery.

[0036] (2) Depositing a layer of n / pa-Si:H film on the passivation layer can not only transmit electrons, but also allow n / pa-Si:H to form a better film and act as a seed layer. It can also prevent the high-energy ions of n / p-nc-Si:H from damaging the passivation layer. Plating a layer of copper-doped indium tin oxide at the bottom of the main conductive layer as a conductive buffer layer can improve the poor contact between the copper electrode and indium tin oxide, improve the adhesion of the copper electrode, reduce the ohmic contact of the interface, and improve the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a schematic diagram of the structure of a heterojunction solar cell provided by the present invention;

[0038] Figure 2 is a schematic diagram of the structure of a heterojunction solar cell in one embodiment of the present invention;

[0039] Reference numerals

[0040] 1n-type single crystal silicon substrate, 2 silicon dioxide film layer, 3 first hydrogenated intrinsic amorphous silicon layer, 4 second hydrogenated intrinsic amorphous silicon layer, 5n-type H-doped amorphous silicon thin film layer, 6p-type H-doped amorphous silicon thin film layer, 7n-type H-doped nano-silicon thin film layer, 8p-type H-doped nano-silicon thin film layer, 9 seed conductive layer, 10 main conductive layer, 11 conductive buffer layer and 12 metal electrode layer. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. The purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] In the description of this application, the terms "first", "second", "third", etc. are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", "third", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0043] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be a connection between the two elements. The terms "vertical", "horizontal", "left", "right", "upper", "lower" and similar expressions used herein are only for illustrative purposes, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In the description of this application, it should be noted that, unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as those commonly understood by those skilled in the art. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood by specific circumstances.

[0045] While traditional heterojunction solar cells (HJT) show high conversion rates and broad application prospects, they also have some defects and areas that need improvement. For example: obtaining an amorphous silicon / crystalline silicon interface with a low interface state is a key step in the manufacturing process of HJT cells, which has very high requirements for the process environment and operation. Any slight process fluctuation may lead to a decrease in cell performance. Due to the low-temperature process characteristics of HJT cells, the subsequent high-temperature packaging process of traditional crystalline silicon cells cannot be used, and a suitable low-temperature packaging process needs to be developed. This increases the complexity and cost of the packaging process. In addition, in the stacked structure, the separation and transmission of excitons need to be carried out in different material layers, which requires good energy level matching and charge transfer characteristics between the materials in each layer. However, there are often problems of energy level mismatch or low transmission efficiency in actual battery structures.

[0046] In view of the above technical problems, the present invention improves the structure of a heterojunction solar cell and provides a heterojunction solar cell structure. For details, see Figure 1 , Figure 1 A schematic diagram of the structure of a heterojunction solar cell provided by the present invention is shown, comprising:

[0047] 1n-type single crystal silicon substrate, 2 silicon dioxide film layer, 3 first hydrogenated intrinsic amorphous silicon layer, 4 second hydrogenated intrinsic amorphous silicon layer, 5n-type H-doped amorphous silicon thin film layer, 6p-type H-doped amorphous silicon thin film layer, 7n-type H-doped nano-silicon thin film layer, 8p-type H-doped nano-silicon thin film layer, 9 seed conductive layer, 10 main conductive layer, 11 conductive buffer layer and 12 metal electrode layer.

[0048] The silicon dioxide film layer is disposed on one side of the N-type single crystal silicon substrate, and the first hydrogenated intrinsic amorphous silicon layer is disposed on the other side.

[0049] In the embodiment of the present invention, N-type single crystal silicon is selected as the substrate material of the solar cell. N-type single crystal silicon has good conductivity due to the presence of a large number of free electrons. Preferably, the thickness of the N-type single crystal silicon substrate is 120-150 um.

[0050] In some implementations of the present invention, a silicon dioxide (SiO2) film layer is provided on one side of an N-type single crystal silicon substrate, and SiO2 is used as a passivation layer of a solar cell. By depositing a thin and uniform SiO2 layer on the surface of an N-type single crystal silicon substrate, the surface recombination rate can be significantly reduced and the collection efficiency of photogenerated carriers can be improved. The main function of the passivation layer is to reduce the recombination loss at the interface of the solar cell, that is, to reduce the phenomenon of photogenerated carriers (electrons and holes) recombination and release of energy at the interface, thereby improving the photoelectric conversion efficiency of the solar cell.

[0051] It is understandable that due to the presence of the SiO2 film layer, damage to the N-type single crystal silicon substrate can be avoided during the deposition of the hydrogenated intrinsic amorphous silicon layer (ia-Si:H). Preferably, the thickness of the silicon dioxide film layer may be 1-2 nm.

[0052] Further, the first hydrogenated intrinsic amorphous silicon layer refers to an intrinsic amorphous silicon layer provided on the other side of the N-type single crystal silicon substrate. In some embodiments of the present invention, the ia-Si:H layer is used as a passivation layer to improve the passivation effect of the battery structure. Preferably, in this embodiment, the thickness of the first hydrogenated intrinsic amorphous silicon layer is 3-5 nm.

[0053] The p-type H-doped amorphous silicon thin film layer is disposed on a side of the first hydrogenated intrinsic amorphous silicon layer away from the N-type single crystal silicon substrate, and the p-type H-doped nano-silicon thin film layer is disposed on a side of the p-type H-doped amorphous silicon thin film layer away from the first hydrogenated intrinsic amorphous silicon layer.

[0054] In some embodiments of the present invention, a p-type H-doped amorphous silicon thin film layer (pa-Si:H) is disposed on the hydrogenated intrinsic amorphous silicon layer, mainly to provide a transmission channel for holes (positive charge carriers). It forms a heterojunction interface with the ia-Si:H layer, which helps to effectively separate photogenerated electrons and holes. Under illumination, photogenerated electrons are pushed to the n-type layer, while holes flow to the p-type layer. Since pa-Si:H can both transport electrons and act as a seed layer to enable pa-Si:H to form a better film, the pa-Si:H layer is used as a seed layer in an embodiment of the present invention. Preferably, the thickness of the p-type H-doped amorphous silicon thin film layer may be 3-5nm.

[0055] In some embodiments of the present invention, a p-type H-doped nano silicon film layer is disposed on the p-type H-doped amorphous silicon film layer as a hole transport layer. It is understandable that the nano silicon film may provide a more efficient hole transport channel than a conventional amorphous silicon film due to its nanoscale grains and grain boundaries. This helps to reduce the recombination loss of holes during the transmission process. At the nanoscale, the silicon film may exhibit quantum effects, such as quantum confinement effect and tunneling effect. These effects may have a positive impact on the transport and recombination of carriers.

[0056] Preferably, the thickness of the p-type H-doped nano-silicon thin film layer is 5-7 nm.

[0057] The second hydrogenated intrinsic amorphous silicon layer is provided on the side of the silicon dioxide film layer away from the N-type single crystal silicon substrate, and the n-type H-doped amorphous silicon thin film layer is provided on the side of the second hydrogenated intrinsic amorphous silicon layer away from the silicon dioxide film layer. The second hydrogenated intrinsic amorphous silicon layer refers to an intrinsic amorphous silicon layer provided on the silicon dioxide film layer.

[0058] The ia-Si:H layer can form a heterojunction with the SiO2 passivation layer below and the doped amorphous silicon layer above. This structure helps to reduce interface recombination, improve open circuit voltage and fill factor. Preferably, in this embodiment, the thickness of the second hydrogenated intrinsic amorphous silicon layer is 3-5nm.

[0059] In some embodiments of the present invention, an n-type H-doped amorphous silicon thin film layer (na-Si:H) is provided on the ia-Si:H layer as a seed layer. Similar to the above-mentioned p-type H-doped amorphous silicon thin film layer, it mainly provides a transmission channel for electrons, reduces the damage of the nanolayer to the passivation layer and improves the carrier transmission efficiency. Preferably, in some embodiments of the present invention, the thickness of the n-type H-doped amorphous silicon thin film layer is 1-2nm.

[0060] The n-type H-doped nano-silicon thin film layer is disposed on a side of the n-type H-doped amorphous silicon thin film layer away from the second hydrogenated intrinsic amorphous silicon layer.

[0061] Wherein, a seed conductive layer, a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially deposited on the n-type H-doped nano-silicon thin film layer and the p-type H-doped nano-silicon thin film layer respectively.

[0062] In some embodiments of the present invention, an n-type H-doped nano-silicon film layer (n-nc-Si:H) is coated on the n-type H-doped amorphous silicon film layer as an electron transport layer. The n-nc-Si:H layer can form a better interface contact with the na-Si:H layer below and the conductive layer or metal electrode layer above, reduce the interface resistance and recombination center, and further promote the collection and transmission of electrons. Preferably, in this embodiment, the thickness of the n-type H-doped nano-silicon film layer is 5-7nm.

[0063] Further, in the embodiment of the present invention, a plurality of conductive layers are provided, including a seed conductive layer, a main conductive layer and a conductive buffer layer. They are respectively arranged on the n / p type H-doped nano silicon thin film layer in sequence. It can be understood that the seed conductive layer, as the first layer of conductive material, mainly serves to provide a uniform, low-resistance substrate for subsequent deposition of a thicker or more conductive main conductive layer.

[0064] Indium tin oxide (ITO) is mainly composed of indium oxide (In2O3) and tin oxide (SnO2) mixed in a certain proportion. This doping allows ITO to have good transparency and conductivity while maintaining high light transmittance. Therefore, in some embodiments of the present invention, the material of the seed conductive layer is indium tin oxide, and preferably, its thickness can be 20-50nm.

[0065] The main conductive layer is the core part of the electrode system and is mainly responsible for collecting charges and effectively transmitting the collected current to the external circuit. Since ITO has good conductivity, it can effectively transfer electrons (on the n-type side) or holes (on the p-type side) from the nano-silicon film layer to the metal electrode layer. Therefore, in some embodiments of the present invention, the material of the main conductive layer is indium tin oxide, and preferably, its thickness can be 40-150nm. In addition, the main conductive layer also has a certain mechanical strength, which can protect the nano-silicon film layer below from the influence of the external environment.

[0066] The conductive buffer layer is located between the main conductive layer and the metal electrode layer. Its main function is to improve the interface contact between the two, reduce the contact resistance, and prevent the metal electrode layer from having an undesirable chemical reaction with the conductive layer below. In some embodiments of the present invention, the material of the conductive buffer layer is indium tin oxide doped with 1wt% copper (Cu). It can be understood that copper doping can further reduce the resistivity of ITO, improve the conductivity of the battery, and resist adverse factors such as oxidation and corrosion. Preferably, its thickness can be 10-20nm.

[0067] In this embodiment, preferably, the material of the metal electrode layer may be copper.

[0068] In summary, by improving the stacked structure of heterojunction solar cells, a passivation layer is set on an N-type single crystal silicon substrate, and a passivation structure of a SiO2 and ia-Si:H film composite film layer is adopted, the passivation efficiency can be improved and the passivation cost can be reduced; an n / p-type H-doped amorphous silicon film layer and an n / p-type H-doped nano-silicon film layer are set on the passivation layer to reduce the recombination loss of holes and the damage of the film layer during the transmission process, and to improve the carrier transmission efficiency; a multi-layer conductive layer is set on the n / p-type H-doped nano-silicon film layer to improve the transmission efficiency of the load, reduce the interface ohmic contact, and improve the photoelectric conversion efficiency of the battery.

[0069] An embodiment of the present invention provides a method for preparing a heterojunction solar cell, specifically, comprising the following steps:

[0070] S1. Texturing, cleaning and etching the N-type single crystal silicon substrate.

[0071] S2, preparing an intrinsic amorphous silicon layer on the front and back sides of the N-type single crystal silicon substrate respectively, and depositing a silicon dioxide passivation layer between the front side of the N-type single crystal silicon substrate and the bottom side of the intrinsic amorphous silicon layer through a deposition cycle.

[0072] S3, sequentially depositing an n-type H-doped amorphous silicon thin film layer and an n-type H-doped nano-silicon thin film layer on the front intrinsic amorphous silicon layer.

[0073] S4, sequentially depositing a p-type H-doped amorphous silicon thin film layer and a p-type H-doped nano-silicon thin film layer on the intrinsic amorphous silicon layer on the back side.

[0074] S5. Depositing a seed conductive layer on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer respectively by a target deposition method, and depositing a main conductive layer, a conductive buffer layer and a metal electrode layer in sequence on the seed conductive layer.

[0075] According to a specific solution of the preparation method of the present invention, in step S1, KOH or NaOH is used to texture the N-type single crystal silicon substrate. These two alkalis can react with silicon, especially within a certain temperature range, and can effectively form a fine texture structure on the silicon surface. This texture structure helps to increase the roughness of the silicon surface, thereby improving the light absorption efficiency of subsequent processes such as solar cells. During this period, preferably, the etching temperature is set to 70-90°C.

[0076] The texturized substrate is then cleaned with ozone ultrapure water. Ozone has strong oxidizing properties and can effectively remove impurities such as organic matter and metal ions on the surface of the substrate.

[0077] Then, hydrofluoric acid (HF) is used for etching. HF can remove the natural oxide layer on the surface of the substrate, thereby obtaining the N-type single crystal silicon substrate required for preparing the battery.

[0078] According to a specific solution of the preparation method of the present invention, in step S2, a layer of SiO2 is deposited on the front side of the N-type single crystal silicon substrate by atomic vapor deposition, specifically:

[0079] In the first deposition process, SiCl2 (silicon-chlorine mixed gas), argon (Ar) and ozone (O3) are introduced into the front surface of the N-type single crystal silicon substrate in sequence by atomic vapor deposition, and then argon is introduced after heating.

[0080] In some embodiments of the present invention, a deposition cycle has 4 steps:

[0081] Step 1, first introduce SiCl2, ventilation time 15S;

[0082] Step 2: introduce Ar again for 15 seconds;

[0083] Step 3, introducing O3 again for 15 seconds, and heating the substrate to between 403-453°C;

[0084] Step 4: introduce Ar again for 15 s.

[0085] The first deposition process is repeatedly performed in a cycle until the corresponding silicon dioxide passivation layer is obtained.

[0086] In some implementations of the present invention, 3-6 cycles of deposition may be performed. The SiO2 film layer plays a role in passivating the N-type single crystal silicon, and the use of the atomic vapor deposition method reduces the damage to the N-type single crystal silicon substrate.

[0087] A layer of intrinsic amorphous silicon is deposited on the deposited SiO2 film layer. In some embodiments of the present invention, chemical vapor deposition (CVD) is used, and silane (SiH4) and hydrogen (H2) are introduced as precursors for deposition. During the deposition process, on the surface of the substrate, silane molecules begin to decompose to produce silicon atoms and hydrogen. At the same time, hydrogen molecules react with silicon atoms or other groups on the surface of the substrate. These reactions cause silicon atoms to be deposited on the surface of the substrate and gradually form a hydrogenated intrinsic amorphous silicon layer. The hydrogenated intrinsic amorphous silicon layer usually has characteristics such as a wider band gap, a higher light absorption coefficient and a lower dark conductivity. Therefore, depositing intrinsic amorphous silicon layers on the front and back sides of the substrate can help improve the photoelectric conversion efficiency of the battery.

[0088] According to a specific solution of the preparation method of the present invention, in the steps S3 and S4, a doping layer is deposited on the intrinsic amorphous silicon layer deposited on the front and back sides of the substrate respectively.

[0089] In an embodiment of the present invention, the doped layer includes H-doped amorphous silicon and H-doped nano-silicon layer. Preferably, the deposition is carried out by CVD, and silane, hydrogen and phosphine are introduced as precursors to deposit an n-type H-doped amorphous silicon film on the hydrogenated intrinsic amorphous silicon layer on the front side of the substrate.

[0090] Further, the n-type H-doped nano-silicon film layer is prepared by introducing silane, hydrogen and phosphine into the n-type H-doped amorphous silicon film layer by high-frequency chemical vapor deposition. It can be understood that the high-frequency chemical vapor deposition method refers to very high frequency plasma enhanced chemical vapor deposition (VHF-PECVD / very high frequency PECVD) technology, which is a technology that uses a high-frequency electric field to excite gas molecules to form plasma, thereby promoting chemical reactions and deposition processes. The high-frequency electric field can accelerate the collision of electrons and gas molecules, generate more active free radicals and ions, thereby increasing the rate and efficiency of the chemical reaction.

[0091] In the embodiment of the present invention, preferably, the frequency of the very high frequency PECVD that can be used is: 40 MHz, 70 MHz, 110 MHz.

[0092] Similarly, a p-type H-doped amorphous silicon thin film layer and a p-type H-doped nano-silicon thin film layer are prepared on the hydrogenated intrinsic amorphous silicon layer on the back of the substrate. The preparation method is similar to the deposition method on the front of the substrate, except that the gases introduced are silane, hydrogen and borane (B2H6), and the specific process is not repeated here.

[0093] According to a specific solution of the preparation method of the present invention, in step S5, a conductive layer and a metal electrode layer are deposited on the nano-doped layer, specifically:

[0094] A layer of indium tin oxide film is deposited on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer as a seed conductive layer through a target process.

[0095] The target process is a special coating technology that uses two or more targets to simultaneously or alternately emit particles (such as metal atoms or ions) to the substrate to form the desired film on the substrate. Since there is no direct contact between the target and the substrate, and the coating process can be optimized by precisely controlling the coating parameters (such as particle energy, angle, speed, etc.), the mechanical and thermal damage to the n-type H-doped nanosilicon film can be significantly reduced.

[0096] Since the conductivity and light transmission properties of the battery are significantly affected by the uniformity and defects of the film, the double-target process can provide a more uniform coating effect because the emission particles of two or more targets can complement and balance each other, thereby reducing the non-uniformity and defects in the coating process. This is crucial for the formation of a high-quality indium tin oxide conductive seed layer.

[0097] A layer of indium tin oxide film is plated on the seed conductive layer as a main conductive layer by physical vapor deposition (PVD).

[0098] In the embodiment of the present invention, a main conductive layer is plated using a high-purity ITO target or evaporation source. The main conductive layer has good conductivity and light transmittance, and also has good adhesion to the underlying structure.

[0099] A layer of indium tin oxide doped with 1 wt % copper is deposited on the main conductive layer as a conductive buffer layer.

[0100] In the embodiment of the present invention, a conductive buffer layer is deposited on the main conductive layer by physical vapor deposition, which can improve the problem of poor contact between the metal electrode layer and the indium tin oxide film.

[0101] Finally, a metal electrode layer is deposited on the main conductive layer to complete the preparation process of the heterojunction battery of the present invention.

[0102] In order to further clearly reflect the structural characteristics of the heterojunction cell solar cell of the present invention, a perovskite tandem solar cell and a preparation method thereof provided by the present invention are described in detail below in combination with specific embodiments.

[0103] The reagents used in the following examples are all commercially available.

[0104] Example 1

[0105] (1) Select N-type single crystal silicon with a thickness of 130um as the substrate.

[0106] (2) KOH or NaOH is used at an etching temperature of 80°C to texturize the N-type single crystal silicon substrate, and then the substrate is cleaned with ozone ultrapure water, and then etched with HF at a concentration of 35%.

[0107] (3) A layer of SiO2 is deposited on the front side of an N-type single crystal silicon substrate using the PVD method. One deposition cycle includes the following four steps:

[0108] Step 1, first introduce SiCl2, the ventilation time is 15S; Step 2, then introduce Ar, the ventilation time is 15S; Step 3, then introduce O3, the ventilation time is 15S; at the same time, the substrate temperature is heated to 433°C; Step 4, then introduce Ar, the ventilation time is 15S; 4 cycles of co-deposition are performed, and the deposition thickness is 1.5nm.

[0109] (4) Using CVD deposition, silane and hydrogen are introduced to deposit a 4 nm thick hydrogenated intrinsic amorphous silicon layer on the SiO2 film layer. Similarly, a 4 nm thick hydrogenated intrinsic amorphous silicon layer is deposited on the back of the N-type single crystal silicon substrate.

[0110] (5) A layer of n-type H-doped amorphous silicon film with a thickness of 1.5 nm is deposited on the hydrogenated intrinsic amorphous silicon layer on the front side by chemical vapor deposition by introducing silane, hydrogen and phosphine. Similarly, a layer of p-type H-doped amorphous silicon film with a thickness of 4 nm is deposited on the hydrogenated intrinsic amorphous silicon layer on the back side by CVD by introducing silane, hydrogen and borane.

[0111] (6) A high-frequency chemical vapor deposition method with a very high frequency PECVD frequency of 110 MHz was used to introduce silane, hydrogen and phosphine onto the n-type H-doped amorphous silicon film, and a layer of n-type H-doped nano-silicon film with a thickness of 6 nm was deposited on the n-type H-doped amorphous silicon film. Similarly, a high-frequency chemical vapor deposition method with a very high frequency PECVD frequency of 110 MHz was used to introduce silane, hydrogen and borane, and a layer of p-type H-doped nano-silicon film with a thickness of 6 nm was deposited on the p-type H-doped amorphous silicon film.

[0112] (7) Using a target-to-target process, a layer of ITO film is deposited on the n-type H-doped nano-silicon film and the p-type H-doped nano-silicon film as a seed conductive layer, each with a thickness of 35 nm.

[0113] (8) A layer of ITO film with a thickness of 150 nm is deposited on the ITO seed conductive layer using the PVD method as the main conductive layer.

[0114] (9) A 1 wt % Cu-doped ITO film layer is deposited on the ITO main conductive layer using the PVD method as a conductive buffer layer with a thickness of 15 nm, and a Cu electrode is deposited accordingly.

[0115] A solar cell is prepared according to the method for preparing a heterojunction solar cell in Embodiment 1. For details, see Figure 2 , Figure 2 A schematic diagram of the structure of a heterojunction solar cell in one embodiment of the present invention is shown, and the photoelectric conversion efficiency of the heterojunction solar cell prepared in Implementation 1 is tested.

[0116] Example 2

[0117] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0118] (3) The thickness of the prepared SiO2 film is: 0.5nm, 1nm, 2nm, 2.5nm. The thickness of the other film layers is the same, and the effect of SiO2 film layers of different thicknesses on the photoelectric conversion efficiency of the battery is observed.

[0119] Example 3

[0120] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0121] (4) The thickness of the deposited hydrogenated intrinsic amorphous silicon layer is 2 nm, 3 nm, 5 nm, and 6 nm. The thickness of the other film layers is the same, and the effect of hydrogenated intrinsic amorphous silicon layers of different thicknesses on the photoelectric conversion efficiency of the battery is observed.

[0122] Example 4

[0123] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0124] (5) The thickness of the n-type H-doped amorphous silicon film was changed to 0.5 nm, 1 nm, 2 nm, and 2.5 nm. The thickness of the other film layers was the same, and the effect of the different thicknesses of the n-type H-doped amorphous silicon film layers on the photoelectric conversion efficiency of the battery was observed.

[0125] Example 5

[0126] Similar to Example 4, a heterojunction solar cell was prepared according to the method of Example 1, and the thickness of the p-type H-doped amorphous silicon film was changed to 2nm, 3nm, 5nm, and 6nm. The thickness of the other film layers was the same, and the effect of n-type H-doped amorphous silicon film layers of different thicknesses on the photoelectric conversion efficiency of the cell was observed.

[0127] Example 6

[0128] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0129] (6) The thickness of the n-type H-doped nano-silicon film is 4 nm, 5 nm, 7 nm, and 8 nm. The thickness of the other film layers is the same, and the effect of n-type H-doped nano-silicon film layers of different thicknesses on the photoelectric conversion efficiency of the battery is observed.

[0130] Example 7

[0131] Similar to Example 6, a heterojunction solar cell was prepared according to the method of Example 1, and the thickness of the p-type H-doped nano-silicon film was changed to 3 nm, 5 nm, 7 nm, and 9 nm. The thickness of the other film layers was the same, and the effect of the p-type H-doped nano-silicon film layers of different thicknesses on the photoelectric conversion efficiency of the cell was observed.

[0132] Example 8

[0133] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0134] (7) The thickness of the seed conductive layer was changed to 10 nm, 20 nm, 50 nm, and 60 nm. The thickness of the other film layers was the same, and the effect of seed conductive layers of different thicknesses on the photoelectric conversion efficiency of the battery was observed.

[0135] Example 9

[0136] A heterojunction solar cell was prepared according to the method of Example 1, except that:

[0137] (9) The thickness of the conductive buffer layer was changed to: 5nm, 10nm, 20nm, 25nm. The thickness of the other film layers was the same, and the effect of conductive buffer layers of different thicknesses on the photoelectric conversion efficiency of the battery was observed.

[0138] Based on the preparation, observation and testing process of Examples 1 to 9, each example and comparison are shown in Table 1:

[0139] Table 1 Effect of different thicknesses of different film layers on the performance of heterojunction solar cells

[0140]

[0141]

[0142]

[0143]

[0144] It can be seen from the results in Table 1 that the photoelectric conversion efficiency of the solar cell prepared by Example 1 of the present invention is 23.14%, which is better than the photoelectric conversion efficiency of the solar cells prepared by Examples 2-9.

[0145] From the corresponding data of each embodiment in Table 1, it can be seen that the photoelectric conversion efficiency measured by the ITO conductive buffer layer with different thicknesses in Embodiment 9 is not better than that of the conductive buffer layer with a thickness of 15 nm in Embodiment 1, but is better than the photoelectric conversion efficiency measured by other embodiments except Embodiments 1 and 9. That is to say, the Cu-doped ITO conductive buffer layer has a great influence on the photoelectric conversion efficiency of the solar cell of the present invention, and the ITO conductive buffer layer with 1wt% Cu can greatly improve the photoelectric conversion efficiency of the solar cell.

[0146] In addition, it is worth noting that the thickness of each film layer has a significant impact on the conversion performance of the battery, but the thickness of the film layer does not necessarily mean that the thicker / thinner the film layer, the higher the conversion performance of the battery. It is necessary to find the best matching state of the thickness of each film layer through experiments and simulations to achieve the best light absorption, the lowest reflectivity and carrier recombination rate, so as to obtain the highest battery conversion performance.

[0147] Another embodiment of the present invention provides a heterojunction solar cell, including the above-mentioned heterojunction solar cell structure. The heterojunction solar cell of the present invention uses a heterojunction between different semiconductor materials as the main structure for photoelectric conversion, combines the high efficiency of amorphous silicon, and the excellent interface characteristics of doped amorphous silicon and doped nano-silicon, and has excellent photoelectric conversion efficiency.

[0148] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A heterojunction solar cell structure, characterized in that: include: N-type single crystal silicon substrate, silicon dioxide film layer, first hydrogenated intrinsic amorphous silicon layer, second hydrogenated intrinsic amorphous silicon layer, n-type H-doped amorphous silicon thin film layer, p-type H-doped amorphous silicon thin film layer, n-type H-doped nano-silicon thin film layer, p-type H-doped nano-silicon thin film layer, seed conductive layer, main conductive layer, conductive buffer layer and metal electrode layer; The silicon dioxide film layer is disposed on one side of the N-type single crystal silicon substrate, and the first hydrogenated intrinsic amorphous silicon layer is disposed on the other side; The p-type H-doped amorphous silicon thin film layer is provided on a side of the first hydrogenated intrinsic amorphous silicon layer away from the N-type single crystal silicon substrate, and the p-type H-doped nano-silicon thin film layer is provided on a side of the p-type H-doped amorphous silicon thin film layer away from the first hydrogenated intrinsic amorphous silicon layer; The second hydrogenated intrinsic amorphous silicon layer is provided on a side of the silicon dioxide film layer away from the N-type single crystal silicon substrate, and an n-type H-doped amorphous silicon thin film layer is provided on a side of the second hydrogenated intrinsic amorphous silicon layer away from the silicon dioxide film layer; The n-type H-doped nano-silicon thin film layer is disposed on a side of the n-type H-doped amorphous silicon thin film layer away from the second hydrogenated intrinsic amorphous silicon layer; Wherein, a seed conductive layer, a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially deposited on the n-type H-doped nano-silicon thin film layer and the p-type H-doped nano-silicon thin film layer respectively.

2. The heterojunction solar cell structure according to claim 1, characterized in that: The seed conductive layer and the main conductive layer are both made of indium tin oxide, wherein: The thickness of the seed conductive layer is 20-50 nm, and the thickness of the main conductive layer is 40-150 nm.

3. The heterojunction solar cell structure according to claim 1, characterized in that: The conductive buffer layer is made of indium tin oxide doped with 1 wt% copper and has a thickness of 10-20 nm.

4. The heterojunction solar cell structure according to claim 1, characterized in that: The n-type H-doped amorphous silicon thin film layer and the p-type H-doped amorphous silicon thin film layer are seed layers, wherein: The thickness of the n-type H-doped amorphous silicon thin film layer is 1-2 nm, and the thickness of the p-type H-doped amorphous silicon thin film layer is 3-5 nm.

5. The heterojunction solar cell structure according to claim 1, characterized in that: The p-type H-doped nano-silicon thin film layer is used as a hole transport layer and has a thickness of 5-7 nm.

6. A method for preparing a heterojunction solar cell, applied to the heterojunction solar cell structure according to any one of claims 1 to 5, characterized in that: include: Texturing, cleaning and etching of N-type single crystal silicon substrate; Prepare a layer of intrinsic amorphous silicon layer on the front and back of the N-type single crystal silicon substrate respectively, and deposit a layer of silicon dioxide passivation layer between the front of the N-type single crystal silicon substrate and the bottom of the intrinsic amorphous silicon layer through a deposition cycle; Depositing an n-type H-doped amorphous silicon thin film layer and an n-type H-doped nano-silicon thin film layer in sequence on the intrinsic amorphous silicon layer on the front side; Depositing a p-type H-doped amorphous silicon thin film layer and a p-type H-doped nano-silicon thin film layer in sequence on the intrinsic amorphous silicon layer on the back side; A seed conductive layer is deposited on the top surface of the n-type H-doped nano-silicon film layer and the bottom surface of the p-type H-doped nano-silicon film layer respectively by a target deposition method, and a main conductive layer, a conductive buffer layer and a metal electrode layer are sequentially deposited on the seed conductive layer.

7. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The step of depositing a silicon dioxide passivation layer between the front surface of the N-type single crystal silicon substrate and the bottom surface of the intrinsic amorphous silicon layer through a deposition cycle comprises: In the first deposition process, SiCl2, argon and ozone are introduced into the front surface of the N-type single crystal silicon substrate in sequence by an atomic vapor deposition method, and then argon is introduced after heating; The first deposition process is repeatedly performed in a cycle until the corresponding silicon dioxide passivation layer is obtained.

8. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The n-type H-doped nano-silicon thin film layer is prepared by introducing silane, hydrogen and phosphine into the n-type H-doped amorphous silicon thin film layer through a high-frequency chemical vapor deposition method.

9. The method for preparing a heterojunction solar cell according to claim 6, characterized in that: The method of using a target deposition method to deposit a seed conductive layer on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer, and sequentially depositing a main conductive layer and a conductive buffer layer on the seed conductive layer, comprises: Depositing a layer of indium tin oxide film as a seed conductive layer on the top surface of the n-type H-doped nano-silicon thin film layer and the bottom surface of the p-type H-doped nano-silicon thin film layer respectively through a target process; A layer of indium tin oxide film is plated on the seed conductive layer as a main conductive layer by physical vapor deposition; A layer of indium tin oxide doped with 1 wt % copper is deposited on the main conductive layer as a conductive buffer layer.

10. A heterojunction solar cell, characterized in that: It comprises the heterojunction solar cell structure as claimed in any one of claims 1 to 6.

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