Display panel and display device

Abstract

The invention provides a display panel and a display device, and relates to the technical field of display. A first active layer of a first transistor in the first pixel circuit and a second active layer of a second transistor in the second pixel circuit are both metal oxide active layers, the second pixel circuit is close to the hole opening area, the first pixel circuit is far away from the hole opening area, the first pixel circuit is provided with a first signal wire, and the second pixel circuit is provided with a second signal wire. The first pixel is provided with a first signal line, the orthographic projection of the first active layer on the substrate and the orthographic projection of the first signal line on the substrate are overlapped in the second direction, the second pixel is provided with a second signal line, and the orthographic projection of the second active layer on the substrate and the orthographic projection of the second signal line on the substrate are overlapped in the second direction. The second pixel circuit close to the hole opening area and the first pixel circuit far away from the hole opening area have the same routing design on the peripheries of the metal oxide active layers of the transistors in the two pixel circuits, the problem that the second pixel circuit close to the hole opening area is prone to failure is solved, and the display effect of the display panel is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of science and technology, various display devices have been widely used in people's lives and work, bringing great convenience to people's daily lives. As one of the important components of a display device, the design of the display panel will directly or indirectly affect the display effect of the display device.

[0003] Based on current display panels, in order to reduce power consumption during display, pixel circuits are usually implemented using LTPO (Low Temperature Polycrystalline Oxide) technology. In order to place components such as cameras, the display panel is designed with holes to form an opening area.

[0004] Currently, the wiring designs around the metal oxide active layer of the transistors in the pixel circuits of pixels close to the opening area and pixels far from the opening area are different. The pixel circuits close to the opening area are prone to failure, which in turn lights up the pixels, resulting in bright spots, affecting the display effect of the display panel. Summary of the invention

[0005] In view of the above problems, the present application provides a display panel and a display device, which improves the pixel wiring near the opening area so that the wiring design around the metal oxide active layer of the transistor in the pixel circuit of the pixel near the opening area and the pixel far from the opening area is the same, thereby solving the problem that the pixel circuit near the opening area is prone to failure and improving the display effect of the display panel. The specific solution is as follows:

[0006] In a first aspect, the present application provides a display panel, the display panel comprising: a pixel, an opening area, and a display area at least partially surrounding the opening area; the pixel comprises a first pixel arranged away from the opening area and a second pixel arranged close to the opening area;

[0007] The first pixel includes a first pixel circuit, the first pixel circuit includes a first transistor, the first transistor includes a first active layer and a first bottom gate and a first top gate located on both sides of the first active layer in a first direction; the first direction is perpendicular to the plane where the display panel is located;

[0008] The second pixel includes a second pixel circuit, the second pixel circuit includes a second transistor, the second transistor includes a second active layer and a second bottom gate and a second top gate located on both sides of the second active layer in the first direction; the first active layer and the second active layer are both metal oxide active layers;

[0009] The first pixel further includes a first signal line, the first signal line is arranged in the same layer as the first top gate, and an orthographic projection of the first active layer on the substrate overlaps with an orthographic projection of the first signal line on the substrate in a second direction;

[0010] The second pixel also includes a second signal line, which is arranged in the same layer as the second top gate, and the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second signal line on the substrate in a second direction; the second direction is parallel to the plane where the display panel is located and perpendicular to the length extension direction of the signal line, and the signal line is the first signal line or the second signal line.

[0011] A second aspect of the present application provides a display device, which includes the display panel described above.

[0012] By means of the above technical scheme, the present application provides a display panel and a display device, wherein the first active layer of the first transistor in the first pixel circuit and the second active layer of the second transistor in the second pixel circuit are both metal oxide active layers, the second pixel circuit is close to the opening area, and the first pixel circuit is far away from the opening area, the first pixel is provided with a first signal line, and the orthographic projection of the first active layer on the substrate overlaps with the orthographic projection of the first signal line on the substrate in a second direction, the second pixel is provided with a second signal line, and the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second signal line on the substrate in the second direction, so that the second pixel close to the opening area and the first pixel far away from the opening area have the same routing design around the metal oxide active layer of the transistors in the pixel circuits, thereby solving the problem that the second pixel circuit close to the opening area is prone to failure, and improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.

[0014] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0015] Figure 2 A schematic structural diagram of a first pixel circuit provided by an embodiment of the present invention;

[0016] Figure 3 A schematic structural diagram of a second pixel circuit provided by an embodiment of the present invention;

[0017] Figure 4 A schematic cross-sectional view of a display panel provided by an embodiment of the present invention;

[0018] Figure 5 A schematic diagram of a partial layout of a display panel provided by an embodiment of the present invention;

[0019] Figure 6 A schematic diagram of a partial layout of another display panel provided by an embodiment of the present invention;

[0020] Figure 7 A schematic diagram of signal routing in an opening area provided by an embodiment of the present invention;

[0021] Figure 8 A schematic diagram of signal routing in another opening area provided by an embodiment of the present invention;

[0022] Fig. 9 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described below in conjunction with the drawings in the embodiments of the present application. The terms used in the implementation method section of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. It is known to those of ordinary skill in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems. It should be noted that the directional words appearing in the present invention are based on the relative position relationship shown in the drawings and cannot be used as an absolute limitation on the present application.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] refer to Figure 1 , Figure 1 The structure diagram of a display panel provided by an embodiment of the present invention is as follows: the display panel 100 comprises: a pixel 10, an opening area A1 and a display area A2 at least partially surrounding the opening area A1. The opening area A1 is used to set other components such as a camera.

[0026] like Figure 1As shown, the display panel 100 includes signal lines extending in the row direction and signal lines extending in the column direction, and the signal lines extending in the row direction and the signal lines extending in the column direction intersect, and the intersection defines a plurality of pixels arranged in an array. Figure 1 As shown, the signal lines extending in the row direction may include Scan signal lines, Vref signal lines, DVH signal lines, etc. The signal lines extending in the row direction may include Data signal lines, PVDD signal lines, etc.

[0027] The pixel 10 includes a first pixel 11 disposed away from the opening area AA and a second pixel 12 disposed close to the opening area AA. The first pixel 11 includes a first pixel circuit 11a and a first light-emitting element 11b, and the second pixel 12 includes a second pixel circuit 12a and a second light-emitting element 12b.

[0028] refer to Figure 2 , Figure 2 A schematic diagram of the structure of a first pixel circuit provided in an embodiment of the present invention. The first pixel circuit 11a includes a first driving transistor T1 and a first light-emitting element 11b. The first driving transistor T1 is used to provide a first driving current to the first light-emitting element 11b, and the first light-emitting element 11b emits light in response to the first driving current. It should be noted that the first driving transistor T1 can be a PMOS driving transistor, or can be other types of driving transistors such as an NMOS driving transistor. In the embodiment of the present invention, the first driving transistor T1 is taken as an example of a PMOS driving transistor. The drain of the first driving transistor T1 is coupled to the first light-emitting element 11b, and provides the first driving current to the first light-emitting element 11b after the first driving transistor T1 is turned on.

[0029] refer to Figure 3 , Figure 3 A schematic diagram of the structure of a second pixel circuit provided in an embodiment of the present invention. The second pixel circuit 12a includes: a second driving transistor M1 and a second light-emitting element 12b, wherein the second driving transistor M1 is used to provide a second driving current to the second light-emitting element 12b, and the second light-emitting element 12b emits light in response to the second driving current; it should be noted that the second driving transistor M1 can be a PMOS driving transistor, or can be other types of driving transistors such as an NMOS driving transistor. In the embodiment of the present invention, the second driving transistor M1 is a PMOS driving transistor as an example for explanation. The drain of the second driving transistor M1 is coupled to the second light-emitting element 12b, and provides the second driving current to the second light-emitting element 12b after the second driving transistor M2 is turned on.

[0030] refer to Figure 4 , Figure 4A cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. The display panel 100 includes: a substrate 13 and an array layer located on the substrate 13. The array layer includes but is not limited to a buffer layer 14, a first insulating layer 15, a second insulating layer 16, a third insulating layer 17, a passivation layer 18, a planarization layer 19 and a pixel definition layer 20. The pixel definition layer 20 has a plurality of opening regions, in which an anode layer 21, a light-emitting layer 22 and a cathode layer 23 are arranged, constituting the light-emitting element required for the pixel 10.

[0031] Optionally, the substrate 13 is a substrate of a flexible insulating material having properties such as stretchability, bendability or flexibility, and its material includes but is not limited to polyimide material (PI for short) or polycarbonate material (PC for short) or polyethylene terephthalate material (PET for short) and the like.

[0032] Optionally, the buffer layer 14 includes but is not limited to an inorganic material layer or an organic material layer, wherein the material of the inorganic material layer includes but is not limited to silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide or aluminum nitride, and the material of the organic material layer includes but is not limited to acrylic or PI.

[0033] like Figure 4 As shown, the display panel 100 further includes a transistor, which forms a first pixel circuit 11a and a second pixel circuit 12a. The first transistor 24 corresponding to the first pixel circuit 11a in the first pixel 11 includes a first active layer 25, a first top gate 26, a first bottom gate 27, a first source 28 and a first drain 29. The first bottom gate 27 is located on the side of the buffer layer 14 away from the substrate 13, the first active layer 25 is located on the side of the first insulating layer 15 away from the substrate 13, the second insulating layer 16 is located between the first active layer 25 and the first top gate 26, the first top gate 26 is located on the side of the second insulating layer 16 away from the substrate 13, and the third insulating layer 17 is located on the side of the first top gate 26 away from the substrate 13. The first source 28 and the first drain 29 are located in the same layer and are located on the side of the third insulating layer 17 away from the substrate 13. The passivation layer 18 is disposed on the side of the first source electrode 28 and the first drain electrode 29 away from the substrate 13, the planarization layer 19 is disposed on the side of the passivation layer 18 away from the substrate 13, and the pixel definition layer 20 is disposed on the side of the planarization layer 19 away from the substrate 13. The first top gate 26 and the first bottom gate 27 are located on both sides of the first active layer 25 in the first direction X.

[0034] The second transistor 30 corresponding to the second pixel circuit 12a in the second pixel 12 includes a second active layer 31, a second top gate 32, a second bottom gate 33, a second source 34 and a second drain 35. The second bottom gate 33 is located on the side of the buffer layer 14 away from the substrate 13, the second active layer 31 is located on the side of the first insulating layer 15 away from the substrate 13, the second insulating layer 16 is located between the second active layer 31 and the second top gate 32, the second top gate 32 is located on the side of the second insulating layer 16 away from the substrate 13, and the third insulating layer 17 is located on the side of the second top gate 32 away from the substrate 13. The second source 34 and the second drain 35 are located in the same layer and on the side of the third insulating layer 17 away from the substrate 13. The passivation layer 18 is arranged on the side of the second source 34 and the second drain 35 away from the substrate 13, the planarization layer 19 is arranged on the side of the passivation layer 18 away from the substrate 13, and the pixel definition layer 20 is arranged on the side of the planarization layer 19 away from the substrate 13. The second top gate 32 and the second bottom gate 33 are located on both sides of the second active layer 31 in the first direction X.

[0035] The first active layer 25 and the second active layer 31 are both metal oxide active layers. The first active layer 25 and the second active layer 31 can be formed in the same layer, for example, both can be located in the film layer where the metal oxide active layer is located.

[0036] It should be noted that, in the embodiment of the present invention, the metal oxide active layer includes but is not limited to an IGZO active layer, and in the embodiment of the present invention, the metal oxide active layer is only described as an IGZO active layer.

[0037] Among them, the buffer layer 14 can be understood as a film layer used to set the bottom gate of the transistor. The second insulating layer 16 can be understood as a film layer used to set the top gate of the transistor, and other signal lines may be formed on the second insulating layer 16 as needed. The buffer layer 14 and the second insulating layer 16 are two different film layers. The buffer layer 14 can be understood as a film layer used to set an electrode plate of a storage capacitor in the pixel circuit, which overlaps with the gate of the driving transistor in the pixel circuit to form a storage capacitor, and other signal lines may be formed on the buffer layer 14 as needed.

[0038] refer to Figure 5 , Figure 5 A partial schematic diagram of a display panel provided in an embodiment of the present invention. The first pixel 11 further includes a first signal line 36, and the first signal line 36 is arranged in the same layer as the first top gate 26. From the perspective of the top view of the layout, the orthographic projection of the first active layer 25 on the substrate 13 and the orthographic projection of the first signal line 36 on the substrate 13 overlap in the second direction Y.

[0039] The second pixel 12 further includes a second signal line 37, and the second signal line 37 is disposed in the same layer as the second top gate 32. From the perspective of the top view of the layout, the orthographic projection of the second active layer 31 on the substrate 13 and the orthographic projection of the second signal line 37 on the substrate 13 overlap in the second direction Y. The second direction Y is parallel to the plane where the display panel 100 is located, and is perpendicular to the length extension direction of the signal line, and the signal line is the first signal line 36 or the second signal line 37.

[0040] It should be noted that in Figure 4 The first signal trace 234 and the second signal trace 234 are not illustrated.

[0041] Specifically, the applicant found that the transistors of the metal oxide active layer in the pixel circuit realized by LTPO technology are usually transistors of top-bottom dual-gate structure. In the current pixel preparation process, due to the design of the opening area A1 of the display panel, the number of pixels in the upper and lower rows in the column direction is not equal. For the uniformity of process etching, the wiring design of the metal oxide active layer around the transistors in the pixel circuits of the pixels close to the opening area A1 and the pixels far from the opening area A1 is different. The pixel circuit close to the opening area A1 is prone to failure and then the pixel is lit, resulting in bright spots, which affects the display effect of the display panel.

[0042] Based on this, in an embodiment of the present invention, by improving the wiring of the second pixel 12 close to the opening area A1, the second pixel 12 close to the opening area A1 and the first pixel 11 far from the opening area A1 have the same routing design around the metal oxide active layer of the transistor in the pixel circuit, thereby solving the problem that the second pixel circuit 12a close to the opening area A1 is prone to failure and improving the display effect of the display panel 100.

[0043] Specifically, Figure 5 As shown, the first active layer 25 of the first transistor 24 in the first pixel circuit 11a and the second active layer 31 of the second transistor 30 in the second pixel circuit 12a are both metal oxide active layers, the second pixel circuit 12a is close to the opening area A1, and the first pixel circuit 11a is far away from the opening area A1, the first pixel 11 is provided with a first signal wiring 36, and the orthographic projection of the first active layer 25 on the substrate 13 overlaps with the orthographic projection of the first signal wiring 36 on the substrate 13 in the second direction Y. Figure 5 As shown, the first active layer 25 and the first signal wiring 36 exist in opposite regions in the second direction Y (ie, the region shown in the dotted box 38 ).

[0044] The second pixel 12 is provided with a second signal wiring 37, and the orthographic projection of the second active layer 31 on the substrate 13 overlaps with the orthographic projection of the second signal wiring 37 on the substrate 13 in the second direction Y. Figure 5 As shown, the second active layer 31 and the second signal wiring 37 also have a relative area in the second direction Y (ie, the area shown in the dotted box 39 ).

[0045] It can be understood that in the embodiment of the present application, based on the relative position relationship between the first signal wiring 36 and the first active layer 25, a second signal wiring 37 is added to the second pixel 22, so that the second pixel 12 close to the opening area A1 and the first pixel 11 far away from the opening area A1 have the same wiring design around the metal oxide active layer of the transistor in the pixel circuit, thereby improving the characteristics of the second transistor 30 in the second pixel 12, solving the problem of easy failure of the second transistor 30 in the second pixel 12, improving the stability of the second pixel circuit 12a, and ultimately improving the display effect of the display panel 100.

[0046] In an optional embodiment of the present invention, Figure 1 As shown, the orthographic projection figure of the opening area A1 in the first direction X includes at least one arc segment.

[0047] Specifically, in this embodiment, Figure 1 The opening area A1 is illustrated as an ellipse. It should be noted that the shape of the opening area A1 is not limited in the embodiment of the present invention and can be determined according to actual conditions, as long as the orthographic projection of the opening area A1 in the first direction X includes at least one arc segment.

[0048] In an optional embodiment of the present invention, reference Figure 6 , Figure 6 A partial schematic diagram of another display panel provided by an embodiment of the present invention. The second signal line 37 is a signal line extending from the first signal line 36 to the second pixel 12 .

[0049] Specifically, in the embodiment of the present invention, during the process of preparing the second pixel 12, the first signal wiring 36 corresponding to the first pixel 11 is directly extended to the area where the second pixel 12 is located. At this time, the orthographic projection of the first active layer 25 on the substrate 13 overlaps with the orthographic projection of the first signal wiring 36 on the substrate 13 in the second direction Y, and the orthographic projection of the second active layer 31 on the substrate 13 overlaps with the orthographic projection of the first signal wiring 36 on the substrate 13 in the second direction Y. That is, the orthographic projection of the first active layer 25 on the substrate 13 and the orthographic projection of the second active layer 31 on the substrate 13 both overlap with the orthographic projection of the same signal wiring on the substrate 13 in the second direction Y. In the case of improving the characteristics of the second transistor 30 in the second pixel 12, it is also possible to ensure that the characteristics of the first transistor 24 and the second transistor 30 are the same, thereby ensuring that the luminous performance of the first pixel 11 and the second pixel 12 are the same, and the display effect of the display panel 100 is improved to the greatest extent.

[0050] In an optional embodiment of the present invention, reference Figure 7 , Figure 7 A schematic diagram of a signal routing line at an opening area provided by an embodiment of the present invention. The display panel 100 provided by the embodiment of the present invention further includes: a third signal routing line 40 arranged around the opening area A1.

[0051] One end of the first signal wiring 36 corresponding to each second pixel 12 and close to the third signal wiring 40 is electrically connected to the third signal wiring 40 .

[0052] Specifically, in the embodiment of the present invention, all the first signal lines 36 corresponding to the second pixels 12 arranged near the opening area A1 are electrically connected to the same third signal line 40, so as to realize the series connection of multiple first signal lines 36 in the display panel 100, reduce the influence of the impedance of the first signal line 36 itself on the transmitted signal, thereby improving the uniformity of the signal transmitted on the first signal line 36, and further improving the display effect of the display panel.

[0053] In an optional embodiment of the present invention, the first signal wirings 36 may also be connected and arranged in a grid shape on the plane where the display panel 100 is located.

[0054] Specifically, in the embodiment of the present invention, the first signal lines 36 are connected and arranged in a grid shape on the plane where the display panel 100 is located, which can play a role in sharing voltage with each other, reduce its own load, thereby improving electrical uniformity, and further improving the display effect of the display panel 100.

[0055] In an optional embodiment of the present invention, Figure 5 As shown, there is a gap between the first signal wiring 36 and the second signal wiring 37 .

[0056] Specifically, in the embodiment of the present invention, the second signal line 37 added to the second pixel 12 and the first signal line 36 corresponding to the first pixel 11 are two independent signal lines. That is to say, in the embodiment of the present application, it is not limited to extending the first signal line 36 to the area where the second pixel 12 is located. The second signal line 37 can also be independently formed in the process of preparing the second pixel 12, so that the relative position relationship between the second signal line 37 and the second active layer 31 is the same as the relative position relationship between the first signal line 36 and the first active layer 25. This also reflects that the feasibility of the technical solution of the present application is diverse.

[0057] In an optional embodiment of the present invention, when there is a gap between the first signal line 36 and the second signal line 37 and they are two independent signal lines, the signals transmitted by the first signal line 36 and the second signal line 37 may be the same or different.

[0058] Specifically, in the embodiment of the present invention, when the signals transmitted by the first signal line 36 and the second signal line 37 are the same, while improving the characteristics of the second transistor 30 in the second pixel 12, it is also possible to ensure that the characteristics of the first transistor 24 and the second transistor 30 are the same, thereby ensuring that the luminous performance of the first pixel 11 and the second pixel 12 is the same, thereby maximizing the display effect of the display panel 100.

[0059] When the signals transmitted by the first signal wire 36 and the second signal wire 37 are different, it is necessary to ensure that the voltage value represented by the signal transmitted by the first signal wire 36 is as close as possible to the voltage value represented by the signal transmitted by the second signal wire 37, so as to avoid a large difference between the characteristics of the first transistor 24 and the characteristics of the second transistor 30. In this case, the second signal wire 37 can transmit a signal different from the first signal wire 36, and based on different circuit designs, it is obvious that the second pixel 12 can realize some additional functions, thereby increasing the display diversity of the display panel 100.

[0060] In an optional embodiment of the present invention, reference Figure 8 , Figure 8 A schematic diagram of another signal routing in an opening area provided by an embodiment of the present invention. The display panel provided by the embodiment of the present invention further includes: a third signal routing 40 arranged around the opening area A1.

[0061] The second signal wiring 37 corresponding to each second pixel 12 is electrically connected to the third signal wiring 40 .

[0062] Specifically, in the embodiment of the present invention, all the second signal lines 37 corresponding to the second pixels 12 arranged near the opening area A1 are electrically connected to the same third signal line 40, so as to realize the series connection of multiple second signal lines 37 in the display panel, reduce the influence of the impedance of the second signal line 37 itself on the transmitted signal, thereby improving the uniformity of the signal transmitted on the second signal line 37, and further improving the display effect of the display panel 100.

[0063] It should be noted that Figure 7 and Figure 8 The third signal lines 40 shown are all described by taking a closed-loop signal line surrounding the opening area A1 as an example. In some optional embodiments, the third signal line 40 can also be a signal line that is not connected at the beginning and the end.

[0064] In an optional embodiment of the present invention, the first signal wirings 36 are connected and arranged in a grid shape on the plane where the display panel 100 is located; and / or the second signal wirings 37 are connected and arranged in a grid shape on the plane where the display panel 100 is located.

[0065] Specifically, in the embodiment of the present invention, the signal lines are connected and arranged in a grid shape on the plane where the display panel is located, which can play a role in sharing voltage with each other, reduce their own load, thereby improving electrical uniformity, and further improving the display effect of the display panel.

[0066] In an optional embodiment of the present invention, Figure 2 As shown, the first pixel circuit 11a further includes:

[0067] The first data writing transistor T2 has a first end for receiving a data signal Vdata, a second end for connecting to the source of the first driving transistor T1, and a control signal S1 for controlling the on and off of the first data writing transistor T2.

[0068] The first reset transistor T3 has a first terminal receiving the first reset signal Vref1A and a second terminal electrically connected to the gate of the first driving transistor T1. The control signal S2 received by the gate of the first reset transistor T3 is used to control the on and off of the first reset transistor T3.

[0069] The first anode reset transistor T4, one end of the first driving module 28 is electrically connected to the anode of the first light emitting element 11b, the first end of the first anode reset transistor T4 receives the first anode reset signal Vref1B, and the second end is electrically connected to the anode of the first light emitting element 11b. The control signal S3 received by the gate of the first anode reset transistor T4 is used to control the conduction and shutoff of the first anode reset transistor T4.

[0070] The first threshold compensation transistor T5 is used to compensate the threshold voltage of the first driving transistor T1. The control signal S4 received by the gate of the first threshold compensation transistor T5 is used to control the conduction and cut-off of the first threshold compensation transistor T5. The connection relationship between the first threshold compensation transistor T5 and other transistors is as follows: Figure 2 As shown, no further description is given here.

[0071] The first A light emitting control transistor T6 and the first B light emitting control transistor T7, one end of the first A light emitting control transistor T6 is electrically connected to the first power supply terminal PVDD, and the other end is electrically connected to the anode of the first light emitting element 11b through the first driving transistor T1 and the first B light emitting control transistor T7 in sequence, and the anode of the first light emitting element 11b is electrically connected to the second power supply terminal PVEE. The control signal EM1 received by the gate of the first A light emitting control transistor T6 and the gate of the first B light emitting control transistor T7 is used to control the conduction and disconnection of the two.

[0072] The first bias transistor T8, the first end of the first bias transistor T8 receives the first bias signal DVH1, and the second end is electrically connected to one end of the first driving module 28. The control signal S5 received by the gate of the first bias transistor T8 is used to control the conduction and cutoff of the first bias transistor T8. The first bias signal DVH1 is used to reset the state of the first driving transistor T1, which has a good improvement effect on the hysteresis performance such as short residual / first frame brightness.

[0073] like Figure 2 As shown, the first pixel circuit 11a also includes a first capacitor C11, and its specific connection relationship is as follows: Figure 2 It should be noted that the first capacitor C11 serves as a storage capacitor of the first pixel circuit 11a.

[0074] It should be noted that the operation process of the first pixel circuit 11 a requires the timing processes of various transistors to cooperate with each other to be realized, and only a brief introduction is given here.

[0075] like Figure 3 As shown, the second pixel circuit 12a also includes: a second data writing transistor M2, the first end of the second data writing transistor M2 is used to receive the data signal Vdata, the second end of the second data writing transistor M2 is connected to the source of the second driving transistor M1, and the control signal K1 received by the gate of the second data writing transistor M2 is used to control the conduction and disconnection of the second data writing transistor M2.

[0076] The second reset transistor M3 has a first terminal receiving the second reset signal Vref2A and a second terminal electrically connected to the gate of the second driving transistor M1. The control signal K2 received by the gate of the second reset transistor M3 is used to control the on and off of the second reset transistor M3.

[0077] The second anode reset transistor M4, one end of the second driving module M1 is electrically connected to the anode of the second light emitting element 12b, the first end of the second anode reset transistor M4 receives the second anode reset signal Vref2B, and the second end is electrically connected to the anode of the second light emitting element 12b. The control signal K3 received by the gate of the second anode reset transistor M4 is used to control the conduction and shutoff of the second anode reset transistor M4.

[0078] The second threshold compensation transistor M5 is used to compensate the threshold voltage of the second driving transistor M1. The control signal K4 received by the gate of the second threshold compensation transistor M5 is used to control the conduction and cut-off of the second threshold compensation transistor M5. The connection relationship between the second threshold compensation transistor M5 and other transistors is as follows: Figure 3 As shown, no further description is given here.

[0079] The second A light emitting control transistor M6 and the second B light emitting control transistor M7, one end of the second A light emitting control transistor M6 is electrically connected to the first power supply terminal PVDD, and the other end is electrically connected to the anode of the second light emitting element 12b through the second driving transistor M1 and the second B light emitting control transistor M7 in sequence, and the anode of the second light emitting element 12b is electrically connected to the second power supply terminal PVEE. The control signal EM2 received by the gate of the second A light emitting control transistor M6 and the gate of the second B light emitting control transistor M7 is used to control the conduction and disconnection of the two.

[0080] The second bias transistor M8, the first end of the second bias transistor M8 receives the second bias signal DVH2, and the second end is electrically connected to one end of the second driving module 29. The control signal K5 received by the gate of the second bias transistor M8 is used to control the conduction and cutoff of the second bias transistor M8. The second bias signal DVH2 is used to reset the state of the second driving transistor M1, which has a good improvement effect on the hysteresis performance such as short residual / first frame brightness.

[0081] like Figure 3 As shown, the second pixel circuit also includes a second capacitor C21, and its specific connection relationship is as follows: Figure 3 It should be noted that the second capacitor C21 serves as a storage capacitor of the second pixel circuit 12a.

[0082] It should be noted that the operation process of the second pixel circuit 12 a requires the timing processes of various transistors to cooperate with each other to be realized, and only a brief introduction is given here.

[0083] Figure 2 The first pixel circuit 11a and Figure 3 The second pixel circuit 12a shown is also known as an 8T1C circuit in the art, wherein the threshold compensation transistor and the reset transistor are usually transistors of a metal oxide active layer with a top-bottom double-gate structure. In the embodiment of the present invention, the first transistor 24 can be a first reset transistor T3, and the second transistor 30 can be a second reset transistor M3.

[0084] In the prior art, the first signal wiring 36 is correspondingly arranged below the metal oxide active layer of the first reset transistor T3 in the area where the first pixel 11 is located, while there is no corresponding wiring below the metal oxide active layer of the second reset transistor M3 in the area where the second pixel 12 is located. At this time, the characteristics of the second reset transistor M3, such as the threshold voltage Vth, will be affected, causing the second reset transistor M3 to fail to open at the timing when it needs to be turned off, thereby affecting the potential of the gate of the second driving transistor M1, and further affecting the display effect of the display panel.

[0085] Based on this, in the embodiment of the present invention, based on the relative position relationship between the first signal wiring 36 and the first active layer 25, by adding a second signal wiring 37 to the second pixel 22, the metal oxide active layer of the second reset transistor M3 in the area where the second pixel 22 is located also has a corresponding signal wiring below, so that the second pixel 12 close to the opening area A1 and the first pixel 11 far away from the opening area A1 have the same wiring design around the metal oxide active layer of the reset transistor in the pixel circuit, which improves the characteristics of the second reset transistor M3 in the second pixel 12, solves the problem that the second reset transistor M3 in the second pixel 12 is prone to failure, improves the stability of the second pixel circuit 12a, and ultimately improves the display effect of the display panel.

[0086] In an optional embodiment of the present invention, the first end of the first reset transistor T3 is electrically connected to the first signal wire 36, and the first reset signal Vref1A is transmitted on the first signal wire 36; the first end of the second reset transistor M3 is electrically connected to the second signal wire 37, and the second reset signal Vref2A is transmitted on the second signal wire 37. Alternatively, the first end of the first anode reset transistor T4 is electrically connected to the first signal wire 36, and the first anode reset signal Vref1B is transmitted on the first signal wire 36; the first end of the second anode reset transistor M4 is electrically connected to the second signal wire 37, and the second anode reset signal Vref2B is transmitted on the second signal wire 37. Alternatively, the first end of the first bias transistor T8 is electrically connected to the first signal wire 36, and the first bias signal DVH1 is transmitted on the first signal wire 36; the first end of the second bias transistor M8 is electrically connected to the second signal wire 37, and the second bias signal DVH2 is transmitted on the second signal wire 37.

[0087] In other words, the first signal line 36 may be a signal line for transmitting the first reset signal Vref1A, or a signal line for transmitting the first anode reset signal Vref1B, or a signal line for transmitting the first bias signal DVH1. Similarly, the second signal line 37 may be a signal line for transmitting the second reset signal Vref2A, or a signal line for transmitting the second anode reset signal Vref2B, or a signal line for transmitting the second bias signal DVH2.

[0088] It should be noted that when there is a gap between the first signal line 36 and the second signal line 37 and they are independent signal lines, the signals transmitted by the first signal line 36 and the second signal line 37 may be the same or different; for example, the first signal line 36 transmits the first reset signal Vref1A, and the second signal line 37 transmits the second reset signal Vref2A; or the first signal line 36 transmits the first bias signal DVH1, and the second signal line 37 transmits the second bias signal DVH2; or the first signal line 36 transmits the first reset signal Vref1A, and the second signal line 37 transmits the second anode reset signal Vref2B. When the second signal line 37 is a signal line extending from the first signal line 36 to the second pixel 22, the same signal is transmitted.

[0089] Further, when the second signal line 37 is a signal line extending from the first signal line 36 to the second pixel 22, one end of the first signal line 36 corresponding to each second pixel 12 close to the third signal line 40 is electrically connected to the third signal line 40, thereby realizing the connection of multiple first signal lines 36 in the display panel 100, reducing the influence of the impedance of the first signal line 36 itself on the transmitted signal, thereby improving the uniformity of the signal transmitted on the first signal line 36, and further improving the display effect of the display panel 100. Exemplarily, when a reset signal is transmitted on the first signal line 36, the uniformity of the reset signal transmitted on the first signal line 36 can be improved to ensure that the reset signal received by the pixel circuit in each pixel 10 is as consistent as possible, and finally improve the display effect of the display panel.

[0090] When there is a gap between the first signal line 36 and the second signal line 37, and they are independent signal lines, the second signal line 37 corresponding to each second pixel 12 is electrically connected to the third signal line 40, so as to realize the connection of multiple second signal lines 37 in the display panel 100, reduce the influence of the impedance of the second signal line 37 itself on the transmitted signal, and improve the uniformity of the signal transmitted on the second signal line 37, so as to further improve the display effect of the display panel. Exemplarily, when the bias signal is transmitted on the second signal line 37, the uniformity of the bias signal transmitted on the second signal line 37 can be improved to ensure that the bias signal received by the pixel circuit in each pixel 10 is as consistent as possible, and finally improve the display effect of the display panel.

[0091] Accordingly, the embodiment of the present application further provides a display device, referring to Fig. 9 , Fig. 9 A schematic diagram of the structure of a display device provided in an embodiment of the present invention. The display device 200 includes the display panel 100 described in the above embodiment of the present application, and the display device 200 includes an opening area A1, and the design of the opening area A1 is mainly for integrating and setting functional components. Exemplarily, the opening area A1 can be used to set a front camera or other functional components. The display device 200 can be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book or a TV.

[0092] The display panel and display device provided by the present invention are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

[0093] It should be noted that each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0094] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device that includes a series of elements is inherent to the elements, or also includes elements inherent to these processes, methods, articles or devices. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0095] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: The display panel comprises: a pixel, an opening area and a display area at least partially surrounding the opening area; the pixel comprises a first pixel arranged away from the opening area and a second pixel arranged close to the opening area; The first pixel includes a first pixel circuit, the first pixel circuit includes a first transistor, the first transistor includes a first active layer and a first bottom gate and a first top gate located on both sides of the first active layer in a first direction; the first direction is perpendicular to the plane where the display panel is located; The second pixel includes a second pixel circuit, the second pixel circuit includes a second transistor, the second transistor includes a second active layer and a second bottom gate and a second top gate located on both sides of the second active layer in the first direction; the first active layer and the second active layer are both metal oxide active layers; The first pixel further includes a first signal line, the first signal line is arranged in the same layer as the first top gate, and an orthographic projection of the first active layer on the substrate overlaps with an orthographic projection of the first signal line on the substrate in a second direction; The second pixel also includes a second signal line, which is arranged on the same layer as the second top gate, and the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second signal line on the substrate in the second direction; the second direction is parallel to the plane where the display panel is located and perpendicular to the length extension direction of the signal line, and the signal line is the first signal line or the second signal line.

2. The display panel according to claim 1, characterized in that: The orthographic projection figure of the opening area in the first direction includes at least one arc segment.

3. The display panel according to claim 1, characterized in that: The second signal line is a signal line extending from the first signal line to the second pixel.

4. The display panel according to claim 1, characterized in that: There is a gap between the first signal wiring and the second signal wiring.

5. The display panel according to claim 4, characterized in that: The first signal line and the second signal line transmit the same signal.

6. The display panel according to claim 3, characterized in that: The display panel further includes: a third signal wiring arranged around the opening area; One end of the first signal wire corresponding to each of the second pixels and close to the third signal wire is electrically connected to the third signal wire.

7. The display panel according to claim 4 or 5, characterized in that: The display panel further includes: a third signal wiring arranged around the opening area; The second signal wiring corresponding to each of the second pixels is electrically connected to the third signal wiring.

8. The display panel according to claim 3, characterized in that: The first signal wirings are connected and arranged in a grid shape on the plane where the display panel is located.

9. The display panel according to claim 4 or 5, characterized in that: The first signal wiring is connected and arranged in a grid shape on the plane where the display panel is located; And / or, the second signal wirings are connected and arranged in a grid pattern on the plane where the display panel is located.

10. The display panel according to claim 1, characterized in that: The first pixel circuit includes a first driving module, and the second pixel circuit includes a second driving module; The first transistor is a first reset transistor, and the second transistor is a second reset transistor; The first end of the first reset transistor receives a first reset signal, and the second end is electrically connected to the control end of the first driving module; The first end of the second reset transistor receives a second reset signal, and the second end is electrically connected to the control end of the second driving module.

11. The display panel according to claim 10, characterized in that: The first end of the first reset transistor is electrically connected to the first signal wiring, and the first reset signal is transmitted on the first signal wiring; The first end of the second reset transistor is electrically connected to the second signal wiring, and the second reset signal is transmitted on the second signal wiring.

12. The display panel according to claim 10, characterized in that: The first pixel further includes a first light emitting element, and the second pixel further includes a second light emitting element; The first pixel circuit further includes a first anode reset transistor, and the second pixel circuit further includes a second anode reset transistor; One end of the first driving module is electrically connected to the anode of the first light emitting element, and one end of the second driving module is electrically connected to the anode of the second light emitting element; The first end of the first anode reset transistor receives a first anode reset signal, and the second end is electrically connected to the anode of the first light emitting element; The first end of the second anode reset transistor receives a second anode reset signal, and the second end is electrically connected to the anode of the second light emitting element.

13. The display panel according to claim 12, characterized in that: The first end of the first anode reset transistor is electrically connected to the first signal wiring, and the first anode reset signal is transmitted on the first signal wiring; The first end of the second anode reset transistor is electrically connected to the second signal wiring, and the second anode reset signal is transmitted on the second signal wiring.

14. The display panel according to claim 10, characterized in that: The first pixel circuit further includes a first bias transistor, and the second pixel circuit further includes a second bias transistor; The first end of the first bias transistor receives a first bias signal, and the second end is electrically connected to one end of the first driving module; A first end of the second bias transistor receives a second bias signal, and a second end is electrically connected to one end of the second driving module.

15. The display panel according to claim 14, characterized in that: The first end of the first bias transistor is electrically connected to the first signal wiring, and the first bias signal is transmitted on the first signal wiring; The first end of the second bias transistor is electrically connected to the second signal trace, and the second bias signal is transmitted on the second signal trace.

16. The display panel according to claim 1, characterized in that: The metal oxide active layer is an IGZO active layer.

17. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1-16.

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