Array testing device for multiple new principle device arrays

Abstract

The invention discloses an array testing device for multiple new principle device arrays, which comprises an array testing mainboard, a semiconductor parameter analyzer and an upper computer, and is characterized in that the array testing mainboard comprises a microcontroller and a plurality of matrix switch board cards, and each matrix switch board card comprises a shift register and a relay group array; wherein the common end of the relay group is connected with an array to be tested, and the contact end is an SMU end connected with a semiconductor parameter analyzer, a Float end without electrical connection, and a Vref end and a GND end connected with an external source meter; the microcontroller receives a communication instruction of an upper computer and sends control signals to the shift registers on the matrix switch board cards in series, and the shift registers output control signals to the control ports of the relay sets on the matrix switch board cards in parallel. And the semiconductor parameter analyzer can test devices on the array to be tested through switching of the relay group. The device provided by the invention has expandability, can efficiently measure various types of new principle device arrays, reduces the influence of various types of noise on to-be-measured signals and the influence of crosstalk, and improves the test precision.

Description

Technical Field

[0001] The invention relates to a new principle device array testing technology, in particular to an array testing device for multiple new principle device arrays. Background Art

[0002] New principle devices refer to electronic devices that achieve higher performance, lower power consumption, and smaller size by introducing new materials, new structures, and new working principles on the basis of traditional semiconductor devices. With the advent of the post-Moore era, the traditional method of improving performance by reducing size has gradually approached the physical limit. Therefore, new principle devices have become an important direction to promote the advancement of microelectronics technology, and people's demand for new principle devices has grown rapidly. In this regard, researchers have developed a variety of new principle devices based on the unique physical and chemical properties of new materials, and have continuously achieved new results in the fields of electronics, optoelectronics, and sensing. Although researchers have made great progress in the research of single devices, the array application of devices has always been the goal pursued by everyone. Therefore, the demand for array test devices for new principle devices is becoming more and more urgent.

[0003] The existing testing device mainly uses a semiconductor parameter analyzer in conjunction with a probe station to manually test a single device. The testing process includes the following steps:

[0004] Place the sample: First, place the prepared array sample to be tested on the horizontal translation stage of the probe station, turn on the microscope illumination source, and turn the knob of the horizontal translation stage to make the array sample appear in the field of view. At this time, the virtual shadows of the array sample and the four probes should appear in the field of view. Adjust the vertical distance between the microscope and the sample so that the sample is at the focal plane of the microscope.

[0005] Probe placement: After being able to see the virtual shadows of the array sample to be tested and the four probes in the field of view, determine the metal PAD (pin pad) where the probes need to be placed according to the test requirements. Manually rotate the two knobs of the probe holder corresponding to the four probes, and the knobs control the movement of the probes in the horizontal plane and vertical direction respectively. Continuously fine-tune the horizontal and vertical positions of the probes until the probes are in good contact with the target metal PAD.

[0006] Device testing: For the SMU (source measurement unit) channels corresponding to different metal PADs, the B1500A semiconductor parameter analyzer is used to apply voltage and current signals to a single device or different PADs of a row and column of the array sample to be tested. Alternatively, a certain intensity of light is applied at the same time as required by the test plan. The SMU collects the current and voltage of its response to complete the measurement of some samples of the array sample to be tested.

[0007] Repeat the probe placement test: lift the placed probe, turn the knob of the horizontal translation stage and the two knobs of the four probes, adjust the relative position of the sample and the probe, make the probe be located above the corresponding PAD of the next single device or a row and column of devices to be tested, repeat the probe placement and device test, and thus complete the test of the entire array sample to be tested.

[0008] In the test scheme based on the above test device, the probe station is generally equipped with four probes, with a small number of channels, and the probes need to be repeatedly lifted and lowered and manually adjusted. The degree of automation is extremely low, and it is very time-consuming when used for array testing tasks, and cannot meet the testing requirements for new principle device arrays.

[0009] In response to this problem, previous related work has expanded the array test function of semiconductor parameter analyzers. For example, the invention patent applied for by Shandong University, "A non-volatile memory device and storage array test circuit and test method", expanded the testing of non-volatile memory devices and storage arrays; the invention patent applied for by Huazhong University of Science and Technology, "A storage array selection test system", expanded the selection of storage arrays; but the above invention patents are mostly for the expansion of specific device arrays, and are not extensible to other types of new principle devices.

[0010] In addition, the invention patents "Array Device Test Device and Test Method" and "A Test Circuit and Device for Array Devices" applied by the Institute of Microelectronics of the Chinese Academy of Sciences have respectively expanded the problem that the number of channels of semiconductor parameter analyzers is small and the switching problem of DC signals and pulse signals is inconsistent with the small bandwidth and output resistance in the test circuit, but neither of them takes into account the noise problem existing in the line. The measurement and application of signals for the device array are not protected in the extended circuit board, and there may be problems of signal distortion caused by noise. At the same time, there is no effective solution to the crosstalk problem that may exist in the array, that is, when electrical operations are performed on some devices in the array, the electrical operation may affect the status of other devices through the parasitic effects of the circuit and potential pathways, and even affect the current test. Summary of the invention

[0011] Purpose of the invention: The purpose of the present invention is to provide an array testing device for arrays of various new principle devices, so as to achieve efficient measurement of arrays of various types of new principle devices.

[0012] Technical solution: To achieve the above-mentioned purpose, the array test device for multiple new principle device arrays described in the present invention includes an array test mainboard and a semiconductor parameter analyzer. The array test mainboard includes a microcontroller and multiple matrix switch boards. The matrix switch board includes a shift register and a relay array containing multiple relay groups, wherein the common end of the relay group is connected to the array to be tested, and the contact ends of the relay group are respectively a measurement state SMU end connected to the semiconductor parameter analyzer, a floating state Float end without electrical connection, and a given reference voltage V connected to an external source meter. ref end and the grounding state GND end; the microcontroller sends a control signal serially to the shift register on each matrix switch board, and the shift register outputs the control signal in parallel to the control port of the relay group on the matrix switch board based on the received control signal, and the semiconductor parameter analyzer is used to test the devices on the array to be tested through the switch switching of the relay group.

[0013] The relay group includes two independent relays. The common ports of the two relays are connected in parallel as the Array terminal of a device in the array to be tested. The two contact terminals of one relay are connected to the measurement state SMU and floating state Float terminals of the semiconductor parameter analyzer, and the two contact terminals of the other relay are connected to the given reference voltage V of the external source meter. ref terminal, grounding state GND terminal.

[0014] It also includes a host computer, and the microcontroller sends control signals in series to the shift registers on each matrix switch board by receiving communication instructions from the host computer.

[0015] The common terminals of all relay groups on a single matrix switch board are connected one by one to the electrodes of the same type of all devices on the array to be tested.

[0016] Among them, the shift registers of each matrix switch board are connected to the corresponding clock lines, signal lines and chip selection lines of the microcontroller.

[0017] Wherein, the shift registers on all the matrix switch boards share the clock line and the signal line of the microcontroller, and the shift registers on all the matrix switch boards are connected to different chip select lines of the microcontroller.

[0018] Wherein, an isolation chip for isolating relay interference is provided between the control signal output end of the shift register and the control port of each relay group.

[0019] Among them, the wiring on the array test mainboard and the matrix switch board is shielded, specifically: the array test mainboard and the matrix switch board include a signal transmission layer, and a GND shielding layer and a signal equipotential layer are provided on both sides of the signal transmission layer, wherein the GND shielding layer and the signal equipotential layer are alternately and symmetrically arranged on both sides of the signal transmission layer.

[0020] The GND shielding layer includes a GND routing network and a signal equipotential layer routing network, wherein the signal equipotential layer routing network forms a shielding layer with the same potential as the signal to reduce signal leakage;

[0021] The signal equipotential layer includes a GND routing network and a signal equipotential layer routing network, wherein the GND routing network is a continuation of the GND routing network in the GND shielding layer, and the signal equipotential layer routing network is a continuation of the routing networks of other signal equipotential layers;

[0022] The signal transmission layer includes a GND routing network, a signal equipotential layer routing network, and a signal transmission line. The GND routing network is a continuation of the GND routing network in the GND shielding layer and the signal equipotential layer; the signal equipotential layer routing network is a continuation of the signal equipotential layer routing network in the GND shielding layer and the signal equipotential layer; the signal transmission line is surrounded by the GND shielding layer and the signal equipotential layer;

[0023] The GND shielding layer is used to shield electromagnetic interference.

[0024] Among them, the GND routing network uses but is not limited to copper plating, through holes or blind buried holes for grounding; the signal equipotential layer routing network uses but is not limited to copper plating, through holes or blind buried holes to be equipotential with the signal.

[0025] Beneficial effects: The present invention has the following advantages: 1. The device described in the present invention utilizes an expandable array test mainboard and a matrix switch board to realize efficient measurement of arrays of various new principle devices; 2. Shielding treatment is adopted for the routing on the array test mainboard and the matrix switch board, and the wrapping of the signal transmission line is increased, which greatly reduces the influence of various types of noise on the measured signal and avoids the problem of signal distortion; 3. The switching state of each relay in the relay array is controlled by a shift register, which reduces the crosstalk effect of the measured array during the test and further improves the test accuracy; 4. Electrical isolation is achieved by setting an isolation chip for isolating relay interference between the control signal output end of the shift register and the control port of the relay. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the array test device framework;

[0027] Figure 2It is a schematic diagram of the connection relationship between the microcontroller and the matrix switch board;

[0028] Figure 3 It is a schematic diagram of the relay group port structure;

[0029] Figure 4 It is a schematic diagram of the principle of the V / 2 voltage bias method or the V / 3 voltage bias method;

[0030] Figure 5 This is a schematic diagram of shielding processing for signal transmission lines;

[0031] Figure 6 A schematic diagram for testing a floating gate device array;

[0032] Figure 7 Test flow chart for array testing. DETAILED DESCRIPTION

[0033] The technical solution of the present invention is described in detail below in conjunction with the embodiments and drawings.

[0034] like Figure 1 , 2 As shown, the array test device of the present invention comprises an array test mainboard, a semiconductor parameter analyzer, a host computer and an array to be tested. The array test mainboard comprises a microcontroller (MCU), a plurality of matrix switch boards (matrix switch boards 1-N), an array interface to be tested and a matrix switch board interface. Each matrix switch board is completely consistent, including a shift register and a precision relay array. And according to the size of the array to be tested, different numbers of matrix switch boards can be added to the array test mainboard.

[0035] The microcontroller is connected to the host computer through a USB interface, and the communication instructions of the host computer are transmitted to the microcontroller through a USB to TTL module. The shift registers of each matrix switch board are connected to the corresponding clock line, signal line and chip select line of the microcontroller through the corresponding matrix switch board interface on the array test motherboard. The shift registers on all matrix switch boards (1-N) share the clock line and signal line given by the microcontroller, but are connected to different chip select lines (1-N). Different chip select lines can be added to the microcontroller by adding a decoder to increase chip selection efficiency and reduce hardware overhead.

[0036] The precision relay array is connected to each device of the array under test through the array interface under test. The precision relay array on each matrix switch board is divided into multiple precision relay groups. One precision relay group contains two independent precision relays. A single precision relay includes a control port, a common port, and two contacts. Figure 3As shown in the figure, in a single precision relay group, the common ports of two independent precision relays are connected in parallel as the Array terminal of a device in the array to be measured. The two contacts of one precision relay (precision relay 1) are connected to the SMU (measurement state) terminal of the semiconductor parameter analyzer and the Float (floating state) terminal without electrical connection. The two contacts of the other precision relay (precision relay 2) are connected to the V ref (given reference voltage) terminal, GND (ground state) terminal.

[0037] After the shift registers on each matrix switch board are connected to the microcontroller through the above connection relationship, the control signals output by the microcontroller are serially received, and the control signals output in parallel to the control ports of all precision relays on the same matrix switch board are controlled to control the closing relationship between the common port of each precision relay and the two contacts. An isolation chip is also provided between the control signal output end of the shift register and the control port of each precision relay to isolate the interference of the relay, and the control signal output end of the shift register is electrically isolated from the control port of the precision relay to achieve electrical isolation, while independently controlling the electrical state of each precision relay in the precision relay array, effectively avoiding the influence of the digital signal on the analog signal of the array to be measured.

[0038] Based on the above connection relationship, during the test, if one end of a device in the device array (Array) needs to be connected to the SMU of the semiconductor parameter analyzer, the shift register on the same matrix switch board connected to the device will output a control signal in parallel to the corresponding precision relay group, so that the common port of precision relay 1 is connected to the SMU end, and the common port of precision relay 2 is connected to V ref end, at this time V ref No voltage is applied to the terminal, which is in Float state, thus completing the connection between the Array and the SMU terminal;

[0039] If one end of a device in the array to be tested (Array) needs to be connected to Float, the specific operating state of the precision relay group including precision relay 1 and precision relay 2 is: precision relay 1 is connected to the Float terminal to connect Array to the Float terminal, and precision relay 2 is connected to V ref (given reference voltage) terminal, at this time V ref (given reference voltage) No voltage is applied, it is Float (floating state), thus completing the connection between Array and Float (floating state) terminals;

[0040] If you need to connect one end of a device in the device array (Array) to V refWhen a reference voltage is applied to the (given reference voltage) terminal, the specific operating state of the group of precision relays including precision relay 1 and precision relay 2 is: precision relay 1 is connected to the Float (floating state) terminal, so that Array is connected to the Float (floating state) terminal, and precision relay 2 is connected to V ref (given reference voltage) terminal, at this time V ref (given reference voltage) applies a certain reference voltage to complete the Array and V ref (given reference voltage) terminal is connected;

[0041] If one end of a device in the device array (Array) needs to be connected to GND (ground state), the specific operating state of the group of precision relays including precision relay 1 and precision relay 2 is: precision relay 1 is connected to the Float (floating state) end to connect the Array to the Float (floating state) end, and precision relay 2 is connected to the GND (ground state) end to complete the connection between the Array and the GND (ground state) end.

[0042] The Float terminals of each precision relay group are all floating; the GND terminals are all connected to the analog ground of the array test mainboard; V ref The terminal can be optionally connected to an external source meter.

[0043] Where V ref The terminal can apply a certain reference voltage to other array interfaces that are not tested according to the test requirements of different arrays to be tested. For example, when testing a memristor array, in order to reduce the impact of crosstalk, the V / 2 voltage bias method or the V / 3 voltage bias method can be used to program and read the resistance of the memristor, such as Figure 4 shown.

[0044] The SMU ends of the precision relay groups on each matrix switch board in the array test device described in the present invention can be connected to the same channel of the semiconductor parameter analyzer, and the combination of the control port connection states of the precision relay groups is controlled in parallel by a shift register to improve the test efficiency of a single channel of the semiconductor parameter analyzer.

[0045] When the SMU end of the precision relay group on each matrix switch board is connected to the channel of the semiconductor parameter analyzer, in order to effectively shield various possible external noises, the array test mainboard and the wiring on each matrix switch board need to be shielded. The number of layers in the layout is M, M = 1 + 4 * L (L ≥ 1). Among them, 1 is the signal transmission layer wrapped in the middle, 4 * L is the shielding layer periodically distributed with the middle signal transmission layer as the symmetry axis, and the 2 * L layer above the signal transmission layer is the GND shielding layer-signal equipotential layer-GND shielding layer... arranged alternately and periodically, and the signal equipotential layer is arranged close to the signal transmission layer.

[0046] By symmetrically adding signal equipotential layers and GND layers to the upper and lower layers of the signal transmission line located on the signal transmission layer, and connecting the upper and lower layers again through through holes, the wrapping of the signal transmission line is further increased, which greatly reduces the influence of various types of noise on the signal to be measured, avoids signal distortion problems, and improves signal accuracy.

[0047] like Figure 5 As shown in the figure, taking the layout of each level of shielding processing when the lowest number of layers M is 5 as an example, the three layers involved in the shielding processing are as follows:

[0048] 1. GND shielding layer: This layer is arranged in two parts: the GND routing network, which can be directly grounded using copper plating, through holes or blind buried holes, forming a metal shell similar to a Faraday cage, in order to prevent external electromagnetic interference and play the role of electrostatic shielding; the other part is the signal equipotential layer routing network, forming a shielding layer with the same potential as the signal, further protecting the signal transmission line;

[0049] 2. Signal equipotential layer: This layer is arranged in two parts: the GND routing network, which is the continuation of the GND routing network in the GND shielding layer, and its purpose and function are the same as those in the GND shielding layer; the other part is the signal equipotential layer routing network, which can be but not limited to using copper plating, through holes or blind buried holes with the signal equipotential, which is the continuation of the routing network of the signal equipotential layer in other shielding layers, and its purpose and function are the same as those at the first point. This routing network surrounds the signal transmission line in several layers in the vertical direction, forming a shielding layer with the same potential as the signal, further protecting the signal transmission line;

[0050] 3. Signal transmission layer: The signal transmission layer is sandwiched in the middle, and this layer consists of three parts: the first part is the GND routing network, which is a continuation of the GND routing network in the above two shielding layers, and its purpose and function are the same as the previous one; the second part is the routing network to the signal equipotential layer, which is a continuation of the signal equipotential layer routing network of the above two shielding layers, and its purpose and function are the same as the previous one. This routing network further surrounds the signal transmission line in the horizontal direction to form a shielding layer with the same potential as the signal; the last part is the signal transmission line, which is tightly surrounded by the above two shielding layers on all sides, thereby greatly reducing the influence of various types of noise on the signal to be measured.

[0051] A three-terminal floating gate device array is used as the array to be tested, and the array test device of the present invention is used to test it. The floating gate device array has a size of N×N, that is, it includes N 2Devices are provided, each device includes a gate G, a drain D, and a source S. The electrodes of the floating gate device array are numbered as gates (G1-GN), sources (S1-SN), and drains (D1-DN).

[0052] First, the array test device is connected to the power supply to complete power-on and initialization. The precision relay groups on each matrix switch board are set to GND state. The host computer is connected to the array test mainboard via the USB interface, and the semiconductor parameter analyzer is connected to the array test mainboard via a BNC coaxial cable.

[0053] The floating gate device array is Figure 6 As shown, it is connected to the array test device. As a three-terminal device, its gate (G1-GN), source (S1-SN) and drain (D1-DN) are respectively connected to the precision relay arrays in the three matrix switch boards, and are all connected to the Array end of the precision relay group in the corresponding matrix switch board.

[0054] When the array test device is used to operate the floating gate device array, the operation process is as follows: Figure 7 shown.

[0055] 1. Parameter setting: When programming the floating gate device array, set the pulse width, amplitude number and other parameters of the programming pulse on the host computer;

[0056] 2. Array status setting: Complete the setting of the array port status on the host computer. After the setting is completed, the host computer sends instructions to the microcontroller to set the electrical status of each of the three types of ports of the array independently: connect all the sources of the array to GND; connect the gates of the selected devices in the array to the SMU terminal, and connect the gates of the remaining unselected devices to GND; connect the drains of the selected devices in the array to the SMU terminal, and connect the drains of the remaining unselected devices to GND;

[0057] 3. Device programming: After completing the independent settings of each port of the array, the host computer sends instructions to the semiconductor parameter analyzer B1500A to issue the set programming pulses to the gate and drain of the array to complete the programming of a selected floating gate device in the floating gate device array;

[0058] 4. Repeat gating and programming: After setting the parameters on the host computer, the host computer's automatic programming program automatically repeats the above operations to complete the independent programming of each floating gate device in the entire floating gate device array.

[0059] Through the above operations, independent programming of each floating gate device in the entire floating gate device array can be completed, and through independent setting of the array state and shielding of the circuits, the influence of electrical operations during the programming process on the states of other programmed or unprogrammed devices can be greatly reduced.

[0060] When reading a floating gate device array:

[0061] 1. Parameter setting: Set the amplitude and time of the read voltage on the host computer;

[0062] 2. Array status setting: Complete the setting of the array port status on the host computer. After the setting is completed, the host computer sends instructions to the microcontroller to set the electrical status of each of the three types of ports of the array independently. When reading and measuring a single floating gate device: connect the source and gate of the array to GND; connect the drain of the selected device in the array to the SMU terminal, and connect the drain of the remaining unselected devices to GND;

[0063] 3. Device test: After completing the independent settings of each port of the array, the host computer sends a command to the semiconductor parameter analyzer B1500A to apply the set read voltage to the drain of the array to complete the current reading of a selected floating gate device in the floating gate device array.

[0064] 4. Repeated selection and reading: After setting the parameters on the host computer, the host computer automated test program automatically repeats the above operations to complete the independent measurement of each floating gate device in the entire floating gate device array.

[0065] Through the above operations, independent measurement of each floating gate device in the entire floating gate device array can be completed, and through independent setting of the array state and shielding of the circuit, the influence of noise introduced by potential electrical paths on the measurement during the measurement process can be greatly reduced.

[0066] When using the V / 2 bias method to read a device in a floating gate device array, it is necessary to set the electrical state of each port of the array source, drain, and gate independently: connect the source of the selected device in the array to GND, and connect the source of the remaining unselected devices to V ref ; Connect all gates of the array to GND; Connect the drain of the selected device in the array to the SMU terminal, and the drain of the remaining unselected devices to V ref During the read operation, the source V ref The source meter applies half the voltage to the drain. ref The source meter applies a voltage half the read voltage to the end. Complete the independent setting of each port of the array and set V ref After applying a suitable voltage to the end, the host computer sends a command to the semiconductor parameter analyzer to apply a set read voltage to the drain of the array to complete the current reading of a selected floating gate device in the floating gate device array.

[0067] When using the V / 3 bias method to read a device in a floating gate device array, it is necessary to set the electrical state of each port of the array source, drain, and gate independently: connect the source of the selected device in the array to GND, and connect the source of the remaining unselected devices to V ref ; Connect all gates of the array to GND; Connect the drain of the selected device in the array to the SMU terminal, and the drain of the remaining unselected devices to V ref During the read operation, the source V ref The source meter applies a voltage of two-thirds of the reading voltage to the drain. ref The source meter applies a voltage that is one-third of the read voltage to the end. Complete the independent settings of each port of the array and set the V ref After applying a suitable voltage to the end, the host computer sends a command to the semiconductor parameter analyzer to apply a set read voltage to the drain of the array to complete the current reading of a selected floating gate device in the floating gate device array.

Claims

1. An array test device for multiple new principle device arrays, comprising an array test mainboard and a semiconductor parameter analyzer, characterized in that: The array test mainboard includes a microcontroller and multiple matrix switch boards. The matrix switch board includes a shift register and a relay array containing multiple relay groups, wherein the common end of the relay group is connected to the array to be tested, and the contact ends of the relay group are respectively a measurement state SMU end connected to a semiconductor parameter analyzer, a floating state Float end without electrical connection, and a given reference voltage V connected to an external source meter. ref End and ground state GND end; The microcontroller sends control signals serially to the shift registers on each matrix switch board. Based on the received control signals, the shift registers output control signals in parallel to the control ports of the relay groups on the matrix switch boards. The semiconductor parameter analyzer tests the devices on the array to be tested through the switching of the relay groups.

2. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The relay group includes two independent relays. The common ports of the two relays are connected in parallel as the Array terminal of a device in the array to be tested. The two contact terminals of one relay are connected to the measurement state SMU and the floating state Float terminal of the semiconductor parameter analyzer, and the two contact terminals of the other relay are connected to the given reference voltage V of the external source meter. ref terminal, grounding state GND terminal.

3. The array test device for multiple new principle device arrays according to claim 1, characterized in that: It also includes a host computer, and the microcontroller sends control signals in series to the shift registers on each matrix switch board by receiving communication instructions from the host computer.

4. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The common terminals of all relay groups on a single matrix switch card are connected one by one to the same type of electrodes of all devices on the array to be tested.

5. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The shift registers of each matrix switch board are connected to the corresponding clock lines, signal lines and chip select lines of the microcontroller.

6. The array test device for multiple new principle device arrays according to claim 5, characterized in that: The shift registers on all the matrix switch boards share the clock line and the signal line of the microcontroller, and the shift registers on all the matrix switch boards are connected to different chip select lines of the microcontroller.

7. The array test device for multiple new principle device arrays according to claim 1, characterized in that: An isolation chip for isolating relay interference is provided between the shift register control signal output end and the control port of each relay group.

8. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The wiring on the array test mainboard and the matrix switch board is shielded, specifically: the array test mainboard and the matrix switch board include a signal transmission layer, and a GND shielding layer and a signal equipotential layer are provided on both sides of the signal transmission layer, wherein the GND shielding layer and the signal equipotential layer are alternately and symmetrically arranged on both sides of the signal transmission layer.

9. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The GND shielding layer includes a GND routing network and a signal equipotential layer routing network, wherein the signal equipotential layer routing network forms a shielding layer with the same potential as the signal to reduce signal leakage; The signal equipotential layer includes a GND routing network and a signal equipotential layer routing network, wherein the GND routing network is a continuation of the GND routing network in the GND shielding layer, and the signal equipotential layer routing network is a continuation of the routing networks of other signal equipotential layers; The signal transmission layer includes a GND routing network, a signal equipotential layer routing network, and a signal transmission line. The GND routing network is a continuation of the GND routing network in the GND shielding layer and the signal equipotential layer; the signal equipotential layer routing network is a continuation of the signal equipotential layer routing network in the GND shielding layer and the signal equipotential layer; the signal transmission line is surrounded by the GND shielding layer and the signal equipotential layer; The GND shielding layer is used to shield electromagnetic interference.

10. The array test device for multiple new principle device arrays according to claim 1, characterized in that: The GND routing network is grounded using, but not limited to, copper plating, through holes or blind buried vias; the signal equipotential layer routing network is equipotential with the signal using, but not limited to, copper plating, through holes or blind buried vias.

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