Pattern generation and operation method for realizing free logic

Abstract

The invention provides a pattern generation and operation method for realizing free logic, which comprises the following steps: acquiring test information of a tested chip, and editing a program text based on a program language to generate a first pattern file; and the upper computer converts the first pattern file in the text format into a second pattern file in a machine language form based on the conversion table, and the second pattern file is issued to the test machine. According to the method and the device, the first pattern file can be freely edited based on the program language and is converted into the second pattern file occupying smaller memory, so that the issuing efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a pattern generation and operation method for realizing free logic. Background Art

[0002] Pattern files are input files for IC automatic testers in the semiconductor industry to define clock, digital input, and digital output information. The clock is used to synchronize digital input and digital output; digital input is the stimulus sent to the chip under test; digital output is the response sent by the chip under test. By comparing the clock and chip response defined in the Pattern file, it is determined whether the function of the chip under test meets the test expectations.

[0003] With the continuous development and expansion of integrated circuit technology, chip verification and testing have become increasingly important. In particular, during the chip development process, it is necessary to frequently modify the test parameters recorded in the pattern file to test chip performance.

[0004] The host computer modifies the parameters in the pattern file, and the host computer sends the modified pattern file to the automatic tester to test the chip. Pattern files usually occupy a large amount of memory, which makes the pattern file sending time longer. When the staff does not understand the pattern file format well, it takes a lot of time to find the test parameters that need to be modified, which affects the chip R&D efficiency. Summary of the invention

[0005] In view of this, the problem to be solved by the present invention is to provide a pattern generation and operation method that realizes free logic, which can freely edit the first pattern file based on the programming language and convert it into a second pattern file that occupies less memory, thereby improving the distribution efficiency.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A pattern generation method for implementing free logic includes acquiring test information of a chip under test, editing a program text based on a program language to generate a first pattern file; The host computer converts the first pattern file in text format into a second pattern file in machine language based on the conversion table, and the second pattern file is sent to the test machine.

[0007] Furthermore, the program file is composed of several program languages ​​arranged in sequence.

[0008] Furthermore, the program language is set manually.

[0009] Furthermore, the test machine includes a main control unit, which communicates with a number of functional registers for storing input data, output data, comparison data, and timing data, and controls the coordinated operation of the several functional registers to test the performance of the chip under test.

[0010] Furthermore, the conversion table includes command information, value information and programming language, the command information includes command codes corresponding one-to-one to several function registers, the value information corresponds to the command code and is used to control the action of the test component, and the programming language corresponds to several command codes arranged in a fixed format.

[0011] Furthermore, the host computer and the test machine communicate via TCP protocol.

[0012] A pattern operation method for realizing free logic includes a test machine receiving a second pattern file, a main control unit sequentially reading the second pattern file, calling corresponding function registers according to a number of command codes arranged in a fixed format and controlling the register action to test chip performance.

[0013] The advantages and positive effects of the present invention are: By setting the program language and the corresponding conversion table, the conversion relationship between the machine language and the program language is constructed, and the user can freely write the first pattern file using the program language. Since the first pattern file is a simple and easy-to-understand program text, it is convenient for the user to load, display and freely adjust the content of the first pattern file, thereby improving the flexibility of chip testing.

[0014] The host computer converts the first pattern file into the second pattern file according to the conversion table. Since the second pattern file uses machine language, it occupies less memory, so the sending speed of the second pattern file is much higher than the sending speed of the conventional pattern file, which can improve the sending efficiency of the test information.

[0015] The tester is composed of a main control unit and several functional registers. The main control unit receives the second pattern file, and calls and runs several corresponding functional registers according to the command code and corresponding value information in the file to complete the performance test of the chip. Since the functions of the chip test are all completed by registers, the comprehensiveness of the test function of the tester is improved, and it can test chips with any functions on the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1It is a flow chart of a pattern generation method for realizing free logic of the present invention. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0019] The present invention provides a pattern generation method for realizing free logic, such as Figure 1 As shown, it includes acquiring test information of the chip under test and editing the program text based on the program language to generate a first pattern file.

[0020] The program language is set manually, and the program file is composed of several program languages ​​arranged in sequence. An embodiment of the present application is: the program language for loop detection is: loopJudge(iRegType,iTimeout,iInterval,iRegRead,iRegCompData,resultAddr) indicates loop comparison of the output of the chip under test. Among them: iRegType indicates the register type, 0=FPGA register, 1=data cache register; iTimeout indicates the timeout judgment time; iInterval indicates the register query interval time; iRegRead indicates the (FPGA / cache) register address to be read; iRegCompData: indicates the register data to be compared; resultAddr: indicates the cache register address of the compared execution result.

[0021] The programming language for data input is: writeReg(iType,iDataType,addr,data), which means writing data to the register address addr so that data can be input to the chip under test. Among them: iType represents FPGA or cache, 0=FPGA; 1=cache; iDataType represents data type; addr represents register address; data represents register data.

[0022] The test information of the chip under test includes instructions such as delay control, condition judgment, loop, register reading and writing, relay switch switching, voltage and current output and measurement, etc. The user writes according to the set program language to generate a first pattern file for testing chip performance, which can save the memory of the first pattern file and facilitate quick viewing and user modification. An embodiment of the present application is that the first pattern file can be written using an editor.

[0023] The host computer converts the first pattern file in text format into the second pattern file in machine language based on the conversion table, and the second pattern file is sent to the test machine. The test machine includes a main control unit, which communicates with several functional registers for storing input data, output data, comparison data, timing data, etc., controls the coordinated operation of different functional registers, and completes instructions such as delay control, condition judgment, loop, register reading and writing, relay switch switching, voltage and current output and measurement during chip testing.

[0024] The conversion table includes command information, value information and program language. The command information includes several command codes. The command codes correspond to function registers one by one. The corresponding function registers are called through the command codes. The value information corresponds to the command code and is used to control the action of the corresponding function register. The program language corresponds to several command codes arranged in a fixed format. According to the conversion relationship between the program language and the command code, the language conversion is realized. According to the corresponding relationship between the command code and the value information, the data information in the program language is converted.

[0025] Compared with the traditional pattern file, the second pattern file in machine language format occupies less memory and can improve the efficiency of issuing the second pattern file.

[0026] The host computer and the test machine communicate through the TCP protocol (Transmission Control Protocol). TCP is a connection-oriented, reliable, byte-stream-based transport layer communication protocol.

[0027] An embodiment of the present application is: the delay instruction of the first pattern file is: delayus(10) / / Wait for 10us.

[0028] The conversion table is:

[0029] The second pattern file in machine language format is: 0x10,0x00 / / us delay 0x11,10 / / Delay 10us.

[0030] An embodiment of the present application is: the loop detection instruction of the first pattern file is: loopJudge(0x00,20, 2, 0x505, 0x7f, 100).

[0031] The conversion table is:

[0032] The second pattern file in machine language format is: / / Loop FPGA register value changes 0x20,0x00 / / points to FPGA register 0x21,20 / / Timeout 20ms 0x22,1 / / Read data once every 1ms 0x23,0x505 / / Read FPGA address 0x505 0x24,0x7f / / The data read from FPGA address 0x505 is compared with this data value 0x7f 0x25,0 / / Store the comparison result in cache address 0. The value in the cache address is 1->comparison success, 0->comparison failure.

[0033] An embodiment of the present application is: the data input instruction of the first pattern file is: writeReg (0,0,0x505, 0x71).

[0034] The conversion is expressed as:

[0035] The second pattern file in machine language format is: / / Read the value 0x12 of FPGA register address 0x505 and save it to cache address 100 0x60,0x00 / / Read FPGA data to cache 0x61,0x00 / / Data type: 0-integer 0x62,0x505 / / Read register address 0x63,100 / / Save the cache address.

[0036] A method for running a pattern file includes a test machine receiving a second pattern file, a main control unit sequentially reading the second pattern file, calling corresponding function registers according to a number of command codes arranged in a fixed format and controlling the register action to test chip performance.

[0037] The second pattern file is a machine language. The second pattern file is read sequentially, and the corresponding devices are called in sequence according to the command codes in the second pattern file. The device operation is controlled according to the value information after the command code to complete the chip test.

[0038] The embodiments of the present invention are described in detail above, but the contents described are only preferred embodiments of the present invention and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of this patent.

Claims

1. A pattern generation method for realizing free logic, characterized in that: include, Acquire test information of the chip under test, and edit the program text based on the program language to generate a first pattern file; The host computer converts the first pattern file in text format into a second pattern file in machine language based on the conversion table, and the second pattern file is sent to the test machine.

2. A pattern generation method for implementing free logic according to claim 1, characterized in that: The program file is composed of several program languages ​​arranged in sequence.

3. A pattern generation method for implementing free logic according to claim 1, characterized in that: The program language is set manually.

4. A pattern generation method for implementing free logic according to claim 1, characterized in that: The test machine includes a main control unit, which communicates with a number of function registers for storing input data, output data, comparison data, and timing data, and controls the coordinated operation of the function registers to test the performance of the chip under test.

5. A pattern generation method for implementing free logic according to claim 1, characterized in that: The conversion table includes command information, value information and program language. The command information includes command codes corresponding to several function registers one by one. The value information corresponds to the command code and is used to control the action of the test component. The program language corresponds to several command codes arranged in a fixed format.

6. A pattern generation method for implementing free logic according to claim 1, characterized in that: The host computer and the test machine communicate via TCP protocol.

7. A method for running a pattren file, according to a method for generating a pattern for implementing free logic according to any one of claims 1 to 6, characterized in that: The test machine receives the second pattern file, the main control unit sequentially reads the second pattern file, calls corresponding function registers according to a number of command codes arranged in a fixed format and controls the register action to test the chip performance.

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