Data synchronization method, chip and sound-following vibration system

Abstract

The invention provides a data synchronization method, a chip and a sound-following vibration system. The data synchronization method comprises the following steps: receiving a node input signal based on a first clock signal; outputting a node output signal based on the second clock signal; in the output process of the node output signal, judging whether the synchronization signal is valid or not; when the synchronization signal is valid, preparing to output a next node output signal; when the synchronization signal is invalid, if the node output signal is not output completely, continuing to output the node output signal until the node output signal is output completely or the synchronization signal is valid; and if the node output signal is output, continuously outputting the compensation signal until the synchronization signal is effective. The synchronism of the node output signal and the node input signal is realized without setting a phase-locked loop circuit, and the circuit area and the manufacturing cost of a driving chip are reduced.

Description

Technical Field

[0001] The present application relates to the technical field of data conversion, and in particular to a data synchronization method, a chip, and a sound-vibrating system. Background Art

[0002] For the application circuits of devices such as motors or speakers, digital signals need to be converted into analog signals to drive the load. Therefore, the synchronization of digital signals and analog signals must be ensured to avoid data loss.

[0003] In some implementation scenarios, a phase-locked loop (PLL) circuit may be used to make the update clocks of the digital signal and the analog signal the same clock source, thereby ensuring the synchronization of the digital signal and the analog signal.

[0004] However, in order to achieve synchronization between digital signals and analog signals based on this technical approach, a phase-locked loop circuit needs to be set up in the corresponding driver chip (such as a motor driver chip or an audio driver chip), which leads to an increase in the driver chip area and an increase in the cost of a single chip. Summary of the invention

[0005] The present application provides a data synchronization method, a chip and a sound vibration system to solve the above technical problems.

[0006] In a first aspect, the present application provides a data synchronization method, including: receiving a node input signal based on a first clock signal; outputting a node output signal based on a second clock signal; during the output process of the node output signal, determining whether the synchronization signal is valid; when the synchronization signal is valid, preparing to output the next node output signal; when the synchronization signal is invalid, if the node output signal has not been completely output, continuing to output the node output signal until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continuing to output the compensation signal until the synchronization signal is valid.

[0007] In some embodiments, a node input signal is received once every preset number of cycles of a first clock signal, and a node output signal is output once within each cycle of a synchronization signal; wherein the first clock signal and the second clock signal are signals of different sources and / or different phases, and an average period of the synchronization signal is equal to a preset number of periods of the first clock signal.

[0008] In some embodiments, a node input signal is received based on a first clock signal and a data input clock, and the node input signal is received once in each cycle of the data input clock; wherein the first clock signal and the second clock signal are signals of different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the data input clock.

[0009] In some embodiments, the synchronization signal includes a synchronization pulse signal. During the output process of the node output signal, the step of determining whether the synchronization signal is valid includes: during the output process of the node output signal, determining whether the pulse of the synchronization signal has arrived; when the pulse of the synchronization signal arrives, preparing to output the next node output signal; when the pulse of the synchronization signal has not arrived, if the node output signal has not been completely output, continuing to output the node output signal until the node output signal is completely output or the pulse of the synchronization pulse signal arrives; if the node output signal is completely output, continuing to output the compensation signal until the pulse of the synchronization pulse signal arrives.

[0010] In some embodiments, the data synchronization method also includes: during the output process of the node output signal, counting the period of the second clock signal to obtain a counting result; when the synchronization signal is valid, changing the counting result to a second preset value; when the synchronization signal is invalid, judging whether the counting result reaches the first preset value, if the counting result reaches the first preset value, maintaining the counting result as the first preset value until the synchronization signal is valid.

[0011] In some embodiments, after the counting result changes to the second preset value, the next node output signal starts to be output after a preset number of cycles of the second clock signal have passed.

[0012] In some embodiments, the second preset value is the next count value after the first preset value.

[0013] In some embodiments, the synchronization signal is generated based on the data input clock and the second clock signal, and each cycle of the synchronization signal is equal to an integer multiple of a cycle of the second clock signal.

[0014] In a second aspect, the present application provides a chip, which is used to execute the data synchronization method of the first aspect.

[0015] In some embodiments, the chip includes: a storage module, configured to receive a node input signal based on a first clock signal; a digital-to-analog conversion module, configured to output a node output signal based on a second clock signal; a synchronization judgment module, configured to judge whether the synchronization signal is valid during the output process of the node output signal, and when the synchronization signal is valid, prepare to output the next node output signal; when the synchronization signal is invalid, keep outputting the node output signal until the synchronization signal is valid.

[0016] In some embodiments, the synchronization judgment module includes: a counting unit, configured to count the period of the second clock signal to obtain a counting result; a first execution unit, configured to determine whether the synchronization signal is valid, and when the synchronization signal is valid, change the counting result to a second preset value; a second execution unit, configured to determine whether the counting result reaches the first preset value when the synchronization signal is invalid, and if the counting result reaches the first preset value, maintain the counting result at the first preset value until the synchronization signal is valid.

[0017] In a third aspect, the present application provides a sound-vibrating system, comprising: a processor configured to output audio data and vibration waveform data; an audio driver chip configured to receive audio data and generate an audio simulation signal based on the audio data; a vibration motor driver chip configured to receive vibration waveform data and generate a vibration simulation signal based on the vibration waveform data; an audio player configured to receive the audio simulation signal and play music based on the audio simulation signal; a vibration motor configured to receive the vibration simulation signal and vibrate based on the vibration simulation signal; wherein the audio driver chip and / or the vibration motor driver chip executes the data synchronization method as exemplified in the first aspect to synchronize the audio data with the audio simulation signal, and / or synchronize the vibration waveform data with the vibration simulation signal.

[0018] The present application receives a node input signal based on a first clock signal, and outputs a node output signal based on a second clock signal. During the output process of the node output signal, if the synchronization signal is valid (for example, a rising edge or a falling edge arrives), the node output signal is prepared to be output for the next time. If the synchronization signal is invalid and the node output signal has not been outputted, the node output signal will continue to be outputted until the node output signal is outputted or the synchronization signal is valid; if the synchronization signal is invalid and the node output signal is outputted, the compensation signal will continue to be outputted until the synchronization signal is valid, so that the node output signal is outputted once in each cycle of the synchronization signal. Since the average cycle of the synchronization signal is equal to the cycle of the data input clock in the embodiment of the present application, the receiving frequency of the node input signal is equivalent to the output frequency of the node output signal. At the same time, since the first clock signal and the second clock signal can be signals of different sources and / or different phases, the synchronization of the node output signal and the node input signal can be finally achieved without setting a phase-locked loop circuit, which is beneficial to reducing the circuit area and manufacturing cost of the driver chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 It is a schematic diagram of data synchronization in related technologies;

[0021] Figure 2 It is a flow chart of a data synchronization method provided in an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of related signals provided in an embodiment of the present application;

[0023] Figure 4 is another schematic diagram of related signals provided in an embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a synchronization signal, a data input clock, and a second clock signal provided in an embodiment of the present application;

[0025] Figure 6 is another schematic diagram of a synchronization signal, a data input clock, and a second clock signal provided in an embodiment of the present application;

[0026] Figure 7 It is a schematic diagram of a flow chart of an output node output signal provided in an embodiment of the present application;

[0027] Figure 8 is another schematic diagram of related signals provided in an embodiment of the present application;

[0028] Fig. 9 is a schematic diagram of a chip provided in an embodiment of the present application;

[0029] Fig.10 is another schematic diagram of a chip provided in an embodiment of the present application;

[0030] Fig.11 It is a schematic diagram of the sound-induced vibration system provided in the embodiment of the present application.

[0031] Among them, 10 first-in-first-out storage modules, 20 digital-to-analog conversion modules, 30 timing modules, 40 synchronization judgment modules, 50 OSC clock modules, 100 processors, 200 audio driver chips, 300 motor driver chips, 400 audio players, and 500 vibration motors. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0033] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0034] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0035] At the same time, the present application uses specific words to describe the embodiments of the present application. For example, "one embodiment", "an embodiment", and / or "some embodiments" refer to a certain feature, structure or characteristic related to at least one embodiment of the present application. Therefore, it should be emphasized and noted that "one embodiment" or "an embodiment" or "an alternative embodiment" mentioned twice or more in different positions in this specification does not necessarily refer to the same embodiment. In addition, some features, structures or characteristics in one or more embodiments of the present application can be appropriately combined.

[0036] Similarly, it should be noted that in order to simplify the description of the disclosure of this application and thus help understand one or more embodiments of the invention, in the above description of the embodiments of this application, multiple features are sometimes combined into one embodiment, figure or description thereof. However, this disclosure method does not mean that the features required by the object of this application are more than the features mentioned in the claims. In fact, the features of the embodiments are less than all the features of the single embodiment disclosed above.

[0037] In some embodiments, numbers describing the number of components and attributes are used. It should be understood that such numbers used in the description of the embodiments are modified by the modifiers "about", "approximately" or "substantially" in some examples. Unless otherwise specified, "about", "approximately" or "substantially" indicate that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may change according to the required features of individual embodiments. In some embodiments, numerical parameters should consider specifying significant digits and adopting a general method of retaining digits. Although the numerical domains and parameters used to confirm the breadth of their range in some embodiments of the present application are approximate values, in specific embodiments, the setting of such numerical values ​​is as accurate as possible within the feasible range.

[0038] Each patent, patent application, patent application publication, and other materials, such as articles, books, instructions, publications, documents, etc., cited in this application is hereby incorporated by reference in its entirety, except for application history documents that are inconsistent with or conflicting with the content of this application, and documents that limit the broadest scope of the claims of this application (currently or later attached to this application). It should be noted that if the descriptions, definitions, and / or use of terms in the accompanying materials of this application are inconsistent or conflicting with the examples of this application, the descriptions, definitions, and / or use of terms in this application shall prevail.

[0039] In some implementation scenarios, a phase locked loop (PLL) circuit can be used to make the update clock frequencies of the digital signal and the analog signal the same clock source, thereby ensuring the synchronization of the digital signal and the analog signal. Figure 1 , Figure 1 A schematic diagram of data synchronization in the related art is shown, wherein the data synchronization circuit includes a first-in-first-out memory (First Input First Output, FIFO) and a phase-locked loop circuit (Phase Locked Loop, PLL), the node data is stored in the first-in-first-out memory through a bus according to the input clock, and the phase-locked loop circuit obtains the output clock by multiplying the input clock, and the node data in the FIFO outputs an output signal of a corresponding frequency according to the output clock. Since the input clock and the output clock are associated based on the PLL, the input clock and the output clock are the same clock source, so the synchronization of the input signal and the output signal can be guaranteed.

[0040] However, in order to achieve synchronization between input and output signals based on this technical approach, a phase-locked loop circuit needs to be set up in the corresponding chip (such as a motor driver chip or an audio driver chip), which leads to an increase in the driver chip area and an increase in the cost of a single chip.

[0041] To this end, the embodiments of the present application provide a data synchronization method, a chip, and a sound vibration system, which are described in detail below.

[0042] First, see Figure 2 , Figure 2 A flow chart of a data synchronization method in an embodiment of the present application is shown, wherein the data synchronization method comprises: steps S201 to S203.

[0043] Step S201: receiving a node input signal based on a first clock signal.

[0044] In some embodiments, the node input signal can be input into the memory through the bus based on the first clock signal and the data input clock, thereby completing the receiving process of the node input signal.

[0045] Generally, the first clock signal and the data input clock are homologous clock signals, that is, the first clock signal and the data input clock can be generated based on the same crystal oscillator circuit. Exemplarily, the bus can be an I2C bus, an I2S bus, an SPI bus, a CAN bus or an SSP bus, and the memory can be a synchronous first-in-first-out memory or an asynchronous first-in-first-out memory.

[0046] Specifically, the node input signal is received once in each cycle of the data input clock. Taking the I2S bus using the standard iis mode to transmit the node input signal as an example, the input frequency of the node input signal is 48kHz, and the data length of each node input signal is 32bit, that is, the period of the data input clock is 1 / 48000 seconds, the node input signal is received once every 1 / 48000 seconds, and the frequency of the first clock signal is 32*48kHz=1.536mHz. Taking the I2S bus using the standard TMD mode to transmit the node input signal as an example, the input frequency of the node input signal is 48kHz, and the data length of each node input signal is 64bit, that is, the period of the data input clock is 1 / 48000 seconds, the node input signal is received once every 1 / 48000 seconds, and the frequency of the first clock signal is 64*48kHz=3.072mHz.

[0047] In some embodiments, the node input signal can be received once every preset number of cycles of the first clock signal. For example, when the memory receives the node input signal, the memory counts the first clock signal. When the count reaches a set value (for example, from 0 to 31), it indicates that a node input signal with a data length of 32 bits has been received. The memory clears the count and then starts receiving the next node input signal, and the node input signal is received in a cycle. In one example, if the data length of each node input signal is 32 bits and the frequency of the first clock signal is 1.536 MHz, then the fixed duration is 1 / 1.536 MHz*32=1 / 48000 seconds.

[0048] Step S202, outputting a node output signal based on a second clock signal (on-chip OSC).

[0049] It should be noted that since the node input signal is received once in each cycle of the data input clock, the memory has written the complete N-1th node input signal after starting to receive the Nth node input signal. Then, after starting to receive the Nth node input signal (for example, after an interval of a preset number of cycles of the second clock signal), the circuit (for example, a digital-to-analog converter) can start outputting the Nmth node output signal based on the second clock signal and the synchronization signal according to the node input signal received for the Nmth time in the memory, where m is a positive integer greater than or equal to 1.

[0050] Generally, the second clock signal and the synchronization signal are the same clock signal, and the second clock signal and the synchronization signal can be generated based on the same crystal oscillator circuit.

[0051] Specifically, the node output signal can be generated based on a second clock signal, which is different from the source and / or different from the first clock signal, that is, there is no need to set a phase-locked loop circuit to generate the second clock signal based on the first clock signal, or there is no need to set a phase-locked loop circuit to generate the second clock signal based on the data input clock. In one example, the first clock signal can be generated based on a crystal oscillator circuit, and the second clock signal is generated based on another crystal oscillator circuit.

[0052] In some embodiments, the ideal frequency of the second clock signal may be different from the frequency of the first clock signal. For example, taking the I2S bus using the standard iis mode to transmit node input signals, the input frequency of the node input signal is 48kHz, the data length of each node input signal is 32 bits, the frequency of the first clock signal is 32*48kHz=1.536mHz, the output frequency of the node output signal is also 48kHz, and the ideal data length of each node output signal is 128 bits. The ideal frequency of the second clock signal is 128*48kHz=6.144mHz.

[0053] In some embodiments, the ideal frequency of the second clock signal may also be equal to the frequency of the first clock signal.

[0054] It should be noted that in the specific circuit implementation, there is a deviation between the actual frequency of the second clock signal and the ideal frequency. This deviation will cause the node output signal and the node input signal to be input and output asynchronously, and as time goes on, the synchronization error between the node output signal and the node input signal caused by this frequency deviation becomes larger and larger. Therefore, a synchronization signal is required to correct the synchronization between the node output signal and the node input signal.

[0055] Step S203: during the output process of the node output signal, determine whether the synchronization signal is valid.

[0056] It should be noted that determining whether the synchronization signal is valid may refer to determining whether the rising edge or falling edge of the synchronization signal has arrived. For example, an edge trigger may be used to determine whether the rising edge or falling edge of the synchronization signal has arrived. When the rising edge / falling edge of the synchronization signal arrives, it indicates that the synchronization signal is valid.

[0057] Specifically, when the synchronization signal is invalid, if the node output signal has not been completely output, continue to output the node output signal until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continue to output the compensation signal (for example, a high-level signal, a low-level signal, or an alternating high and low-level AC signal) until the synchronization signal is valid; and when the synchronization signal is valid, prepare to output the next node output signal so that the node output signal is output once in each cycle of the synchronization signal.

[0058] In some embodiments, see Figure 3 , Figure 3 A schematic diagram of relevant signals in an embodiment of the present application is shown. During the process of outputting the N-1th node output signal, the N-1th node output signal has been output before the synchronization signal is valid, so a compensation signal maintained at a low level is output until the synchronization signal is valid; when the synchronization signal is valid, the output of the current N-1th node output signal is immediately stopped, and the output of the Nth node output signal is immediately started according to the Nth node input signal received by the memory.

[0059] In some embodiments, see Figure 4 , Figure 4Another schematic diagram of related signals in an embodiment of the present application is shown. In the process of the N-1th node output signal, the N-1th node output signal has been output before the synchronization signal is valid, so a compensation signal maintained at a high level is output until the synchronization signal is valid; after the synchronization signal is valid, the current N-1th node output signal continues to be output for a preset number (for example, 3) cycles of the second clock signal, and after the preset number of cycles of the second clock signal, the Nth node output signal is output according to the Nth node input signal received by the memory.

[0060] It is understandable that the drawings of the present application illustrate the preset number as 3, which does not constitute a limitation on the present embodiment. In specific applications, the preset number can be set to any positive integer or 0.

[0061] This embodiment receives a node input signal based on a first clock signal, and outputs a node output signal based on a second clock signal. During the output process of the node output signal, if the synchronization signal is valid (for example, a rising edge or a falling edge arrives), the node output signal is prepared to be output for the next time. If the synchronization signal is invalid and the node output signal has not been outputted, the node output signal will continue to be outputted until the node output signal is outputted or the synchronization signal is valid; if the synchronization signal is invalid and the node output signal is outputted, the compensation signal will continue to be outputted until the synchronization signal is valid, so that the node output signal is outputted once in each cycle of the synchronization signal. Since the cycle of the synchronization signal is equal to the cycle of the data input clock in the embodiment of the present application, the receiving frequency of the node input signal is equivalent to the output frequency of the node output signal. At the same time, since the first clock signal and the second clock signal can be signals of different sources and / or different phases, the synchronization of the node output signal and the node input signal can be finally achieved without the need for a phase-locked loop circuit, which is beneficial to reducing the circuit area and manufacturing cost of the driver chip.

[0062] In some embodiments, for example, in an embodiment where a node input signal is received once every preset number of periods of the first clock signal, the average period of the synchronization signal is equal to the preset number of periods of the first clock signal.

[0063] In some embodiments, for example, for embodiments in which the node input signal is received based on the first clock signal and a data input clock, the average period of the synchronization signal is equal to the period of the data input clock.

[0064] In some embodiments, the synchronization signal includes a synchronization pulse signal. During the output process of the node output signal, the step of determining whether the synchronization signal is valid includes: during the output process of the node output signal, determining whether the pulse of the synchronization pulse signal has arrived; when the pulse of the synchronization pulse signal arrives, preparing to output the next node output signal; when the pulse of the synchronization pulse signal has not arrived, if the node output signal has not been completely output, continuing to output the node output signal until the node output signal is completely output or the pulse of the synchronization pulse signal arrives; if the node output signal is completely output, continuing to output the compensation signal until the pulse of the synchronization pulse signal arrives.

[0065] For example, taking the I2S bus using the standard iis mode to transmit node input signals as an example, the period of the data input clock is 1 / 48000 seconds. If the first pulse period of the synchronization pulse signal is 1.2 / 48000 seconds, the second pulse period of the synchronization pulse signal is 0.8 / 48000 seconds, the third pulse period of the synchronization pulse signal is 0.9 / 48000 seconds, and the fourth pulse period of the synchronization pulse signal is 1.1 / 48000 seconds, it can be seen that the average period of the synchronization pulse signal of the four pulse periods is also 1 / 48000 seconds. Then, from the overall point of view, the average period of the synchronization pulse signal is equal to the period of the data input clock, that is, the input frequency of the node input signal is equivalent to the output frequency of the node output signal. Ultimately, it can be avoided that the input frequency of the node input signal is greater than the output frequency of the node output signal, thereby causing more and more data to be stored in the memory and causing data overflow in the memory. At the same time, since the first clock signal and the second clock signal in the embodiment of the present application can be signals of different sources and / or different phases, the synchronization of the node output signal and the node input signal can be achieved without setting up a phase-locked loop circuit, which is beneficial to reducing the circuit area of ​​the driver chip and the single-chip manufacturing cost.

[0066] In some embodiments, the synchronization signal is generated based on the data input clock and the second clock signal, and each pulse period of the synchronization signal is equal to an integer multiple of the period of the second clock signal. Figure 5 , Figure 5 A schematic diagram of the synchronization signal, data input clock and second clock signal in an embodiment of the present application is shown. After the first rising edge of the data input clock arrives and the rising edge of the second clock signal arrives, the synchronization signal generating circuit outputs a first pulse, and the pulse period of the first pulse is 13 periods of the second clock signal. After the second rising edge of the data input clock arrives and the rising edge of the second clock signal arrives, the synchronization signal generating circuit (e.g., a pulse generator) outputs a second pulse, and the pulse period of the second pulse is 12 periods of the second clock signal.

[0067] It can be seen that since the pulse of the synchronization signal needs to wait until the rising edge of the data input clock and the second clock signal is valid before it can be output, the pulse of the synchronization signal is actually controlled by the data input clock, and each cycle of the synchronization signal can also be equal to an integer multiple of the cycle of the second clock signal, and finally the average cycle of the synchronization signal is equal to the cycle of the data input clock, so that the average cycle of each output of the node output signal is equal to the cycle of the data input clock, and the duration of each output is an integer multiple of the cycle of the second clock signal.

[0068] In some embodiments, the synchronization signal generating circuit that outputs the synchronization signal may include a digital circuit composed of a trigger, a pulse generator, a logic gate circuit, etc.

[0069] In some embodiments, the synchronization signal can also be generated based on the delayed data input clock and the second clock signal, for example, see Figure 6 , Figure 6 Another schematic diagram of the synchronization signal, data input clock and second clock signal in an embodiment of the present application is shown. The delayed data input clock has the same period as the original data input clock, so that the average period of the synchronization signal can also be equal to the period of the data input clock.

[0070] In some embodiments, see Figure 7 , Figure 7 A schematic diagram of a process of outputting a signal from an output node in an embodiment of the present application is shown, and the data synchronization method further includes steps S701 to S704.

[0071] Step S701: During the output process of the node output signal, the cycle of the second clock signal is counted to obtain a counting result.

[0072] Step S702: when the synchronization signal is invalid, determine whether the counting result reaches a first preset value.

[0073] Step S703: if the counting result reaches the first preset value, the counting result is maintained as the first preset value until the synchronization signal is valid.

[0074] Step S704: when the synchronization signal is valid, the counting result is changed to a second preset value.

[0075] It should be noted that the change of the counting result of the counter to the second preset value indicates that the next node output signal can be prepared to be output. Therefore, when the synchronization signal is valid, after the counting result is changed to the second preset value, regardless of whether the counting result of the counter reaches the first preset value, the next node output signal can be prepared to be output. At this time, it is equivalent to shortening the output duration of the node output signal, and the shortened duration is one cycle or multiple cycles of the second clock signal; conversely, when the synchronization signal is invalid, if the counting result of the counter reaches the first preset value, the counting result is maintained at the first preset value until the synchronization signal is valid. In the process of maintaining the counting result at the first preset value, a low-level compensation signal is output, which is equivalent to extending the output duration of the node output signal. The extended duration is the number of cycles of the second clock signal during the process of maintaining the counting result at the first preset value.

[0076] It can be seen that this embodiment counts the period of the second clock signal and combines the control logic of whether the synchronization signal is valid and whether the counting result reaches the first preset value, so as to shorten the output duration of the node output signal and extend the output duration of the node output signal, and finally makes the output frequency of the node output signal equal to the input frequency of the node input signal, thereby avoiding the phenomenon of memory data overflow.

[0077] In some embodiments, after the counting result changes to the second preset value, the next node output signal starts to be output after a preset number of cycles of the second clock signal have passed. Figure 8 , Figure 8 A schematic diagram of relevant signals in an embodiment of the present application is shown, wherein after the counting result changes to the second preset value, the next node output signal starts to be output after an interval of 3 cycles of the second clock signal.

[0078] It should be noted that the drawings of the present application use the period of a preset number of second clock signals as 3 as an example, which does not constitute a limitation on the present embodiment; in specific applications, the period of an interval of a preset number of second clock signals is not limited to this, for example, the period of an interval of a preset number of second clock signals can also be 0, 1, 2 or even more periods of a preset number of second clock signals.

[0079] In some embodiments, the second preset value is the next count value after the first preset value. Figure 8, taking the counting result from 0, 1, 2...127 as an example, when the counting result is 0, the next counting value of the counting result is 1, when the counting result is 125, the next counting value of the counting result is 126, and when the counting result is 127, the next counting value of the counting result is 0. If the first preset value is 124, the second preset value is 125. In the process of outputting the N-1th node output signal, the counting result is 123 when the synchronization signal is valid, and the counting result changes to 125 after the synchronization signal is valid; in the process of outputting the N-2th node output signal, the counting result has been maintained at 124 when the synchronization signal is valid, and the counting result changes to 125 after the synchronization signal is valid. After the counting result changes to 125, the counting result changes to 0 after 3 cycles of the second clock signal. Therefore, in some embodiments, the node output signal can be output each time the counting result is 0.

[0080] In other embodiments, taking the negative cycle counting of counting results 127, 126, 125...0 as an example, when the counting result is 127, the next counting value of the counting result is 126, when the counting result is 4, the next counting value of the counting result is 3, and when the counting result is 0, the next counting value of the counting result is 127. If the first preset value is 4, the second preset value is 3, combined with the embodiment of starting to output the next node output signal after the counting result changes to the second preset value with an interval of 3 cycles of the second clock signal, that is, in some embodiments, the node output signal can be output each time the counting result is 0.

[0081] It can be understood that the above embodiment is an illustrative description using integer counting as an example and does not constitute a limitation of the present embodiment. In some embodiments, the counting result can also be counted in sequence according to the set encoding. For example, it can be counted in sequence according to the odd numbers 1, 3, 5...127. For another example, it can be counted in sequence according to the even numbers 0, 2, 4, 6...126.

[0082] It is worth noting that the above content about the data synchronization method is intended to clearly illustrate the implementation verification process of the present application. Under the guidance of the present application, technical personnel in this field can also make equivalent modified designs. For example, the delayed data input clock can also be used as a synchronization signal and the output node output signal can be used. In this way, the average period of the synchronization signal can be equal to the period of the data input clock.

[0083] In order to better implement the data synchronization method in the embodiment of the present application, on the basis of the data synchronization method, another embodiment of the present application further provides a chip, the chip is used to execute the data synchronization method as in any of the above embodiments, illustratively, the chip can be a motor driver chip or an audio driver chip. Since the chip in the embodiment of the present application is provided with the data synchronization method of the above embodiment, it has all the beneficial effects of the above data synchronization method, which will not be described in detail here.

[0084] See also Fig. 9 , Fig. 9 A module schematic diagram of a chip in an embodiment of the present application is shown, wherein the chip includes a storage module 10, a digital-to-analog conversion module 20 and a synchronization judgment module 40, wherein the storage module 10 is used to receive a node input signal based on a first clock signal and a data input clock, and the storage module 10 is used to output a node output signal based on a second clock signal generated by an OSC clock module 30, the digital-to-analog conversion module 20 outputs a PWM signal based on the node output signal, and the synchronization judgment module 40 is used to judge whether a synchronization signal (such as whether a pulse arrives) is valid during the output process of the node output signal, so as to prepare to output the next node output signal when the synchronization signal is valid; and when the synchronization signal is invalid, if the node output signal has not been outputted completely, the node output signal continues to be outputted until the node output signal is outputted completely or the synchronization signal is valid; if the node output signal is outputted completely, the compensation signal continues to be outputted until the synchronization signal is valid.

[0085] In some embodiments, see Fig.10 Another module schematic diagram of the chip in the embodiment of the present application is shown, wherein the synchronization judgment module 40 includes a counting unit 41, a first execution unit 42 and a second execution unit 43, the counting unit 41 is configured to count the period of the second clock signal to obtain a counting result, and the counting result is used to output a PWM signal according to the node output signal; the first execution unit, the first execution unit 42 is configured to determine whether the synchronization signal is valid, and when the synchronization signal is valid, the counting result is changed to a second preset value; the second execution unit 43 is configured to determine whether the counting result reaches the first preset value when the synchronization signal is invalid, and if the counting result reaches the first preset value, the counting result is maintained at the first preset value until the synchronization signal is valid.

[0086] It should be noted that Fig. 9 or Fig.10The modules shown can be implemented in various ways. For example, in some embodiments, the device and its modules can be implemented by hardware, software, or a combination of software and hardware. Among them, the hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware. Those skilled in the art will understand that the above methods and systems can be implemented using computer executable instructions and / or included in processor control code.

[0087] The chip and its modules provided in this embodiment can be implemented not only by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic circuits, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., but also by a combination of the above hardware circuits and software (for example, firmware).

[0088] It should be noted that the above description of the device and its modules is only for convenience of description and does not limit the present application to the scope of the embodiments. It is understandable that, after understanding the principle of the system, those skilled in the art may arbitrarily combine the modules or form a subsystem to connect with other modules without deviating from the principle. For example, Fig. 9 or Fig.10 The digital-to-analog conversion module 20 and the synchronization determination module 40 disclosed in the specification can be different modules in a system, or one module can realize the functions of two or more modules mentioned above.

[0089] In order to better implement the chip in the embodiment of the present application, based on the chip, another embodiment of the present application also provides a sound vibration system, see Fig.11 , Fig.11 A schematic diagram of a sound-induced vibration system in an embodiment of the present application is shown, wherein the sound-induced vibration system includes: a processor 100, configured to output audio data and vibration waveform data; an audio driver chip 200, configured to receive audio data and generate an audio simulation signal based on the audio data; a vibration motor driver chip 300, configured to receive vibration waveform data and generate a vibration simulation signal based on the vibration waveform data; an audio player 400, configured to receive an audio simulation signal and play music based on the audio simulation signal; and a vibration motor 500, configured to receive a vibration simulation signal and vibrate based on the vibration simulation signal.

[0090] The audio driver chip 200 and / or the vibration motor driver chip 300 in the sound-vibration system provided in this embodiment can execute the data synchronization method of any of the above embodiments, so that the audio data and the audio simulation signal can be synchronized, and / or the vibration waveform data and the vibration simulation signal can be synchronized to avoid the phenomenon of audio data and vibration waveform data being lost. Since the driver chip in the sound-vibration system of the embodiment of the present application is provided with the data synchronization method of the above embodiment, it has all the beneficial effects of the above data synchronization method, which will not be repeated here.

[0091] In some embodiments, the processor uses the same protocol to transmit audio data and vibration waveform data. For example, taking the I2S protocol to transmit audio data and vibration waveform data as an example, the left channel of the I2S bus can be used to transmit audio data to the audio driver chip, and the right channel can be used to transmit vibration waveform data to the motor driver chip, so that the audio data and vibration waveform data can be transmitted synchronously, and the audio player and the motor can work synchronously to better achieve the vibration effect with the sound, and finally avoid the phenomenon of asynchronous audio signal and vibration signal.

[0092] In order to better implement the sound-vibrating system in the embodiment of the present application, on the basis of the sound-vibrating system, another embodiment of the present application further provides an electronic device, which can be but is not limited to a car, a smart wearable device, a mobile terminal, a smart home device, etc. Among them, smart wearable devices include but are not limited to smart watches, smart bracelets, and cervical massagers. Mobile terminals include but are not limited to smart phones, laptops, tablets, and point of sales terminals (POS). Smart home devices include but are not limited to smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0093] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0094] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and amendments to the present application. Such modifications, improvements and amendments are suggested in the present application, so such modifications, improvements and amendments still belong to the spirit and scope of the exemplary embodiments of the present application.

[0095] The above is a detailed introduction to a data synchronization method, a driver chip and a sound vibration system provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those skilled in the art, according to the ideas of the present invention, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A data synchronization method, characterized in that: include: receiving a node input signal based on a first clock signal; outputting a node output signal based on a second clock signal; During the outputting process of the node output signal, determining whether the synchronization signal is valid; When the synchronization signal is valid, prepare to output the node output signal next time; When the synchronization signal is invalid, if the node output signal has not been completely output, continue to output the node output signal until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continue to output the compensation signal until the synchronization signal is valid.

2. The data synchronization method according to claim 1, characterized in that: The node input signal is received once every preset number of cycles of the first clock signal; The first clock signal and the second clock signal are signals of different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the preset number of first clock signals.

3. The data synchronization method according to claim 1, characterized in that: The node input signal is received based on the first clock signal and a data input clock, and the node input signal is received once in each cycle of the data input clock; The first clock signal and the second clock signal are signals of different sources and / or different phases, and the average period of the synchronization signal is equal to the period of the data input clock.

4. The data synchronization method according to claim 2 or 3, characterized in that: The synchronization signal includes a synchronization pulse signal, and the step of judging whether the synchronization signal is valid during the output process of the node output signal includes: During the output process of the node output signal, determining whether a pulse of the synchronization signal arrives; When the pulse of the synchronization pulse signal arrives, prepare to output the node output signal next time; When the pulse of the synchronization pulse signal has not arrived, if the node output signal has not been completely output, continue to output the node output signal until the node output signal is completely output or the pulse of the synchronization pulse signal arrives; if the node output signal is completely output, continue to output the compensation signal until the pulse of the synchronization pulse signal arrives.

5. The data synchronization method according to claim 1, characterized in that: The method further comprises: During the outputting process of the node output signal, counting the period of the second clock signal to obtain a counting result; When the synchronization signal is valid, changing the counting result to a second preset value; When the synchronization signal is invalid, it is determined whether the counting result reaches a first preset value; if the counting result reaches the first preset value, the counting result is maintained at the first preset value until the synchronization signal is valid.

6. The data synchronization method according to claim 5, characterized in that: After the counting result changes to the second preset value, the node output signal starts to be outputted for the next time after a preset number of cycles of the second clock signal have passed.

7. The data synchronization method according to claim 5, characterized in that: The second preset value is the next count value of the count result after the first preset value.

8. The data synchronization method according to claim 4, characterized in that: The synchronization signal is generated based on the second clock signal, and each cycle of the synchronization signal is equal to an integer multiple of a cycle of the second clock signal.

9. A chip, characterized in that: The chip is used to execute the data synchronization method as described in any one of claims 1 to 8.

10. The chip according to claim 9, characterized in that The chip comprises: A storage module configured to receive a node input signal based on a first clock signal; A digital-to-analog conversion module, configured to output a signal at a node based on a second clock signal; The synchronization judgment module is configured to judge whether the synchronization signal is valid during the output process of the node output signal; when the synchronization signal is valid, prepare to output the node output signal for the next time; when the synchronization signal is invalid, if the node output signal has not been completely output, continue to output the node output signal until the node output signal is completely output or the synchronization signal is valid; if the node output signal is completely output, continue to output the compensation signal until the synchronization signal is valid.

11. The chip according to claim 10, characterized in that: The synchronization judgment module comprises: a counting unit, configured to count the period of the second clock signal to obtain a counting result; A first execution unit is configured to determine whether the synchronization signal is valid, and when the synchronization signal is valid, change the counting result to a second preset value; The second execution unit is configured to, when the synchronization signal is invalid, determine whether the counting result reaches a first preset value, and if the counting result reaches the first preset value, maintain the counting result at the first preset value until the synchronization signal is valid.

12. A sound-induced vibration system, characterized in that: include: A processor configured to output audio data and vibration waveform data; an audio driver chip, configured to receive the audio data and generate an audio analog signal based on the audio data; a vibration motor driving chip configured to receive the vibration waveform data and generate a vibration simulation signal based on the vibration waveform data; an audio player configured to receive the audio analog signal and play music based on the audio analog signal; a vibration motor configured to receive the vibration simulation signal and vibrate based on the vibration simulation signal; Wherein, the audio driver chip and / or the vibration motor driver chip executes the data synchronization method as described in any one of claims 1 to 8.

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