Wafer test data processing method and device, computer equipment and storage medium

Abstract

The invention discloses a wafer test data processing method and device, computer equipment and a storage medium. The wafer test data processing method comprises the steps that first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units on the wafer are acquired, and the first local test data are test data corresponding to a first test type; the second local test data is test data corresponding to the second test type; generating first global synthesis test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthesis test data corresponding to all chip units on the wafer according to the second local test data; and performing correlation analysis on the synthetic test data of the first test type and the second test type of the wafer based on the first global synthetic test data and the second global synthetic test data. According to the embodiment of the invention, correlation analysis of the synthetic test data of different test types of the wafer is realized.

Description

Technical Field

[0001] The present application belongs to the field of data processing, and in particular, relates to a wafer test data processing method, device, computer equipment and storage medium. Background Art

[0002] In the field of integrated circuits, the wafer manufacturing process is cumbersome and complex, and the process standards are extremely high. During the wafer manufacturing process, each wafer will go through many processes, such as diffusion, deposition, etching and lithography. The process quality of each process will ultimately be reflected in the functional parameters of the components and the final yield. When the process quality is stable, the functions of various components are normal, and the product yield will also be stable and maintained at a good level.

[0003] In order to ensure the production yield of the final product and the stability and controllability of the manufacturing process, the wafer manufacturing process often adds multiple testing links. However, due to the different test purposes of the various tests, the test locations selected in the various test processes are also different. Due to the limitations of the test location selection, multiple tests often cannot obtain different test data at the same location. Therefore, the test data of various tests are analyzed separately and cannot be analyzed together. When the test data is analyzed separately, the various feedback problems of the test data exist in isolation. It is impossible to trace back from the functional data to the production and manufacturing process to find problems, and it is impossible to predict the functional data from the measurement data. Summary of the invention

[0004] The embodiments of the present application provide a wafer test data processing method, apparatus, computer equipment and storage medium, which solve the problem in the prior art that test data of different test types can only be analyzed separately due to different test points of wafers of different test types.

[0005] On the one hand, an embodiment of the present application provides a wafer test data processing method, the wafer test data processing method comprising:

[0006] Acquire first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units, wherein the first local test data is test data corresponding to a first test type, and the second local test data is test data corresponding to a second test type;

[0007] Generate first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generate second global synthetic test data corresponding to all chip units on the wafer according to the second local test data;

[0008] Based on the first global synthetic test data and the second global synthetic test data, correlation analysis is performed on synthetic test data of the first test type and the second test type of the wafer.

[0009] In some embodiments, generating first global synthetic test data corresponding to all chip units on a wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on a wafer according to the second local test data, comprises:

[0010] The first local test data is interpolated using a spatial interpolation method to generate first global synthetic test data corresponding to all chip units on the wafer, and the second local test data is interpolated using a spatial interpolation method to generate second global synthetic test data corresponding to all chip units on the wafer.

[0011] In some embodiments, generating first global synthetic test data corresponding to all chip units on a wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on a wafer according to the second local test data, comprises:

[0012] Inputting the first local test data into a test data generation model to generate first global synthetic test data;

[0013] The second local test data is input into the test data generation model to generate second global synthetic test data.

[0014] In some embodiments, the test data generation model is trained based on a generative adversarial network model, and the generative adversarial network model includes a first generator and a first discriminator;

[0015] Before generating first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on the wafer according to the second local test data, the method further includes:

[0016] Acquire first global test data corresponding to all chip units on the wafer;

[0017] Acquire third local test data corresponding to some chip units from the first global test data;

[0018] Interpolating the third local test data using a spatial interpolation method to generate first interpolated global test data corresponding to all chip units on the wafer;

[0019] Inputting the first interpolated global test data into the first generator to obtain the first predicted global test data;

[0020] Inputting the first predicted global test data and the first global test data into the first discriminator to obtain a first discrimination result;

[0021] When the first discrimination result does not meet the preset training stop condition, the model parameters of the first generator and the first discriminator are adjusted according to the first predicted global test data, the first discrimination result and the first global test data to obtain an updated generative adversarial network model, and the first interpolated global test data is returned to the first generator to obtain the first predicted global test data, until the first discrimination result meets the preset training stop condition.

[0022] In some embodiments, the first generator includes an encoder, a residual network layer, and a decoder;

[0023] Inputting the first interpolated global test data into the first generator to obtain the first predicted global test data includes:

[0024] Inputting the first interpolated global test data into the encoder to perform feature extraction on the first interpolated global test data to obtain first test data features;

[0025] Mapping the first test data feature through a residual network layer to obtain a second test data feature;

[0026] The decoder performs deconvolution processing on the second test data feature to obtain first predicted global test data.

[0027] In some implementations, adjusting model parameters of the first generator and the first discriminator according to the first predicted global test data, the first discrimination result, and the first global test data to obtain an updated generative adversarial network model includes:

[0028] The loss is calculated according to the first discrimination result and the target loss function to obtain the first generator loss and the discriminator loss;

[0029] Adjust the model parameters of the first discriminator through the discriminator loss;

[0030] Performing similarity calculation on the first predicted global test data and the first global test data through a similarity function to obtain a second generator loss;

[0031] Perform a weighted sum of the first generator loss and the second generator loss to obtain the third generator loss;

[0032] The model parameters of the first generator are adjusted through the third generator loss.

[0033] In some embodiments, the generative adversarial network model further includes a second generator and a second discriminator, the size of the second generator input data is smaller than the size of the first generator input data, and the size of the second discriminator input data is smaller than the size of the second discriminator input data;

[0034] Inputting the first interpolated global test data into the first generator to obtain the first predicted global test data; inputting the first predicted global test data and the first global test data into the first discriminator to obtain the first discrimination result, including:

[0035] Down-sampling the first interpolated global test data to obtain first sampled data, and down-sampling the first global test data to obtain second sampled data;

[0036] Inputting the first sample data into the second generator to obtain second predicted global test data;

[0037] Inputting the second predicted global test data and the second sampled data into the second discriminator to obtain a second discrimination result;

[0038] In the case where the second discrimination result does not meet the training stop condition, the model parameters of the second generator and the second discriminator are adjusted according to the second predicted global test data, the second discrimination result, and the second sampled data, and the first sampled data is input into the second generator to obtain the second predicted global test data, until the second discrimination result meets the training stop condition, and the second predicted global test data whose second discrimination result meets the training stop condition is output;

[0039] Performing feature extraction on the first interpolated global test data by the first generator to obtain third test data features;

[0040] Performing bitwise summation of the second predicted global test data output by the second generator and the third test data feature to obtain a fourth test data feature;

[0041] The first generator sequentially performs mapping processing and deconvolution processing on the fourth test data feature to obtain first predicted global test data;

[0042] The first predicted global test data and the first global test data are input into the first discriminator to obtain a first discrimination result.

[0043] On the other hand, an embodiment of the present application provides a wafer test data processing device, the wafer test data processing device comprising:

[0044] A data acquisition module is configured to acquire first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units, wherein the first local test data is test data corresponding to a first test type, and the second local test data is test data corresponding to a second test type;

[0045] A data generation module is configured to generate first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and to generate second global synthetic test data corresponding to all chip units on the wafer according to the second local test data;

[0046] The analysis module is configured to perform correlation analysis on synthetic test data of a first test type and a second test type of the wafer based on the first global synthetic test data and the second global synthetic test data.

[0047] On the other hand, an embodiment of the present application provides a computer device, including: at least one processor; and a memory, the memory storing a computer program that can be run on the processor, and the processor executes the steps of the method described in any of the above embodiments when executing the program.

[0048] On the other hand, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method described in any of the above embodiments are performed.

[0049] In an embodiment of the present application, first global synthetic test data and second synthetic global test data corresponding to different test types on the same wafer can be obtained based on first local test data and second local test data corresponding to different test types on the wafer. Through the first global synthetic test data and the second global synthetic test data, correlation analysis of synthetic test data of different test types on the wafer is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0051] Figure 1 is a schematic diagram of an exemplary WAT test point;

[0052] Figure 2 is a schematic diagram of an exemplary MET test point;

[0053] Figure 3 is a schematic diagram of an exemplary combination of WAT test points and MET test points;

[0054] Figure 4 A schematic diagram of a process flow of a wafer test data processing method provided in an embodiment of the present application;

[0055] Figure 5 A schematic diagram of the structure of a generative adversarial network model provided in an embodiment of the present application;

[0056] Figure 6 A schematic diagram of a process flow of a wafer test data processing method provided in an embodiment of the present application;

[0057] Figure 7 A schematic diagram of a process for adjusting parameters of a generative adversarial network model provided in an embodiment of the present application;

[0058] Figure 8 A schematic diagram of the training process of the generative adversarial network model provided in the embodiment of the present application;

[0059] Fig. 9 A flowchart of a method for generating predicted global test data provided by an embodiment of the present application;

[0060] Fig.10 A schematic diagram of the structure of a generative adversarial network model provided in an embodiment of the present application;

[0061] Fig.11 A flowchart of a method for training a generative adversarial network model provided in an embodiment of the present application;

[0062] Fig.12 A wafer test data processing device provided in an embodiment of the present application;

[0063] Fig.13 A schematic diagram of the hardware structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0065] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0066] The wafer manufacturing process usually includes a variety of tests, such as CP (Chip Probing, wafer level) test, WAT (Wafer Acceptance Test, wafer acceptance test) test, MET (Metrology, measurement) test, etc. CP test is used to measure the chip function and electrical parameter performance on the wafer. WAT test is used to measure the electrical parameters of specific test structures. WAT tests the electrical parameters of specific test structures on the wafer to detect the process conditions of each wafer product, thereby evaluating the quality and stability of the semiconductor manufacturing process. MET test is used to measure the structural dimensions and material properties of the wafer circuit to be tested, such as the measurement of physical parameters such as film thickness, critical dimensions, etching depth, surface morphology, etc.

[0067] By analyzing the test data, problems existing in the wafer production process can be traced back, laying the foundation for improving wafer quality. Usually, different types of test data are analyzed separately. The applicant found that when different types of test data are analyzed separately, the feedback problems also exist in isolation. For example, it is impossible to trace back from the functional data to the production process to find problems, and it is impossible to predict the functional data from the measurement data. To a certain extent, the separate analysis of different types of test data reduces the use value of the test data and cannot meet the analysis needs of engineers.

[0068] However, since the test points of different types of tests are inconsistent, the analysis of different types of test data is usually impossible to be conducted jointly.

[0069] Figure 1 is a schematic diagram of an exemplary WAT test point; Figure 2 is a schematic diagram of an exemplary MET test point; Figure 3 A schematic diagram of an exemplary combination of WAT test points and MET test points.

[0070] like Figure 1As shown, when performing WAT testing on a wafer, multiple WAT test points are usually selected on the wafer for testing, such as 9, 13 or 15, etc. Each WAT test point includes multiple chip units, such as 3×4, 4×5 or 6×6, etc.

[0071] like Figure 2 As shown, when performing MET testing on a wafer, a plurality of MET test points are usually selected on the wafer for testing, such as 9, 13 or 15 test points, and each MET test point includes a chip unit.

[0072] pass Figure 3 It can be seen that when the WAT test point schematic diagram and the MET test point schematic diagram are matched together, it is impossible to guarantee that the WAT test data and the MET test data are obtained at the same location at the same time, and it is meaningless to directly analyze the correlation of different types of test data using test data at different points. Therefore, a method is urgently needed to obtain different types of test data at the same location to analyze the correlation between different types of test data.

[0073] In order to solve at least one of the above technical problems, the embodiments of the present application provide a wafer test data processing method, device and computer storage medium. The wafer test data processing method provided by the embodiments of the present application is first introduced below.

[0074] Figure 4 A schematic diagram of a process flow of a wafer test data processing method provided in an embodiment of the present application. Figure 4 As shown, the wafer test data processing method of the embodiment of the present application includes: S401 to S403.

[0075] S401, obtaining first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units, the first test data being test data corresponding to a first test type, and the second test data being test data corresponding to a second test type.

[0076] A chip unit refers to a unit with complete functions in a separate area on a wafer or a unit with related functions that forms a group with other chip units.

[0077] The first test type may include any one of the test types such as CP test, WAT test, and MET test, etc. The second test type may include any one of the test types such as CP test, WAT test, and MET test, etc., but the type of the second test type is different from the first test type.

[0078] The first part of the chip unit and the second part of the chip unit are determined according to the test type.

[0079] The local test data corresponds to the test data on some chip units on the wafer, and refers to the real data directly obtained by testing the wafer. The first local test data and the second local test data can be stored in a database or a storage medium. When it is necessary to analyze the test data of different test types of the same wafer, the required test data can be obtained from the location where the wafer test data is stored.

[0080] S402 , generating first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on the wafer according to the second local test data.

[0081] The first global synthetic test data corresponds to all chip units on the wafer, and refers to data generated according to the first local test data. The second global synthetic test data corresponds to all chip units on the wafer, and refers to data generated according to the second local test data.

[0082] There are many ways to generate global synthetic test data.

[0083] In a specific implementation, global synthetic test data can be generated by spatial interpolation. Spatial interpolation is a method of inferring unknown position values ​​through discrete data points at known partial positions. Data of all regions on the entire wafer can be interpolated based on data of existing points on the wafer, thereby realizing the generation of global test data from local test data.

[0084] Specifically, the first local test data is interpolated by a spatial interpolation method to generate first global synthetic test data, and the second local test data is interpolated by a spatial interpolation method to generate second global synthetic test data.

[0085] In another specific implementation, global synthetic test data can also be generated by a test data generation model. The data generation model is trained by a neural network model and is used to generate global synthetic test data. Specifically, the first local test data is input into the test data generation model to generate first global synthetic test data; the second local test data is input into the test data generation model to generate second global synthetic test data.

[0086] S403 . Perform correlation analysis on synthetic test data of the first test type and the second test type of the wafer based on the first global synthetic test data and the second global synthetic test data.

[0087] Correlation analysis is used to analyze the relationship between the first global synthetic test data and the second global synthetic test data of the same wafer. In a specific implementation, a fitting function can be generated based on the first global synthetic test data and the second global synthetic test data, and a correlation analysis can be performed on the synthetic test data of the first test type and the second test type of the wafer through the fitting function. For example, the target analysis function can be determined based on the characteristics of the first global synthetic test data and the characteristics of the second global synthetic test data, and the target analysis function includes but is not limited to y=kx+b, y=ax 2 etc., taking one of the first global synthetic test data and the second global synthetic test data as the target variable, taking the other of the first global synthetic test data and the second global synthetic test data as the feature variable, obtaining the coefficient of the target analysis function according to the first global synthetic test data and the second global synthetic test data as well as the target variable and the feature variable, thereby generating a fitting function.

[0088] In another specific implementation, the synthetic test data of the first test type and the second test type corresponding to a specific chip unit may be directly acquired, and a correlation analysis may be directly performed on the data of the two test types.

[0089] In order to better understand the embodiment of the present application, the correlation analysis of the MET test data and the WAT test data of the wafer is explained by taking the first test type as the MET test type and the second test type as the WAT test type as an example.

[0090] Obtain the MET local test data and WAT local test data on different chip units on the wafer, and generate the MET global test data and WAT global test data corresponding to each chip unit on the wafer based on the MET local test data and WAT local test data. Perform a correlation analysis on the MET global test data and the WAT global test data to check whether there is a correlation between the two. In general, MET data can reflect the process effect of a certain process step. Therefore, according to the conclusion of the correlation analysis, it is possible to see the impact of the corresponding process step on the electrical structure represented by the WAT data, and then adjust and optimize the process steps based on the impact relationship. By jointly analyzing the correlation between the MET global test data and the WAT global test data, and starting from the subsequent functional data through the analysis conclusion, problems can be traced back to the wafer production and manufacturing process.

[0091] In an embodiment of the present application, first global synthetic test data and second synthetic global test data corresponding to different test types on the same wafer can be obtained based on first local test data and second local test data corresponding to different test types on the wafer, and correlation analysis of the synthetic test data of the first test type and the second test type of the wafer can be implemented through the first global synthetic test data and the second global synthetic test data.

[0092] Figure 5 A schematic diagram of the structure of a generative adversarial network model provided in an embodiment of the present application.

[0093] like Figure 5 As shown, the generative adversarial network model 50 includes a first generator 51 and a first discriminator 52.

[0094] In some embodiments, Figure 6 As shown, the present application implements Figure 4 The wafer testing method shown in the figure includes steps S401 to S403, and further includes the following steps: Figure 6 Steps S601 to S606 are shown in FIG. Figure 5 The illustrated generative adversarial network model 50 performs.

[0095] S601, obtaining first global test data corresponding to all chip units on a wafer.

[0096] The first global test data includes the test data of each chip unit on the wafer. It is the real test data obtained by testing the chip. In the production process of the wafer, a batch of wafers can be selected, and each chip unit on the selected wafer can be tested by the first test type and the second test type, respectively, so as to obtain the first global test data of the first test type and the first global test data of the second test type.

[0097] S602: Obtain third local test data corresponding to some chip units from the first global test data.

[0098] According to the test rules, the test data corresponding to the corresponding chip unit is selected from the first global test data, that is, the third local test data. Different test types have different test rules. For example, when performing WAT testing on a wafer, chip units corresponding to multiple WAT test points can be selected on the wafer for testing to obtain third local data of the MET test type. When performing MET testing on a wafer, chip units corresponding to multiple MET test points are usually selected on the wafer for testing to obtain third local data of the MET test type.

[0099] S603 , interpolating the third local test data using a spatial interpolation method to generate first interpolated global test data corresponding to all chip units on the wafer.

[0100] The first interpolation global test data is data generated by the third local test data according to the spatial interpolation method. Although the first interpolation global test data is different from the real first global test data, it can reflect certain local trend characteristics in the real first global test data to a certain extent. Compared with the local discrete test data with less information directly input into the first generator, it will improve the accuracy of model training and make the model training process more reliable.

[0101] In one example, the interpolation process in step S603 is illustrated.

[0102] Assume that the third local test data is Data local , the first global test data is Data global . The first global test data collected According to the point selection rules in the actual test process, the data of specific points are selected to form scattered local data on a single wafer This simulates the limitation that only local test data can be obtained in real situations. Then, according to the spatial interpolation method, Interpolate to form the first interpolation global test data Thus, the test data of all chip units on the entire wafer are obtained.

[0103] In an embodiment of the present application, after obtaining a plurality of first interpolated global test data, the plurality of first interpolated global test data and the first global test data can also be processed to form a first interpolated global test data set and a first global test data set. In the data set, the first interpolated global test data and the first global test data corresponding to the wafer can be numbered according to the wafer number, so that there is a one-to-one correspondence between the first interpolated global test data, the first global test data and the wafer. The first interpolated global test data in the first interpolated global test data set is used for training of the subsequent generator, and the first global test data in the first global test data set is used for training of the subsequent discriminator, as well as reconstruction of the generator loss.

[0104] S604. Input the first interpolated global test data into the first generator to obtain the first predicted global test data.

[0105] The first generator is used to generate first predicted global test data according to the input first interpolated global test data. By using the first interpolated global test data to generate the first predicted global test data, the accuracy of model training is improved, making the model training process more reliable.

[0106] S605 . Input the first predicted global test data and the first global test data into a first discriminator to obtain a first discrimination result.

[0107] In the first discriminator, whether the first predicted global test data is true data or false data can be discriminated according to the first global test data and the probability distribution function to obtain a first discrimination result. The first discrimination result is a two-dimensional vector, and the first discrimination result includes the probability that the first global test data is true data and the probability that the first global test data is false data.

[0108] S606. When the first discrimination result does not meet the preset training stop condition, adjust the model parameters of the first generator and the first discriminator according to the first predicted global test data, the first discrimination result and the first global test data to obtain an updated generative adversarial network model, and return to input the first interpolated global test data into the first generator to obtain the first predicted global test data, until the first discrimination result meets the preset training stop condition.

[0109] The training stopping condition of the first discriminator may be that the training is stopped when the first discrimination result reaches a preset threshold.

[0110] When the first discrimination result does not meet the preset threshold, the model parameters of the first generator and the first discriminator can be adjusted according to the first predicted global test data, the first discrimination result and the first global test data to obtain an updated generative adversarial network model. Figure 7 A flow chart of a method for adjusting parameters of a generative adversarial network model provided in an embodiment of the present application. In a specific implementation, the following can be used: Figure 7 The method shown in Figure 2 adjusts the parameters of the generative adversarial network model. Figure 7 As shown, the method for adjusting parameters of a generative adversarial network model may include steps S701 to S705.

[0111] S701. Perform loss calculation based on the first discrimination result and the target loss function to obtain a first generator loss and a discriminator loss.

[0112] S702: Adjust the model parameters of the first discriminator through the discriminator loss.

[0113] S703. Calculate the similarity between the first predicted global test data and the first global test data using a similarity function to obtain a second generator loss.

[0114] S704. Perform a weighted sum of the first generator loss and the second generator loss to obtain a third generator loss.

[0115] S705. Adjust the model parameters of the first generator through the loss of the third generator.

[0116] Each stage of training uses a game-adversarial training method to jointly train the corresponding first generator and first discriminator. As the game-adversarial training continues, the first predicted global test data generated by the first generator becomes closer to the first global test data, and the ability of the first discriminator to identify true and false data becomes stronger and stronger, until a dynamic balance is reached, that is, the first generator can use the input first interpolated global test data to generate first predicted global test data that is very close to the first global test data, and the first discriminator can distinguish the first predicted global test data from the first global test data by a preset threshold.

[0117] Figure 8 A schematic diagram of the training process of the generative adversarial network model provided in an embodiment of the present application. Figure 8 The specific structure of the generative adversarial network model in is as follows Figure 5 shown.

[0118] For ease of understanding, the following Figure 8 For this application Figure 6 In the embodiment shown, steps S204 to S206 are described.

[0119] After data preparation and preprocessing, two data sets were obtained, namely the first global test data set {Data global,real}, the first interpolation global test data set {Data global,interpolation}, the data in the two data sets correspond one to one according to the wafer number. In each training process, firstly, a batch of first interpolated global test data in the first interpolated global test data set is input into the first generator (G) 51. global,interpolation , generate a batch of first prediction global test data Data generated , at this time, this batch of first interpolation global test data Data global,interpolation The corresponding first global test data set {Data global,real The first global test data Data in} global,real and Data generated by the first generator 51 generated The first discriminator (D) 52 is input, and the first discriminant probability P is output by the first discriminator 52. d,g , according to the first discriminant probability P d,g The loss is calculated by the target loss function to obtain the loss Loss_GAN. Loss_GAN consists of two parts: one is the discriminator loss Loss_D, which is used to guide the optimization of the first discriminator D; the other is the first generator loss Loss_G, which is used to make a weighted sum of the second generator loss Loss_ReC to guide the optimization of the first generator 51. The second generator loss Loss_ReC is composed of Data global,real and Datagenerated The similarity is calculated. As the game confrontation training continues, the data generated by the first generator 51 is closer to the real data, and the first discriminator 52 is more capable of identifying true and false data, until a dynamic equilibrium state is reached, that is, the first generator 51 can use the input interpolation data to generate data that is very close to the real data, and the first discriminator 52 distinguishes the real data from the generated data with a probability of 1 / 2, indicating that the current training stage is completed.

[0120] In some embodiments, the present application Figure 5 The first generator 51 in the generative adversarial network model 50 shown may include an encoder 511, a residual network layer 512 and a decoder 513.

[0121] like Figure 5 The first generator 51 shown is used to perform Figure 6 Step S604 in the illustrated embodiment.

[0122] The encoder 511 can be composed of a convolutional layer, which is used to perform a convolution operation on the input data, gradually extract features, and obtain corresponding data features; the residual network layer 512 includes a residual block group, which includes multiple residual blocks. The residual network layer 512 is used to perform feature mapping on the data features extracted by the convolutional layer to obtain mapped data features; the decoder 513 can be composed of a deconvolution layer, which is used to reconstruct the mapped data features to obtain output data.

[0123] Fig. 9 A flowchart of a method for generating predictive global test data provided in an embodiment of the present application.

[0124] In some examples, the present application Figure 6 Step S604 in the illustrated embodiment may include: Fig. 9 Steps S901 to S903 in .

[0125] S901. Input first interpolated global test data to an encoder to perform feature extraction on the first interpolated global test data to obtain first test data features.

[0126] S902. Mapping the first test data feature through a residual network layer to obtain a second test data feature.

[0127] S903 . Perform deconvolution processing on the second test data features through a decoder to obtain first predicted global test data.

[0128] Fig.10 A schematic diagram of the structure of a generative adversarial network model provided in an embodiment of the present application. Fig.11 A flowchart of a generative adversarial network model training method provided in an embodiment of the present application.

[0129] In some embodiments, Fig.10 As shown, the generative adversarial network model 10 may include a first generator 11, a first discriminator 12, a second generator 13 and a second discriminator 14. The first generator 11 includes an encoder 111, a residual network layer 112 and a decoder 113. The second generator 13 and the second discriminator 14 are located between the encoder 111 and the residual network layer 112 of the first generator 11. The size of the input data of the second generator 13 is smaller than the size of the input data of the first generator 11, and the size of the input data of the second discriminator 14 is smaller than the size of the input data of the first discriminator 12. This application is as follows Fig.10 The training method of the generative adversarial network model shown is as follows Fig.11 As shown. Fig.11 The generative adversarial network model training method shown may include steps S1101 to S1108.

[0130] S1101 . Downsample first interpolated global test data to obtain first sampled data, and downsample the first global test data to obtain second sampled data.

[0131] Downsampling refers to extracting data points from the first interpolation global test data through a certain sampling rule to obtain the first sampled data. The data volume of the first sampled data is less than that of the first interpolation global test data. For example, the data volume of the first sampled data may be 1 / 4, 3 / 4, 1 / 2, 2 / 3, etc. of the first interpolation global test data. The data volume of the second sampled data is less than that of the first global test data. For example, the data volume of the second sampled data may be 1 / 4, 3 / 4, 1 / 2, 2 / 3, etc. of the second interpolation global test data.

[0132] S1102. Input the first sampling data into the second generator to obtain second predicted global test data.

[0133] S1103 , input the second predicted global test data and the second sampled data into a second discriminator to obtain a second discrimination result.

[0134] S1104. When the second discrimination result does not meet the training stop condition, adjust the model parameters of the second generator and the second discriminator according to the second predicted global test data, the second discrimination result, and the second sampling data, and return to the step of inputting the first sampling data into the second generator to obtain the second predicted global test data until the second discrimination result meets the training stop condition, and output the second predicted global test data when the second discrimination result meets the training stop condition.

[0135] S1105. Perform feature extraction on the first interpolated global test data by using the first generator to obtain third test data features.

[0136] S1106. Perform bitwise summation of the second predicted global test data output by the second generator and the third test data feature to obtain a fourth test data feature.

[0137] S1107. Use the first generator to perform mapping processing and deconvolution processing on the fourth test data features in sequence to obtain first predicted global test data.

[0138] S1108 . Input the first predicted global test data and the first global test data into a first discriminator to obtain a first discrimination result.

[0139] In an embodiment of the present application, the second generator and the second discriminator are nested between the encoder and the residual network of the first generator. The input of the second generator is the first sampling data of a certain size downsampled from the first interpolated global data. The input of the second discriminator is the output of the second generator and the second sampling data of a certain size downsampled from the first global test data. By cascading multiple generators and multiple discriminators, the training accuracy of the generative adversarial network model is improved.

[0140] It should be noted that the generative adversarial network model of the embodiment of the present application includes two generators and two discriminators. In the actual generative adversarial network model design process, more generators and corresponding discriminators may be included, and the sizes of each generator and discriminator may be the same or different.

[0141] On the other hand, an embodiment of the present application provides a wafer test data processing device, which is used to execute the wafer test data processing method of the embodiment of the present application.

[0142] Fig.12 A wafer test data processing device is provided in an embodiment of the present application. Fig.12 As shown, the wafer test data processing device 120 of the embodiment of the present application may include:

[0143] The data acquisition module 121 is configured to acquire first local test data corresponding to a first part of chip units on the wafer and second local test data corresponding to a second part of chip units, wherein the first local test data is test data corresponding to a first test type, and the second local test data is test data corresponding to a second test type;

[0144] The data generation module 122 is configured to generate first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and to generate second global synthetic test data corresponding to all chip units on the wafer according to the second local test data;

[0145] The analysis module 123 is configured to perform a correlation analysis on the synthetic test data of the first test type and the second test type of the wafer based on the first global synthetic test data and the second global synthetic test data.

[0146] In an embodiment of the present application, first global synthetic test data and second synthetic global test data corresponding to different test types on the same wafer can be obtained based on first local test data and second local test data corresponding to different test types on the wafer, and correlation analysis of the synthetic test data of the first test type and the second test type of the wafer can be implemented through the first global synthetic test data and the second global synthetic test data.

[0147] Fig.13 A schematic diagram of the hardware structure of a computer device provided in an embodiment of the present application.

[0148] like Fig.13 The computer device shown may include a processor 1301 and a memory 1302 storing computer program instructions.

[0149] Specifically, the processor 1301 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.

[0150] The memory 1302 may include a large capacity memory for data or instructions. By way of example and not limitation, the memory 1302 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive or a combination of two or more of these. In appropriate cases, the memory 1302 may include a removable or non-removable (or fixed) medium. In appropriate cases, the memory 1302 may be inside or outside the integrated gateway disaster recovery device. In a specific embodiment, the memory 1302 is a non-volatile solid-state memory.

[0151] In certain embodiments, memory 1302 includes read-only memory (ROM). The ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), an electrically alterable ROM (EAROM), or flash memory, or a combination of two or more of the above, where appropriate.

[0152] The memory may include read-only memory (ROM), random access memory (RAM), magnetic disk storage media devices, optical storage media devices, flash memory devices, electrical, optical or other physical / tangible memory storage devices. Thus, typically, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., memory devices) encoded with software including computer-executable instructions, and when the software is executed (e.g., by one or more processors), it is operable to perform the operations described with reference to the method according to an aspect of the present disclosure.

[0153] The processor 1301 implements any one of the wafer test data processing methods in the above embodiments by reading and executing computer program instructions stored in the memory 1302 .

[0154] In one example, the computer device may further include a communication interface 1303 and a bus 1310. Fig.13 As shown, the processor 1301, the memory 1302, and the communication interface 1303 are connected via a bus 1310 and communicate with each other.

[0155] The communication interface 1303 is mainly used to implement communication between various modules, devices, units and / or equipment in the embodiments of the present application.

[0156] Bus 1310 includes hardware, software or both, and the parts of online data flow billing equipment are coupled to each other. For example, but not limitation, bus may include accelerated graphics port (AGP) or other graphics bus, enhanced industrial standard architecture (EISA) bus, front-end bus (FSB), hypertransport (HT) interconnection, industrial standard architecture (ISA) bus, infinite bandwidth interconnection, low pin count (LPC) bus, memory bus, micro channel architecture (MCA) bus, peripheral component interconnection (PCI) bus, PCI-Express (PCI-X) bus, serial advanced technology attachment (SATA) bus, video electronics standard association local (VLB) bus or other suitable bus or two or more of these combinations. In appropriate cases, bus 1310 may include one or more buses. Although the present application embodiment describes and shows a specific bus, the application considers any suitable bus or interconnection.

[0157] The computer device can execute the wafer test data processing method in the embodiment of the present application based on the wafer test data.

[0158] In addition, in combination with the wafer test data processing method in the above embodiment, the embodiment of the present application can provide a computer storage medium for implementation. The computer storage medium stores computer program instructions; when the computer program instructions are executed by the processor, any locomotive reconnection method in the above embodiment is implemented.

[0159] In addition, in combination with the wafer test data processing method in the above embodiment, the present application embodiment can provide a computer program product to implement. When the instructions in the computer program product are executed by the processor of the electronic device, the electronic device executes any one of the wafer test data processing methods in the above embodiment.

[0160] It should be clear that the present application is not limited to the specific configuration and processing described above and shown in the figures. For the sake of simplicity, a detailed description of the known method is omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method process of the present application is not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between the steps after understanding the spirit of the present application.

[0161] The functional blocks shown in the above-described block diagram can be implemented as hardware, software, firmware or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application specific integrated circuit (ASIC), appropriate firmware, a plug-in, a function card, etc. When implemented in software, the elements of the present application are programs or code segments that are used to perform the required tasks. The program or code segment can be stored in a machine-readable medium, or transmitted on a transmission medium or a communication link by a data signal carried in a carrier wave. "Machine-readable medium" can include any medium capable of storing or transmitting information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, optical fiber media, radio frequency (RF) links, etc. The code segment can be downloaded via a computer network such as the Internet, an intranet, etc.

[0162] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.

[0163] Aspects of the present disclosure are described above with reference to the flowchart and / or block diagram of the method, device (system) and computer program product according to the embodiment of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine so that these instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the function / action specified in one or more boxes of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field programmable logic circuit. It can also be understood that each box in the block diagram and / or flowchart and the combination of boxes in the block diagram and / or flowchart can also be implemented by dedicated hardware that performs a specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0164] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. A wafer test data processing method, characterized in that: include: Acquire first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units, wherein the first local test data is test data corresponding to a first test type, and the second local test data is test data corresponding to a second test type; Generate first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generate second global synthetic test data corresponding to all chip units on the wafer according to the second local test data; Based on the first global synthetic test data and the second global synthetic test data, correlation analysis is performed on synthetic test data of the first test type and the second test type of the wafer.

2. The method according to claim 1, characterized in that The step of generating first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on the wafer according to the second local test data, comprises: The first local test data is interpolated using a spatial interpolation method to generate first global synthetic test data corresponding to all chip units on the wafer, and the second local test data is interpolated using a spatial interpolation method to generate second global synthetic test data corresponding to all chip units on the wafer.

3. The method according to claim 1, characterized in that The step of generating first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on the wafer according to the second local test data, comprises: Inputting the first local test data into a test data generation model to generate the first global synthetic test data; The second local test data is input into a test data generation model to generate the second global synthetic test data.

4. The method according to claim 3, characterized in that The test data generation model is obtained by training based on a generative adversarial network model, wherein the generative adversarial network model includes a first generator and a first discriminator; Before generating first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and generating second global synthetic test data corresponding to all chip units on the wafer according to the second local test data, the method further includes: Acquire first global test data corresponding to all chip units on the wafer; Acquire third local test data corresponding to some chip units from the first global test data; Interpolating the third local test data using a spatial interpolation method to generate first interpolated global test data corresponding to all chip units on the wafer; Inputting the first interpolated global test data into a first generator to obtain first predicted global test data; Inputting the first predicted global test data and the first global test data into a first discriminator to obtain a first discriminant result; When the first discrimination result does not meet the preset training stop condition, the model parameters of the first generator and the first discriminator are adjusted according to the first predicted global test data, the first discrimination result and the first global test data to obtain an updated generative adversarial network model, and the first interpolated global test data is returned to the first generator to obtain the first predicted global test data, until the first discrimination result meets the preset training stop condition.

5. The method according to claim 4, characterized in that The first generator includes an encoder, a residual network layer and a decoder; The step of inputting the first interpolated global test data into a first generator to obtain first predicted global test data comprises: Inputting the first interpolated global test data into the encoder to perform feature extraction on the first interpolated global test data to obtain first test data features; Mapping the first test data feature through the residual network layer to obtain a second test data feature; The decoder performs deconvolution processing on the second test data feature to obtain the first predicted global test data.

6. The method according to claim 4, characterized in that The method of adjusting the model parameters of the first generator and the first discriminator according to the first predicted global test data, the first discrimination result and the first global test data to obtain an updated generative adversarial network model includes: Perform loss calculation according to the first discrimination result and the target loss function to obtain a first generator loss and a discriminator loss; Adjusting the model parameters of the first discriminator by discriminator loss; Performing similarity calculation on the first predicted global test data and the first global test data by using a similarity function to obtain a second generator loss; Performing a weighted summation on the first generator loss and the second generator loss to obtain a third generator loss; The model parameters of the first generator are adjusted through the third generator loss.

7. The method according to claim 4, characterized in that The generative adversarial network model further includes a second generator and a second discriminator, the size of the second generator input data is smaller than the size of the first generator input data, and the size of the second discriminator input data is smaller than the size of the second discriminator input data; said inputting the first interpolated global test data into a first generator to obtain first predicted global test data; Inputting the first predicted global test data and the first global test data into a first discriminator to obtain a first discrimination result includes: Downsampling the first interpolated global test data to obtain first sampled data, and downsampling the first global test data to obtain second sampled data; Inputting the first sample data into the second generator to obtain second predicted global test data; Inputting the second predicted global test data and the second sampled data into the second discriminator to obtain a second discrimination result; In the case where the second discrimination result does not meet the training stop condition, adjusting the model parameters of the second generator and the second discriminator according to the second predicted global test data, the second discrimination result, and the second sampled data, and returning to the step of inputting the first sampled data into the second generator to obtain the second predicted global test data, until the second discrimination result meets the training stop condition, and outputting the second predicted global test data whose second discrimination result meets the training stop condition; Performing feature extraction on the first interpolation global test data by a first generator to obtain third test data features; Performing bitwise summation of the second predicted global test data output by the second generator and the third test data feature to obtain a fourth test data feature; The first generator sequentially performs mapping processing and deconvolution processing on the fourth test data feature to obtain first predicted global test data; The first predicted global test data and the first global test data are input into the first discriminator to obtain the first discriminant result.

8. A wafer test data processing device, characterized in that: include: A data acquisition module is configured to acquire first local test data corresponding to a first part of chip units on a wafer and second local test data corresponding to a second part of chip units, wherein the first local test data is test data corresponding to a first test type, and the second local test data is test data corresponding to a second test type; A data generation module is configured to generate first global synthetic test data corresponding to all chip units on the wafer according to the first local test data, and to generate second global synthetic test data corresponding to all chip units on the wafer according to the second local test data; The analysis module is configured to perform a correlation analysis on the synthetic test data of the first test type and the second test type of the wafer based on the first global synthetic test data and the second global synthetic test data.

9. A computer device, characterized in that: include: at least one processor; as well as A memory storing a computer program executable on the processor, wherein the processor executes the steps of the method according to any one of claims 1 to 7 when executing the program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are performed.

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