Electronic fuse device, method for electronic fuse device and computing equipment

Abstract

The invention provides an electronic fuse device, a method for the electronic fuse device and computing equipment, the electronic fuse device comprises a plurality of electronic fuses, a plurality of register blocks and a selection output module, each electronic fuse is connected to the selection output module through a single register block, and the register blocks are connected to the selection output module through a single register block. The data in each electronic fuse comprises data information and verification information of the data information obtained by applying a specific verification algorithm; the register block receives data in the connected electronic fuse and transmits the data to the selection output module; and the selection output module receives the data from the register block, performs automatic selection and comparison in the selection output module, and finally outputs correct data to the outside. According to the technical scheme provided by the invention, correct eFuse data can be automatically selected and output, and an error prompt is given to the outside under the condition that all the output data of the eFuse have errors.

Description

Technical Field

[0001] The present invention relates to the field of chip storage technology, and in particular to an electronic fuse device and a method and a computing device used for the electronic fuse device. Background Art

[0002] Electronic fuses (eFuse: electrical fuse) store information based on the principle of blowing a micro fuse through an electric current. When the current passing through the eFuse exceeds the threshold value, the fuse will be permanently blown, thereby changing its electrical characteristics. This change can be detected and used to represent a binary "0" or "1". After the fuse is blown, the information will be permanently saved, even after power failure, which is particularly suitable for storing important configuration information and encryption keys. The storage capacity of eFuse is generally calculated in bits, and each storage bit has a corresponding address, like a regular memory. If eFuse is used, the chip will generally read out the preset information when it starts, and decide how to run the chip based on this information. Each storage bit of eFuse only supports one write operation (fusing, burning and writing have the same meaning in this article). For example, the default storage is 0. Once it is written to 1, this bit can no longer be written to 0 and can only be 1 forever.

[0003] Since each eFuse bit can only be written once, an abnormality may cause the chip to be scrapped, and there are also yield and reliability issues. Therefore, eFuse vendors usually recommend using a double bit design, that is, placing 1 main eFuse and 1 backup eFuse, the two eFuses have the same capacity, or placing an eFuse with twice the capacity (which is equivalent to 1 main eFuse and 1 backup eFuse when separated). When writing eFuse, the same information will be written to the main and backup eFuse to avoid failure of only using a single eFuse. See Figure 1 The figure shows a typical application recommended by the eFuse vendor. The figure includes two eFuses, namely eFuse 0 and eFuse 1, both of which have read-write interfaces. Writing to the read-write interface can change the storage content in the eFuse, and reading from the read-write interface can make the eFuse output the storage content. Among them, Q0 and Q1 are the outputs of eFuse 0 and eFuse1 respectively, which are usually multi-bit signals. When reading eFuse 0, the information stored in eFuse 0 is output from Q0, and the same is true for eFuse 1 / Q1. For ease of understanding, assume Figure 1Q0 in the chip has only 1 bit. If Q0 should output 1 after eFuse 0 is written, but due to an error (maybe it is not written correctly, or the eFuse output is abnormal), Q0 outputs 0, while Q1 can normally output 1. After the two are ORed, the final output Q is still 1. Although eFuse0 outputs an error, eFuse 1 outputs correctly, and the chip can still work normally.

[0004] Although the current double bit design is useful, it still has shortcomings. Assume that the eFuse stores 0 by default and stores 1 after writing. Then the disadvantage of the double bit design is that it is only effective for situations where 1 cannot be output, and is invalid for situations where 0 cannot be output. For example, when a certain bit of an eFuse abnormally outputs 0, and the bit at the same position of another eFuse can output 1, the final output is still 1, which reflects the effect of the double bit design. However, if a certain bit abnormally outputs 1, the final output must be 1 instead of 0. Without any error prompt, the wrong data is output, and the design effect is not achieved.

[0005] Therefore, a technical solution is needed that can automatically select and output the correct eFuse data and issue an error prompt when all the eFuse output data are wrong. Summary of the invention

[0006] The present invention aims to provide an electronic fuse device and a method and a computing device for the electronic fuse device, which can automatically select and output correct eFuse data and issue an error prompt to the outside when all the output data of the eFuse are wrong.

[0007] According to one aspect of the present invention, an electronic fuse device is provided, comprising: a plurality of electronic fuses, a plurality of register groups and a selection output module, wherein:

[0008] Each of the electronic fuses is connected to the selection output module via a single register group, and the data in each of the electronic fuses includes: data information and verification information of the data information obtained by applying a verification algorithm;

[0009] The register group receives data from the electronic fuse and transmits the data to the selection output module;

[0010] The selection output module receives data from the register group and performs automatic selection comparison inside the selection output module to output correct data externally.

[0011] According to some embodiments, the selection output module includes: an automatic selection unit, a verification calculation unit, and a comparison output unit, wherein:

[0012] The automatic selection unit receives a first control signal from the comparison output unit, and outputs the data read from the single electronic fuse to the verification calculation unit according to the first control signal;

[0013] The verification calculation unit receives the data from the automatic selection unit, applies the verification algorithm to verify the data information in the data, first calculates the verification calculation result, and outputs the verification calculation result and the verification information to the comparison output unit;

[0014] The comparison output unit receives and compares the verification calculation result and the verification information, and outputs the first control signal to the automatic selection unit and outputs the data information or error status prompt to the outside according to the comparison result.

[0015] According to some embodiments, the automatic selection unit includes: a multiplexer, which receives data from the register group and a first control signal from the comparison output unit, and sequentially selects data from a single register group to transmit to the comparison output unit according to the first control signal.

[0016] According to some embodiments, each register group includes two registers, one storing the data information and the other storing the check information.

[0017] According to some embodiments, the verification calculation unit is configured to:

[0018] The data from the automatic selection unit is restored into the data information and the verification information.

[0019] Apply the verification algorithm to the data information to obtain a verification calculation result;

[0020] Output the verification calculation result and the verification information to the comparison output unit.

[0021] According to some embodiments, the comparison output unit is configured as:

[0022] receiving the verification calculation result and the verification information from the verification calculation unit;

[0023] The verification calculation result and the verification information are compared, and if the two are equal, the current electronic fuse is output normally.

[0024] According to some embodiments, the comparison output unit is further configured to:

[0025] The verification calculation result and the verification information are compared, and if the two are not equal, it is determined whether the comparison of all register groups is completed.

[0026] If it is determined that the comparison is not completed, outputting a first control signal to the automatic selection unit so that the automatic selection unit reads the encrypted data of the next register group and performs the comparison of the next register group;

[0027] If the comparison is determined to be complete, an error status indication is output.

[0028] According to one aspect of the present invention, there is provided a method for an electronic fuse device as described in any one of the above, comprising:

[0029] Select a verification algorithm suitable for the chip and agree on the storage format;

[0030] Applying the verification algorithm to obtain verification information of the data information to be written;

[0031] The data information and the corresponding verification information are stored in the same electronic fuse according to the agreed storage format, and written into all electronic fuses.

[0032] According to one aspect of the present invention, there is provided an integrated circuit chip, characterized in that it comprises the electronic fuse device as described in any one of the above items.

[0033] According to one aspect of the present invention, there is provided an electronic device, characterized in that it comprises the integrated circuit chip as described above.

[0034] According to another aspect of the present invention, there is provided a computing device, comprising:

[0035] Processor; and

[0036] A memory storing a computer program, which, when executed by the processor, enables the processor to execute any of the methods described above.

[0037] According to another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having computer-readable instructions stored thereon, and when the instructions are executed by a processor, the processor is caused to execute any of the above methods.

[0038] According to an embodiment of the present invention, a register is used to store the data in the electronic fuse, and the data is transmitted to the selection output module. Inside the selection output module, the data in the electronic fuse is restored to data information and the verification information, and then the original verification algorithm is applied to perform verification calculation on the data information to obtain the verification calculation result, and automatic selection and comparison are performed inside the selection output module, and correct data is output externally. The method of the present invention replaces the design of two-phase data comparison in the dual-bit design in the prior art, avoids the design shortcoming of two sets of data errors in the dual-bit design without knowing it, realizes the automatic selection and output of multiple electronic fuses, and improves the accuracy and safety of electronic fuse data.

[0039] It is to be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0041] Figure 1 A schematic diagram of a commonly used dual-bit eFuse design according to an example embodiment is shown.

[0042] Figure 2 A schematic diagram of an electronic fuse device architecture according to an example embodiment is shown.

[0043] Figure 3 A schematic diagram of a selection output module architecture of an electronic fuse device according to an example embodiment is shown.

[0044] Figure 4 A schematic diagram of an electronic fuse device architecture according to another example embodiment is shown.

[0045] Figure 5 A method flow chart for the electronic fuse device according to an example embodiment is shown.

[0046] Figure 6 A schematic diagram showing a storage format of a method for the electronic fuse device according to an example embodiment.

[0047] Figure 7 A schematic diagram of an electronic fuse device and an application method according to an example embodiment is shown.

[0048] Figure 8 A block diagram of a computing device is shown according to an exemplary embodiment. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present invention will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.

[0050] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0051] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0052] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0053] It should be understood that although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another component. Therefore, the first component discussed below can be referred to as the second component without departing from the teachings of the present inventive concept. As used herein, the term "and / or" includes any one of the associated listed items and all combinations of one or more.

[0054] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in the present invention are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0055] Those skilled in the art will appreciate that the drawings are merely schematic diagrams of example embodiments, and the modules or processes in the drawings are not necessarily necessary for implementing the present invention, and therefore cannot be used to limit the protection scope of the present invention.

[0056] Although the current double bit design is useful, it still has shortcomings. Assume that the eFuse stores 0 by default and stores 1 after writing. Then the disadvantage of the double bit design is that it is only effective for situations where 1 cannot be output, and is invalid for situations where 0 cannot be output. For example, when a certain bit of an eFuse abnormally outputs 0, and the bit at the same position of another eFuse can output 1, the final output is still 1, which reflects the effect of the double bit design. However, if a certain bit abnormally outputs 1, the final output must be 1 instead of 0. Without any error prompt, the wrong data is output, and the design effect is not achieved.

[0057] To this end, the present invention proposes an electronic fuse device and a method and computing device for the electronic fuse device, which can automatically select and output the correct eFuse data, and issue an error prompt to the outside when all the output data of the eFuse are wrong. According to the embodiment, the verification information of the data to be written is obtained by selecting the verification algorithm of the appropriate chip, and stored in accordance with the agreed storage format, and the data information to be written is processed and written into the efuse, which is convenient for subsequent automatic reading and judgment. The data in the efuse is read and restored into two parts: the verification information and the original data information, and the verification calculation result is obtained by using the selected algorithm, and the verification calculation result is automatically compared with the verification information, and then it is judged whether the data in the current efuse is correct, which replaces the design of two-phase data comparison in the dual-bit design in the prior art, avoids the design shortcomings of the two sets of data errors in the dual-bit design without knowing it, and improves the accuracy and security of the efuse data.

[0058] Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

[0059] Figure 2 A schematic diagram of an electronic fuse device architecture according to an example embodiment is shown.

[0060] See also Figure 2 According to an example embodiment, an electronic fuse device includes: a plurality of electronic fuses, a plurality of register groups, and a selection output module, wherein each of the electronic fuses is connected to the selection output module through a single register group, and the data in each of the electronic fuses includes: data information and verification information of the data information obtained by applying a specific verification algorithm. The register group receives the data in the connected electronic fuses and transmits the data to the selection output module.

[0061] According to some embodiments, each eFuse is used to store a piece of data information and verification information of the data information. The multiple register groups are used to store data read from the eFuse and transmit the data to the selection output module. Among them, each register group contains at least two registers, one for storing data information and the other for storing verification information, and the number of register groups matches the number of eFuse. That is to say, during the eFuse writing, in addition to writing regular data information, an additional piece of verification information is also written. For example, assuming that the eFuse capacity is 512-bit, let the data information occupy the first 384-bit of the capacity, and the verification information occupies the remaining 128-bit. Before writing the eFuse, select a verification algorithm suitable for chip implementation, use this algorithm to perform verification calculations on the 384-bit data information, obtain 128-bit verification information, and then write the data information and verification information into the eFuse according to the agreed storage format.

[0062] According to some embodiments, the selection output module receives data from the register group, and automatically selects and compares it inside the selection output module, and finally outputs the correct data to the outside. The selection output module automatically compares the data information and the verification information in each register group to determine which data in the eFuse is correct, and finally outputs the correct data information.

[0063] According to some embodiments, during the eFuse burning process, the data information to be written and the verification information obtained by applying a specific verification algorithm are written into each eFuse. When the chip is powered on, the data information and verification information in each eFuse are read and stored in the corresponding register group. The output selection module reads the data information and verification information from each register group. The verification value of the data information is recalculated using the same verification algorithm. The calculated verification value is compared with the verification information stored in the verification information register. If the verification is successful, it means that the data in the eFuse is correct; if it fails, it means that the data may be damaged or the verification information is incorrect. The output selection module automatically selects the correct data information and uses it as the final output.

[0064] According to some embodiments, the electronic fuse device ensures data integrity and reliability by using multiple eFuse and register groups, and selecting output modules. By automatically comparing the check information and data information, the device can select the correct data output among multiple eFuse units, and can ensure the validity of the data even if some eFuse units fail. The solution of the present invention can be widely used in application scenarios with strict requirements on data integrity, such as automotive electronics, aerospace and other fields.

[0065] Figure 3 A schematic diagram of a selection output module architecture of an electronic fuse device according to an example embodiment is shown.

[0066] See also Figure 3 According to the exemplary embodiment, the selection output module includes: an automatic selection unit 01, a verification calculation unit 03, and a comparison output unit 05.

[0067] According to some embodiments, the automatic selection unit receives a first control signal from the comparison output unit, and outputs the data in the read single electronic fuse to the verification calculation unit according to the first control signal. Receive a first control signal from the comparison output unit. According to the first control signal, select the data of an electronic fuse (including data information and verification information) from the register group, and output the data of the selected electronic fuse to the verification calculation unit.

[0068] According to some embodiments, the verification calculation unit receives data from the automatic selection unit, applies the specific verification algorithm to verify the data information in the data to obtain a verification calculation result, and outputs the verification calculation result and the verification information to the comparison output unit.

[0069] According to some embodiments, the comparison output unit receives and compares the verification calculation result and the verification information, and outputs the first control signal to the automatic selection unit and outputs the data information or error status prompt to the outside according to the comparison result. If the two are equal, it means that the data information is correct, and the first control signal is output to the automatic selection unit to indicate the selection of the correct data information. If the two are not equal, it means that the data information is wrong, and the first control signal is output to the automatic selection unit to indicate the selection of the data of the next electronic fuse, and an error status prompt is output. If the data of all electronic fuses fails to pass the verification, an error status prompt is output.

[0070] According to some embodiments, the design of the present invention ensures that only verified data information is output, thereby improving the reliability and security of the system. By using a verification algorithm to verify the integrity of the data information, even if some electronic fuses fail, it can ensure that correct data can be output.

[0071] Figure 4 A schematic diagram of an electronic fuse device architecture according to another example embodiment is shown.

[0072] See also Figure 4According to an example embodiment of an electronic fuse device architecture, the automatic selection unit includes: a multiplexer, which receives data from the register group and a first control signal from the comparison output unit, and sequentially selects data from a single register group to transmit to the comparison output unit according to the first control signal.

[0073] According to some embodiments, the automatic selection unit selects and outputs the data in a single register group to the verification calculation unit according to the first control signal from the comparison output unit. Specifically, the multiplexer is in a standby state, waiting for the first control signal. After receiving the first control signal, a register group is selected according to the signal indication, and the data (data information and verification information) in the selected register group is transmitted to the verification calculation unit. If the first control signal indicates to continue to select the next register group, the above process is repeated.

[0074] According to some embodiments, the verification calculation unit is configured to: restore the data from the automatic selection unit to the data information and the verification information; apply the verification algorithm to the data information to obtain a verification calculation result; and output the verification calculation result and the verification information to the comparison output unit.

[0075] According to some embodiments, the verification calculation unit includes a data reading subunit, a verification information reading subunit, and a verification calculation subunit, see Figure 4 After starting the chip, the register groups 0 and 1 read out the information of eFuse 0 and eFuse 1 respectively, and store them in the register groups 0 (register group 0) and 1 (register group 1) respectively. Obviously, each register group (register group) contains the data information and verification information of its own eFuse. The device configures the multiplexer to select register group 0 output by default first, and divides registergroup 0 into a register data part and a register check part according to the agreed storage format. The data information stored in the register group is read by the data reading subunit and the data information is input into the verification calculation subunit for verification calculation, and then the obtained verification calculation result is sent to the comparison output unit. The verification information in the register group is read by the verification information reading subunit and input into the comparison output unit.

[0076] According to some embodiments, the comparison output unit is configured to: receive the verification calculation result and the verification information from the verification calculation unit; compare the verification calculation result and the verification information, and output the current electronic fuse normally if the two are equal. Figure 4 , perform verification calculation on register data, the verification calculation adopts the same verification method for generating verification information to obtain the verification calculation result, compare the verification calculation result with the register check, that is, compare the verification calculation result with the verification information part stored in efuse, if the two are consistent, it is considered that eFuse0 is normal, and the register data of eFuse 0 is output through Q.

[0077] According to some embodiments, the comparison output unit is further configured to: compare the verification calculation result and the verification information, and if the two are not equal, determine whether the comparison of all register groups is completed. If it is determined that the comparison is not completed, output a first control signal to the automatic selection unit so that the automatic selection unit reads the encrypted data of the next register group and compares the next register group. Compare the verification calculation result and register check, if the two are inconsistent, it is considered that eFuse 0 is abnormal. Determine whether the comparison of all register groups is completed. If it is determined that the comparison is not completed, the comparison output unit outputs a first control signal so that the selector selects register group 1 output, that is, controls the automatic selection unit to input the data of the next register group, and performs the next verification, and re-separates the group, verifies the calculation and compares. If the comparison is consistent, it is considered that eFuse1 is normal, and the register data of eFuse 1 is output through Q, otherwise it is considered that eFuse 1 is abnormal.

[0078] According to some embodiments, the comparison output unit is further configured to output an error indication if it is determined that the comparison is completed.

[0079] If both eFuse 0 and eFuse 1 are abnormal, and the comparison output unit determines that the comparison of all register groups has been completed at this time, the status is made to output an abnormal indication signal to notify the outside of the eFuse system that Q is wrong at this time and cannot be used.

[0080] Figure 5 A method flow chart for the electronic fuse device according to an example embodiment is shown.

[0081] See also Figure 5 , according to an example embodiment, a method for the electronic fuse device includes:

[0082] In S501, a verification algorithm suitable for the chip is selected and a storage format is agreed upon.

[0083] According to some embodiments, the computing resources available to the chip are determined, including processor speed, memory size, etc. A verification algorithm is selected that matches the chip performance to ensure that the verification algorithm can run efficiently.

[0084] According to some embodiments, different verification algorithms can be selected according to different application scenario requirements. Generally speaking, algorithms with lower complexity can reduce computing time and power consumption. The longer the verification code, the stronger the ability to detect errors, but it also takes up more storage space. Select algorithms that are easy to implement to reduce development cycle and cost. Consider the degree of standardization of the algorithm, as standardized algorithms are usually easier to integrate. Ensure that the selected algorithm is compatible with other system components, such as processor architecture, compiler support, etc.

[0085] Figure 6 A schematic diagram showing a storage format of a method for the electronic fuse device according to an example embodiment.

[0086] According to some embodiments, the storage format is agreed upon to determine the order in which the data information and the verification information are arranged. Figure 6 , assuming that the eFuse capacity is 512 bits, the write addresses are distributed from 0 to 511, and each write address stores 1 bit of information. Write addresses 0 to 383 store data information, and write addresses 384 to 511 store check information. See Figure 4 In the example above, the registerdata is the blue part of the above picture, and the register check is the green part of the above picture.

[0087] In S503, the verification algorithm is applied to obtain verification information of the data information to be written.

[0088] According to some embodiments, a selected verification algorithm is used to perform verification calculations on the data information to be written to obtain verification information, which will be stored together with the data information.

[0089] In S505, the data information and the corresponding verification information are stored in the same electronic fuse according to an agreed storage format, and written into all electronic fuses.

[0090] According to some embodiments, data information and check information are stored in the same eFuse in an agreed storage format, and this process is performed for all eFuses to ensure redundancy and data integrity.

[0091] At S507 , the data in all the electronic fuses are read into a plurality of register groups.

[0092] According to some embodiments, when the chip is powered on, data information and verification information are read from all eFuses, and the read data is stored in a plurality of register groups, wherein each register group corresponds to an eFuse.

[0093] In S509, the data in a single register group is restored into the data information and the verification information according to the agreed storage format, wherein each register group includes two registers, one for storing the data information and the other for storing the verification information.

[0094] According to some embodiments, data information and verification information are extracted from the register group. According to the agreed storage format, the data in a single register group is restored to data information and verification information, which are stored in two registers of each register group, one for storing data information and the other for storing verification information.

[0095] In S511, the data information is verified using the verification algorithm to obtain a verification calculation result.

[0096] According to some embodiments, a selected check algorithm is used to perform check calculations on the data information extracted from the register group to obtain a check calculation result.

[0097] In S513, the verification calculation result and the verification information are compared, and if the two are equal, the data in the current electronic fuse is output normally.

[0098] According to some embodiments, the checksum calculation result is compared with the checksum information extracted from the register group. If the two are equal, it is considered that the data information in the eFuse is correct. If the two are not equal, it is considered that the data information in the eFuse may have been damaged or tampered with.

[0099] According to some embodiments, the method further includes: comparing the verification calculation result and the verification information, and if the two are not equal, determining whether the comparison of all register groups is completed; if it is determined that the comparison is not completed, performing the comparison of the next register group, and if it is determined that the comparison is completed, outputting an error status indication.

[0100] Figure 7 A schematic diagram of an electronic fuse device and an application method according to an example embodiment is shown.

[0101] See also Figure 7 According to an example embodiment, an electronic fuse device and an application method are provided. First, according to the difficulty of implementation, resource limitation, etc., a verification algorithm suitable for a chip is selected. Assume that algorithm A is selected. Algorithm A is used to calculate the data information to be written into the eFuse to obtain verification information. The data information and verification information are written into all eFuses according to the agreed storage format. In order to restore the data information and verification information in the chip, the storage format must be agreed upon.

[0102] After the chip is powered on, the data information and verification information of all eFuse are read out and stored in multiple register groups. In the output selection module, the data information and verification information of a register group are restored according to the agreed storage format, which is equivalent to dividing a register group into two registers, one for storing data information and the other for storing verification information. The data information stored in the register group is input into the verification calculation unit and calculated using algorithm A. The calculation result of the verification calculation unit is compared with the verification information stored in the register. If the two are equal, it means that the eFuse output is normal. At this time, the data information stored in the register can be used as the final output of the eFuse system for the chip to use, and a correct status indication is given. Otherwise, it is determined whether all register groups are compared. If it is, it means that all eFuse outputs are wrong. At this time, the final output of the eFuse system is unavailable, and an error status indication is given. Otherwise, the next register group is selected to continue the verification calculation step.

[0103] According to some embodiments, the scheme of the present invention stores data information and corresponding verification information in the eFuse by applying a specific verification algorithm and storage format, and then re-verifies and calculates the data information of the eFuse in the chip after reading the eFuse information, and determines whether the data information output by the eFuse is normal by comparing the verification calculation result with the verification information stored in the eFuse. If one eFuse fails to compare, switch to other eFuse and compare again. When a certain eFuse compares successfully, the correct data information is output on the final output interface. If all eFuses fail to compare, it means that all eFuses are abnormal.

[0104] According to some embodiments, only the data that has passed the verification will be output in the solution of the present invention, which replaces the design of two-phase data comparison in the dual-bit design in the prior art, avoids the design shortcoming of two sets of data errors in the dual-bit design without knowing it, and improves the accuracy and security of efuse data. By using a verification algorithm to verify the integrity of data information, even if some eFuse fails, it can ensure that the system can work normally, which can be widely used in applications that require high reliability.

[0105] Figure 8 A block diagram of a computing device according to an example embodiment of the invention is shown.

[0106] like Figure 8 As shown, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include bus 22, network interface 16, and I / O interface 18. Processor 12, memory 14, network interface 16, and I / O interface 18 may communicate with each other via bus 22.

[0107] The processor 12 may include one or more general-purpose CPUs (Central Processing Units, processors), microprocessors, or application-specific integrated circuits, etc., for executing relevant program instructions. According to some embodiments, the computing device 30 may also include a high-performance graphics card (GPU) 20 for accelerating the processor 12.

[0108] The memory 14 may include a machine system readable medium in the form of a volatile memory, such as a random access memory (RAM), a read-only memory (ROM) and / or a cache memory. The memory 14 is used to store one or more programs including instructions and data. The processor 12 can read the instructions stored in the memory 14 to execute the above-mentioned method according to the embodiment of the present invention.

[0109] The computing device 30 may also communicate with one or more networks via the network interface 16. The network interface 16 may be a wireless network interface.

[0110] The bus 22 may include an address bus, a data bus, a control bus, etc. The bus 22 provides a path for exchanging information between components.

[0111] It should be noted that, in the specific implementation process, the computing device 30 may also include other components necessary for normal operation. In addition, those skilled in the art may understand that the above device may only include components necessary for implementing the embodiments of this specification, and need not include all components shown in the figure.

[0112] The present invention also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor. The computer-readable storage medium may include, but is not limited to, any type of disk, including a floppy disk, an optical disk, a DVD, a CD-ROM, a microdrive, and a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a DRAM, a VRAM, a flash memory device, a magnetic card or an optical card, a nanosystem (including a molecular memory IC), a network storage device, a cloud storage device, or any type of medium or device suitable for storing instructions and / or data.

[0113] An embodiment of the present invention also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute part or all of the steps of any method recorded in the above method embodiments.

[0114] Those skilled in the art can clearly understand that the technical solution of the present invention can be implemented with the help of software and / or hardware. "Unit" and "module" in this specification refer to software and / or hardware that can independently complete or cooperate with other components to complete specific functions, where the hardware can be, for example, a field programmable gate array, an integrated circuit, etc.

[0115] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should know that the present invention is not limited by the described order of actions, because according to the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0116] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0117] In the several embodiments provided by the present invention, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some service interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

[0118] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0119] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0120] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product, which is stored in a memory and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention.

[0121] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0122] The exemplary embodiments of the present invention are specifically shown and described above. It should be understood that the present invention is not limited to the detailed structures, configurations or implementations described herein; on the contrary, the present invention is intended to cover various modifications and equivalent configurations included in the spirit and scope of the appended clauses.

Claims

1. An electronic fuse device, characterized in that: include: A plurality of electronic fuses, a plurality of register groups, and a selection output module, wherein: Each of the electronic fuses is connected to the selection output module via a single register group, and the data in each of the electronic fuses includes: data information and verification information of the data information obtained by applying a verification algorithm; The register group receives data from the electronic fuse and transmits the data to the selection output module; The selection output module receives data from the register group and performs automatic selection comparison inside the selection output module to output correct data externally.

2. The electronic fuse device according to claim 2, characterized in that: The selection output module includes: an automatic selection unit, a verification calculation unit, and a comparison output unit, wherein: The automatic selection unit receives a first control signal from the comparison output unit, and outputs the data read from the single electronic fuse to the verification calculation unit according to the first control signal; The verification calculation unit receives the data from the automatic selection unit, applies the verification algorithm to verify the data information in the data, first calculates the verification calculation result, and outputs the verification calculation result and the verification information to the comparison output unit; The comparison output unit receives and compares the verification calculation result and the verification information, and outputs the first control signal to the automatic selection unit and outputs the data information or error status prompt to the outside according to the comparison result.

3. The electronic fuse device according to claim 2, characterized in that: The automatic selection unit includes: a multiplexer, which receives data from the register group and a first control signal from the comparison output unit, and sequentially selects data from a single register group according to the first control signal to transmit to the comparison output unit.

4. The electronic fuse device according to claim 2, characterized in that: The verification calculation unit is configured as follows: The data from the automatic selection unit is restored into the data information and the verification information. Apply the verification algorithm to the data information to obtain a verification calculation result; Output the verification calculation result and the verification information to the comparison output unit.

5. The electronic fuse device according to claim 4, characterized in that: Each register group includes two registers, one for storing the data information and the other for storing the check information.

6. The electronic fuse device according to claim 2, characterized in that: The comparison output unit is configured as follows: receiving the verification calculation result and the verification information from the verification calculation unit; The verification calculation result and the verification information are compared, and if the two are equal, the current electronic fuse is output normally.

7. The electronic fuse device according to claim 6, characterized in that: The comparison output unit is further configured as: The verification calculation result and the verification information are compared, and if the two are not equal, it is determined whether the comparison of all register groups is completed. If it is determined that the comparison is not completed, outputting a first control signal to the automatic selection unit so that the automatic selection unit reads the encrypted data of the next register group and performs the comparison of the next register group; If the comparison is determined to be complete, an error status indication is output.

8. A method for an electronic fuse device according to any one of claims 1 to 7, characterized in that: include: Select a verification algorithm suitable for the chip and agree on the storage format; Applying the verification algorithm to obtain verification information of the data information to be written; The data information and the corresponding verification information are stored in the same electronic fuse according to the agreed storage format, and written into all electronic fuses.

9. An integrated circuit chip, characterized in that: The invention comprises the electronic fuse device as claimed in any one of claims 1 to 7.

10. An electronic device, characterized in that: Comprising the integrated circuit chip as claimed in claim 8.

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