Preparation method of semiconductor device and semiconductor device
By combining plasma-enhanced chemical vapor deposition process and dry etching technology, an efficient and uniform insulating layer is formed, which solves the problem of high cost caused by slow preparation speed of oxide insulating layer, and achieves efficient preparation and cost reduction of semiconductor devices.
Patent Information
- Application Number
- CN202411447375.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-01-17
AI Technical Summary
In the prior art, the preparation speed of the oxide insulating layer is low, resulting in a high production cost, especially in the mass production stage, requiring a large amount of equipment investment, which increases the production cost of semiconductor devices.
The insulating material layer is formed by a plasma-enhanced chemical vapor deposition process, and thinned by dry-etching gas to form an insulating layer with uniform thickness, which improves the preparation efficiency and uniformity of the insulating layer.
It significantly improves the preparation speed and uniformity of the insulating layer, reduces the investment costs of equipment, and thus reduces the preparation cost of semiconductor devices, and improves its price competitiveness.
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Abstract
Description
Technical Field
[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a semiconductor device and a semiconductor device. Background Art
[0002] During the preparation process of some semiconductor devices, a groove structure is prepared, and an oxide insulating layer is prepared on the inner wall of the groove structure. In the prior art, the oxide insulating layer is prepared by an atomic layer deposition (ALD) process. Since the preparation speed of the oxide insulating layer prepared by the ALD process is very slow and the output per hour is low, a huge amount of equipment investment will be generated in the mass production stage, resulting in a high preparation cost of the oxide insulating layer. Summary of the invention
[0003] The purpose of the present application is to at least solve the problem that the preparation rate of the insulating layer is low and thus the preparation cost is high. This purpose is achieved through the following technical solutions:
[0004] The first aspect of the present application provides a method for preparing a semiconductor device, comprising:
[0005] Providing a semiconductor structure layer, the semiconductor structure layer comprising a first surface and a groove structure formed by depression of the first surface;
[0006] forming an insulating material layer on the first surface and the inner wall of the groove structure by using a plasma enhanced chemical vapor deposition process;
[0007] A dry etching gas is introduced from a side of the insulating material layer away from the semiconductor structure layer in a direction perpendicular to the first surface to thin at least a portion of the insulating material layer and form an insulating layer.
[0008] In the method for preparing a semiconductor device provided in the present application, a plasma enhanced chemical vapor deposition process is used to form an insulating material layer, and the film forming speed of the plasma enhanced chemical vapor deposition process is greater than the film forming speed of the atomic layer deposition (ALD) process, thereby improving the preparation speed of the insulating material layer. A dry etching gas is used to etch and thin the insulating material layer to form an insulating layer, and the dry etching gas is introduced from the side of the insulating material layer away from the semiconductor structure layer in a direction perpendicular to the first surface, and the dry etching gas contacts the portion of the insulating material layer located on the first surface, thereby thinning the portion of the insulating material layer located on the first surface, and the dry etching gas contacts the portion of the insulating material layer located at the opening of the groove structure, thereby thinning the portion of the insulating material layer located at the opening of the groove structure. Due to process limitations, when forming an insulating material layer, the thickness of the portion of the insulating material layer located on the first surface and the thickness of the portion located at the opening of the groove structure are both greater than the thickness of the portion located on the inner wall of the groove structure. The portion of the insulating material layer located on the first surface and the portion located at the opening of the groove structure can be thinned by dry etching gas to reduce the difference between the thickness of the portion of the insulating material layer located on the first surface and the portion located at the opening of the groove structure and the thickness of the portion of the insulating material layer located on the inner wall of the groove structure, thereby forming an insulating layer with better thickness uniformity. The dry etching process is used to dry-etch the insulating material layer at a faster rate. The use of the semiconductor device preparation method provided in the present application to prepare and form an insulating layer improves the preparation efficiency of the insulating layer and improves the thickness uniformity of the insulating layer.
[0009] The second aspect of the present application also provides a semiconductor device, which is prepared using any semiconductor device preparation method provided in the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0011] Figure 1 A flowchart schematically shows a method for preparing a semiconductor device according to an embodiment of the present application;
[0012] Figures 2 to 4 A schematic diagram of local film layer changes in a method for preparing a semiconductor device according to an embodiment of the present application is schematically shown.
[0013] The reference numerals are as follows:
[0014] 1. Semiconductor structure layer; 10. First surface; 11. Groove structure; 110. Opening; 2. Insulating material layer; 3. Insulating layer. DETAILED DESCRIPTION
[0015] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0016] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.
[0017] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.
[0018] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.
[0019] The inventors have found that in the manufacturing process of semiconductor devices, the quality of the oxide insulating layer is crucial to the performance of the device. Atomic layer deposition (ALD) technology is widely used in the preparation of oxide insulating layers because it can accurately control the thickness and uniformity of the film. The oxide insulating layer located on the inner wall of the groove structure in the semiconductor device is often prepared by atomic layer deposition (ALD) process. The ALD process achieves the growth of the film by injecting different reaction gases A and B in sequence. Although this layer-by-layer deposition method can provide extremely high precision, it also limits the growth rate of the film. In each cycle, only a very thin layer of material is deposited, which means that a large number of cycles are required to achieve the required film thickness. This low film growth rate directly leads to low productivity, especially in applications where thicker films need to be prepared. In large-scale production, in order to meet market demand, manufacturers need to add more ALD equipment to increase production. However, ALD equipment is usually expensive, which increases the equipment investment cost, making the cost of semiconductor devices higher, thereby causing the cost competitiveness of semiconductor devices to decline.
[0020] like Figure 1 As shown, according to an embodiment of the present application, a method for preparing a semiconductor device is proposed, comprising:
[0021] S200, such as Figure 2 As shown, a semiconductor structure layer 1 is provided. The semiconductor structure layer 1 includes a first surface 10 and a groove structure 11 formed by the first surface 10 being recessed.
[0022] Specifically, the groove structure 11 can adopt a shallow trench isolation structure. When multiple semiconductor devices are included, the electrical isolation between adjacent semiconductor devices can be achieved by forming a groove structure 11 on the semiconductor structure layer 1, thereby preventing current leakage and interference. The shallow trench isolation structure is particularly important for manufacturing high-density integrated circuits, which can effectively reduce the crosstalk between adjacent semiconductor devices and improve the overall performance of the integrated circuit. The groove structure 11 can also be designed as a vertically stacked channel of a logic device, a storage device, and a power device, so that the device can not only be expanded on a plane, but also can be stacked vertically, thereby realizing more functions in a limited space. This three-dimensional integration technology can significantly improve the integration of semiconductor devices, improve the performance and energy efficiency after integration, and reduce the space they occupy. The groove structure 11 can also include an interlayer interconnection contact hole structure, which is the key to achieving electrical connection between different film layers in a semiconductor device, and can achieve effective communication between different layers.
[0023] Specifically, the groove structure 11 is usually formed by photolithography mask etching technology, i.e., photolithography technology. Photolithography is a fine manufacturing process that uses photosensitive materials and light sources to transfer the pattern on the mask to the semiconductor structure layer 1. In this way, the desired groove structure 11 can be accurately formed on the surface of the semiconductor structure layer 1. This preparation process requires high-precision control to ensure the performance and reliability of the semiconductor device.
[0024] S400, such as Figure 3 As shown, the insulating material layer 2 is formed on the first surface 10 and the inner wall of the groove structure 11 by using a plasma enhanced chemical vapor deposition process.
[0025] Specifically, the plasma enhanced chemical vapor deposition (PECVD) process technology can deposit a uniform and high-quality insulating material layer at a relatively low temperature.
[0026] Specifically, the insulating material layer 2 is partially located on the first surface 10 and partially located on the inner wall of the groove structure 11, wherein the inner wall includes a side wall and a bottom wall, and the bottom wall is opposite to the opening 110 of the groove structure 11. The insulating material layer 2 can be located on the side wall, or the insulating material layer 2 is partially located on the side wall and partially located on the bottom wall.
[0027] S600, such as Figure 4 As shown, a dry etching gas is introduced from the side of the insulating material layer 2 facing away from the semiconductor structure layer 1 in a direction perpendicular to the first surface 10 to thin at least a portion of the insulating material layer 2 and form an insulating layer 3.
[0028] Specifically, the dry etching gas contacts the insulating material layer 2 and etches and thins the insulating material layer 2 .
[0029] In the method for preparing a semiconductor device provided in the present application, a plasma enhanced chemical vapor deposition process is used to form an insulating material layer 2. The film forming speed of the plasma enhanced chemical vapor deposition process is greater than the film forming speed of the atomic layer deposition (ALD) process, thereby improving the preparation speed of the insulating material layer 2. A dry etching gas is used to etch and thin the insulating material layer 2 to form an insulating layer 3. The dry etching gas is introduced from the side of the insulating material layer 2 away from the semiconductor structure layer 1 in a direction perpendicular to the first surface 10. The dry etching gas contacts the portion of the insulating material layer 2 located on the first surface 10, thereby thinning the portion of the insulating material layer 2 located on the first surface 10, and the dry etching gas contacts the portion of the insulating material layer 2 located at the opening 110 of the groove structure 11, thereby thinning the portion of the insulating material layer 2 located at the opening 110 of the groove structure 11. Due to process limitations, when forming the insulating material layer 2, the thickness of the portion of the insulating material layer 2 located on the first surface 10 and the thickness of the portion located at the opening 110 of the groove structure 11 are both greater than the thickness of the portion located on the inner wall of the groove structure 11. The portion of the insulating material layer 2 located on the first surface 10 and the portion located at the opening 110 of the groove structure 11 can be thinned by dry etching gas to reduce the difference between the thickness of the portion of the insulating material layer 2 located on the first surface 10 and the portion located at the opening 110 of the groove structure 11 and the thickness of the portion of the insulating material layer 2 located on the inner wall of the groove structure 11, thereby forming an insulating layer 3 with better thickness uniformity. The dry etching process is used to dry-etch the insulating material layer 2 at a faster rate. The use of the method for preparing a semiconductor device provided in the present application to prepare and form the insulating layer 3 improves the preparation efficiency of the insulating layer 3 and improves the thickness uniformity of the insulating layer 3.
[0030] The above-mentioned preparation method has high preparation efficiency, which can reduce the investment cost of equipment and further reduce the preparation cost, which helps to improve the price competitiveness of semiconductor devices.
[0031] In a feasible implementation, the plasma enhanced chemical vapor deposition process includes a plasma enhanced tetraethoxysilane (PE-TEOS) process.
[0032] In the above embodiment, the material of the insulating layer 3 includes silicon dioxide.
[0033] In the above embodiment, the insulating material layer 2 is prepared by a plasma-enhanced tetraethyl orthosilicate deposition silicon dioxide process. The preparation method is simple, low-cost, and has high stability and high productivity. It can reduce the preparation difficulty and preparation cost of the insulating material layer 2, and improve the stability and preparation speed of the insulating material layer 2, thereby achieving an increase in the preparation speed of the insulating layer 3.
[0034] In the above embodiment, the plasma enhanced tetraethoxysilane deposition silicon dioxide process is a thin film preparation technology based on plasma enhanced chemical vapor deposition. The principle is to react tetraethoxysilane with oxygen to generate a silicon dioxide film and deposit it on the semiconductor structure layer 1. In this process, the activation effect of plasma and chemical reaction are mainly relied on to achieve precise control of the quality and thickness of the silicon dioxide film.
[0035] Specifically, in the PE-TEOS process, tetraethoxysilane (TEOS) is used as a silicon source, which is an organic silicon compound that is a colorless liquid at room temperature. During the deposition process, TEOS is mixed with oxygen or other reactive gases and introduced into the reaction chamber. By applying a radio frequency power supply, a plasma is generated to excite the gas to ionize and form a plasma state. The ions and free radicals in these plasmas react chemically with the first surface of the semiconductor structure layer and the inner wall of the groove structure to promote the deposition of the insulating material layer. A key step in the PE-TEOS process is to gasify the TEOS liquid to produce TEOS gas, and then pass oxygen and TEOS gas into the reaction chamber. The ratio of the gas flow rate of oxygen to the flow rate of TEOS liquid is usually not less than 3.2 to ensure sufficient reaction. In the reaction chamber, oxygen and TEOS gas are dissociated by radio frequency to promote chemical reactions to generate silicon dioxide films. Parameters such as reaction pressure, temperature and gas flow need to be precisely controlled to ensure the quality and uniformity of the film. The PE-TEOS process can deposit a uniform and high-quality insulating material layer at a lower temperature, thereby improving the performance and reliability of semiconductor devices.
[0036] In a feasible implementation manner, the coverage rate D of the portion of the insulating layer 3 located on the sidewall of the groove structure 11 to the sidewall of the groove structure 11 is greater than or equal to 50%.
[0037] Specifically, D may be 50%, 53%, 67%, 75%, 82%, etc., and this application does not make any special limitation thereto.
[0038] Specifically, the step coverage D may be: a ratio of an average thickness of the portion of the insulating layer on the sidewall of the recess structure 11 to a diameter of the recess structure 11 .
[0039] Specifically, the larger the ratio D is, the better the coverage uniformity of the insulating layer 3 is, and the better the electrical isolation performance and reliability of the groove structure 11 are. If the step coverage is insufficient, the insulating layer 3 may be too thin in certain parts of the groove structure 11, thereby causing electrical breakdown or signal interference. In the preparation method of the semiconductor device provided in the present application, the coverage rate D of the part of the insulating layer 3 located on the side wall of the groove structure 11 to the side wall of the groove structure 11 can be greater than or equal to 50%, which effectively improves the thickness uniformity of the insulating layer 3, thereby further improving the preparation yield and performance of the semiconductor device.
[0040] In a feasible implementation manner, the thickness of the insulating layer 3 is greater than or equal to 2000 angstroms.
[0041] In the above-mentioned embodiments, the thickness of the insulating layer 3 may be 2000 angstroms, 2001 angstroms, 2010 angstroms, 2300 angstroms, 3000 angstroms, 4000 angstroms, 5500 angstroms, etc., and the present application does not impose any particular limitation on this.
[0042] Specifically, during the preparation of the insulating layer 3, the insulating material layer 2 is first formed by a plasma enhanced chemical vapor deposition process, and then the insulating material layer 2 is etched by a dry etching process. Step S400 and step S600 can be performed alternately for multiple times, specifically 1 to 10 times, to form an insulating layer 3 that meets the above-mentioned thickness range requirements and ratio D range requirements.
[0043] In a possible implementation, the dry etching gas includes nitrogen trifluoride.
[0044] Specifically, nitrogen trifluoride gas has high etching rate, high efficiency, high chemical stability and excellent electrical properties.
[0045] In the above embodiment, the insulating material layer 2 is dry-etched and thinned by nitrogen trifluoride gas, so as to quickly thin the thicker part of the insulating material layer 2, thereby improving the preparation rate.
[0046] In a feasible implementation, the plasma enhanced chemical vapor deposition process and the step of introducing the dry etching gas from the side of the insulating material layer 2 facing away from the semiconductor structure layer 1 in a direction perpendicular to the first surface 10 are performed in the same reaction chamber.
[0047] In the above embodiment, the preparation and thinning of the insulating material layer 2 are performed in the same reaction chamber, that is, an in-situ preparation method is adopted, which can reduce the process steps, further improve the production efficiency, and reduce cross contamination.
[0048] In the method for preparing a semiconductor device provided by the present application, the insulating layer 3 is prepared by combining a plasma enhanced chemical vapor deposition process with a dry etching process. The plasma enhanced chemical vapor deposition process and the dry etching process are carried out in situ in the same reaction chamber, thereby greatly improving the output of the equipment per hour. Specifically, when calculated based on a device with 6 groups of 3 reaction chambers (each group of reaction chambers includes two reaction chambers), the number of wafers per hour (UPEH) of the equipment for preparing the insulating layer 3 by traditional atomic layer deposition is 4.8 sheets. By using the method for preparing a semiconductor device provided by the present application, the step of forming the insulating material layer 2 by a plasma enhanced chemical vapor deposition process and the step of etching the insulating material layer 2 by a dry etching process are alternately performed 5 times, and the number of wafers per hour of the equipment can be 30 sheets. That is, the preparation rate is increased by 6 times.
[0049] In a possible implementation, Figure 2 As shown, the dimension of the groove structure 11 along the thickness direction of the semiconductor structure layer 1 is H, and the dimension of the groove structure 11 along the direction perpendicular to the thickness direction of the semiconductor structure layer 1 is W, and H:W≥10.
[0050] In the above-mentioned embodiment, the method for manufacturing a semiconductor device provided by the present application can be applied to a groove structure 11 with an aspect ratio greater than or equal to 10. For example, H is 40 μm, and W is 4 μm.
[0051] Specifically, the groove structure 11 may be a shallow trench isolation structure. In this case, the semiconductor structure layer 1 may include a silicon substrate, and the insulating layer 3 may be a linear oxide layer (liner oxide). The linear oxide layer can be used to repair the damage to the silicon substrate caused by etching to form the groove structure 11, and protect the semiconductor structure layer from the impact of subsequent process steps. The linear oxide layer can round the sharp corners generated when etching to form the groove structure 11 to reduce the problem of stress concentration and reduce the risk of failure of the semiconductor device. The linear oxide layer can isolate the substance filled in the groove structure from the semiconductor structure layer to prevent the substance filled in the groove structure from diffusing into the interior of the semiconductor structure layer and affecting the performance and reliability of the semiconductor device. The linear oxide layer can also reduce the stress caused by the mismatch of thermal expansion coefficients between the semiconductor structure layer and the substance filled in the groove structure, thereby improving the mechanical stability of the semiconductor device.
[0052] Specifically, the groove structure 11 may also include vertically stacked channels of logic devices, storage devices, and power devices, or the groove structure 11 may also include an interlayer interconnection contact hole structure. In this case, the insulating layer 3 may be an insulating liner layer, which has good anti-diffusion capability and acts as a diffusion barrier to prevent metal elements in the groove structure 11 from diffusing into the semiconductor structure layer 1 and affecting the dielectric characteristics around the groove structure 11, thereby improving the performance of the semiconductor device.
[0053] The present application also provides a semiconductor device, such as Figure 4 As shown, the semiconductor device is prepared by the above-mentioned preparation method of the present application. The preparation speed of the semiconductor device is effectively improved, thereby reducing the preparation cost.
[0054] In the above implementation mode, if Figure 4 As shown, the semiconductor device includes a semiconductor structure layer 1 and an insulating layer 3 . The semiconductor structure layer 1 includes a first surface 10 and a groove structure 11 formed by the first surface 10 being recessed.
[0055] In a feasible embodiment, the semiconductor structure layer 1 includes a silicon substrate, the groove structure 11 includes a shallow trench isolation structure, the insulating layer 3 is located on the first surface 10 and the inner wall of the groove structure 11, and the ratio of the portion of the insulating layer 3 located on the inner wall of the groove structure 11 to the portion located on the first surface 10 is greater than or equal to 50%. The insulating layer 3 is a linear oxide layer (liner oxide), which can be used to repair the damage to the silicon substrate caused when etching to form the groove structure 11, and at the same time, the sharp corner position generated when etching to form the groove structure 11 can be rounded.
[0056] In another feasible embodiment, the semiconductor structure layer 1 includes a silicon substrate and other structure layers, and the groove structure 11 may also include a vertically stacked channel of a logic device, a memory device, or a power device, or the groove structure 11 may also include an interlayer interconnection contact hole structure. In this case, the insulating layer 3 may be an insulating liner layer, and the insulating liner layer has a good anti-diffusion capability and acts as a diffusion barrier to prevent the metal elements in the groove structure 11 from diffusing into the semiconductor structure layer 1 and affecting the dielectric characteristics around the groove structure 11, thereby improving the performance of the semiconductor device. The insulating layer 3 only covers the sidewalls of the groove structure 11, or the insulating layer 3 covers the sidewalls and bottom wall of the groove structure 11. In this case, the insulating layer 3 may have no contact with the first surface 10.
[0057] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor structure layer, the semiconductor structure layer comprising a first surface and a groove structure formed by depression of the first surface; forming an insulating material layer on the first surface and the inner wall of the groove structure by using a plasma enhanced chemical vapor deposition process; A dry etching gas is introduced from a side of the insulating material layer away from the semiconductor structure layer in a direction perpendicular to the first surface to thin at least a portion of the insulating material layer and form an insulating layer.
2. The method for preparing a semiconductor device according to claim 1, wherein: The material of the insulating layer includes silicon dioxide.
3. The method for preparing a semiconductor device according to claim 2, characterized in that: The plasma enhanced chemical vapor deposition process includes a plasma enhanced tetraethyl orthosilicate deposition silicon dioxide process.
4. The method for preparing a semiconductor device according to claim 1, wherein: The coverage rate of the portion of the insulating layer located on the sidewall of the groove structure to the sidewall of the groove structure is greater than or equal to 50%.
5. The method for preparing a semiconductor device according to claim 1, characterized in that: The thickness of the insulating layer is greater than or equal to 2000 angstroms.
6. The method for preparing a semiconductor device according to claim 1, wherein: The dry etching gas includes nitrogen trifluoride.
7. The method for preparing a semiconductor device according to claim 1, characterized in that: The plasma enhanced chemical vapor deposition process and the step of introducing a dry etching gas from a side of the insulating material layer away from the semiconductor structure layer in a direction perpendicular to the first surface are performed in the same reaction chamber.
8. The method for preparing a semiconductor device according to claim 1, characterized in that: The dimension of the groove structure along the thickness direction of the semiconductor structure layer is H, and the dimension of the groove structure along the direction perpendicular to the thickness direction of the semiconductor structure layer is W, and H:W≥10.
9. The method for preparing a semiconductor device according to claim 1, wherein: The semiconductor structure layer includes a silicon substrate.
10. The method for preparing a semiconductor device according to claim 1, characterized in that: The step of forming an insulating material layer on the first surface and the inner wall of the groove structure using a plasma enhanced chemical vapor deposition process and the step of introducing a dry etching gas from the side of the insulating material layer away from the semiconductor structure layer in a direction perpendicular to the first surface to thin at least a portion of the insulating material layer and form an insulating layer are alternately performed 1 to 10 times.
11. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for preparing the semiconductor device according to any one of claims 1 to 10.