Inverter starting method, inverter and storage medium

Abstract

The invention provides an inverter starting method, an inverter and a storage medium, the inverter starting method is applied to a first chip of the inverter, the inverter comprises a second chip connected with the first chip, and the method comprises the following steps: detecting a communication state between the first chip and the second chip in response to a power-on instruction; when the communication state is a normal state, sending a first configuration parameter stored in the first chip to the second chip; after it is determined that the first configuration parameter is sent, reading a second configuration parameter in the second chip; and if the second configuration parameter is the same as the first configuration parameter, an operation instruction is sent to the second chip, and the second chip is triggered to operate to start the inverter. According to the method, the operation efficiency of the inverter can be improved.

Description

Technical Field

[0001] The present application relates to the field of inverters, and in particular to a method for starting an inverter, an inverter, and a storage medium. Background Art

[0002] The relevant parameter settings of the digital signal processor (DSP) in the inverter system are usually set through the human-machine interface of the Advanced RISC Machines (ARM) and then forwarded to the DSP. Usually, the parameters forwarded by ARM will be backed up in the internal memory of ARM. If the parameters forwarded by ARM to the DSP involve the parameters required for DSP operation, the DSP will also back them up in the internal memory of DSP. This requires the existence of two storage chips at the same time in the hardware design, which increases the hardware cost and reduces the flexibility. Summary of the invention

[0003] The embodiments of the present application disclose an inverter startup method, an inverter, and a storage medium, which solve the technical problems of high hardware cost of the existing inverter system, such as high maintenance difficulty, low flexibility, and low operating efficiency.

[0004] The present application provides a method for starting an inverter, which is applied to a first chip of the inverter, wherein the inverter includes a second chip connected to the first chip, and the method includes: responding to a power-on instruction, detecting a communication state between the first chip and the second chip; when the communication state is normal, sending a first configuration parameter stored in the first chip to the second chip; after determining that the sending of the first configuration parameter is completed, reading a second configuration parameter in the second chip; if the second configuration parameter is the same as the first configuration parameter, sending a run instruction to the second chip, triggering the second chip to run and start the inverter.

[0005] In some embodiments of the present application, the detecting of the communication status between the first chip and the second chip includes: sending communication data to the second chip; if the data fed back by the second chip includes the communication data within a preset time, determining that the communication status is the normal state; if the data fed back by the second chip is not received within the preset time, or the data fed back by the second chip does not include the communication data, determining that the communication status is an abnormal state.

[0006] In some embodiments of the present application, if the second configuration parameter is the same as the first configuration parameter, sending an operating instruction to the second chip includes: if the second configuration parameter is the same as the first configuration parameter, sending a preset flag to the second chip; if the second chip feeds back the preset flag within a preset time, sending the operating instruction to the second chip; if the second chip does not feed back the preset flag within the preset time, re-detecting the communication status between the first chip and the second chip.

[0007] In some embodiments of the present application, the method also includes: obtaining a first verification value of the first configuration parameter and a second verification value of the second configuration parameter; if the first verification value is the same as the second verification value, determining that the second configuration parameter is the same as the first configuration parameter; if the first verification value is different from the second verification value, determining that the second configuration parameter is different from the first configuration parameter.

[0008] In some embodiments of the present application, the method also includes: if the second configuration parameter is different from the first configuration parameter, re-sending the first configuration parameter stored in the first chip to the second chip, reading the second configuration parameter in the second chip, and calculating the number of re-executions; if the number exceeds a preset number, and the second configuration parameter is different from the first configuration parameter, determining that the second chip is abnormal, and issuing an abnormal prompt message.

[0009] In some embodiments of the present application, sending the first configuration parameter stored in the first chip to the second chip includes: using the last byte of the first configuration parameter as a data identifier; sending the first configuration parameter carrying the data identifier to the second chip through a preset synchronization protocol, so that the second chip determines the parameter type of the first configuration parameter by identifying the data identifier, and the parameter type includes an operating parameter.

[0010] In some embodiments of the present application, triggering the second chip to operate to start the inverter includes: controlling the second chip to operate using the first configuration parameters when identifying the operating parameters.

[0011] In some embodiments of the present application, the method further includes: when the communication state is an abnormal state, re-detecting the communication state between the first chip and the second chip.

[0012] The present application also provides an inverter, which includes a processor and a memory, and the processor is used to implement the inverter startup method when executing a computer program stored in the memory.

[0013] The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the inverter startup method is implemented.

[0014] In the startup method of the inverter provided in the present application, in response to the power-on instruction, the communication status between the first chip and the second chip is detected to provide a communication basis for the subsequent operations. When the communication status is normal, the first configuration parameter stored in the first chip is sent to the second chip; after determining that the sending of the first configuration parameter is completed, the second configuration parameter in the second chip is read; by interacting with the configuration parameter of the second chip, it is determined that the second chip can receive the first configuration parameter of the first chip, avoiding directly storing the first configuration parameter in the second chip, reducing hardware costs and reducing maintenance difficulties. If the second configuration parameter is the same as the first configuration parameter, indicating that the data received by the second chip is the first configuration parameter, a running instruction is sent to the second chip, triggering the second chip to run to start the inverter, thereby improving the operating efficiency of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a schematic diagram of an application scenario of the inverter startup method provided in an embodiment of the present application.

[0016] Figure 2 It is a flow chart of the inverter startup method provided in an embodiment of the present application.

[0017] Figure 3 It is a state diagram of the inverter provided in an embodiment of the present application.

[0018] Figure 4 It is a schematic diagram of the structure of the inverter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] To facilitate understanding, some illustrations of concepts related to the embodiments of the present application are given by way of example for reference.

[0020] It should be noted that in this application, "at least one" means one or more, and "more than one" means two or more than two. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The terms "first", "second", "third", "fourth", etc. (if any) in the specification, claims and drawings of this application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0021] The relevant parameter settings of the digital signal processor (DSP) in the inverter system are usually set through the human-machine interface of the Advanced RISC Machines (ARM) and then forwarded to the DSP. Usually, the parameters forwarded by ARM will be backed up in the internal memory of ARM. If the parameters forwarded by ARM to the DSP involve the parameters required for DSP operation, the DSP will also back them up in the internal memory of DSP. This requires the existence of two storage chips at the same time in the hardware design, which increases the hardware cost and reduces the flexibility.

[0022] In addition, once the parameters need to be modified, the parameters stored in ARM and DSP need to be modified synchronously, which increases the difficulty of maintaining the inverter system and reduces flexibility. Moreover, during the process of synchronous modification of parameters, the quality of data synchronization cannot be ensured, affecting the operating efficiency of the inverter system.

[0023] In order to solve the technical problems of high hardware cost of the existing inverter system, such as high maintenance difficulty, low flexibility and low operating efficiency. The embodiment of the present application provides an inverter startup method, an inverter and a storage medium, which can reduce hardware cost, reduce the maintenance difficulty of the inverter and improve the operating efficiency of the inverter. The application scenario of the inverter startup method of the present application is first described below.

[0024] Figure 1 1 is a schematic diagram of an application scenario of the inverter startup method provided in the embodiment of the present application. The inverter startup method provided in the embodiment of the present application is applied to the inverter 10.

[0025] In some embodiments of the present application, the battery connection terminal of the inverter 10 is used to connect the photovoltaic storage device 20. The off-grid output port and the grid-connected output port of the inverter 10 are both connected to the power device 30, and the grid-connected output port is also used to connect to the power grid 40. The photovoltaic storage device 20 can be powered by the inverter 10 via the off-grid output port power device 30. When the inverter 10 is in the grid-connected state, that is, when the power grid 40 is connected to the grid-connected output port, the power grid 40 can also power the power device 30 through the grid-connected output port.

[0026] In addition, the inverter 10 may have a built-in wireless transmission module, such as Wi-Fi or Bluetooth. The inverter 10 uses the wireless transmission module ( Figure 1 Not shown) can be used with pre-configured monitoring devices ( Figure 1 The inverter 10 can indirectly realize wireless communication with the power-consuming device 30 through the monitoring device (not shown), wherein the monitoring device can be a mobile phone, a computer, a cloud server, etc., and the monitoring software or a corresponding application is set on the monitoring device.

[0027] The inverter 10 is an electronic device that converts direct current (DC) into alternating current (AC).

[0028] The solar energy storage device 20 is a device composed of a solar panel and an energy storage battery, and is used to store the electrical energy generated by the solar panel.

[0029] The electric device 30 may include but is not limited to household appliances, such as washing machines, refrigerators, air conditioners, etc. The electric device 30 may also include electronic products such as computers.

[0030] The indication Figure 1 It is only an example of an application scenario and does not constitute a limitation of the application scenario. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the inverter 10 may also be connected to a monitoring device, etc.

[0031] Figure 2 is a flowchart of a method for starting an inverter provided in an embodiment of the present application, which is applied to an inverter (eg Figure 1 According to different requirements, the order of the steps in the flowchart can be changed, and some steps can be omitted.

[0032] Step S201, responding to a power-on instruction, detecting a communication state between the first chip and the second chip.

[0033] In some embodiments of the present application, the power-on instruction is used to instruct the inverter to start the operation. When the inverter receives the power-on instruction, it can first enter the startup process. The power-on instruction received by the inverter can be triggered in many ways, for example, it can be triggered by the hardware switch of the inverter itself, it can also be triggered by the photovoltaic storage device connected to the inverter, and it can also be triggered by an external control signal.

[0034] The method of triggering the inverter by its own hardware switch may include equipping the inverter with a hardware switch (e.g., a button), the hardware switch may include a start switch and a shutdown switch, or the start and shutdown functions may be integrated into one switch. In one example, the inverter determines that a power-on instruction is received when it detects that a user or other device (e.g., a robot) presses the start switch.

[0035] The method of triggering the photovoltaic storage device connected to the inverter may include: for a photovoltaic storage system with intelligent control function, the inverter can communicate with the photovoltaic storage device and automatically start according to the status of the photovoltaic storage device. In one example, the inverter detects the status of the photovoltaic storage device in real time. When the voltage generated by the solar panel in the photovoltaic storage device reaches a certain threshold, the power-on instruction is triggered to enter the startup process. After completing the startup process, the inverter can convert DC power into AC power to supply it to the load.

[0036] The method of triggering by an external control signal may include: the inverter may receive a signal from an external controller to start working, and such an external controller may be an automated control device with an energy management system. The inverter determines the start, schedule, shutdown and other states by receiving a specific control signal sent by the external controller. In one example, when the inverter receives a start signal sent by an external controller, it determines that a power-on instruction has been received and enters the start-up process.

[0037] In some embodiments of the present application, the inverter includes a first chip, which may be a low-power, high-performance ARM (Advanced RISC Machines) processor. The first chip may receive instructions and signals from other parts of the optoelectronic system, execute corresponding control algorithms, adjust the operating parameters of the inverter, and exchange data with other parts of the optoelectronic system or external devices through various communication interfaces. A first memory is provided in the first chip, which may be used to store all configuration parameters for the operation of the inverter and the operating parameters generated during the operation.

[0038] The inverter further includes a second chip, which may be a microprocessor for digital signal processing, such as a digital signal processor (DSP). The second chip has various complex digital signal processing algorithms.

[0039] In some embodiments of the present application, the first chip responds to the power-on instruction, enters the startup process, and sets the state of the first chip to the waiting synchronization state. When the first chip is in the waiting synchronization state, the first chip can detect the state of other chips in the inverter so that the inverter can start normally. In one example, the first chip can detect the communication state between the first chip and the second chip in the waiting synchronization state.

[0040] In some embodiments of the present application, the communication status between the first chip and the second chip can be detected by communication data, and the communication data can be specified data for detecting whether the communication link is normal. The first chip sends communication data to the second chip. If the data fed back by the second chip includes the communication data sent by the first chip to the second chip within the preset time, it is determined that the communication status between the first chip and the second chip is a normal state. If the data fed back by the second chip is not received within the preset time, or the data fed back by the second chip does not include communication data within the preset time, it is determined that the communication status between the first chip and the second chip is an abnormal state. Among them, the preset time can be set according to actual needs, and this application is not limited to this.

[0041] In one example, the communication data includes a first data packet and a second data packet. If the second chip feeds back the first data packet and the second data packet within a preset time, the communication state between the first chip and the second chip is determined to be a normal state. If the second chip feeds back the first data packet or the second data packet, or even other data packets within a preset time, the communication state between the first chip and the second chip is determined to be an abnormal state.

[0042] In some embodiments of the present application, if it is determined that the communication state between the first chip and the second chip is normal, the state of the first chip can be updated from the waiting synchronization state to the data synchronization state. If it is determined that the communication state between the first chip and the second chip is abnormal, the first chip waits for normal communication in the waiting synchronization state, and jumps to the data synchronization state after the communication is restored.

[0043] Step S202: When the communication state is a normal state, the first configuration parameters stored in the first chip are sent to the second chip.

[0044] In some embodiments of the present application, in order to reduce hardware costs, a storage interval for storing configuration parameters (such as first configuration parameters) may not be set in the second chip. A synchronization protocol corresponding to the configuration parameters is added to the original protocol between the first chip and the second chip. Based on the synchronization protocol, the first chip can provide the second chip with the first configuration parameter for starting the second chip.

[0045] In some embodiments of the present application, after the communication state between the first chip and the second chip is normal, the first chip can use the last byte of the first configuration parameter as a data identification bit. The first configuration parameter carrying the data identification bit is sent to the second chip through a preset synchronization protocol, so that the second chip determines the parameter type of the first configuration parameter by identifying the data identification bit, and the parameter type includes an operating parameter. Among them, at the second chip end, the second chip receives the data sent from the first chip, and when the data identification bit is identified, it is determined that the first configuration parameter sent by the first chip is an operating parameter for startup.

[0046] Step S203: after determining that the sending of the first configuration parameter is completed, read the second configuration parameter in the second chip.

[0047] In some embodiments of the present application, the first chip uses the last byte of the first configuration parameter as a data identification bit, and when the data identification bit is sent, the first chip determines that the sending of the first configuration parameter is completed. In order to verify whether the second chip has received the first configuration parameter or whether the received data is complete, the first chip reads the second configuration parameter in the second chip after determining that the sending of the first configuration parameter is completed based on the data identification bit, so as to compare whether the second configuration parameter is the same as the first configuration parameter.

[0048] In some embodiments, when the first chip is reading the second configuration parameter, if the data identification bit is read, it indicates that the reading of the second configuration parameter is completed, and the data synchronization state of the first chip is updated to the data comparison state. If the data identification bit is not read within the preset time, it indicates that the communication between the first chip and the second chip is abnormal, or the second chip has not received the complete first configuration parameter, the data synchronization state of the first chip is jumped to the waiting synchronization state, and the communication state between the first chip and the second chip is re-detected, for example, the process returns to step S201.

[0049] Step S204: If the second configuration parameter is the same as the first configuration parameter, send an operation instruction to the second chip to trigger the second chip to operate and start the inverter.

[0050] In some embodiments of the present application, in order to improve the efficiency of verifying the first configuration parameter of the second configuration parameter, the first chip may calculate the first check value of the first configuration parameter before sending the first configuration parameter to the second chip. The first check value may be calculated by checksum check, XOR check, polynomial calculation, and hash algorithm, etc., which is not limited by the present application. The first chip sends the first configuration parameter carrying the first check value to the second chip. After receiving the second configuration parameter fed back by the second chip, the first chip obtains the first check value from the first configuration parameter and obtains the second check value from the second configuration parameter.

[0051] In some embodiments of the present application, if the first check value is different from the second check value, it is determined that the second configuration parameter is different from the first configuration parameter, indicating that an abnormality occurs in the transmission process of the first configuration parameter or the second configuration parameter. The first chip can be updated from the data comparison state to the waiting synchronization state, re-detect the communication state between the first chip and the second chip, and re-send the first configuration parameter stored in the first chip to the second chip, and read the second configuration parameter in the second chip, and calculate the number of re-executions.

[0052] If the number of re-executions exceeds the preset number, and the second configuration parameter is different from the first configuration parameter, the second chip is determined to be abnormal and an abnormal prompt message is issued, wherein the preset number of times can be set according to actual needs, for example, the number of times can be 3 times, and this application does not limit this.

[0053] If the first check value is the same as the second check value, it is determined that the second configuration parameter is the same as the first configuration parameter, and the data comparison state of the first chip can be updated to a synchronization completion state.

[0054] In addition, in order to avoid the situation where the first check value and the second check value pass the check, but the actual data sequence is disordered, when it is determined that the first check value is the same as the second check value, the data corresponding to the first configuration parameter and the second configuration parameter can also be read and compared one by one according to the order of reading. If it is determined that the first configuration parameter is the same as the second configuration parameter based on the sequence matching method, the data comparison state of the first chip is updated to the synchronization completion state.

[0055] In some embodiments of the present application, after determining that the second configuration parameter is the same as the first configuration parameter, the default flag bit and the preset flag bit can be used to verify whether the second chip has a restart operation, wherein the default flag bit is a flag bit pre-configured by the second chip, and the preset flag bit is a flag bit sent by the first chip to the second chip. If the second chip feeds back the preset flag bit within a preset time, indicating that the second chip does not have a restart operation, the first chip can send an operation instruction to the second chip, triggering the second chip to start operation using the first configuration parameter when the operation parameter is identified, so as to start the inverter.

[0056] If the second chip does not feedback the preset flag within the preset time, or the second chip feedbacks the default flag within the preset time, it indicates that the second chip has a restart operation, the synchronization completion state is updated to the waiting synchronization state, and the communication state between the first chip and the second chip is re-detected.

[0057] In one example, the preset time is 30 seconds, the default flag is flag 0, and the preset flag is flag 1. Within 30 seconds, if the first chip receives flag 1, it indicates that there is no restart operation on the second chip. Within 30 seconds, if the first chip receives flag 0, it indicates that there is a restart operation on the second chip.

[0058] In an embodiment of the present application, in response to a power-on instruction, the communication status between the first chip and the second chip is detected to provide a communication basis for subsequent operations. When the communication status is normal, the first configuration parameter stored in the first chip is sent to the second chip; after determining that the sending of the first configuration parameter is completed, the second configuration parameter in the second chip is read; by interacting with the second chip configuration parameter, it is determined that the second chip can receive the first configuration parameter of the first chip, avoiding direct storage of the first configuration parameter in the second chip, reducing hardware costs and reducing maintenance difficulties. If the second configuration parameter is the same as the first configuration parameter, indicating that the data received by the second chip is the first configuration parameter, a run instruction is sent to the second chip to trigger the second chip to start the inverter and improve the operating efficiency of the inverter.

[0059] Figure 3 is a schematic diagram of the state of the inverter provided in the embodiment of the present application, such as Figure 3 As shown, the first chip has four states, including a synchronization waiting state, a data synchronization state, a data comparison state, and a synchronization completion state.

[0060] When the first chip responds to the power-on instruction, the first chip enters a waiting synchronization state.

[0061] When the first chip is in the waiting synchronization state and determines that the communication state between the first chip and the second chip is in a normal state, the waiting synchronization state is updated to the data synchronization state. When the first chip determines that the communication state between the first chip and the second chip is in an abnormal state, the first chip remains in the waiting synchronization state until the communication state is in a normal state. Alternatively, if the communication between the first chip and the second chip is lost, the first chip remains in the waiting synchronization state until the communication state is in a normal state.

[0062] When the first chip is in the data synchronization state and determines that the second configuration parameter in the second chip has been read, the data synchronization state is updated to the data comparison state. When the first chip determines that the second configuration parameter in the second chip has not been read, the data synchronization state is updated to the waiting synchronization state. Alternatively, if the communication between the first chip and the second chip is lost, the data synchronization state is updated to the waiting synchronization state.

[0063] When the first chip is in the data comparison state and determines that the second configuration parameter is the same as the first configuration parameter, the data comparison state is updated to the synchronization completion state. When the first chip determines that the second configuration parameter is not the same as the first configuration parameter, the data comparison state is updated to the waiting synchronization state. Alternatively, if the communication between the first chip and the second chip is lost, the data comparison state is updated to the waiting synchronization state.

[0064] When the first chip is in the synchronization completion state, if the communication between the first chip and the second chip is lost, the synchronization completion state is updated to the waiting synchronization state. Alternatively, if other abnormal operations cause the second chip to restart (or restore default data), the synchronization completion state is updated to the waiting synchronization state.

[0065] Figure 4 Schematic diagram of the structure of the inverter provided in the embodiment of the present application. Figure 4 As shown, the inverter 10 includes a communication module 101, a first chip 102, a second chip 103, an off-chip memory 104, an input / output (I / O) interface 105, and a bus 106. The first chip 102 is respectively coupled to the communication interface 101, the second chip 103, the off-chip memory 104, and the I / O interface 105 through the bus 106, and the first chip 102 includes an on-chip memory 1021.

[0066] The communication module 101 may include a wired communication module and / or a wireless communication module. The wired communication module may provide one or more wired communication solutions such as Universal Serial Bus (USB), Controller Area Network (CAN), etc. The wireless communication module may provide one or more wireless communication solutions such as Wireless Fidelity (Wi-Fi), Bluetooth (BT), mobile communication network, Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), etc.

[0067] The first chip 102 may include one or more processing units, for example, the first chip 102 may include an application processor (AP), a modem processor, a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors. The on-chip memory 1021 is used to store data required for the operation of the first chip 102.

[0068] The second chip 103 may be a microprocessor for digital signal processing, such as a digital signal processor (DSP). The second chip has various complex digital signal processing algorithms.

[0069] The off-chip memory 104 may include one or more random access memories (RAM) and one or more non-volatile memories (NVM). The random access memory can be directly read and written by the first chip 102, and can be used to store executable programs (such as machine instructions) of the operating system or other running programs, and can also be used to store user and application data. The random access memory may include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc.

[0070] The non-volatile memory may also store executable programs and user and application data, etc., and may be loaded into the random access memory in advance for direct reading and writing by the first chip 102. The non-volatile memory may include a disk storage device and a flash memory.

[0071] The off-chip memory 104 is used to store one or more computer programs. The one or more computer programs are configured to be executed by the first chip 102. The one or more computer programs include multiple instructions. When the multiple instructions are executed by the first chip 102, a startup method of an inverter of multiple devices executed on the inverter 10 can be implemented. Among them, the off-chip memory 104 is designed to meet the requirements of large capacity, persistence, scalability, cost-effectiveness and system stability, and the on-chip memory 1021 in the first chip 102 is designed to provide high-speed access and reduce the number of external accesses. In an embodiment of the present application, the first configuration parameters for the second chip 103 to run are stored in the on-chip memory 1021 to improve the startup efficiency of the inverter 10.

[0072] In other embodiments, the inverter 10 further includes an external memory interface for connecting to an external memory to expand the storage capacity of the inverter 10 .

[0073] The I / O interface 105 is used to provide a channel for user input or output. For example, the I / O interface 105 can be used to connect various input and output devices, such as a mouse, keyboard, touch device, display screen, etc., so that the user can enter information or visualize information.

[0074] The bus 106 is at least used to provide a channel for mutual communication among the communication module 101 , the first chip 102 , the second chip 103 , the off-chip memory 104 , and the I / O interface 105 in the inverter 10 .

[0075] An embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. The computer program includes program instructions. The method implemented when the program instructions are executed can refer to the methods in the above-mentioned embodiments of the present application.

[0076] The computer-readable storage medium may be an internal memory of the electronic device described in the above embodiment, such as a hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device.

[0077] In some embodiments, the computer-readable storage medium may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function, etc.; the data storage area may store data created according to the use of the electronic device, etc.

[0078] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0079] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0080] In the embodiments provided in the present application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0081] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0082] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for starting an inverter, applied to a first chip of the inverter, characterized in that: The inverter includes a second chip connected to the first chip, and the method includes: In response to a power-on instruction, detecting a communication state between the first chip and the second chip; When the communication state is a normal state, sending the first configuration parameter stored in the first chip to the second chip; After determining that the sending of the first configuration parameter is completed, reading the second configuration parameter in the second chip; If the second configuration parameter is the same as the first configuration parameter, an operation instruction is sent to the second chip to trigger the second chip to operate and start the inverter.

2. The inverter startup method according to claim 1, characterized in that: The detecting the communication state between the first chip and the second chip includes: sending communication data to the second chip; If the data fed back by the second chip within the preset time includes the communication data, determining that the communication state is the normal state; If the data fed back by the second chip is not received within a preset time, or the data fed back by the second chip does not include the communication data, it is determined that the communication state is an abnormal state.

3. The inverter startup method according to claim 1, characterized in that: If the second configuration parameter is the same as the first configuration parameter, sending an operation instruction to the second chip includes: If the second configuration parameter is the same as the first configuration parameter, sending a preset flag bit to the second chip; If the second chip feeds back the preset flag bit within a preset time, sending the operation instruction to the second chip; If the second chip does not feed back the preset flag within the preset time, the communication status between the first chip and the second chip is re-detected.

4. The inverter startup method according to claim 1, characterized in that: The method further comprises: Obtaining a first check value of the first configuration parameter and a second check value of the second configuration parameter; If the first check value is the same as the second check value, determining that the second configuration parameter is the same as the first configuration parameter; If the first check value is different from the second check value, it is determined that the second configuration parameter is different from the first configuration parameter.

5. The inverter startup method according to claim 1, characterized in that: The method further comprises: If the second configuration parameter is different from the first configuration parameter, resending the first configuration parameter stored in the first chip to the second chip, reading the second configuration parameter in the second chip, and calculating the number of re-executions; If the number exceeds a preset number, and the second configuration parameter is different from the first configuration parameter, it is determined that the second chip is abnormal, and an abnormal prompt message is issued.

6. The inverter startup method according to claim 1, characterized in that: The sending the first configuration parameter stored in the first chip to the second chip includes: Using the last byte of the first configuration parameter as a data identification bit; The first configuration parameter carrying the data identification bit is sent to the second chip through a preset synchronization protocol, so that the second chip determines the parameter type of the first configuration parameter by identifying the data identification bit, and the parameter type includes an operating parameter.

7. The inverter startup method according to claim 6, characterized in that: The triggering the second chip to operate so as to start the inverter includes: The second chip is controlled to operate using the first configuration parameter when the operating parameter is identified.

8. The inverter startup method according to claim 1, characterized in that: The method further comprises: When the communication state is an abnormal state, the communication state between the first chip and the second chip is re-detected.

9. An inverter, characterized in that: The inverter comprises a processor and a memory, wherein the processor is configured to execute a computer program stored in the memory to implement the inverter startup method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one instruction, and when the at least one instruction is executed by a processor, the inverter startup method according to any one of claims 1 to 8 is implemented.

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