Cascaded half-band filter chain under electric energy metering chip, acceleration method and chip

Abstract

The invention provides an electric energy metering chip cascade half-band filter chain, an acceleration method and a chip wherein the electric energy metering chip cascade half-band filter acceleration method comprises the following steps: step 1, constructing a parallel-in parallel-out half-band filter accelerator; step 2, performing cascade calculation by using the half-band filter accelerator to complete the acceleration of the cascade half-band filter; according to the cascade half-band filter chain under the electric energy metering chip, based on the cascade half-band filter acceleration method, the parallel-in parallel-out half-band filter accelerator is used as a half-band filter, and the cascade half-band filter chain is constructed and used for selecting calculation results of different half-band filters in the electric energy metering chip. The electric energy is metered; according to the electric energy metering chip, the cascade half-band filter chain is constructed by adopting the method, so that the electric energy metering application is realized.

Description

Technical Field

[0001] The invention relates to a half-band filter chain, an acceleration method and a chip, in particular to a half-band filter chain cascaded under an electric energy metering chip, an acceleration method and a chip. Background Art

[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.

[0003] With the development of smart grids, the number of sensor nodes (electricity metering ASICs) deployed in the ubiquitous power Internet of Things has increased dramatically. As the core of the sensor node, the energy metering ASIC plays a vital role in the entire system. The requirements for energy metering ASICs mainly include the following aspects: first, it is necessary to meet high-precision metering requirements; second, the bandwidth needs to be flexibly adjusted to adapt to new requirements in complex environments; in addition, it is also necessary to achieve the goals of low cost and low power consumption. This poses a huge challenge to the accuracy and flexibility of the metering algorithm and cost control. Specifically:

[0004] First, the technical specifications of the new generation of smart energy meters require not only the traditional full-wave and fundamental wave metering and measurement data, but also the provision of data related to power quality and meter operation status, and the realization of harmonic analysis and harmonic metering functions. Therefore, high-precision energy metering with higher indicators places higher demands on the performance of metering algorithms and metering filters.

[0005] Second, energy metering usually requires customized algorithms and filters, and it is difficult for a specific filter design to achieve ideal results in terms of flexible bandwidth adjustment. When the harmonic metering frequency changes, the filter design often needs to be modified specifically, which lacks flexibility and adaptability.

[0006] Third, three-phase metering requires the simultaneous calculation of seven independent signals, which requires a huge amount of calculation and usually requires higher computing power, which requires a higher main frequency, which in turn leads to increased chip power consumption and cost.

[0007] Therefore, under existing technical conditions, how to achieve flexible adjustment of bandwidth while ensuring high precision and controlling cost and power consumption is a difficult problem that needs to be solved urgently.

[0008] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0009] Purpose of the invention: The technical problem to be solved by the present invention is to provide a cascaded half-band filter chain, an acceleration method and a chip under an electric energy metering chip in view of the deficiencies in the prior art.

[0010] In order to solve the above technical problems, the present invention discloses a cascaded half-band filter chain under an electric energy metering chip, an acceleration method and a chip, wherein the method comprises the following steps:

[0011] Step 1, construct an in-and-out half-band filter accelerator;

[0012] Step 2: Use the half-band filter accelerator to perform cascade calculation to complete the cascade half-band filter acceleration.

[0013] Further, the in-and-out half-band filter accelerator specifically includes:

[0014] A merge-in-and-out half-band filter for performing calculations and a control module for controlling the merge-in-and-out half-band filter.

[0015] Further, the in-and-out half-band filter specifically includes:

[0016] 9 registers and 5 adding units;

[0017] The register specifically includes:

[0018] 4 half-band filter input registers, namely, a first input register XD0, a second input register XD1, a third input register XD2 and a fourth input register XD3;

[0019] 4 half-band filter intermediate result registers, namely a first intermediate result register Y1D1, a second intermediate result register Y1D2, a third intermediate result register Y2D1 and a fourth intermediate result register Y2D2;

[0020] And 1 half-band filter result register Y;

[0021] The adding unit specifically comprises:

[0022] The first adder S1, the second adder S2 and the third adder S3 are used to calculate the data in the first intermediate result register Y1D1, the third intermediate result register Y2D1 and the half-band filter result register Y respectively;

[0023] The fourth adder S4 is used for converting the multiplication 9 / 32 operation performed on the second input register XD1 into a shift addition operation.

[0024] A fifth adder S5, used for converting the multiplication-9 / 16 operation performed on the fourth intermediate result register Y2D2 into a shift addition operation;

[0025] The first input register XD0, the third input register XD2 and the second intermediate result register Y1D2 are connected to the second adder S2 as inputs, and the second adder S2 adds the above inputs and outputs them to the first intermediate result register Y1D1;

[0026] The second input register XD1, the fourth input register XD3 and the fourth intermediate result register Y2D2 are connected to the third adder S3 as inputs, and the third adder S3 adds the above inputs and outputs them to the third intermediate result register Y2D1;

[0027] The first intermediate result register Y1D1 and the third intermediate result register Y2D1 are connected to the first adder S1 as inputs, and the first adder S1 adds the above inputs and outputs them to the half-band filter result register Y;

[0028] The second input register XD1 is connected to the fourth adder S4 as an input, and the fourth adder S4 adds the shift values ​​of the above inputs and outputs the sum to the third adder S3;

[0029] The fourth intermediate result register Y2D2 is connected to the fifth adder S5 as an input. The fifth adder S5 adds the shift values ​​of the above inputs and outputs the added values ​​to the third adder S3.

[0030] Furthermore, the control module specifically includes:

[0031] An input and output address mapping module for performing read and write control, wherein the input and output address mapping module is respectively connected with the 9 register data and performs data exchange;

[0032] The merge-in and merge-out address mapping modules are also connected to the static random access memory SRAM data and perform data interaction to adapt to the dedicated DSP module and the general processor;

[0033] The in-and-out address mapping module is also connected to the decoder Decoder and the read-only memory ROM data, and is used to control the in-and-out half-band filter. The control includes noise reduction sampling control, priority control and channel mapping.

[0034] Furthermore, the calculation process of incorporating and outputting the half-band filter is implemented in hardware or software;

[0035] The in-and-out half-band filter accelerator is implemented in hardware or software;

[0036] The method is implemented in software, that is, it is implemented by calling software under processors with different instruction sets and different pipeline levels.

[0037] The present invention also proposes a cascaded half-band filter chain under an electric energy metering chip. Based on the above-mentioned cascaded half-band filter acceleration method, the merge-in and merge-out half-band filter accelerator is used as a half-band filter to construct a cascaded half-band filter chain for selecting calculation results of different half-band filters in the electric energy metering chip to perform the electric energy metering.

[0038] Further, the cascaded half-band filter chain comprises:

[0039] Cascaded half-band filter chains for downsampling and cascaded half-band filter chains for free call of signals with different frequencies.

[0040] Furthermore, the cascaded half-band filter chain for downsampling specifically includes:

[0041] The cascaded half-band filter chain for downsampling is implemented by using a half-band filter accelerator for cascading.

[0042] Furthermore, the cascaded half-band filter chain for freely accessing signals of different frequencies specifically includes:

[0043] N stages of in-and-out half-band filter accelerators are cascaded, wherein each stage of in-and-out half-band filter accelerator reduces the frequency of the input signal to half of the output frequency, thereby realizing the cascaded half-band filter chain for freely accessing signals of different frequencies.

[0044] The present invention also proposes an electric energy metering chip, which adopts the above-mentioned method and uses the program memory, data memory, instruction decoder, general register, program pointer generator and address mapping module in the electric energy metering chip to construct the above-mentioned cascaded half-band filter chain to realize electric energy metering application.

[0045] Beneficial effects:

[0046] 1. The flexibly extractable cascaded half-band filter chain designed by the present invention can freely adjust the metering bandwidth of the power metering signal by adjusting the number of stages of the half-band filter output. This design greatly enhances the adaptability of the system and can meet the needs of different application scenarios.

[0047] 2. By introducing a half-band filtering operation that is consistent with the signal frequency on the half-band filter chain, the filtering effect can be flexibly adjusted. This not only improves the filtering performance, but also enhances the flexibility of customizing the filtering effect, allowing the system to better cope with various complex signal processing requirements.

[0048] 3. The half-band filter accelerator proposed in the present invention adopts an extremely compact structural design, which includes a total of 9 registers and 5 adders. This design not only occupies less hardware resources, but also polls the half-band filter hardware accelerator through 7 power metering signals, significantly reducing the hardware area overhead required to implement high-precision power metering algorithms. This optimized hardware structure effectively improves the efficiency of the overall system.

[0049] 4. The half-band filter implemented by the acceleration method proposed in the present invention has excellent performance in terms of amplitude-frequency characteristics. It can not only filter out noise efficiently, but also has high flatness while retaining the in-band signal, ensuring that the amplitude attenuation close to 0dB is achieved within the measurement bandwidth. Such performance enables it to provide accurate and stable signal processing effects in various power metering applications.

[0050] 5. The present invention adopts a parallel-input and parallel-output structure to achieve high data throughput. Through this structure, the number of calculation steps required for a complete half-band filter calculation is reduced from 17 beats to 9 beats, and the computing power is increased by about one-fold. This improvement significantly enhances the performance of the system and can process large amounts of data more efficiently.

[0051] 6. The present invention adopts a single-ended SRAM with a data width of 64 bits, which simplifies the control and provides a higher cost-effectiveness while maintaining a low area overhead and power consumption. Such a design not only improves the data processing speed, but also reduces the overall energy consumption of the system, and is suitable for various high-performance application scenarios.

[0052] 7. The cascaded half-band filter chain proposed in the present invention is applicable to both accelerator hardware and processor software calling modes. The data and control end definitions of the half-band filter hardware accelerator are simple, and it can be used as a hardware accelerator for processors with different instruction sets and different pipeline levels. At the same time, the half-band filter calculation process is simple and standardized, and the half-band filter calculation can be implemented on any chip in the processor software calling mode, which has extremely high versatility and portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments, and the above and / or other advantages of the present invention will become more clear.

[0054] Figure 1 It is a schematic diagram of low-pass filtering and downsampling CIC+COMP to obtain full-wave signal and fundamental signal.

[0055] Figure 2 This is a schematic diagram of the amplitude-frequency response of a half-band filter.

[0056] Figure 3 It is a schematic diagram of the overall structure of a freely decimable cascaded half-band filter chain.

[0057] Figure 4 It is a schematic diagram of the overall architecture of a compact in-and-out half-band filter accelerator.

[0058] Figure 5 It is a schematic diagram of the architecture of the computing core in the power metering ASIC based on the merge-in and merge-out half-band filter acceleration method.

[0059] Figure 6 It is a schematic diagram of the RTL simulation results of the output of each level of half-band filters. DETAILED DESCRIPTION

[0060] The overall idea of ​​the present invention is to solve the practical problems in the prior art, to achieve flexible adjustment of bandwidth while ensuring high precision, and to control cost and power consumption, as follows:

[0061] For the first problem existing in the prior art, the down-conversion process (low-pass filtering and down-sampling process) has large passband attenuation and inflexible bandwidth. The technical solution of the present invention is designed as follows:

[0062] In the field of electric energy metering, down-conversion processing (low-pass filtering and downsampling processing) technology runs through the entire signal processing. In the application of electric meters, the analog-to-digital converter (ADC) is first used to sample the grid signal, and then the electric energy metering application-specific integrated circuit (ASIC) obtains the full-wave signal through low-pass filtering and downsampling processing. Based on the full-wave signal, various types of electric energy signals can be calculated and processed. The fundamental signal can be obtained by processing the full-wave signal, and low-pass filtering and downsampling processing are also required to gradually reduce the calculation frequency, reduce power consumption and filter out harmonic interference.

[0063] At present, the conventional low-pass filtering and downsampling processing method adopts CIC+COMP (Cascaded Integrator-Comb and Compensator). This structure is essentially a low-pass filter, which also plays a filtering role while downsampling. Its main advantage is that it can achieve a large proportion of downsampling while having low computational complexity. However, the CIC+COMP structure has certain limitations. Its passband range is narrow and there is attenuation, which limits the bandwidth and performance of power metering.

[0064] Take the above full wave signal and fundamental wave signal acquisition as an example, as shown in Figure 1As shown in the figure, the signal frequency of the code stream data is 3.2MHz, and the full-wave signal frequency is 6.4KHz after downsampling by 512. However, the attenuation at 3.2KHz is -8.148dB, and the bandwidth is limited. For the fundamental signal, the 6.4KHz full-wave signal is downsampled by 32 to obtain a 200Hz fundamental signal, and the signal attenuation near the 50Hz fundamental is not flat, which limits the fundamental measurement performance under frequency deviation.

[0065] In addition, the downsampling rate of CIC is relatively fixed, and its downsampling is achieved through periodic sampling of the counter, which results in only obtaining full-wave signals and fundamental signals with fixed signal frequencies. In order to cope with complex scenarios and support higher standards in the future, flexible and adjustable bandwidth is necessary.

[0066] In view of the above problems, the present invention introduces a cascaded half-band filter. The amplitude-frequency characteristic of the half-band filter is as follows: Figure 2 As shown. On the one hand, the half-band filter has excellent in-band flatness and bandwidth attenuation, which can filter out noise while retaining the in-band signal with high flatness. The cascaded half-band filter meets this requirement well and can achieve an amplitude attenuation close to 0dB within the measurement bandwidth.

[0067] On the other hand, Figure 3 As shown in the figure, each half-band filter in the cascaded half-band filter chain can reduce the signal frequency to 1 / 2 of the original frequency, and N stages of half-band filters can reduce the signal frequency to 1 / 2^N of the original frequency. When it is necessary to flexibly call signals of different frequencies for calculation, the output end of the half-band filter of the corresponding frequency can be extracted, which greatly improves the flexibility.

[0068] For the second problem existing in the prior art, the three-phase seven-way signal has a huge demand for computing power, and a compact and repeatable half-band filter accelerator is needed to improve the computing power without increasing the system clock frequency. The design ideas of the technical solution of the present invention are as follows:

[0069] In the down-conversion process, the cascaded half-band filter operates at different signal frequencies, with the highest operating frequency being 51.2KHz. In three-phase metering, there are a total of 7 channels of data, which places a huge demand on computing power. Since the ADC sampling frequency is fixed, the calculation needs to be completed within a fixed time, which makes the calculation time-sensitive.

[0070] Although increasing the calculation frequency of the arithmetic logic unit (ALU) can effectively increase computing power, this will increase power consumption, which is not conducive to low-power design. Multi-stage half-band filters can reduce computing power requirements by sampling hardware, but this method will increase area overhead, thereby increasing costs.

[0071] The present invention proposes a new solution and designs a compact half-band filter accelerator basic unit, such as Figure 4 As shown in the figure, it only uses adders and registers to achieve good filtering effects. It can be called repeatedly for calculation of 7 signals. Without increasing the system clock frequency, the computing power is improved and the area overhead is reduced by reusing the compact half-band filter hardware accelerator basic unit.

[0072] For the third problem existing in the prior art, the data transmission rate between the half-band filter hardware module and the SRAM is limited. The design ideas of the technical solution of the present invention are as follows:

[0073] The half-band filter hardware module contains 9 registers. It takes 16 operation steps to read data from SRAM, but only one operation step is needed to execute the operation. Obviously, the reading of data has become the bottleneck of the operation.

[0074] Therefore, in the process of multiplexing, for the data transmission and operation flow between the half-band filter hardware module and SRAM, the present invention proposes a novel parallel-in and parallel-out structure to achieve high-speed data throughput. Dual 64-bit SRAM is used to achieve rapid transfer of large-scale data in memory, parallel writing and writing of the half-band filter hardware module, and significantly improve the operation throughput.

[0075] Summarize:

[0076] By designing a cascaded half-band filter chain, the in-band signal is retained with high flatness while filtering out noise, achieving an amplitude attenuation close to 0dB within the measurement bandwidth. By freely selecting any number of half-band filter outputs, the measurement bandwidth can be freely adjusted, greatly improving flexibility. By introducing half-band filtering operations with the same signal frequency on the half-band filter chain, the filtering effect can be freely adjusted, further improving the flexibility of customizing filtering performance.

[0077] The compact half-band filter accelerator can significantly improve computing power at a lower system clock frequency and lower area overhead, and implement complex and high-precision power metering algorithms. The parallel-in and parallel-out structure achieves high-speed data throughput, increasing computing power by about 1 times.

[0078] The half-band filter unit has good versatility and portability. The half-band filter calculation supports two calling modes: the accelerator hardware calling mode and the processor software calling mode.

[0079] On the one hand, in the accelerator hardware call mode, half-band filter calculations can be efficiently implemented by reading and reading the data of the 9 registers of the half-band filter hardware accelerator and performing shift and addition operations. More importantly, the data and control end definitions of the half-band filter hardware accelerator are simple, and it can be used as a hardware accelerator for processors with different instruction sets and different pipeline levels, with good versatility and portability.

[0080] On the other hand, by using the processor software call mode to operate on data and shift addition, half-band filter calculations can be implemented on any chip, and even concurrent half-band filter calculations can be implemented on high-performance processors, which has extremely high versatility and portability.

[0081] In one embodiment, Figure 5 As shown, the present invention designs an architecture design of a computing core in an electric power metering ASIC. The chip completes the sampling of the voltage and current signals of the power system and the operation of the electric energy metering algorithm. It can measure the effective value of the full-wave or fundamental voltage and current, the active power, reactive power, apparent power and fundamental frequency of the full-wave or fundamental voltage and current, etc. The metering results such as the effective value of the full-wave or fundamental voltage and current, active power, reactive power, etc. calculated by the ESP core and stored in the RAM or result register can be read through the Data BUS.

[0082] The computing core in the power metering ASIC has an exclusive program memory, data memory, instruction decoder, general register, program pointer (PC) generator and address mapping module. Among them, the program memory (ROM) stores the metering algorithm instruction program to be executed. The PC generator determines the address of the next instruction to be read. The instruction decoder receives the instruction code read from the program memory and performs decoding operations according to the definition of the instruction set, thereby obtaining relevant control signals for modules such as general registers, ALU and data memory, so that these modules can coordinate to complete the execution of instructions. The address mapping module can remap a virtual data address to a different physical address, so that some signal nodes of the metering can be flexibly configured, and waveform signals obtained by different filtering methods can be selected for metering. The data memory is used to store variables and results when the DSP program is running, which consists of RAM and registers (REGS). SRAM stores the intermediate variables of the DSP for use by the DSP, as well as the operation results, which can be accessed by the bus. REGS is used to store some results processed in real time by other hardware modules. ALU is used to complete various arithmetic and logical operations, including addition, subtraction, multiplication, shift, square root and comparison operations. The arbiter is responsible for arbitrating bus access to data memory and ALU, ensuring that the computing core in the power metering ASIC can execute its instruction program in an orderly manner even when there is a resource access conflict.

[0083] In one embodiment, the present invention proposes a compact in-and-out half-band filter acceleration method, including designing a specific structure and operation flow of a half-band filter accelerator, which embodies the advantages of compact structure, as follows:

[0084] like Figure 4 As shown, the overall architecture of the compact in-and-out half-band filter accelerator is shown, wherein the half-band filter module contains 9 registers (half-band filter input registers: XD0, XD1, XD2, XD3, half-band filter intermediate result registers: Y1D1, Y1D2, Y2D1, Y2D2, half-band filter result register: Y), five adding units (three adders are required to calculate Y1D1, Y2D1, Y, the multiplication -9 / 16 operation on Y2D2 is converted into shift addition calculation, and the multiplication 9 / 32 operation on XD1 is converted into shift addition calculation, a total of five adders). The above half-band filter accelerator does not use multipliers, but only uses 9 registers and five adders. Compared with the FIR filter, which does not use multipliers, it significantly reduces the area overhead.

[0085] The specific half-band filter calculation process is as follows: since the seven paths share one half-band filter accelerator, it is necessary to read the data from the SRAM before each path is operated, and store the data output in the SRAM after the operation is completed.

[0086] First, the calculation data is read in. The required data in the input registers (XD0, XD1, XD2, XD3) and the intermediate result registers (Y1D1, Y1D2, Y2D1, Y2D2) are read in from the SRAM. The read data is the result register (Y) stored in the corresponding channel in the previous half-band filter operation cycle.

[0087] Secondly, the half-band filter accelerator has 9 registers and 5 adders, supports parallel operation, and can complete the operation and obtain the result (Y) in only one operation step.

[0088] Finally, enter the calculation result storage operation. The input registers (XD1, XD2, XD3) and the intermediate result registers (Y1D1, Y1D2, Y2D1, Y2D2) are stored with the result register (Y). The input registers (XD1, XD2, XD3) and the intermediate result registers (Y1D1, Y1D2, Y2D1, Y2D2) will be called in the next half-band filter operation cycle. The result register (Y) is the calculation result of the half-band filter, which can be periodically extracted according to downsampling to realize the cascaded half-band filter chain, achieving good filtering effect and flexible bandwidth adjustment.

[0089] In one embodiment, the half-band filter hardware accelerator proposed in the present invention has a detailed design for the operation of reading calculation data and storing calculation results, reflecting the advantages of merging in and out, as follows:

[0090] The half-band filter has a total of 9 registers and 5 adders. The complete half-band filter calculation requires 16 operation steps, of which the calculation data reading operation (input registers (XD0, XD1, XD2, XD3) and intermediate result registers (Y1D1, Y1D2, Y2D1, Y2D2)) requires 8 operation steps. The operation operation requires 1 operation step. The calculation result storage operation (input registers (XD1, XD2, XD3) and intermediate result registers (Y1D1, Y1D2, Y2D1, Y2D2) and result register (Y)) requires 8 operation steps, a total of 17 operation steps.

[0091] A complete half-band filter calculation takes 17 operation steps, of which the operation operation takes only 1 operation step, and most of the operation steps are processing the reading in and reading out of data. For the half-band filter hardware accelerator that multiplexes 7 data channels to save hardware area overhead, data reading in and reading out is necessary, which is a cost reduction in exchange for computing power. However, in the power metering ASIC, higher computing power means higher main frequency and power consumption. Therefore, in order to save computing power under the premise of multiplexing the half-band filter hardware accelerator, the present invention carries out a merge-in and merge-out design.

[0092] In order to improve the data reading and writing efficiency between the half-band filter accelerator and the SRAM, the present invention proposes a solution based on register pairing and optimized storage architecture. Specifically, by pairing nine 32-bit wide data registers in pairs, parallel operation can be achieved when reading and writing data, that is, reading and writing two registers each time, which is equivalent to reading or reading 64 bits of data at the same time. To cooperate with this optimization, the width of the SRAM is expanded from 32 bits to 64 bits, and the more cost-effective single-ended SRAM design is still adopted.

[0093] For systems where the SRAM storing data is directly connected to the half-band filter accelerator, the design introduces the input and output address mapping, read and write priority control, and downsampling control mechanisms to achieve unified scheduling control. These mechanisms ensure the efficiency and consistency of data read and write operations in a multi-task concurrent environment. In bus-connected systems, in order to further improve the robustness of scheduling control, this solution adds an asynchronous FIFO as a bridge to buffer data flow and handle possible clock domain crossing issues. This design not only enhances the adaptability of the system, but also effectively avoids the bottleneck problem of bus transmission, thereby ensuring the stable transmission of data flow between different modules.

[0094] Regarding the comparison between single-ended SRAM and dual-ended SRAM, although dual-ended SRAM can realize simultaneous data reading and reading, due to its larger area requirements and more complex decoding and control logic, single-ended SRAM is selected in combination with a data reading and writing solution that combines input and output, which achieves a better area-performance ratio while ensuring high efficiency. By reducing the half-band filter calculation that originally required 17 steps to 9 steps, the overall computing efficiency has been significantly improved.

[0095] The dual-input and dual-output reading and writing improves the data throughput rate (reduced from 17 operation steps to 9), but also increases the complexity of the structure. For this reason, the present invention sets a special instruction identifier to guide the data reading and reading operations of the half-band filter accelerator.

[0096] The half-band filter chain is extremely flexible and can freely select the bandwidth of the output signal. Furthermore, when the filtering effect of a certain level of signal does not meet the requirements, an additional level of half-band filtering operation can be added without performing downsampling. This further enriches the flexibility of the half-band filter chain and can freely extract signals with different bandwidths and different filtering performances.

[0097] like Figure 6 As shown in the figure, in one embodiment, the RTL simulation results of the output of each level of half-band filter can be seen, as the half-band filtering operation and downsampling are carried out, the waveform signal achieves the expected effect. It can be observed from the figure that the RTL simulation model presents five waveforms from top to bottom, which represent the results of the same signal after filtering by the half-band filter chain. The output of each level of the filter not only shows a trend of decreasing signal frequency, but also the overall characteristics of the signal are well preserved and inherited. Specifically, in each layer of waveform, the amplitude change, phase information and spectrum structure of the signal are still clearly discernible after filtering and downsampling, which shows that the filter maintains the integrity and stability of the signal while achieving frequency reduction.

[0098] Summarize:

[0099] By designing a cascaded half-band filter chain, the in-band signal is retained with high flatness while filtering out noise, achieving an amplitude attenuation close to 0dB within the measurement bandwidth. By freely selecting any number of half-band filter outputs, the measurement bandwidth can be freely adjusted, greatly improving flexibility. By introducing half-band filtering operations with the same signal frequency on the half-band filter chain, the filtering effect can be freely adjusted, further improving the flexibility of customizing filtering performance.

[0100] The compact half-band filter accelerator can significantly improve computing power at a lower system clock frequency and lower area overhead, and implement complex and high-precision power metering algorithms. The parallel-in and parallel-out structure achieves high-speed data throughput, increasing computing power by about 1 times.

[0101] The cascaded half-band filter chain is suitable for both accelerator hardware and processor software calling modes. The data and control end definitions of the half-band filter hardware accelerator are simple, and it can be used as a hardware accelerator for processors with different instruction sets and different pipeline levels. At the same time, the half-band filter calculation process is simple and standardized, and the half-band filter calculation can be implemented on any chip in the processor software calling mode, which has extremely high versatility and portability.

[0102] In a specific implementation, the present application provides a computer storage medium and a corresponding data processing unit, wherein the computer storage medium can store a computer program, and when the computer program is executed by the data processing unit, the invention content of a cascaded half-band filter chain under an electric energy metering chip, an acceleration method and a chip provided by the present invention, as well as some or all steps in each embodiment. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0103] Those skilled in the art can clearly understand that the technical solutions in the embodiments of the present invention can be implemented by means of computer programs and their corresponding general hardware platforms. Based on such an understanding, the technical solutions in the embodiments of the present invention can be essentially or partly contributed to the prior art in the form of computer programs, i.e., software products, which can be stored in a storage medium and include several instructions for enabling a device including a data processing unit (which can be a personal computer, a server, a single-chip microcomputer, an MCU or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0104] The present invention provides a cascaded half-band filter chain under an electric energy metering chip, an acceleration method, and a chip idea and method. There are many methods and ways to implement the technical solution. The above is only a preferred implementation of the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made, and these improvements and modifications should also be regarded as the protection scope of the present invention. All components not specified in this embodiment can be implemented by existing technologies.

Claims

1. A method for accelerating a cascaded half-band filter under an electric energy metering chip, characterized in that: The following steps are involved: Step 1, construct an in-and-out half-band filter accelerator; Step 2: Use the half-band filter accelerator to perform cascade calculation to complete the cascade half-band filter acceleration.

2. The method for accelerating the cascaded half-band filter under an electric energy metering chip according to claim 1, characterized in that: The in-and-out half-band filter accelerator specifically comprises: A merge-in-and-out half-band filter for performing calculations and a control module for controlling the merge-in-and-out half-band filter.

3. The method for accelerating the cascaded half-band filter under an electric energy metering chip according to claim 2 is characterized in that: The merge-in and merge-out half-band filter specifically comprises: 9 registers and 5 adding units; The register specifically includes: 4 half-band filter input registers, namely, a first input register XD0, a second input register XD1, a third input register XD2 and a fourth input register XD3; 4 half-band filter intermediate result registers, namely a first intermediate result register Y1D1, a second intermediate result register Y1D2, a third intermediate result register Y2D1 and a fourth intermediate result register Y2D2; And 1 half-band filter result register Y; The adding unit specifically comprises: The first adder S1, the second adder S2 and the third adder S3 are used to calculate the data in the first intermediate result register Y1D1, the third intermediate result register Y2D1 and the half-band filter result register Y respectively; A fourth adder S4, used for converting the multiplication 9 / 32 operation performed on the second input register XD1 into a shift addition operation; A fifth adder S5, used for converting the multiplication-9 / 16 operation performed on the fourth intermediate result register Y2D2 into a shift addition operation; The first input register XD0, the third input register XD2 and the second intermediate result register Y1D2 are connected to the second adder S2 as inputs, and the second adder S2 adds the above inputs and outputs them to the first intermediate result register Y1D1; The second input register XD1, the fourth input register XD3 and the fourth intermediate result register Y2D2 are connected to the third adder S3 as inputs, and the third adder S3 adds the above inputs and outputs them to the third intermediate result register Y2D1; The first intermediate result register Y1D1 and the third intermediate result register Y2D1 are connected to the first adder S1 as inputs, and the first adder S1 adds the above inputs and outputs them to the half-band filter result register Y; The second input register XD1 is connected to the fourth adder S4 as an input, and the fourth adder S4 adds the shift values ​​of the above inputs and outputs the sum to the third adder S3; The fourth intermediate result register Y2D2 is connected to the fifth adder S5 as an input. The fifth adder S5 adds the shift values ​​of the above inputs and outputs the added values ​​to the third adder S3.

4. The method for accelerating the cascaded half-band filter under an electric energy metering chip according to claim 3 is characterized in that: The control module specifically includes: An input and output address mapping module for performing read and write control, wherein the input and output address mapping module is respectively connected with the 9 register data and performs data exchange; The merge-in and merge-out address mapping modules are also connected to the static random access memory SRAM data and perform data interaction to adapt to the dedicated DSP module and the general processor; The in-and-out address mapping module is also connected to the decoder Decoder and the read-only memory ROM data, and is used to control the in-and-out half-band filter. The control includes noise reduction sampling control, priority control and channel mapping.

5. The method for accelerating the cascaded half-band filter under an electric energy metering chip according to claim 4 is characterized in that: The calculation process of incorporating and outputting the half-band filter is implemented in hardware or software; The in-and-out half-band filter accelerator is implemented in hardware or software; The method is implemented in software, that is, it is implemented by calling software under processors with different instruction sets and different pipeline levels.

6. A cascaded half-band filter chain under an electric energy metering chip, characterized in that: Based on the cascaded half-band filter acceleration method described in any one of claims 1 to 5, the merge-in and merge-out half-band filter accelerator is used as a half-band filter to construct a cascaded half-band filter chain for selecting calculation results of different half-band filters in the electric energy metering chip to perform the electric energy metering.

7. The cascaded half-band filter chain under the electric energy metering chip according to claim 6, characterized in that: The cascaded half-band filter chain comprises: Cascaded half-band filter chains for downsampling and cascaded half-band filter chains for free call of signals with different frequencies.

8. The cascaded half-band filter chain under the electric energy metering chip according to claim 7, characterized in that: The cascaded half-band filter chain for downsampling specifically comprises: The cascaded half-band filter chain for downsampling is implemented by using a half-band filter accelerator for cascading.

9. The cascaded half-band filter chain under the electric energy metering chip according to claim 8, characterized in that: The cascaded half-band filter chain for freely accessing signals of different frequencies specifically comprises: N stages of in-and-out half-band filter accelerators are cascaded, wherein each stage of in-and-out half-band filter accelerator reduces the frequency of the input signal to half of the output frequency, thereby realizing the cascaded half-band filter chain for freely accessing signals of different frequencies.

10. An electric energy metering chip, characterized in that: By adopting the method described in any one of claims 1 to 5, using the program memory, data memory, instruction decoder, general register, program pointer generator and address mapping module in the power metering chip, the cascaded half-band filter chain described in any one of claims 6 to 9 is constructed to realize the application of power metering.

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