Low-delay TCP or UDP checksum calculation method based on FPGA

Abstract

The invention discloses a low-delay TCP (Transmission Control Protocol) or UDP (User Datagram Protocol) checksum calculation method based on an FPGA (Field Programmable Gate Array), which relates to the technical field of data communication and comprises the following steps of: determining the scale, performance and dominant frequency parameters of the FPGA, and multiplying the bit width of original data to be calculated before the data is input into a buffer area; dividing the multiplied data bit width into a plurality of 16b-it data segments based on DSP resources in the FPGA, and performing accumulation operation in parallel; and processing a parallel accumulation result by adopting a pipeline mode, and adjusting sequential logic. Through the parallel processing capability of the FPGA, the calculation of the TCP / UDP checksum can process a plurality of data segments at the same time, the overall processing speed is remarkably improved, the calculation of the checksum is completed in a short time by designing the parallel accumulation operation and the pipeline structure, the uncertainty and the error rate in the calculation process are reduced, and the calculation efficiency is improved. The reliability and stability of data transmission are further enhanced, and the risks of retransmission and packet loss caused by data errors are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a method for calculating a checksum of a TCP or UDP with low latency based on FPGA. Background Art

[0002] With the development of TOE technology, especially the widespread application of low-latency technology, there is an urgent need for optimization methods for related calculations of various types of messages. Traditional software methods have strict requirements on the computing power of the CPU, especially with 100GE Ethernet. The emergence of TOE technology can move part of the TCP / IP protocol stack down to hardware such as FPGA for implementation. The delay of the TCP / UDP checksum calculation method is a key factor affecting the overall delay of TOE. FPGA has the advantages of high performance and programmability. Many TOE systems are implemented based on FPGA, which can shorten the millisecond processing time of the software protocol stack to the nanosecond level of FPGA. There is a field called "checksum" in the TCP / UDP header, which is used to detect whether there are errors in the data transmission process.

[0003] For example, Chinese patent publication number CN115037814A and a method for determining a TCP / UDP checksum based on FPGA hardware acceleration include: the FPGA receives a data packet, calculates a checksum on the TCP / UDP data payload portion of the data packet and obtains a calculation result R1, and adds the calculation result R1 to one end of the data packet to obtain a new data packet containing a private header.

[0004] In the prior art, FPGA with excellent computing power is used to implement the data payload checksum calculation part which has a greater impact on performance in the checksum calculation process, so as to significantly increase the checksum calculation rate, and significantly improve the processing efficiency and the check accuracy. However, since the result after the checksum calculation needs to be filled back into the TCP / UDP header, the traditional implementation method is to store the message in the FPGA internal RAM, use the address accumulation method to read the data while performing related accumulation operations, and finally invert the result, and then read the message from the RAM and replace the checksum with the TCP / UDP checksum position in the corresponding clock cycle. However, it is necessary to wait for one more message storage cycle, which increases the delay of the overall TOE framework to a certain extent. Therefore, a low-latency TCP or UDP checksum calculation method based on FPGA is proposed. Summary of the invention

[0005] The present invention aims to provide a method for calculating a checksum of TCP or UDP with low latency based on FPGA, so as to solve the problems raised in the above-mentioned background technology.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A method for calculating a low-latency TCP or UDP checksum based on FPGA includes the following steps:

[0008] Step 1: clarify the scale, performance and main frequency parameters of the FPGA so as to determine the multiplication multiple of the data bit width in the future, and multiply the bit width of the original data to be calculated before entering the buffer, and the multiplication multiple is determined according to the specific performance parameters of the FPGA;

[0009] Step 2: Based on the DSP resources inside the FPGA, the multiplied data bit width is divided into multiple 16-bit data segments, and the accumulation operation is performed in parallel, which can significantly reduce the number of clock cycles required to complete the accumulation operation;

[0010] Step 3, process the parallel accumulation results in a pipeline manner, and adjust the timing logic to complete the parallel accumulation calculation within 2-3 clock cycles, and obtain a large-bit width accumulation parallel calculation result to solve the problem that the internal timing of the FPGA is difficult to converge;

[0011] Step 4: Based on the obtained large-bit-width accumulated parallel calculation results, an enable signal for reading the original data bit-width message is generated in advance, without waiting for the entire original message cache to be complete before reading, which reduces the delay, and the parallel accumulated result is negated to generate a TCP / UDP checksum result. The checksum result is the key data that is subsequently filled back into the TCP / UDP header. The checksum will be used to detect whether there is an error in the data during transmission;

[0012] Step 5, combined with the enable signal of the original data bit width message that has been read in advance, after the checksum result is generated, within the corresponding clock cycle, the checksum result is backfilled into the checksum field of the TCP / UDP header, and the reading and subsequent processing of the message are completed.

[0013] A further improvement of the technical solution of the present invention is that in step 1, the process of doubling the bit width of the original data to be calculated is:

[0014] Step 101, evaluate the scale of the FPGA, analyze the performance of the FPGA, and determine the working main frequency of the FPGA, wherein the scale evaluation of the FPGA includes determining the number of logic units, available DSP resources, memory resources, and I / O ports of the FPGA, which will affect the data bit width and parallel processing capability that can be processed. The performance analysis of the FPGA includes analyzing the performance processing speed and parallel processing capability of the FPGA, understanding the maximum data bit width and processing speed that the FPGA can support, and the timing requirements under different data bit widths. The working main frequency of the FPGA directly affects the data processing speed and clock cycle. The higher the main frequency, the more data can be processed in each clock cycle in theory.

[0015] Step 102, according to the size, performance and main frequency parameters of the FPGA, the corresponding data bit width multiplication factor is calculated, and the multiplication factor should be able to fully utilize the resources of the FPGA while avoiding exceeding its processing capacity, so as to determine the data type, range and accuracy requirements to be processed;

[0016] Step 103, using Verilog hardware description language to design a data bit width multiplication circuit, so that the original data is subjected to a bit width multiplication operation before the data enters the input buffer, and the data bit width multiplication circuit is synchronized with the clock system of the FPGA, and the timing parameters are adjusted to avoid data loss or misalignment;

[0017] Step 104, implement the data bit width multiplication circuit design on the FPGA, and perform simulation tests to verify whether the data bit width multiplication is correctly performed, and check whether the function and performance of the data bit width multiplication circuit meet expectations.

[0018] A further improvement of the technical solution of the present invention is that in step 2, the process of performing the accumulation operation in parallel is:

[0019] Step 201, read m bits of original data from a data source of the FPGA module, so that its original bit width is m, and multiply the original bit width from m bits to k×m bits, where k is a data bit width multiplication factor, which depends on the resources and performance of the FPGA;

[0020] Step 202, split the multiplied data into 16-bit data segments, each 16-bit data segment can be processed independently;

[0021] Step 203, using the DSP resources inside the FPGA, distributes the divided multiple 16-bit data segments to different DSP resources. After receiving the data, each DSP resource performs accumulation operations in parallel, calculates the accumulation operation results of each DSP resource, and outputs the overall parallel accumulation operation results in each clock cycle.

[0022] A further improvement of the technical solution of the present invention is that the calculation expression of the accumulation operation result of each DSP resource is:

[0023]

[0024] Among them, S i is the result of the accumulation of the i-th 16-bit data segment, a ij is the value of the jth bit in the i-th 16-bit data segment, where i ranges from 0 to The index of the 16-bit data segment after segmentation. ij The value range is 0 to 2 15 -1.

[0025] A further improvement of the technical solution of the present invention is that the calculation expression of the overall parallel accumulation operation result is:

[0026]

[0027] Among them, S is the overall parallel accumulation result, S i，n is the cumulative result of each DSP resource output, n is the number of DSP resources, a and b are reference values ​​used to adjust the cumulative result, m is the original data bit width, k is the data bit width multiplication factor, and i is from 0 to The index of the 16-bit data segment after segmentation, S i It is the result of the accumulation of the i-th 16-bit data segment.

[0028] A further improvement of the technical solution of the present invention is that in step 3, the process of obtaining the large bit width cumulative parallel calculation result is:

[0029] Step 301, according to the processing capability of the FPGA and the required processing speed, determine the number of pipeline stages, each stage will process a part of the computing task, and distribute the parallel accumulation computing tasks to each pipeline stage, for example, using a three-stage pipeline, the first stage processes part of the accumulation, the second stage processes another part of the accumulation, and the third stage completes the final accumulation and output;

[0030] Step 302, at the end of each pipeline stage, a register is set to store the intermediate result of the current pipeline stage, the register passes the data to the next stage under the drive of the clock signal, and a parallel computing unit is implemented in each pipeline stage to execute the computing task assigned to the current pipeline stage;

[0031] Step 303, according to the operating frequency of the FPGA and the processing time required for each pipeline stage, the workload planned to be completed in each clock cycle is calculated, and then the timing of each pipeline stage is optimized and adjusted to ensure smooth data transmission in the pipeline and avoid conflicts and data competition between clock domains;

[0032] Step 304, before processing the data, the pipeline is initialized to put all registers and parallel computing units in the correct initial state, and the data to be processed is input into the first stage of the pipeline to start parallel processing of the data;

[0033] Step 305 controls the start, stop and reset operations of each pipeline stage to ensure that the pipeline can work stably under different operating conditions, complete the parallel accumulation calculation within 2-3 clock cycles, and output the final large-bit width accumulation parallel calculation result at the last stage of the pipeline.

[0034] A further improvement of the technical solution of the present invention is that in step 4, the process of generating the TCP / UDP checksum result is:

[0035] Step 401, in the FPGA, multiple 16-bit data segments are accumulated through parallel processing and pipeline technology to obtain a series of intermediate accumulation results D p , and add all the intermediate cumulative results D p Merge to generate a large bit width accumulation result, ensure that the accumulation result is completed within the predetermined clock cycle, and store it in the corresponding register;

[0036] Step 402, setting a state machine in the pipeline to track the amount of data currently accumulated, and when the amount of accumulated data reaches a preset total message length ratio, generating a read enable signal, the read enable signal is used to control the operation of reading data from the original data cache;

[0037] Step 403, using the generated read enable signal to control the data flow, starting to read the message of the original data bit width from the input buffer of the FPGA, ensuring that the reading operation is synchronized with the data generation operation to avoid data loss or misalignment;

[0038] Step 404, at the last stage of the pipeline, all parallel accumulation results are collected and merged into a single large-bit-width accumulation result. If the bit width of the large-bit-width accumulation result exceeds the 16 bits required by the TCP / UDP checksum, it is necessary to truncate; if the bit width of the large-bit-width accumulation result is less than the 16 bits required by the TCP / UDP checksum, it is necessary to sign-extend or zero-extend;

[0039] Step 405, performing a bitwise inversion operation on the large bit width accumulation result, specifically comprising: for each intermediate accumulation result D p , calculate the logarithm with base 2 rounded up to determine each intermediate accumulation result D p The number of digits to be represented, and each intermediate cumulative result D p Perform division operation and perform modulo 2 on the calculation result 16 Operation, each intermediate accumulation result D p Normalize to 16 bits, and add all normalized intermediate results D p The values ​​are added to get a cumulative sum, which represents the combined result of all data segments. The cumulative sum is bitwise inverted, and then 1 is added to implement binary complement to generate the final TCP / UDP checksum result.

[0040] A further improvement of the technical solution of the present invention is that the calculation expression of the TCP / UDP checksum result is:

[0041]

[0042] Where C is the final TCP / UDP checksum result, M is the number of 16-bit data segments processed in parallel, and D p is the intermediate accumulation result, is rounded up to base 2 (D p +1), used to determine how many bits are needed to represent each segment, mod 2 16 Represents a modulo operation to ensure that the result is within the range of a 16-bit integer. Represents a bitwise exclusive OR operation, used to implement two's complement.

[0043] A further improvement of the technical solution of the present invention is that in step 5, the process of backfilling the checksum result into the TCP / UDP header checksum field is:

[0044] Step 501, the final TCP / UDP checksum result is stored in a register inside the FPGA, which is close to the output or control logic so that it can be backfilled in the appropriate clock cycle. When reading the TCP / UDP message, the message header information is parsed to find the exact location of the TCP / UDP header checksum field, and the IP header is read and parsed (for IP packets). Since the TCP / UDP header follows the IP header, and the IP header contains instructions about the upper layer protocol (such as TCP or UDP);

[0045] Step 502, find the checksum field of the TCP / UDP header, use the checksum result stored in the register to update the checksum field of the TCP / UDP header, and fill the calculated checksum value in the checksum field within the corresponding clock cycle to complete the checksum backfill operation to ensure data synchronization and consistency;

[0046] Step 503, the check and backfill are completed, the entire message is read, and the message reading operation is marked as completed, the message is sent to the next node of the network, and the message is stored for subsequent use.

[0047] Due to the adoption of the above technical solution, the present invention has the following technical advances compared with the prior art:

[0048] 1. The present invention provides a method for calculating a low-latency TCP or UDP checksum based on FPGA. Through the parallel processing capability of FPGA, the calculation of TCP / UDP checksum can process multiple data segments at the same time, significantly improving the overall processing speed. By designing parallel accumulation operations and pipeline structures, the calculation of the checksum can be completed in a short time, reducing the uncertainty and error rate in the calculation process, further enhancing the reliability and stability of data transmission, and reducing the risk of retransmission and packet loss due to data errors.

[0049] 2. The present invention provides a method for calculating a low-latency TCP or UDP checksum based on FPGA. By generating a read enable signal and pipeline technology in advance, the waiting time for data processing is reduced, and processing can be started before the data arrives completely, thereby reducing the overall processing delay. Moreover, for the calculation of the TCP / UDP checksum, the FPGA can flexibly configure the parallel accumulation process and pipeline structure according to the message size, data bit width and transmission rate parameters to achieve optimal performance and resource utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0051] Figure 1 is a flow chart of the method of the present invention;

[0052] Figure 2 A flow chart of performing cumulative operations in parallel according to the present invention;

[0053] Figure 3 Flowchart for generating TCP / UDP checksum results for the present invention. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] Embodiment 1, as Figure 1 , Figure 2 As shown, the present invention provides a method for calculating a checksum of a low-latency TCP or UDP based on FPGA, comprising the following steps:

[0056] Step 1: Clarify the scale, performance, and main frequency parameters of the FPGA in order to determine the multiplication multiple of the data bit width in the future, and multiply the original data bit width to be calculated before entering the buffer. The multiplication multiple is determined according to the specific performance parameters of the FPGA. Evaluate the scale of the FPGA, analyze the performance of the FPGA, and determine the working main frequency of the FPGA. The scale evaluation of the FPGA includes determining the number of logic units, available DSP resources, memory resources, and the number of I / O ports of the FPGA, which will affect the data bit width and parallel processing capabilities that can be processed. The performance analysis of the FPGA includes analyzing the performance processing speed and parallel processing capabilities of the FPGA, understanding the maximum data bit width and processing speed that the FPGA can support, as well as the timing requirements under different data bit widths. The working main frequency of the FPGA directly affects data processing Speed ​​and clock cycle. The higher the main frequency, the more data can be processed in each clock cycle in theory. According to the size, performance and main frequency parameters of FPGA, calculate the corresponding data bit width multiplication multiple. The multiplication multiple should be able to make full use of the resources of FPGA while avoiding exceeding its processing capacity to determine the type of data, range and accuracy requirements to be processed. Use Verilog hardware description language to design data bit width multiplication circuit so that the original data is multiplied before entering the input buffer, and synchronize the data bit width multiplication circuit with the FPGA clock system, adjust the timing parameters to avoid data loss or misalignment, implement the data bit width multiplication circuit design on FPGA, and perform simulation tests to verify whether the data bit width multiplication is performed correctly and check whether the function and performance of the data bit width multiplication circuit meet expectations.

[0057] Step 2: Based on the DSP resources inside the FPGA, the multiplied data bit width is divided into multiple 16-bit data segments, and the accumulation operation is performed in parallel, which can significantly reduce the number of clock cycles required to complete the accumulation operation. The original data of m bits is read from the data source of the FPGA module, so that its original bit width is m, and the original bit width is doubled from m bits to k×m bits, where k is the data bit width multiplication factor, which depends on the resources and performance of the FPGA. The multiplied data is divided into 16-bit data segments, each 16-bit data segment can be processed independently, and the DSP resources inside the FPGA are used to distribute the divided multiple 16-bit data segments to different DSP resources. After receiving the data, each DSP resource performs accumulation operations in parallel, calculates the accumulation operation results of each DSP resource, and outputs the overall parallel accumulation operation results in each clock cycle;

[0058] Furthermore, the calculation expression of the accumulation operation result of each DSP resource is:

[0059]

[0060] Among them, S i is the result of the accumulation of the i-th 16-bit data segment, a ij is the value of the jth bit in the i-th 16-bit data segment, where i ranges from 0 to The index of the 16-bit data segment after segmentation. ij The value range is 0 to 2 15 -1, is a value in the 16-bit data segment, S i The value range depends on a ij The value is 0 to 2 15 -The cumulative sum of 1;

[0061] Furthermore, the calculation expression of the overall parallel accumulation operation result is:

[0062]

[0063] Among them, S is the overall parallel accumulation result, S i，n is the cumulative result of each DSP resource output, n is the number of DSP resources, a and b are reference values ​​used to adjust the cumulative result, m is the original data bit width, k is the data bit width multiplication factor, and i is from 0 to The index of the 16-bit data segment after segmentation, S i It is the result of the accumulation of the i-th 16-bit data segment. The value range of S is all S i The result of the accumulation and subtraction of the limit function is used to simulate the adjustment of the accumulation result when the number of DSP resources increases infinitely. Through this parallel processing method, each DSP resource can independently process one or more 16-bit data segments in each clock cycle, which significantly reduces the number of clock cycles required to complete the entire data accumulation, thereby improving the data processing speed and the performance of the overall system. The model utilizes the parallel capability of DSP resources and the high-speed processing capability of FPGA to achieve high-speed and efficient data processing;

[0064] Step 3, process the parallel accumulation results in a pipeline manner, and adjust the timing logic to complete the parallel accumulation calculation within 2-3 clock cycles to obtain a large bit width accumulation parallel calculation result, so as to solve the problem that the internal timing of the FPGA is difficult to converge. According to the processing capability of the FPGA and the required processing speed, the number of pipeline stages is determined. Each stage will process a part of the calculation task, and the parallel accumulation calculation task is assigned to each pipeline stage. For example, a three-stage pipeline is used, the first stage processes part of the accumulation, the second stage processes another part of the accumulation, and the third stage completes the final accumulation and output. At the end of each pipeline stage, a register is set to store the intermediate result of the current pipeline stage. The register passes the data to the next stage under the drive of the clock signal, and a parallel calculation unit is implemented in each pipeline stage. Execute the computing tasks assigned to the current pipeline stage, calculate the workload planned to be completed in each clock cycle according to the operating frequency of the FPGA and the processing time required for each pipeline stage, and then optimize and adjust the timing of each pipeline stage to ensure that data is smoothly transmitted in the pipeline and avoid conflicts and data competition between clock domains. Before processing data, initialize the pipeline to make all registers and parallel computing units in the correct initial state, input the data to be processed into the first stage of the pipeline, start parallel processing of the data, control the start, stop and reset operations of each pipeline stage, ensure that the pipeline can work stably under different operating conditions, complete parallel accumulation calculations within 2-3 clock cycles, and output the final large-bit width accumulation parallel calculation results at the last stage of the pipeline;

[0065] Step 4: Based on the obtained large-bit-width accumulated parallel calculation results, an enable signal for reading the original data bit-width message is generated in advance, without waiting for the entire original message cache to be complete before reading, which reduces the delay, and the parallel accumulated result is negated to generate a TCP / UDP checksum result. The checksum result is the key data that is subsequently filled back into the TCP / UDP header. The checksum will be used to detect whether there is an error in the data during transmission;

[0066] Step 5, combined with the enable signal of the original data bit width message that has been read in advance, after the checksum result is generated, within the corresponding clock cycle, the checksum result is backfilled into the checksum field of the TCP / UDP header, and the reading and subsequent processing of the message are completed.

[0067] Embodiment 2, as Figure 3 As shown, based on Example 1, the present invention provides a technical solution: Preferably, in step 4, the process of generating the TCP / UDP checksum result is:

[0068] Inside the FPGA, through parallel processing and pipeline technology, the multiple 16-bit data segments after segmentation are accumulated to obtain a series of intermediate accumulation results D p , and add all the intermediate cumulative results D p Merge to generate a large-bit-width accumulation result, ensure that the accumulation result is completed within a predetermined clock cycle, store it in the corresponding register, set a state machine in the pipeline, track the current amount of accumulated data, and generate a read enable signal when the accumulated data reaches a preset total message length ratio. The read enable signal is used to control the operation of reading data from the original data cache. The generated read enable signal is used to control the data flow, and the message of the original data bit width is read from the input buffer of the FPGA to ensure that the reading operation is synchronized with the data generation operation to avoid data loss or misalignment. In the final stage of the pipeline, all parallel accumulation results are collected and merged into a single large-bit-width accumulation result. If the bit width of the large-bit-width accumulation result exceeds the 16 bits required by the TCP / UDP checksum, it needs to be truncated; if the bit width of the large-bit-width accumulation result is less than the 16 bits required by the TCP / UDP checksum, it needs to be sign-extended or zero-extended, and the large-bit-width accumulation result is bit-inverted, specifically including: for each intermediate accumulation result D p , calculate the logarithm with base 2 rounded up to determine each intermediate accumulation result D p The number of digits to be represented, and each intermediate cumulative result D p Perform division operation and perform modulo 2 on the calculation result 16 Operation, each intermediate accumulation result D p Normalize to 16 bits, and add all normalized intermediate results D p The values ​​are added to get a cumulative sum, which represents the combined result of all data segments. The cumulative sum is bitwise inverted, and then 1 is added to implement the binary complement to generate the final TCP / UDP checksum result;

[0069] Furthermore, the calculation expression of the TCP / UDP checksum result is:

[0070]

[0071] Where C is the final TCP / UDP checksum result, M is the number of 16-bit data segments processed in parallel, and D p is the intermediate accumulation result, is rounded up to base 2 (D p +1), used to determine how many bits are needed to represent each segment, mod 2 16 Represents a modulo operation to ensure that the result is within the range of a 16-bit integer. Indicates a bitwise XOR operation, which is used to implement binary complement. The value range of C is 0 to 2. 16 -1, M represents the number of data segments involved in the calculation, and its value depends on the FPGA processing capability and the size of the data message. 2 Represents the logarithm with base 2, which is used to calculate the bit width of each data segment. Indicates the round-up function, ensuring that each data segment has enough bit width to represent it. The value of C will be affected by all D p The influence of the value is calculated step by step through the parallel processing inside the FPGA in each clock cycle. p When the value of is large, log 2 (D p +1) will increase, resulting in more bits used to represent each data segment, which may affect the final checksum result, bitwise XOR operation Ensure that the calculation of the checksum result complies with the requirements of the TCP / UDP protocol regarding binary complement;

[0072] In step 5, the process of filling the checksum result back into the TCP / UDP header checksum field is as follows:

[0073] The final TCP / UDP checksum result is stored in a register inside the FPGA, which is close to the output or control logic so that it can be backfilled in the appropriate clock cycle. When reading the TCP / UDP message, the message header information is parsed to find the exact location of the TCP / UDP header checksum field, and the IP header is read and parsed (for IP packets). Since the TCP / UDP header follows the IP header and the IP header contains instructions about the upper layer protocol (such as TCP or UDP), the checksum field of the TCP / UDP header is found, and the checksum result stored in the register is used to update the checksum field of the TCP / UDP header. The calculated checksum value is backfilled in the checksum field within the corresponding clock cycle to complete the checksum backfill operation to ensure data synchronization and consistency. After the checksum backfill is completed, the entire message is read, and the message reading operation is marked as completed. The message is sent to the next node of the network and the message is stored for subsequent use.

[0074] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for calculating a low-latency TCP or UDP checksum based on FPGA, characterized in that: The following steps are involved: Step 1, clarify the scale, performance and main frequency parameters of the FPGA, and double the bit width of the original data to be calculated before entering the buffer; Step 2: divide the doubled data bit width into multiple 16-bit data segments based on the DSP resources inside the FPGA, and perform accumulation operations in parallel; Step 3, process the parallel accumulation results in a pipeline manner, and adjust the timing logic to complete the parallel accumulation calculation within 2-3 clock cycles to obtain a large bit width accumulation parallel calculation result; Step 4: Based on the obtained large bit width accumulated parallel calculation result, an enable signal for reading the original data bit width message is generated in advance, and the parallel accumulated result is inverted to generate a TCP / UDP checksum result; Step 5, combined with the enable signal of the original data bit width message that has been read in advance, after the checksum result is generated, within the corresponding clock cycle, the checksum result is backfilled into the checksum field of the TCP / UDP header, and the reading and subsequent processing of the message are completed.

2. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 1, characterized in that: In step 1, the process of doubling the bit width of the original data to be calculated is: Step 101, evaluating the scale of the FPGA, analyzing the performance of the FPGA, and determining the operating main frequency of the FPGA, wherein the scale evaluation of the FPGA includes determining the number of logic units, available DSP resources, memory resources, and the number of I / O ports of the FPGA, and the performance analysis of the FPGA includes analyzing the performance processing speed and parallel processing capability of the FPGA; Step 102, calculating the corresponding data bit width multiplication factor according to the size, performance and main frequency parameters of the FPGA to determine the data type, range and accuracy requirements to be processed; Step 103, using Verilog hardware description language to design a data bit width multiplication circuit, so as to perform a bit width multiplication operation on the original data before the data enters the input buffer, and synchronize the data bit width multiplication circuit with the clock system of the FPGA; Step 104, implement the data bit width multiplication circuit design on the FPGA, and perform simulation tests to verify whether the data bit width multiplication is correctly performed, and check whether the function and performance of the data bit width multiplication circuit meet expectations.

3. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 2, characterized in that: In step 2, the process of performing the accumulation operation in parallel is: Step 201, read m-bit original data from the data source of the FPGA module, so that its original bit width is m, and multiply the original bit width from m bits to k×m bits, where k is the data bit width multiplication factor; Step 202, split the multiplied data into 16-bit data segments, each 16-bit data segment can be processed independently; Step 203, using the DSP resources inside the FPGA, distributes the divided multiple 16-bit data segments to different DSP resources. After receiving the data, each DSP resource performs accumulation operations in parallel, calculates the accumulation operation results of each DSP resource, and outputs the overall parallel accumulation operation results in each clock cycle.

4. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 3, characterized in that: The calculation expression of the accumulation operation result of each DSP resource is: Among them, S i is the result of the accumulation of the i-th 16-bit data segment, a ij is the value of the jth bit in the i-th 16-bit data segment, where i ranges from 0 to The index of the 16-bit data segment after segmentation.

5. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 4, characterized in that: The calculation expression of the overall parallel accumulation operation result is: Among them, S is the overall parallel accumulation result, S i，n is the cumulative result of each DSP resource output, n is the number of DSP resources, a and b are reference values ​​used to adjust the cumulative result, m is the original data bit width, k is the data bit width multiplication factor, and i is from 0 to The index of the 16-bit data segment after segmentation, S i It is the result of the accumulation of the i-th 16-bit data segment.

6. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 5, characterized in that: In step 3, the process of obtaining the large bit width accumulation parallel calculation result is as follows: Step 301, according to the processing capability of the FPGA and the required processing speed, determine the number of pipeline stages, each stage will process a part of the computing task, and distribute the parallel accumulated computing tasks to each pipeline stage; Step 302, at the end of each pipeline stage, a register is set to store the intermediate result of the current pipeline stage, the register passes the data to the next stage under the drive of the clock signal, and a parallel computing unit is implemented in each pipeline stage to execute the computing task assigned to the current pipeline stage; Step 303, calculating the workload planned to be completed in each clock cycle according to the operating frequency of the FPGA and the processing time required for each pipeline stage, and then optimizing and adjusting the timing of each pipeline stage; Step 304, before processing the data, the pipeline is initialized to put all registers and parallel computing units in the correct initial state, and the data to be processed is input into the first stage of the pipeline to start parallel processing of the data; Step 305, control the start, stop and reset operations of each pipeline stage, complete the parallel accumulation calculation within 2-3 clock cycles, and output the final large-bit width accumulation parallel calculation result at the last stage of the pipeline.

7. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 6, characterized in that: In step 4, the process of generating the TCP / UDP checksum result is: Step 401, in the FPGA, multiple 16-bit data segments are accumulated through parallel processing and pipeline technology to obtain a series of intermediate accumulation results D p , and add all the intermediate cumulative results D p Merge to generate a large-bit-width accumulation result and store it in the corresponding register; Step 402, setting a state machine in the pipeline to track the amount of data currently accumulated, and when the amount of accumulated data reaches a preset total message length ratio, generating a read enable signal, the read enable signal is used to control the operation of reading data from the original data cache; Step 403, using the generated read enable signal to control the data flow, and starting to read the message of the original data bit width from the input buffer of the FPGA; Step 404, at the last stage of the pipeline, all parallel accumulation results are collected and merged into a single large-bit-width accumulation result. If the bit width of the large-bit-width accumulation result exceeds the 16 bits required by the TCP / UDP checksum, it is necessary to truncate; if the bit width of the large-bit-width accumulation result is less than the 16 bits required by the TCP / UDP checksum, it is necessary to sign-extend or zero-extend; Step 405, performing a bitwise inversion operation on the large bit width accumulation result, specifically comprising: for each intermediate accumulation result D p , calculate the logarithm with base 2 rounded up to determine each intermediate accumulation result D p The number of digits to be represented, and each intermediate cumulative result D p Perform division operation and perform modulo 2 on the calculation result 16 Operation, each intermediate accumulation result D p Normalize to 16 bits, and add all normalized intermediate results D p The values ​​are added to get a cumulative sum, which represents the combined result of all data segments. The cumulative sum is bitwise inverted, and then 1 is added to implement binary complement to generate the final TCP / UDP checksum result.

8. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 7, characterized in that: The calculation expression of the TCP / UDP checksum result is: Where C is the final TCP / UDP checksum result, M is the number of 16-bit data segments processed in parallel, and D p is the intermediate accumulation result, [log2(D p +1)] is rounded up to the base 2 (D p +1), mod2 16 represents the modulo operation, Represents a bitwise exclusive OR operation, used to implement two's complement.

9. The method for calculating a low-latency TCP or UDP checksum based on FPGA according to claim 8, characterized in that: In step 5, the process of backfilling the checksum result into the TCP / UDP header checksum field is as follows: Step 501, the final TCP / UDP checksum result is stored in the register inside the FPGA, and when reading the TCP / UDP message, the message header information is parsed to find the exact location of the TCP / UDP header checksum field, and the IP header is read and parsed; Step 502, find the checksum field of the TCP / UDP header, use the checksum result stored in the register to update the checksum field of the TCP / UDP header, and fill the calculated checksum value in the checksum field within the corresponding clock cycle to complete the checksum backfill operation; Step 503, the check and backfill are completed, the entire message is read, and the message reading operation is marked as completed, the message is sent to the next node of the network, and the message is stored for subsequent use.

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