Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device which comprises a substrate, a first gate electrode layer, a second gate electrode layer and a stacking structure, the first gate electrode layer and the second gate electrode layer are isolated from each other, the substrate is provided with a groove isolation structure, the groove isolation structure defines an active area, the first gate electrode layer is located on the groove isolation structure, and the second gate electrode layer is located on the active area. The stacked structure comprises a dielectric layer and a conductive layer which are stacked in sequence, the stacked structure comprises a first part located on the first gate electrode layer, and the first part and the first gate electrode layer form a capacitor structure. The first gate electrode layer on the trench isolation structure is used as a polar plate of the capacitor structure, so that the integration level of the capacitor structure is improved, and the preparation cost is reduced; moreover, the contact area of the first part and the first gate electrode layer is the effective area of the capacitor structure, and the edge effect caused by etching the stack structure does not affect the stability of the capacitor structure. Correspondingly, the invention also provides a preparation method of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] The MIM (metal-insulator-metal) capacitor composed of a stacked lower plate, a dielectric layer, and an upper plate has the characteristics of a high Q value, good voltage resistance, and low ESR (equivalent series resistance), and has good process compatibility with integrated circuits. It is currently widely used in semiconductor devices.

[0003] In the existing process, MIM capacitors are manufactured separately after the gate structure is formed on the substrate, and the MIM capacitors are integrated between the back-end metal interconnection layers, so the integration level is not high and the manufacturing cost is also high. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for preparing the same, so as to solve the problems of low integration and high preparation cost of existing MIM capacitors.

[0005] In order to achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] A substrate having a trench isolation structure therein, wherein the trench isolation structure defines an active area;

[0007] a first gate electrode layer and a second gate electrode layer isolated from each other, wherein the first gate electrode layer is located on the trench isolation structure, and the second gate electrode layer is located on the active region; and,

[0008] A stacked structure comprises a dielectric layer and a conductive layer stacked in sequence, wherein the stacked structure at least comprises a first portion located on the first gate electrode layer, and the first portion and the first gate electrode layer constitute a capacitor structure.

[0009] Optionally, the first portion is recessed in a direction close to the substrate to contact the first gate electrode layer, and a contact portion between the first portion and the first gate electrode layer is an effective region of the capacitor structure.

[0010] Optionally, the sidewalls and top surface of the first gate electrode layer are covered with a first gate dielectric layer, the first portion is located on the first gate dielectric layer, and the area where the first portion is recessed passes through the first gate dielectric layer and directly contacts the first gate electrode layer.

[0011] Optionally, the first gate electrode layer constitutes a lower plate of the capacitor structure, the dielectric layer in the first part constitutes a dielectric of the capacitor structure, the conductive layer in the first part constitutes an upper plate of the capacitor structure, and the upper plate constitutes a light shielding layer.

[0012] Optionally, the stacked structure further includes a second portion, and the second portion at least covers a side wall of the second gate electrode layer.

[0013] Optionally, the second part constitutes a light-shielding layer.

[0014] Optionally, the first part and the second part are isolated from each other.

[0015] Optionally, also include:

[0016] The etch stop layer is located on the substrate and conformally covers the substrate, the sidewall and a portion of the top surface of the first gate electrode layer, and the sidewall and a portion of the top surface of the second gate electrode layer.

[0017] Optionally, also include:

[0018] an interlayer dielectric layer, located on the substrate and covering the substrate, the first gate electrode layer, the second gate electrode layer and the stacked structure; and,

[0019] A plurality of interconnect structures are located in the interlayer dielectric layer and are interconnected with the first gate electrode layer, the second gate electrode layer and the conductive layer respectively.

[0020] Optionally, the capacitor structure is located below a first metal interconnection layer of the semiconductor device.

[0021] The present invention also provides a method for preparing a semiconductor device, comprising:

[0022] Providing a substrate, wherein the substrate has a trench isolation structure, wherein the trench isolation structure defines an active area;

[0023] forming a first gate electrode layer and a second gate electrode layer isolated from each other on the substrate, wherein the first gate electrode layer is located on the trench isolation structure, and the second gate electrode layer is located on the active area; and,

[0024] forming a stacked structure on the substrate, the first gate electrode layer and the second gate electrode layer, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence; and,

[0025] A partial area of ​​the stacked structure is removed so that the stacked structure at least includes a first portion located on the first gate electrode layer, and the first portion and the first gate electrode layer form a capacitor structure.

[0026] Optionally, after forming the first gate electrode layer and the second gate electrode layer, a first gate dielectric layer is further formed on the top surface and sidewalls of the first gate electrode layer, and the first gate dielectric layer is removed by etching to partially remove the top surface of the first gate electrode layer to form a groove;

[0027] When forming the stacked structure, the stacked structure fills the groove. After removing part of the stacked structure, the first part fills the groove to directly contact the first gate electrode layer. The contact part between the first part and the first gate electrode layer is the effective area of ​​the capacitor structure.

[0028] Optionally, after etching to remove a portion of the stacked structure, the remaining stacked structure further includes a second portion, the second portion at least covers a side wall of the second gate electrode layer, and the second portion constitutes a light shielding layer.

[0029] Optionally, when forming the first gate dielectric layer, a second gate dielectric layer covering the second gate electrode layer is also formed; and,

[0030] Before forming the stacked structure, an etch stop layer is conformally formed on the substrate, the first gate dielectric layer and the second gate dielectric layer, and etching is performed to remove the first gate dielectric layer and the etch stop layer on a portion of the top surface of the first gate electrode layer to form the groove.

[0031] Optionally, after forming the capacitor structure, the method for preparing the semiconductor device further includes:

[0032] forming an interlayer dielectric layer on the substrate, the first gate electrode layer, the second gate electrode layer and the stacked structure; and,

[0033] A plurality of interconnect structures are formed in the interlayer dielectric layer, and the interconnect structures are interconnected with the first gate electrode layer, the second gate electrode layer and the conductive layer respectively.

[0034] Optionally, after forming the stacked structure, a metal interconnection layer of the semiconductor device is formed above the stacked structure, so that the capacitor structure is located below a first metal interconnection layer of the semiconductor device.

[0035] In the semiconductor device provided by the present invention, it includes a substrate, a first gate electrode layer and a second gate electrode layer isolated from each other, and a stacking structure, wherein the substrate has a trench isolation structure, wherein the trench isolation structure defines an active area, wherein the first gate electrode layer is located on the trench isolation structure, wherein the second gate electrode layer is located on the active area, wherein the stacking structure includes a dielectric layer and a conductive layer stacked in sequence, wherein the stacking structure includes a first part located on the first gate electrode layer, wherein the first part and the first gate electrode layer constitute a capacitor structure. In the present invention, on the one hand, the first gate electrode layer on the trench isolation structure is used as a plate of the capacitor structure, thereby improving the integration of the capacitor structure and reducing the preparation cost; on the other hand, the contact area between the first part and the first gate electrode layer is the effective area of ​​the capacitor structure, and the edge effect caused by etching the stacking structure will not have too much influence on the effective area of ​​the capacitor structure, thereby not affecting the stability of the capacitor structure. Accordingly, the present invention also provides a method for preparing a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;

[0037] Figure 2 to Figure 11 A schematic structural diagram corresponding to the corresponding steps of the method for preparing a semiconductor device provided by an embodiment of the present invention, wherein: Fig.10 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, Fig.11 for Fig.10 A schematic diagram of the distribution of the layout structure in the semiconductor device on the substrate;

[0038] Wherein, the accompanying drawings are marked as follows:

[0039] 100-substrate; 101-trench isolation structure; AA-active area; 200-oxide layer; 201-first gate oxide layer; 202-second gate oxide layer; 300-gate electrode material layer; 300a-groove; 301-first gate electrode layer; 302-second gate electrode layer; 400-gate shielding material layer; 401-first gate shielding layer; 402-second gate shielding layer; 501-first gate sidewall; 502-second gate sidewall; 600-etching stop layer; 701-dielectric material layer; 711-dielectric layer; 702-first conductive material layer; 712-first conductive layer; 703-second conductive material layer; 713-second conductive layer; 801-plug; 802-metal interconnection layer. DETAILED DESCRIPTION

[0040] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] Fig.10 A schematic diagram of the structure of a semiconductor device provided in this embodiment, Fig.11 for Fig.10 Schematic diagram of the distribution of the layout structure of the semiconductor device on the substrate. Fig.10 and Fig.11 As shown, the semiconductor device may be, for example, an image sensor or other device that needs to form a MIM capacitor structure, and the semiconductor device includes a substrate 100, a first gate electrode layer 301 and a second gate electrode layer 302 isolated from each other, and a stacked structure.

[0042] Specifically, the substrate 100 may be a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon on insulator (SOI) substrate, a germanium on insulator substrate, a silicon germanium on insulator substrate, or a III-V compound substrate (such as a gallium nitride substrate or a gallium arsenide substrate), etc., or may be other substrates for carrying electronic components known to those skilled in the art. As an example, the substrate 100 is a silicon wafer.

[0043] A trench isolation structure 101 is formed in the substrate 100. The trench isolation structure 101 defines an active area AA. Adjacent active areas AA are isolated by the trench isolation structure 101. The active area AA may include a source area and a drain area ( Fig.10 not shown).

[0044] The first gate electrode layer 301 and the second gate electrode layer 302 are both located on the substrate 100, and the first gate electrode layer 301 is located on the trench isolation structure 101, and the second gate electrode layer 302 is located on the active area AA. Specifically, the second gate electrode layer 302 may be located between the source area and the drain area. Fig.11 As can be seen in the figure, the first gate electrode layer 301 and the second gate electrode layer 302 are isolated from each other and are not electrically connected together.

[0045] As an optional embodiment, the first gate electrode layer 301 and the second gate electrode layer 302 may be a single layer or a multilayer film, and the material thereof may be a semiconductor material or a metal material, for example, polysilicon, metal silicide, Al, W, TiN or other suitable materials.

[0046] like Fig.10As shown, the first gate electrode layer 301 is the gate electrode layer of the first gate structure, and the first gate structure further includes a first gate oxide layer 201 and a first gate dielectric layer for protecting the first gate electrode layer 301. The first gate oxide layer 201 is located between the first gate electrode layer 301 and the substrate 100; the first gate dielectric layer covers the sidewalls and the top surface of the first gate electrode layer 301, and the first gate dielectric layer may specifically include a first gate spacer 501 covering the sidewalls of the first gate electrode layer 301 and a first gate shielding layer 401 covering the top surface of the first gate electrode layer 301.

[0047] Similarly, the second gate electrode layer 302 is the gate electrode layer of the second gate structure, and the second gate structure further includes a second gate oxide layer 202 and a second gate dielectric layer for protecting the second gate electrode layer 302. The second gate oxide layer 202 is located between the second gate electrode layer 302 and the substrate 100; the second gate dielectric layer covers the sidewalls and the top surface of the second gate electrode layer 302, and the second gate dielectric layer may specifically include a second gate spacer 502 covering the sidewalls of the second gate electrode layer 302 and a second gate shielding layer 402 covering the top surface of the second gate electrode layer 302. The second gate structure and the source region and the drain region on both sides thereof may constitute a transistor.

[0048] As an optional embodiment, the first gate shielding layer 401, the second gate shielding layer 402, the first gate sidewall 501 and the second gate sidewall 502 can all be single-layer or multi-layer films, and their materials can be silicon oxide, silicon nitride or other dielectric materials. Generally speaking, the first gate sidewall 501 and the second gate sidewall 502 can be a composite structure film composed of silicon oxide-silicon nitride-silicon oxide.

[0049] Please continue reading Fig.10 The substrate 100 also has an etch stop layer 600, which conformally covers the substrate 100, the sidewalls and a portion of the top surface of the first gate dielectric layer, and the sidewalls and a portion of the top surface of the second gate dielectric layer. The etch stop layer 600 can protect the substrate 100, the first gate structure, and the second gate structure during the etching process of the stacked structure.

[0050] As an optional embodiment, the material of the etch stop layer 600 may be silicon oxide, silicon nitride or other dielectric materials.

[0051] Further, the stacked structure includes a dielectric layer 711 and a conductive layer stacked in sequence. In this embodiment, the conductive layer includes a first conductive layer 712 and a second conductive layer 713 stacked in sequence. The stacked structure includes at least a first part, the first part is located on the first gate electrode layer 301, and the first part and the first gate electrode layer 301 constitute a capacitor structure. The first gate electrode layer 301 can be used as a lower plate of the capacitor structure, and the dielectric layer 711 and the conductive layer in the first part serve as a dielectric and an upper plate of the capacitor structure, respectively. It should be noted that the first gate electrode layer 301 and the second gate electrode layer 302 are formed synchronously. After the gate electrode material layer is formed on the substrate 100 and the gate electrode material layer is patterned, a part of the gate electrode material layer will naturally fall on the trench isolation structure 101 to form the first gate electrode layer 301, and a part of the gate electrode material layer will also fall on the active area AA to form the second gate electrode layer 302. The present invention is equivalent to using the first gate electrode layer 301 originally formed on the trench isolation structure 101 to serve as a plate of the capacitor structure, thereby improving the integration of the capacitor structure and reducing the preparation cost.

[0052] Please continue reading Fig.10 , the first part is a recessed structure. Specifically, the first part is recessed in a direction close to the substrate 100 to contact the first gate electrode layer 301. In this embodiment, the first part is located on the first gate dielectric layer, and the area formed by the recess of the first part passes through the first gate dielectric layer and directly contacts the first gate electrode layer 301. The contact portion between the first part and the first gate electrode layer 301 is the effective area of ​​the capacitor structure. In this way, the edge effect caused by etching the stacked structure will not have too much impact on the effective area of ​​the capacitor structure, thereby not affecting the stability of the capacitor structure.

[0053] Furthermore, in this embodiment, the two ends of the first part also extend to cover the surface of the etch stop layer 600, and these parts of the first part covering the surface of the etch stop layer 600 do not constitute the effective area of ​​the capacitor structure. Therefore, the edge effect caused by etching in the edge area of ​​the first part will not affect the stability of the capacitor structure.

[0054] In this embodiment, the first portion is located on a portion of the top surface of the first gate electrode layer 301 , so as to facilitate leading out the first gate electrode layer 301 , which will be explained later.

[0055] Furthermore, the first conductive layer 712 may be made of a metal material having good adhesion to the dielectric material, such as TiN, etc.; the second conductive layer 713 may be made of a metal material such as W. It should be understood that in this embodiment, the conductive layer includes two film layers, but this is not limited to the present invention. The conductive layer may also be a single-layer film or include more than two film layers.

[0056] As an optional embodiment, the material of the dielectric layer 711 may be silicon oxide, silicon nitride or other high dielectric constant (high-k) materials, for example, it may be at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfO2, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST) or TiO2.

[0057] For further information, please refer to Fig.10 The stacked structure further includes a second portion, the second portion covers the sidewall of the second gate electrode layer 302, and the second portion may also cover the sidewall and a portion of the top surface of the second gate electrode layer 302 at the same time. It should be understood that the second portion should also include the dielectric layer 711 and the conductive layer. In this embodiment, the second portion conformally covers the etch stop layer 600, and the second portion is located as a whole in a partial area of ​​the substrate 100 and a partial surface of the second gate dielectric layer.

[0058] For example, when the semiconductor device is a global exposure image sensor, the first part and the second part can both constitute a light shielding layer. Specifically, the conductive layer of the first part (that is, the upper plate of the capacitor structure) and the conductive layer of the second part are used as light shielding layers to suppress the influence of parasitic light on device performance, thereby improving device performance. Specifically, the active area AA of the global exposure image sensor is arrayed to form a pixel array, and each of the active areas AA also includes a photodiode area PD and a floating diffusion area FD ( Fig.10 The photodiode region PD and the floating diffusion region FD are arranged on both sides of the second gate electrode layer 302. The photodiode region PD converts the received light signal into electric charge through the photoelectric effect. The second gate electrode layer 302 can be used as a shutter to transfer the charge in the photodiode region PD to the floating diffusion region FD. In this embodiment, the light shielding layer can prevent parasitic light from entering the pixel area, generating electric charge, and having an adverse effect on the read signal, thereby solving the problem of parasitic light sensitivity (PLS).

[0059] Furthermore, the second part and the first part are prepared synchronously, that is, the capacitor structure and the light-shielding layer are prepared synchronously, and there is no need to prepare the light-shielding layer separately, which simplifies the preparation process and improves efficiency.

[0060] In this embodiment, combined with Fig.10 and Fig.11 As shown, since the functions of the first part and the second part are different, the second part and the first part are completely isolated and not connected together, but this should not be limited to it. In other embodiments, the second part and the first part may also be connected together.

[0061] In this embodiment, the second portion also covers a portion of the top surface of the second gate electrode layer 302 , which is equivalent to increasing the area of ​​the light shielding layer, thereby enhancing the light shielding effect.

[0062] In some embodiments, the stack structure may further include only the first portion but not the second portion.

[0063] Please continue reading Fig.10 , the semiconductor device further comprises an interlayer dielectric layer, the interlayer dielectric layer is located on the substrate 100, and covers the substrate 100, the first gate electrode layer 301, the second gate electrode layer 302 and the stacked structure. Specifically, the interlayer dielectric layer is located on the etch stop layer 600, and covers the etch stop layer 600 and the stacked structure, and the top surface of the interlayer dielectric layer is flat. The interlayer dielectric layer has a plurality of interconnect structures, and the interconnect structures are respectively interconnected with the first gate electrode layer 301, the second gate electrode layer 302 and the conductive layer, so as to lead out the first gate electrode layer 301, the second gate electrode layer 302 and the conductive layer.

[0064] In this embodiment, each of the interconnect structures includes an electrically connected plug 801 and a metal interconnect layer 802, at least a portion of the plug 801 passes through the etch stop layer 600, the first gate shielding layer 401 and is interconnected with the first gate electrode layer 301, at least a portion of the plug 801 is interconnected with the conductive layer (specifically the second conductive layer 713), at least a portion of the plug 801 passes through the etch stop layer 600 and the second gate shielding layer 402 and is interconnected with the second gate electrode layer 302, the metal interconnect layer 802 is interconnected with the corresponding plug 801, thereby leading out the first gate electrode layer 301, the second gate electrode layer 302 and the conductive layer, and the top surface of the metal interconnect layer 802 can expose the interlayer dielectric layer.

[0065] As an optional embodiment, the material of the interlayer dielectric layer can be selected as needed, for example, it may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride and NDC (Nitrogen doped Silicon Carbide), and may also include borophosphosilicate glass (BPSG), undoped silicate glass (USG), spin-on glass (SOG) or tetraethyl orthosilicate (TEOS), etc.

[0066] Furthermore, the metal interconnection layer 802 serves as the first metal interconnection layer of the semiconductor device, and the capacitor structure is located below the first metal interconnection layer of the semiconductor device, thereby improving the integration of the semiconductor device.

[0067] Based on this, this embodiment also provides a method for preparing the semiconductor device. Figure 1 A flow chart of a method for preparing a semiconductor device provided in this embodiment, such as Figure 1 As shown, the method for preparing the semiconductor device includes:

[0068] Step S100: providing a substrate, wherein the substrate has a trench isolation structure, and the trench isolation structure defines an active area;

[0069] Step S200: forming a first gate electrode layer and a second gate electrode layer isolated from each other on the substrate, wherein the first gate electrode layer is located on the trench isolation structure, and the second gate electrode layer is located on the active area; and,

[0070] Step S300: forming a stacked structure on the substrate, the first gate electrode layer and the second gate electrode layer, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence; and,

[0071] Step S400: removing a portion of the stacked structure so that the stacked structure at least includes a first portion located on the first gate electrode layer, and the first portion and the first gate electrode layer form a capacitor structure.

[0072] Figure 2 to Figure 10 The following is a schematic diagram of the structure corresponding to the corresponding steps of the method for preparing a semiconductor device provided in this embodiment. Figure 2 to Figure 10 The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0073] like Figure 2As shown, step S100 is performed to provide the substrate 100, wherein a trench isolation structure 101 is formed in the substrate 100, and the active area AA is defined by the trench isolation structure 101. The trench isolation structure 101 can be formed by etching the substrate 100 to form an isolation trench, and filling the isolation trench with an isolation material.

[0074] An oxide layer 200 is formed on the substrate 100 , and the oxide layer 200 covers the top surface of the substrate 100 .

[0075] like Figure 3 As shown, step S200 is performed to sequentially form a gate electrode material layer 300 and a gate shielding material layer 400 on the oxide layer 200 , wherein the gate electrode material layer 300 covers the oxide layer 200 , and the gate shielding material layer 400 covers the gate electrode material layer 300 .

[0076] like Figure 4 As shown, etching is performed to remove part of the gate shielding material layer 400, the gate electrode material layer 300 and the oxide layer 200, and the remaining gate shielding material layer 400, the gate electrode material layer 300 and the oxide layer 200 are in a strip structure on the substrate 100, and a portion of each strip structure is located on the trench isolation structure 101, and the other portion is located on the active area AA. The remaining gate shielding material layer 400, the gate electrode material layer 300 and the oxide layer 200 on the trench isolation structure 101 respectively constitute a first gate shielding layer 401, a first gate electrode layer 301 and a first gate oxide layer 201. The remaining gate shielding material layer 400, the gate electrode material layer 300 and the oxide layer 200 on the active area AA respectively constitute a second gate shielding layer 402, a second gate electrode layer 302 and a second gate oxide layer 202.

[0077] like Figure 5 As shown, a first gate spacer 501 is formed on the sidewalls of the first gate shielding layer 401 and the first gate electrode layer 301, and at the same time, a second gate spacer 502 is formed on the sidewalls of the second gate shielding layer 402 and the second gate electrode layer 302. The first gate shielding layer 401 and the first gate spacer 501 constitute a first gate dielectric layer, the second gate shielding layer 402 and the second gate spacer 502 constitute a second gate dielectric layer, the first gate dielectric layer, the first gate electrode layer 301 and the first gate oxide layer 201 constitute the first gate structure, and the second gate dielectric layer, the second gate electrode layer 302 and the second gate oxide layer 202 constitute the second gate structure.

[0078] like Figure 6As shown, an etch stop layer 600 is formed on the substrate 100 , and the etch stop layer 600 conformally covers the substrate 100 , the first gate dielectric layer, and the second gate dielectric layer.

[0079] like Figure 7 As shown, the etching stop layer 600 and the first gate shielding layer 401 on the first gate electrode layer 301 are etched to form a groove 300 a exposing a portion of the top surface of the first gate electrode layer 301 .

[0080] like Figure 8 As shown, step S300 is performed to conformally form a stacked material layer on the etch stop layer 600, the stacked material layer conformally covers the etch stop layer 600 and enters the groove 300a to cover the first gate electrode layer 301. The stacked material layer includes a dielectric material layer 701, a first conductive material layer 702, and a second conductive material layer 703 stacked in sequence.

[0081] like Fig. 9 As shown, step S400 is performed, etching is performed to remove part of the stacked material layer, and the remaining stacked material layer constitutes the stacked structure. Specifically, the remaining dielectric material layer 701 constitutes the dielectric layer 711 in the stacked structure, and the remaining first conductive material layer 702 and the second conductive material layer 703 constitute the conductive layer in the stacked structure. The remaining stacked structure includes the first portion located on the first gate electrode layer 301. It can be understood that when etching to remove part of the stacked material layer, the dielectric layer 711 at the edge of the first portion may be damaged due to the edge effect generated by etching, but since the first portion is a recessed structure, the first portion is recessed in the direction close to the substrate 100 to contact the first gate electrode layer 301, and the contact portion of the first portion with the first gate electrode layer 301 is the effective area of ​​the capacitor structure, and the dielectric layer 711 at the edge of the first portion is not the effective area of ​​the capacitor structure, so it will not have too much impact on the effective area of ​​the capacitor structure, thereby not affecting the stability of the capacitor structure.

[0082] Furthermore, the remaining stacked structure also includes the second portion located on the sidewalls and a portion of the top surface of the second gate electrode layer 302. In devices such as global exposure image sensors, the first portion and the second portion can both serve as light shielding layers to prevent parasitic light from entering the pixel region, generating charges, and causing adverse effects on read signals, thereby solving the problem of parasitic light sensitivity (PLS) and improving device performance.

[0083] like Fig.10As shown, a metal interconnection layer of the semiconductor device is formed on the stacked structure. Specifically, an interlayer dielectric layer is first formed on the etch stop layer 600 and the stacked structure, and then a plurality of plugs 801 are formed in the interlayer dielectric layer, and a metal interconnection layer 802 is formed on each of the plugs 801. The corresponding plugs 801 and the metal interconnection layer 802 constitute the interconnection structure, and the interconnection structure is interconnected with the first gate electrode layer 301, the second gate electrode layer 302 and the conductive layer, respectively. It can be seen that in this embodiment, the metal interconnection layer 802 is the first metal interconnection layer of the semiconductor device, and the capacitor structure is located below the first metal interconnection layer of the semiconductor device, thereby improving the integration of the semiconductor device.

[0084] In summary, in the semiconductor device provided in the embodiment of the present invention, it includes a substrate, a first gate electrode layer and a second gate electrode layer isolated from each other, and a stacking structure, wherein the substrate has a trench isolation structure, wherein the trench isolation structure defines an active area, wherein the first gate electrode layer is located on the trench isolation structure, wherein the second gate electrode layer is located on the active area, wherein the stacking structure includes a dielectric layer and a conductive layer stacked in sequence, wherein the stacking structure includes a first part located on the first gate electrode layer, wherein the first part and the first gate electrode layer constitute a capacitor structure. In the present invention, on the one hand, the first gate electrode layer on the trench isolation structure is used as a plate of the capacitor structure, thereby improving the integration of the capacitor structure and reducing the preparation cost; on the other hand, the contact area between the first part and the first gate electrode layer is the effective area of ​​the capacitor structure, and the edge effect caused by etching the stacking structure will not have too much influence on the effective area of ​​the capacitor structure, thereby not affecting the stability of the capacitor structure. Accordingly, the present invention also provides a method for preparing a semiconductor device.

[0085] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0086] It should also be noted that, although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

[0087] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are merely used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0088] It should also be recognized that the terms described herein are only used to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or", rather than a logical "exclusive or", unless the context clearly indicates otherwise. In addition, the implementation of the method and / or device in the embodiments of the present invention may include performing the selected task manually, automatically, or in combination.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a trench isolation structure therein, wherein the trench isolation structure defines an active area; A first gate electrode layer and a second gate electrode layer isolated from each other, wherein the first gate electrode layer is located on the trench isolation structure, and the second gate electrode layer is located on the active area; as well as, A stacked structure comprises a dielectric layer and a conductive layer stacked in sequence, wherein the stacked structure at least comprises a first portion located on the first gate electrode layer, and the first portion and the first gate electrode layer constitute a capacitor structure.

2. The semiconductor device according to claim 1, wherein The first portion is recessed toward a direction close to the substrate to contact the first gate electrode layer, and a contact portion between the first portion and the first gate electrode layer is an effective region of the capacitor structure.

3. The semiconductor device according to claim 2, wherein: The sidewalls and top surface of the first gate electrode layer are covered with a first gate dielectric layer, the first portion is located on the first gate dielectric layer, and the recessed area of ​​the first portion passes through the first gate dielectric layer and directly contacts the first gate electrode layer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The first gate electrode layer constitutes a lower plate of the capacitor structure, the dielectric layer in the first part constitutes a dielectric of the capacitor structure, the conductive layer in the first part constitutes an upper plate of the capacitor structure, and the upper plate constitutes a light shielding layer.

5. The semiconductor device according to claim 1, wherein: The stack structure further includes a second portion, and the second portion at least covers a sidewall of the second gate electrode layer.

6. The semiconductor device according to claim 5, characterized in that The second portion constitutes a light shielding layer.

7. The semiconductor device according to claim 4 or 5, characterized in that The first portion and the second portion are isolated from each other.

8. The semiconductor device according to claim 1, wherein Also includes: The etch stop layer is located on the substrate and conformally covers the substrate, the sidewall and a portion of the top surface of the first gate electrode layer, and the sidewall and a portion of the top surface of the second gate electrode layer.

9. The semiconductor device according to claim 1, wherein: Also includes: an interlayer dielectric layer, located on the substrate and covering the substrate, the first gate electrode layer, the second gate electrode layer and the stacked structure; as well as, A plurality of interconnect structures are located in the interlayer dielectric layer and are interconnected with the first gate electrode layer, the second gate electrode layer and the conductive layer respectively.

10. The semiconductor device according to claim 1, wherein The capacitor structure is located below the first metal interconnection layer of the semiconductor device.

11. A method for preparing a semiconductor device, characterized in that: include: Providing a substrate, wherein the substrate has a trench isolation structure, wherein the trench isolation structure defines an active area; forming a first gate electrode layer and a second gate electrode layer isolated from each other on the substrate, wherein the first gate electrode layer is located on the trench isolation structure, and the second gate electrode layer is located on the active area; as well as, forming a stacked structure on the substrate, the first gate electrode layer and the second gate electrode layer, the stacked structure comprising a dielectric layer and a conductive layer stacked in sequence; as well as, A partial area of ​​the stacked structure is removed so that the stacked structure at least includes a first portion located on the first gate electrode layer, and the first portion and the first gate electrode layer form a capacitor structure.

12. The method for preparing a semiconductor device according to claim 11, wherein: After forming the first gate electrode layer and the second gate electrode layer, further forming a first gate dielectric layer on the top surface and sidewalls of the first gate electrode layer, and removing the first gate dielectric layer on a portion of the top surface of the first gate electrode layer to form a groove; When forming the stacked structure, the stacked structure fills the groove. After removing part of the stacked structure, the first part fills the groove to directly contact the first gate electrode layer. The contact part between the first part and the first gate electrode layer is the effective area of ​​the capacitor structure.

13. The method for preparing a semiconductor device according to claim 11 or 12, characterized in that: After removing a partial area of ​​the stacked structure, the remaining stacked structure further includes a second portion, the second portion at least covers a side wall of the second gate electrode layer, and the second portion constitutes a light shielding layer.

14. The method for preparing a semiconductor device according to claim 12, wherein: When forming the first gate dielectric layer, a second gate dielectric layer covering the second gate electrode layer is also formed; and, Before forming the stacked structure, an etch stop layer is conformally formed on the substrate, the first gate dielectric layer and the second gate dielectric layer, and the first gate dielectric layer and the etch stop layer on a portion of the top surface of the first gate electrode layer are removed to form the groove.

15. The method for preparing a semiconductor device according to claim 11, wherein: After forming the capacitor structure, the method for preparing the semiconductor device further includes: forming an interlayer dielectric layer on the substrate, the first gate electrode layer, the second gate electrode layer and the stacked structure; and, A plurality of interconnect structures are formed in the interlayer dielectric layer, and the interconnect structures are interconnected with the first gate electrode layer, the second gate electrode layer and the conductive layer respectively.

16. The method for preparing a semiconductor device according to claim 11, wherein: After the stacked structure is formed, a metal interconnection layer of the semiconductor device is formed above the stacked structure, so that the capacitor structure is located below the first metal interconnection layer of the semiconductor device.

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