Semiconductor device

Abstract

Embodiments relate to a semiconductor device. The trench structure portion has: a field plate electrode; a first insulating film provided between the field plate electrode and the semiconductor layer; a second insulating film provided on the field plate electrode, the second insulating film extending and protruding toward a side closer to the first surface of the semiconductor layer than the first insulating film; and a gate electrode having a first portion provided on the second insulating film and a second portion provided on the first insulating film and thicker than the first portion. The gate contact portion extends and protrudes from the gate wiring layer toward the second portion, is in contact with the second portion, and is not located between the first portion and the gate wiring layer. In the second direction, the first portion is located adjacent to a lower end portion where the gate contact portion is in contact with the second portion.

Description

[0001] Related Application

[0002] This application claims the priority of Japanese Patent Application No. 2023-115146 (filing date: July 13, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments relate to a semiconductor device. Background Art

[0004] In a semiconductor device having a trench gate structure, a structure in which a field plate electrode is provided below a gate electrode is known. In such a structure, a structure in which a convex insulating film is provided above between the gate electrode and the field plate electrode is known. Summary of the invention

[0005] According to an embodiment, a semiconductor device comprises: a semiconductor layer having a first surface and a second surface located on the opposite side of the first surface in a first direction; a groove structure extending from the first surface in the first direction; a gate wiring layer provided on the first surface and on the groove structure; and a gate contact extending from the gate wiring layer to the groove structure; the groove structure comprising: a field plate electrode; a first insulating film provided between the field plate electrode and the semiconductor layer; a second insulating film provided on the field plate electrode and extending to a side closer to the first surface than the first insulating film; a gate electrode having a first portion provided on the second insulating film and a second portion provided on the first insulating film and thicker than the first portion; and a third insulating film provided between the second portion of the gate electrode and the semiconductor layer; the gate contact extending from the gate wiring layer to the second portion and in contact with the second portion, and not located between the first portion and the gate wiring layer, and in a second direction orthogonal to the first direction, the first portion is located adjacent to a lower end portion where the gate contact portion is in contact with the second portion.

[0006] According to the embodiment, a semiconductor device having improved characteristics can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view of a semiconductor device according to an embodiment.

[0008] Figure 2 yes Figure 1 Schematic diagram of the cross section at line AA.

[0009] Figure 3 yes Figure 1 Schematic diagram of the cross section at line BB.

[0010] Figure 4 yes Figure 1 Schematic diagram of the cross section at line CC.

[0011] Figure 5 yes Figure 1 Schematic diagram of the cross section at line DD.

[0012] Figure 6 (a) to (c) are schematic plan views showing examples of arrangement of gate contacts.

[0013] Description of Reference Numerals

[0014] 10…semiconductor layer; 10a…first surface; 10b…second surface; 11…first semiconductor portion; 12…second semiconductor portion; 13…third semiconductor portion; 14…fourth semiconductor portion; 15…fifth semiconductor portion; 20…field plate electrode; 30…gate electrode; 31…first portion; 32…second portion; 33…third portion; 41…first insulating film; 42…second insulating film; 43…third insulating film; 44…fourth insulating film; 45…fifth insulating film; 50…gate wiring layer; 55…gate contact portion; 55A…first gate contact portion; 55B…second gate contact portion; 60…first electrode layer; 61…first contact portion; 62…second contact portion; 70…second electrode layer; 80…interlayer insulating layer; t…groove structure portion; R1…first region; R2…second region; R3…third region DETAILED DESCRIPTION

[0015] The following describes the implementation mode with reference to the accompanying drawings. In addition, in each of the drawings, the same reference numerals are used for the same structure. In the following implementation mode, the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0016] Reference Figure 1 to Figure 5 The semiconductor device according to the embodiment is described. The semiconductor device according to the embodiment includes a semiconductor layer 10 , a trench structure portion t, a gate wiring layer 50 , and a gate contact portion 55 .

[0017] like Figure 2 to Figure 5 As shown, the semiconductor layer 10 has a first surface 10a and a second surface 10b. The direction connecting the first surface 10a and the second surface 10b at the shortest distance is set as a first direction Z. The second surface 10b is located on the opposite side of the first surface 10a in the first direction Z. Two directions orthogonal to the first direction Z are set as a second direction Y and a third direction X. The second direction Y and the third direction X are orthogonal to each other.

[0018] In this specification, “thickness” refers to the maximum value of thickness in a specific direction (first direction Z, second direction Y, or third direction X).

[0019] As a material of the semiconductor layer 10, for example, silicon can be used. Alternatively, as a material of the semiconductor layer 10, for example, silicon carbide, gallium nitride, etc. can also be used.

[0020] like Figure 2 As shown in FIG. 1 , in cross-sectional view, the trench structure portion t extends from the first surface 10a along the first direction Z and is located in the semiconductor layer 10. Figure 1 As shown, in a plan view, the groove structure portion t extends along the third direction X. For example, a plurality of groove structure portions t extend along the third direction X.

[0021] The trench structure t includes a field plate electrode 20, a first insulating film 41, a second insulating film 42, a third insulating film 43, and a gate electrode 30. These are provided in a trench formed in the semiconductor layer 10. The field plate electrode 20, the first insulating film 41, the second insulating film 42, and the third insulating film 43 extend in the third direction X in the trench.

[0022] The field plate electrode 20 alleviates the electric field concentration near the gate electrode 30 in the semiconductor layer 10. As a material of the field plate electrode 20, for example, polycrystalline silicon can be used.

[0023] The first insulating film 41 is provided between the field plate electrode 20 and the semiconductor layer 10. The first insulating film 41 is provided between the side surface of the field plate electrode 20 and the semiconductor layer 10 and between the lower end of the field plate electrode 20 and the semiconductor layer 10. As the first insulating film 41, for example, a silicon oxide film can be used.

[0024] The second insulating film 42 is provided on the field plate electrode 20, and extends to the side closer to the first surface 10a of the semiconductor layer 10 than the first insulating film 41. The upper end of the second insulating film 42 is located closer to the first surface 10a than the upper end of the first insulating film 41. As the second insulating film 42, for example, a BPSG (boro-phospho silicate glass) film can be used.

[0025] The gate electrode 30 includes a first portion 31 provided on the second insulating film 42 and a second portion 32 provided on the first insulating film 41. The second insulating film 42 is located between the field plate electrode 20 and the first portion 31 in the first direction Z. The first portion 31 and the second portion 32 are integrally formed of the same material. For example, polycrystalline silicon can be used as the material of the gate electrode 30.

[0026] The thickness of the second portion 32 in the first direction Z is thicker than the thickness of the first portion 31 in the first direction Z. Conversely, the thickness of the first portion 31 in the first direction Z is thinner than the thickness of the second portion 32 in the first direction Z. By extending the second insulating film 42 toward the gate electrode 30, the first portion 31 of the gate electrode 30 located on the second insulating film 42 is thinner than the second portion 32 from which the second insulating film 42 does not extend.

[0027] The second insulating film 42 extends into the gate electrode 30 in such a manner that a portion of the gate electrode 30 is recessed toward the upper surface side of the gate electrode 30 more than the lower surface of the second portion 32. Thus, compared with a case where the second insulating film 42 does not extend into the gate electrode 30, the distance in the first direction Z between the field plate electrode 20 and the gate electrode 30 can be extended. Thus, the insulation breakdown resistance between the gate electrode 30 and the field plate electrode 20 can be improved. In addition, the capacitance between the gate electrode 30 and the field plate electrode 20 can be reduced, thereby improving the switching speed. The second insulating film 42 preferably extends from the lower surface of the second portion 32 into the gate electrode 30 by 25% or more of the thickness of the second portion 32 in the first direction Z.

[0028] The third insulating film 43 is provided between the side surface of the second portion 32 of the gate electrode 30 and the semiconductor layer 10. As the third insulating film 43, for example, a silicon oxide film can be used.

[0029] The gate wiring layer 50 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t via the interlayer insulating layer 80. The gate wiring layer 50 may include, for example, a first metal film 51 provided on the interlayer insulating layer 80, a second metal film 52 provided on the first metal film 51, and a third metal film 53 provided on the second metal film 52. For example, a titanium film may be used as the first metal film 51, a tungsten film may be used as the second metal film 52, and an aluminum film may be used as the third metal film 53. The thickness of each of the second metal film 52 and the third metal film 53 in the first direction Z is thicker than the thickness of the first metal film 51 in the first direction Z. The first metal film 51 functions as a barrier film for preventing metal diffusion of the second metal film 52 and the third metal film 53.

[0030] like Figure 1 As shown, the gate wiring layer 50 may have a gate pad 50A, a first extension 50B, and a second extension 50C. For the gate pad 50A, a first connection component such as a bonding wire is provided. The gate wiring layer 50 is electrically connected to the gate drive circuit via the first connection component. The first extension 50B extends from the gate pad 50A along the third direction X. The second extension 50C extends from the gate pad 50A or the first extension 50B along the second direction Y. A plurality of second extensions 50C extend along the second direction Y.

[0031] like Figure 2 As shown, the interlayer insulating layer 80 may include, for example, a first layer 81 provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t, and a second layer 82 provided on the first layer 81. For example, silicon oxide may be used as a material for the first layer 81, and BPSG may be used as a material for the second layer 82.

[0032] The gate contact 55 extends from the gate wiring layer 50 toward the trench structure t. For example, the gate contact 55 extends from the second metal film 52 toward the trench structure t. For example, the gate contact 55 may be composed of a portion of the same material as the second metal film 52 and the first metal film 51 covering the surface of the portion.

[0033] The gate contact portion 55 extends from the gate wiring layer 50 toward the second portion 32 of the gate electrode 30 and is in contact with the second portion 32. The gate contact portion 55 in contact with the second portion 32 is sometimes distinguished from the gate contact portion 55 in contact with the third portion 33 described later (second gate contact portion 55B) and is represented as a first gate contact portion 55A. The gate electrode 30 is electrically connected to the gate wiring layer 50 via the gate contact portion 55. The gate contact portion 55 is Figure 1 In the illustrated example, the portion is located at the intersection of the second extension portion 50C of the gate wiring layer 50 and the gate electrode 30 .

[0034] The gate contact portion 55 is formed by burying a metal material in the contact groove after forming a contact groove that penetrates the interlayer insulating layer 80 and reaches the gate electrode 30. The contact groove can be formed, for example, by RIE (Reactive Ion Etching). According to the present embodiment, the gate contact portion 55 is not located between the first portion 31 of the gate electrode 30 and the gate wiring layer 50. Therefore, it is possible to prevent the contact groove from penetrating the thinner portion of the gate electrode 30, namely the first portion 31, to reach the field plate electrode 20 below the first portion 31. Thus, it is possible to prevent the gate electrode 30 and the field plate electrode 20 from being short-circuited via the gate contact portion 55, and the reliability of the semiconductor device can be improved. The thickness of the first portion 31 in the first direction Z is, for example, less than 500 nm.

[0035] In the second direction Y, the first portion 31 is located adjacent to the lower end portion 55a where the first gate contact portion 55A and the second portion 32 are connected. Thus, a portion of the gate electrode 30 can be thinned to extend the distance between the gate electrode 30 and the field plate electrode 20, and a decrease in the cross-sectional area of ​​the gate electrode 30 can be suppressed on the upper surface side of the gate electrode 30 to which the gate contact portion 55 is connected, thereby suppressing an increase in gate resistance.

[0036] The gate electrode 30 further includes a third portion 33 located adjacent to the first portion 31 in the second direction Y and provided on the first insulating film 41. The thickness of the third portion 33 in the first direction Z is thicker than the thickness of the first portion 31 in the first direction Z. The first portion 31 is located between the second portion 32 and the third portion 33 in the second direction Y. The first portion 31, the second portion 32, and the third portion 33 are integrally formed of the same material.

[0037] At least two gate contacts 55A and 55B are arranged for one trench structure t and are separated from each other in the second direction Y. As described above, the first gate contact 55A of the two gate contacts 55A and 55B extends from the gate wiring layer 50 to the second portion 32 of the gate electrode 30 and contacts the second portion 32. The second gate contact 55B of the two gate contacts 55A and 55B extends from the gate wiring layer 50 to the third portion 33 and contacts the third portion 33. By making the two gate contacts 55A and 55B contact the gate electrode 30 in one trench structure t, the contact area between the gate wiring layer 50 and the gate electrode 30 is increased, and the gate resistance can be reduced.

[0038] The first portion 31 is located between the lower end 55a where the first gate contact portion 55A is connected to the second portion 32 and the lower end 55b where the second gate contact portion 55B is connected to the third portion 33 in the second direction Y. Thus, a decrease in the cross-sectional area of ​​the gate electrode 30 on the upper surface side of the gate electrode 30 to which the gate contact portion 55 is connected can be suppressed, thereby suppressing an increase in gate resistance.

[0039] like Figure 3 and Figure 4 As shown, the semiconductor device of the embodiment further includes a first electrode layer 60 provided on the first surface 10a and the trench structure t of the semiconductor layer 10. The first electrode layer 60 is provided on the first surface 10a and the trench structure t via an interlayer insulating layer 80.

[0040] As referenced later Figure 4 and Figure 5 As described above, the field plate electrode 20 is electrically connected to the first electrode layer 60 . Therefore, the same potential is applied to the first electrode layer 60 and the field plate electrode 20 .

[0041] For example, the first electrode layer 60 and the gate wiring layer 50 may be formed simultaneously with the same material. In this case, the first electrode layer 60 may include the first metal film 51 , the second metal film 52 , and the third metal film 53 , similarly to the gate wiring layer 50 described above.

[0042] like Figure 1As shown, the first electrode layer 60 is separated from the gate wiring layer 50 on the first surface 10a of the semiconductor layer 10 and the groove structure portion t. The first electrode layer 60 may have a first pad 60A, a third extension portion 60B and a fourth extension portion 60C. For the first pad 60A, a second connection component such as a bonding wire is provided. The first electrode layer 60 is electrically connected to an external circuit via the second connection component. The third extension portion 60B extends from the first pad 60A along a third direction X. A plurality of fourth extension portions 60C extend from the third extension portion 60B along a second direction Y. In the third direction X, the second extension portion 50C of the gate wiring layer 50 is located between the fourth extension portion 60C of the first electrode layer 60 and between the fourth extension portion 60C and the first pad 60A.

[0043] like Figure 1 As shown in FIG. 1 , the semiconductor device of the embodiment includes a first region R1 , a second region R2 , and a third region R3 . The first region R1 , the second region R2 , and the third region R3 are arranged in a third direction X.

[0044] The first region R1 includes the intersection of the second extension portion 50C of the gate wiring layer 50 and the trench structure portion t. Figure 2 As shown, the gate electrode 30 has a first portion 31, a second portion 32, and a third portion 33. In addition, in the first region R1, a second insulating film 42 is provided between the field plate electrode 20 and the first portion 31 of the gate electrode 30. In addition, in the first region R1, the gate contact portion 55 is in contact with the second portion 32 and the third portion 33 of the gate electrode 30.

[0045] like Figure 2 to Figure 4 As shown, the semiconductor layer 10 has an n-type first semiconductor portion 11 and a p-type second semiconductor portion 12 provided on the first semiconductor portion 11. In addition, the semiconductor layer 10 has an n-type fourth semiconductor portion 14. The first semiconductor portion 11 is provided on the fourth semiconductor portion 14. The n-type impurity concentration of the fourth semiconductor portion 14 is higher than the n-type impurity concentration of the first semiconductor portion 11. The surface of the fourth semiconductor portion 14 on the opposite side to the first semiconductor portion 11 is the second surface 10b of the semiconductor layer 10. In the first region R1, the upper surface of the second semiconductor portion 12 is the first surface 10a of the semiconductor layer 10. The semiconductor device of the embodiment has a second electrode layer 70 provided on the second surface 10b and electrically connected to the fourth semiconductor portion 14. The first semiconductor portion 11, the fourth semiconductor portion 14 and the second electrode layer 70 are provided in the first region R1, the second region R2 and the third region R3.

[0046] like Figure 3As shown, in the second region R2, the semiconductor layer 10 further includes an n-type third semiconductor portion 13 provided on the second semiconductor portion 12. The n-type impurity concentration of the third semiconductor portion 13 is higher than the n-type impurity concentration of the first semiconductor portion 11. In the second region R2, the upper surface of the third semiconductor portion 13 is the first surface 10a of the semiconductor layer 10.

[0047] In the second region R2, the first electrode layer 60 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t via the interlayer insulating layer 80. The third semiconductor portion 13 is electrically connected to the first electrode layer 60.

[0048] In the second region R2, the second contact portion 62 extends from the first electrode layer 60 toward the second semiconductor portion 12. The second contact portion 62 penetrates the interlayer insulating layer 80 and the third semiconductor portion 13 and contacts the p-type fifth semiconductor portion 15 provided in the second semiconductor portion 12. The p-type impurity concentration of the fifth semiconductor portion 15 is higher than the p-type impurity concentration of the second semiconductor portion 12. In the second region R2, the second semiconductor portion 12 and the third semiconductor portion 13 are electrically connected to the first electrode layer 60 via the second contact portion 62. Figure 3 In the example shown, the side surface of the second contact portion 62 is in contact with the third semiconductor portion 13. In the second region R2, a plurality of second contact portions 62 are arranged in the second direction Y. In the second direction Y, the second contact portion 62 is located between adjacent trench structures t.

[0049] In the second region R2, the gate electrodes 30 in one trench structure portion t are separated in the second direction Y. In the second region R2, a portion 80A of the interlayer insulating layer 80 extends toward the field plate electrode 20 to separate the gate electrodes 30 in the second direction Y. The side surfaces of the gate electrodes 30 separated in the second direction Y face the second semiconductor portion 12 via the third insulating film 43 .

[0050] The semiconductor device of the embodiment has, for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. For example, the first electrode layer 60 functions as a source electrode, the second electrode layer 70 functions as a drain electrode, the first semiconductor portion 11 functions as a drift layer, the second semiconductor portion 12 functions as a base layer, the third semiconductor portion 13 functions as a source layer, and the fourth semiconductor portion 14 functions as a drain layer.

[0051] When a first potential (for example, a ground potential) is applied to the first electrode layer 60, a second potential (for example, a positive potential) higher than the first potential is applied to the second electrode layer 70, and a gate voltage greater than a threshold value is applied to the gate electrode 30, an n-type inversion layer (channel) is formed in the portion of the second semiconductor portion 12 in the second region R2 that is opposite to the gate electrode 30. In addition, in the second region R2, current flows between the second electrode layer 70 (drain electrode) and the first electrode layer 60 (source electrode) via the fourth semiconductor portion 14 (drain layer), the channel, and the third semiconductor portion 13 (source layer).

[0052] Furthermore, the semiconductor device according to the embodiment may have an IGBT (Insulated Gate Bipolar Transistor) structure.

[0053] In the first region R1, Figure 2 As shown in FIG. 1 , between the second portion 32 of the gate electrode 30 and the second semiconductor portion 12 and between the third portion 33 of the gate electrode 30 and the second semiconductor portion 12, in addition to the third insulating film 43, a fourth insulating film 44 is provided. As the fourth insulating film 44, for example, a silicon oxide film can be used. The thickness of the insulating film (third insulating film 43 and fourth insulating film 44) between the side surface of the gate electrode 30 and the semiconductor layer 10 in the first region R1 is greater than Figure 3 The thickness of the insulating film (third insulating film 43) between the side surface of the gate electrode 30 and the semiconductor layer 10 in the second region R2 shown is thick. As a result, in the first region R1, the insulation breakdown resistance between the gate electrode 30 and the first semiconductor portion 11 to which the drain potential is given can be improved. In particular, since an electric field is directly applied from the first semiconductor portion 11 to a portion of the gate electrode 30 adjacent to the second direction Y where the second semiconductor portion 12 does not exist, thickening the thickness of the insulating film between the side surface of the gate electrode 30 and the semiconductor layer 10 is effective in improving the insulation breakdown resistance.

[0054] like Figure 1 As shown, the third region R3 includes both ends of the groove structure portion t in the third direction X. Figure 4 As shown, in the third region R3, the first electrode layer 60 is provided on the first surface 10a of the semiconductor layer 10 and on the trench structure portion t via the interlayer insulating layer 80. The third region R3 does not include the second semiconductor portion 12 and the third semiconductor portion 13. In the third region R3, the upper surface of the first semiconductor portion 11 is the first surface 10a of the semiconductor layer 10.

[0055] In the third region R3, no gate electrode is provided on the field plate electrode 20, and a first contact portion 61 is provided on the field plate electrode 20. The first contact portion 61 extends from the first electrode layer 60 through the interlayer insulating layer 80 toward the field plate electrode 20 and contacts the field plate electrode 20. The field plate electrode 20 is electrically connected to the first electrode layer 60 via the first contact portion 61.

[0056] like Figure 5 As shown, the field plate electrode 20 has an extended protrusion 20a extending toward the first surface 10a at the end of the trench structure portion t in the third direction X. The first contact portion 61 of the first electrode layer 60 is connected to the extended protrusion 20a.

[0057] Figure 6 (a) to (c) are schematic plan views showing an example of arrangement of the plurality of gate contacts 55 in the first region R1.

[0058] exist Figure 6 (a) and Figure 6 In the example shown in (b), multiple first gate contact portions 55A connected to the second portion 32 of the gate electrode 30 are arranged separately from each other in the third direction X, and multiple second gate contact portions 55B connected to the third portion 33 of the gate electrode 30 are arranged separately from each other in the third direction X.

[0059] exist Figure 6 In the example shown in (a), the first gate contact portion 55A and the second gate contact portion 55B are arranged in parallel with each other in the second direction Y.

[0060] exist Figure 6 In the example shown in (b), the first gate contact portions 55A and the second gate contact portions 55B are arranged alternately and are not arranged side by side in the second direction Y.

[0061] exist Figure 6 In the example shown in (c), the first gate contact portion 55A extends continuously along the third direction X, and the second gate contact portion 55B extends continuously along the third direction X.

[0062] like Figure 2 As shown, the trench structure portion t of the first region R1 may also include a fifth insulating film 45 provided between the field plate electrode 20 and the second insulating film 42. The fifth insulating film 45 is, for example, a silicon oxide film formed by thermal oxidation. Figure 3 As shown, in the second region R2 , the fifth insulating film 45 may also be provided between the field plate electrode 20 and a portion 80A of the interlayer insulating layer 80 .

[0063] Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are included in the scope and subject matter of the invention, and are included in the invention described in the claims and the scope of their equivalents.

Claims

1. A semiconductor device, characterized in that: have: a semiconductor layer having a first surface and a second surface located on an opposite side of the first surface in a first direction; a groove structure portion extending from the first surface along the first direction; a gate wiring layer provided on the first surface and on the groove structure portion; as well as a gate contact portion extending from the gate wiring layer toward the trench structure portion; The groove structure has: Field plate electrode; A first insulating film, which is provided between the field plate electrode and the semiconductor layer; a second insulating film, which is provided on the field plate electrode and extends and protrudes toward a side closer to the first surface than the first insulating film; a gate electrode having a first portion provided on the second insulating film and a second portion provided on the first insulating film and thicker than the first portion; as well as a third insulating film provided between the second portion of the gate electrode and the semiconductor layer; The gate contact portion extends from the gate wiring layer toward the second portion to contact the second portion and is not located between the first portion and the gate wiring layer. In a second direction orthogonal to the first direction, the first portion is located adjacent to a lower end portion of the gate contact portion where the second portion meets.

2. The semiconductor device according to claim 1, wherein: The gate electrode further has a third portion located adjacent to the first portion in the second direction, The gate contact portion extends from the gate wiring layer toward the third portion and contacts the third portion. The first portion is located between a lower end portion of the gate contact portion connected to the second portion and a lower end portion of the gate contact portion connected to the third portion in the second direction.

3. The semiconductor device according to claim 1 or 2, characterized in that: The second insulating film extends into the gate electrode by more than 25% of the thickness of the second portion in the first direction.

4. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device further includes a first electrode layer provided on the first surface and on the trench structure portion and separated from the gate wiring layer. The field plate electrode is electrically connected to the first electrode layer.

5. The semiconductor device according to claim 4, wherein: The semiconductor layer has: a first semiconductor portion of a first conductivity type; a second semiconductor portion of a second conductivity type, provided on the first semiconductor portion and opposed to the gate electrode via the third insulating film; and The third semiconductor portion of the first conductivity type is provided on the second semiconductor portion and is electrically connected to the first electrode layer.

6. The semiconductor device according to claim 5, wherein: have: A first region, in which the first portion and the second portion of the gate electrode are disposed; and a second region provided with the third semiconductor portion; In the second region, the gate electrodes are separated in the second direction.

7. The semiconductor device according to claim 6, wherein: The semiconductor device further includes a third region, In the third region, the gate electrode is not provided on the field plate electrode, but a first contact portion is provided which extends from the first electrode layer toward the field plate electrode and contacts the field plate electrode.

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