Display device and method of manufacturing same

Abstract

The invention discloses a display device and a method of manufacturing the same. The display device includes: a substrate; a first metal layer disposed on the substrate; the active layer is arranged on the first metal layer; the second metal layer is arranged on the active layer; the third metal layer is arranged on the second metal layer; the fourth metal layer is arranged on the third metal layer; and a transistor and a capacitor disposed on the substrate. The transistor includes: a gate electrode disposed in at least one of the first metal layer and the second metal layer; and a drain electrode, a source electrode, and an active region disposed in the active layer. The capacitor includes: a first capacitor including a first electrode disposed in a first metal layer and a second electrode disposed in a second metal layer; a second capacitor including a second electrode and a third electrode disposed in a third metal layer; and a third capacitor including a third electrode and a fourth electrode disposed in the fourth metal layer.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0091558 filed in the Korean Intellectual Property Office on July 14, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] As multimedia develops, display devices are becoming more and more important. Therefore, various display devices, such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices, are being developed.

[0004] Among the display devices, the self-luminous display device includes a self-luminous element, such as an organic light emitting diode. The self-luminous element may include two electrodes facing each other and a light emitting layer between the two electrodes. When the self-luminous element is an organic light emitting diode, electrons and holes provided from the two electrodes may be recombined in the light emitting layer to generate excitons. When the generated excitons change from an excited state to a ground state, light may be emitted.

[0005] Since self-luminous display devices do not require a light source such as a backlight unit, they have low power consumption, can be made lightweight and thin, and have a wide viewing angle, high brightness and contrast, and a fast response speed. Due to these high-quality characteristics, self-luminous display devices have attracted attention as next-generation display devices.

[0006] With the introduction of high-resolution display devices, individual pixels are becoming smaller. As a result, the components that make up each pixel are also becoming smaller. Summary of the invention

[0007] Aspects of the present disclosure may provide a display device and a method of manufacturing the display device, in which the area of ​​each individual electrode of a capacitor is minimized but the total capacitance of the capacitor is increased.

[0008] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0009] An embodiment of a display device includes: a substrate; a first metal layer, arranged on the substrate; an active layer, arranged on the first metal layer; a second metal layer, arranged on the active layer; a third metal layer, arranged on the second metal layer; a fourth metal layer, arranged on the third metal layer; and a transistor and a capacitor, arranged on the substrate, wherein the transistor includes: a gate electrode, arranged in at least one of the first metal layer and the second metal layer; and a drain electrode, a source electrode and an active region, arranged in the active layer, and wherein the capacitor includes: a first capacitor, including a first electrode arranged in the first metal layer and a second electrode arranged in the second metal layer; a second capacitor, including a second electrode and a third electrode arranged in the third metal layer; and a third capacitor, including a third electrode and a fourth electrode arranged in the fourth metal layer.

[0010] In an embodiment, the display device may further include: a first connection electrode provided in the fourth metal layer and electrically connected to any one of the drain electrode and the source electrode; and a light emitting element provided on the fourth metal layer and connected to the first connection electrode.

[0011] In an embodiment, the display device may include: a first overlapping region, in which the first electrode and the second electrode overlap; a second overlapping region, in which the second electrode and the third electrode overlap; and a third overlapping region, in which the third electrode and the fourth electrode overlap, wherein an area of ​​the third overlapping region is greater than an area of ​​the first overlapping region and an area of ​​the second overlapping region.

[0012] In an embodiment, all of the first overlap region and all of the second overlap region overlap with the third overlap region.

[0013] In an embodiment, the light emitting element includes a pixel electrode connected to the first connection electrode, and the pixel electrode and at least one of the first to fourth electrodes include different materials.

[0014] In an embodiment, the conductivity of at least one of the first to fourth electrodes is higher than the conductivity of the pixel electrode.

[0015] In an embodiment, the pixel electrode includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) and indium oxide (In 2 O 3) and at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li) and calcium (Ca), and at least one of the first to fourth electrodes includes at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu).

[0016] In an embodiment, the display device may further include a first via layer disposed between the third metal layer and the fourth metal layer, wherein the first via layer includes an opening or a groove overlapping the capacitor, and the fourth electrode is disposed in the opening or the groove.

[0017] In an embodiment, the fourth electrode is located at a lower level than the first connection electrode.

[0018] In an embodiment, the display device may further include a second connecting electrode, which is arranged in the third metal layer and connects any one of the drain electrode and the source electrode to the first connecting electrode, wherein, in the thickness direction of the substrate, the distance between the third electrode and the fourth electrode is smaller than the distance between the first connecting electrode and the second connecting electrode.

[0019] In an embodiment, the display device may further include a first passivation layer disposed between the first via layer and the third metal layer, wherein the first via layer includes an opening, the first passivation layer is exposed through the opening, and the fourth electrode is disposed on the first passivation layer exposed through the opening.

[0020] In an embodiment, the first via layer includes a groove, the first via layer includes a valley as a lowest surface disposed within the groove and a peak as an highest surface disposed outside the groove, and the fourth electrode is disposed on the valley.

[0021] In an embodiment, the display device may further include a third connection electrode disposed in the third metal layer, wherein the third connection electrode is disposed between the fourth electrode and the second electrode.

[0022] In an embodiment, the third connection electrode electrically connects the fourth electrode and the second electrode to each other.

[0023] In an embodiment, the second electrode and the fourth electrode are electrically connected to each other, and the first electrode and the third electrode are electrically connected to each other.

[0024] In an embodiment, the gate electrode provided in the first metal layer is a lower gate electrode, the gate electrode provided in the second metal layer is an upper gate electrode, the first electrode and the third electrode have the same potential as at least one of the source electrode and the lower gate electrode, and the second electrode and the fourth electrode have the same potential as the upper gate electrode.

[0025] In an embodiment, the second electrode is a portion of the upper gate electrode.

[0026] In an embodiment, the first electrode is a portion of the lower gate electrode.

[0027] An embodiment of a display device includes: a substrate; a first metal layer disposed on the substrate; a second metal layer disposed on the first metal layer; a third metal layer disposed on the second metal layer; a first via layer disposed on the third metal layer and including valleys and peaks; a fourth metal layer disposed on the first via layer; and a capacitor disposed on the substrate, wherein the capacitor includes: a first electrode disposed in the first metal layer; a second electrode disposed in the second metal layer; a third electrode disposed in the third metal layer; and a fourth electrode disposed in the fourth metal layer, and wherein the fourth electrode is disposed on the valley of the first via layer.

[0028] In an embodiment, the second electrode and the fourth electrode are electrically connected to each other, and the first electrode and the third electrode are electrically connected to each other.

[0029] An embodiment of a method for manufacturing a display device (the display device includes a substrate, a first metal layer arranged on the substrate, a second metal layer arranged on the first metal layer, a third metal layer arranged on the second metal layer, a first via layer arranged on the third metal layer, and a capacitor arranged on the substrate) includes: forming a groove in the first via layer using a halftone mask; and forming a fourth metal layer on the first via layer, wherein the capacitor includes: a first electrode arranged in the first metal layer; a second electrode arranged in the second metal layer; a third electrode arranged in the third metal layer; and a fourth electrode arranged in the fourth metal layer, and the fourth electrode is formed in the groove.

[0030] In an embodiment, the method may further include: after forming the groove, forming an opening by reducing a thickness of the first via layer, wherein in forming the fourth electrode, the fourth electrode is formed in the opening.

[0031] In the display device and the method of manufacturing the display device according to the embodiment of the present disclosure, the area of ​​each individual electrode of the capacitor may be minimized, but the total capacitance of the capacitor may be increased.

[0032] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those skilled in the art by referring to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] These and other aspects will become apparent and more readily understood from the following description of embodiments taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0035] Figure 2 It is along Figure 1 A schematic cross-sectional view of the display device taken along line II';

[0036] Figure 3 is a schematic plan view of a display substrate and other components according to an embodiment;

[0037] Figure 4 shows pixels and lines of a display device according to an embodiment;

[0038] Figure 5 is a schematic plan view of a portion of a display area of ​​a display substrate according to an embodiment;

[0039] Figure 6 It is along Figure 5 A cross-sectional view of the display device taken along line II-II';

[0040] Figure 7 is a circuit diagram of a pixel of a display device according to an embodiment;

[0041] Figure 8 is a cross-sectional view of a first transistor and a capacitor of a display device according to an embodiment;

[0042] Fig. 9 yes Figure 8 An enlarged view of region A;

[0043] Fig.10 is a schematic layout diagram of a portion of a display device according to an embodiment;

[0044] Figures 11 to 13 is a plan view of a first overlapping region, a second overlapping region, and a third overlapping region according to an embodiment;

[0045] Fig.14 is a cross-sectional view of a first transistor and a capacitor of a display device according to an embodiment;

[0046] Fig.15 yes Fig.14 An enlarged view of region B;

[0047] Fig.16 is a cross-sectional view of a first transistor and a capacitor of a display device according to an embodiment;

[0048] Fig.17 is a cross-sectional view of a first transistor and a capacitor of a display device according to an embodiment;

[0049] Fig.18It shows the manufacturing basis Fig.14 A flowchart of a method for displaying a device according to an embodiment of the present invention;

[0050] Fig.19 and Fig. 20 It is shown Fig.18 A cross-sectional view of operation S100;

[0051] Fig.21 It is shown Fig.18 A cross-sectional view of operation S200;

[0052] Fig. 22 It is shown Fig.18 A cross-sectional view of operation S300;

[0053] Fig.23 It is shown Fig.18 A cross-sectional view of operation S400;

[0054] Fig.24 and Fig.25 It is shown Fig.18 A cross-sectional view of operation S500;

[0055] Fig.26 It is shown Fig.18 A cross-sectional view of operation S600 of FIG.

[0056] Fig. 27 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S700 . DETAILED DESCRIPTION

[0057] The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0058] It will also be understood that when a layer or substrate is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers or substrates may also be present. Throughout the specification, the same reference numerals refer to the same components.

[0059] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 is a schematic perspective view of a display device 10 according to the embodiment. Figure 2 It is along Figure 1 Schematic cross-sectional view of the display device 10 taken along line II′.

[0061] Reference Figure 1 and Figure 2 The display device 10 can be applied to various electronic devices including small and medium-sized electronic devices (such as tablet personal computers (PCs), smart phones, car navigation units, cameras, central information displays (CIDs) provided in vehicles, watch-type electronic devices, personal digital assistants (PDAs), portable multimedia players (PMPs), and game consoles) and large and medium-sized electronic devices (such as televisions, outdoor billboards, monitors, and PCs (such as notebook computers)). These are presented only as examples, and the display device 10 can also be used in other electronic devices as long as it does not depart from the spirit of the present disclosure.

[0062] In an embodiment, the display device 10 may be rectangular in a plan view. The display device 10 may include two long sides extending in a first direction DR1 and two short sides extending in a second direction DR2 intersecting the first direction DR1. Each corner where the long side and the short side of the display device 10 intersect may be a right angle. However, the present disclosure is not limited thereto, and each corner may also be rounded with a predetermined curvature. In an embodiment, the long side may extend in the second direction DR2, and the short side may extend in the first direction DR1. The planar shape of the display device 10 is not limited to the above examples, but may also be a circular shape or other shapes.

[0063] In the drawings, the first direction DR1 and the second direction DR2 are horizontal directions that intersect each other. For example, the first direction DR1 and the second direction DR2 may be orthogonal to each other. In addition, the third direction DR3 may intersect the first direction DR1 and the second direction DR2, for example, may be a vertical direction orthogonal to the first direction DR1 and the second direction DR2. Unless otherwise specified, in this specification, the direction indicated by the arrows of each of the first direction DR1 to the third direction DR3 may be referred to as one side, and the direction opposite to the direction indicated by the arrows of each of the first direction DR1 to the third direction DR3 may be referred to as the other side. In addition, in this specification, "on...", "upper side", "above...", "top" and "upper surface" refer to the direction in which the arrow of the third direction DR3 points in the drawings, and "below...", "lower side", "below...", "bottom" and "lower surface" refer to the direction opposite to the direction in which the arrow of the third direction DR3 points in the drawings.

[0064] The display device 10 may include a display area DA displaying an image and a non-display area NDA not displaying an image. In an embodiment, the non-display area NDA may be located around the display area DA and may surround the display area DA.

[0065] Regarding the schematic stacking structure of the display device 10, in an embodiment, the display device 10 may include a display substrate (substrate) 100 and a color conversion substrate 200 facing the display substrate 100, and may also include a sealing portion 400 that joins the display substrate 100 and the color conversion substrate 200 together and a filler 300 that fills a space between the display substrate 100 and the color conversion substrate 200.

[0066] The display substrate 100 may include elements and circuits for displaying an image, for example, a pixel circuit such as a switching element, an emission area LA defined in a display area DA (see FIG. Figure 5 ) and non-emitting area NLA (see Figure 5 ) of the pixel defining layer (which will be described later), and a self-luminous element. In an embodiment, the self-luminous element may include at least one of an organic light emitting diode, a quantum dot light emitting diode, an inorganic material-based micro light emitting diode (e.g., a micro LED), and an inorganic material-based nano light emitting diode (e.g., a nano LED). For ease of description, the case where the self-luminous element is an organic light emitting diode will be described below as an example.

[0067] The color conversion substrate 200 may be located on the display substrate 100 and may face the display substrate 100. In an embodiment, the color conversion substrate 200 may include a color conversion pattern that converts the color of incident light. In an embodiment, the color conversion pattern may include at least one of a color filter and a wavelength conversion pattern.

[0068] The sealing portion 400 may be located between the display substrate 100 and the color conversion substrate 200 in the non-display area NDA. The sealing portion 400 may be disposed along the edges of the display substrate 100 and the color conversion substrate 200 in the non-display area NDA to surround the display area DA in a plan view. The display substrate 100 and the color conversion substrate 200 may be bonded to each other by the sealing portion 400.

[0069] In an embodiment, the sealing portion 400 may be made of an organic material, for example, the sealing portion 400 may be made of (but not limited to) epoxy resin.

[0070] Filler 300 may be located in a space formed between display substrate 100 and color conversion substrate 200 and surrounded by sealing portion 400. Filler 300 may fill the space between display substrate 100 and color conversion substrate 200.

[0071] In an embodiment, the filler 300 may be made of a material that can transmit light. In an embodiment, the filler 300 may be made of an organic material. For example, the filler 300 may be made of (but not limited to) a silicon-based organic material or an epoxy-based organic material. In an embodiment, the filler 300 may also be omitted.

[0072] Figure 3 is a schematic plan view of a display substrate 100 and other components according to an embodiment.

[0073] Reference Figure 3 , the display device 10 may include a display substrate 100 , a flexible film 510 , a display driver 520 , a circuit board 530 , a timing controller 540 , a power supply 550 , and a gate driver 560 .

[0074] The display substrate 100 may be rectangular in a plan view. For example, the display substrate 100 may be shaped like a rectangular plane having a long side in a first direction DR1 and a short side in a second direction DR2. Each corner where the long side extending in the first direction DR1 and the short side extending in the second direction DR2 intersect may be a right angle or may be rounded with a predetermined curvature. The planar shape of the display substrate 100 is not limited to a rectangular shape, and may also be another polygonal shape, a circular shape, or an elliptical shape. For example, the display substrate 100 may be formed to be flat, but the present disclosure is not limited thereto. For another example, the display substrate 100 may be formed to be bent with a predetermined curvature.

[0075] The display substrate 100 may include a display area DA and a non-display area NDA.

[0076] The display area DA may be an area for displaying an image, and may be defined as a central area of ​​the display substrate 100. The display area DA may include pixels SP, gate lines GL, data lines DL, initialization voltage lines VIL, first voltage lines VDL, horizontal voltage lines HVDL, vertical voltage lines VVSL, and second voltage lines VSL. The pixels SP may be formed in pixel areas where the data lines DL and the gate lines GL intersect, respectively. The pixels SP may include first to third pixels SP1 to SP3. Each of the first to third pixels SP1 to SP3 may be connected to the gate lines GL and the data lines DL. Each of the first to third pixels SP1 to SP3 may be defined as a minimum unit area for outputting light.

[0077] Each of the first to third pixels SP1 to SP3 may include an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0078] The first pixel SP1 may emit light of a first color or red light, the second pixel SP2 may emit light of a second color or green light, and the third pixel SP3 may emit light of a third color or blue light. The pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be arranged in a direction opposite to the second direction DR2, but the order of the pixel circuits is not limited thereto.

[0079] The gate lines GL may include a first gate line GL1 and a second gate line GL2. The first gate lines GL1 may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2. The first gate lines GL1 may receive a first gate signal from the gate driver 560 and

[0080] The first gate signal is supplied to the first to third pixels SP1 to SP3 .

[0081] The second gate lines GL2 may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The second gate lines GL2 may receive a second gate signal from the gate driver 560 and supply the second gate signal to the first to third pixels SP1 to SP3.

[0082] The data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The data lines DL may include first to third data lines DL1 to DL3. The first to third data lines DL1 to DL3 may supply data voltages to first to third pixels SP1 to SP3, respectively.

[0083] The initialization voltage lines VIL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The initialization voltage lines VIL may supply the initialization voltage received from the display driver 520 to the pixel circuits of the first to third pixels SP1 to SP3. The initialization voltage lines VIL may receive the sensing signals from the pixel circuits of the first to third pixels SP1 to SP3 and supply the sensing signals to the display driver 520.

[0084] The first voltage lines VDL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1 The first voltage lines VDL may supply a driving voltage or a high potential voltage received from the power source 550 to the first to third pixels SP1 to SP3.

[0085] The horizontal voltage lines HVDL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2. The horizontal voltage lines HVDL may be connected to the first voltage lines VDL. The horizontal voltage lines HVDL may receive a driving voltage or a high potential voltage from the first voltage lines VDL.

[0086] The vertical voltage lines VVSL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The vertical voltage lines VVSL may be connected to the second voltage line VSL. The vertical voltage lines VVSL may supply a low potential voltage received from the power supply 550 to the second voltage line VSL.

[0087] The second voltage lines VSL may extend in the first direction DR1 and may be spaced apart from each other in the second direction DR2 The second voltage line VSL may supply a low potential voltage to the first to third pixels SP1 to SP3.

[0088] The connection relationship among the pixels SP, the gate lines GL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL, the horizontal voltage lines HVDL, the vertical voltage lines VVSL and the second voltage lines VSL may be designed and changed according to the number and arrangement of the pixels SP.

[0089] The non-display area NDA may be defined as an area other than the display area DA in the display substrate 100. For example, the non-display area NDA may include a fan-out line connecting the data line DL, the initialization voltage line VIL, the first voltage line VDL, and the vertical voltage line VVSL to the display driver 520, and may include a gate driver 560 and a pad unit (not shown) connected to the flexible film 510.

[0090] The flexible film 510 may be connected to a pad unit disposed at the lower side of the non-display area NDA. An input terminal disposed at one side of the flexible film 510 may be attached to the circuit board 530 by a film attachment process, and an output terminal disposed at the other side of the flexible film 510 may be attached to the pad unit by a film attachment process. For example, each of the plurality of flexible films 510 may be bent like a tape carrier package or a chip on film. The flexible film 510 may be bent toward the bottom of the display substrate 100 to reduce the frame area of ​​the display device 10.

[0091] The display driver 520 may be mounted on the flexible film 510. For example, the display driver 520 may be implemented as an integrated circuit (IC). The display driver 520 may receive digital video data and a data control signal from the timing controller 540, convert the digital video data into an analog data voltage according to the data control signal, and supply the analog data voltage to the data line DL through the fan-out line.

[0092] The circuit board 530 may support the timing controller 540 and the power supply 550, and may supply signals and power to the display driver 520. For example, the circuit board 530 may supply the flexible film 510 and the display driver 520 with a signal supplied from the timing controller 540 and a power supply voltage supplied from the power supply 550 so as to display an image in each pixel SP. To this end, a signal line and a power line may be provided on the circuit board 530.

[0093] The timing controller 540 may be mounted on the circuit board 530, and may receive image data and a timing synchronization signal from a display driving system or a graphics device through a user connector provided on the circuit board 530. The timing controller 540 may generate digital video data by arranging the image data according to the pixel arrangement structure based on the timing synchronization signal, and supply the generated digital video data to the display driver 520. The timing controller 540 may generate a data control signal and a gate control signal based on the timing synchronization signal. The timing controller 540 may control the data voltage supply timing of the display driver 520 based on the data control signal, and may control the gate signal supply timing of the gate driver 560 based on the gate control signal.

[0094] The power supply 550 may be provided on the circuit board 530 to supply a power supply voltage to the flexible film 510 and the display driver 520. For example, the power supply 550 may generate a driving voltage or a high potential voltage and supply the driving voltage or the high potential voltage to the first voltage line VDL, may generate a low potential voltage and supply the low potential voltage to the vertical voltage line VVSL, and may generate an initialization voltage and supply the initialization voltage to the initialization voltage line VIL.

[0095] The gate driver 560 may be disposed on the left and right sides of the non-display area NDA. The gate driver 560 may generate a gate signal based on a gate control signal supplied from the timing controller 540. The gate control signal may include, but is not limited to, a start signal, a clock signal, and a power supply voltage. The gate driver 560 may supply the gate signal to the gate line GL according to a set sequence.

[0096] Figure 4 The pixel SP of the display device 10 according to the embodiment is shown (see Figure 3 ) and line.

[0097] Apart from Figure 3 In addition, refer to Figure 4 The pixel SP may include first to third pixels SP1 to SP3. The pixel circuits of the first pixel SP1, the second pixel SP2, and the third pixel SP3 may be arranged in a direction opposite to the second direction DR2, but the order of the pixel circuits is not limited thereto.

[0098] Each of the first to third pixels SP1 to SP3 may be connected to a first voltage line VDL, an initialization voltage line VIL, a gate line GL, and a data line DL.

[0099] The first voltage line VDL may extend in the second direction DR2. The first voltage line VDL may be disposed on the left side of the pixel circuits of the first to third pixels SP1 to SP3. The first voltage line VDL may supply a driving voltage or a high potential voltage to transistors of the first to third pixels SP1 to SP3.

[0100] The horizontal voltage line HVDL may extend in the first direction DR1. The horizontal voltage line HVDL may be disposed in the kth row ROW. k (where k is a positive integer). The horizontal voltage line HVDL may be connected to the first voltage line VDL. The horizontal voltage line HVDL may receive a driving voltage or a high potential voltage from the first voltage line VDL.

[0101] The initialization voltage line VIL may extend in the second direction DR2. The initialization voltage line VIL may be disposed on the left side of an auxiliary line branched from each second gate line GL2 in the second direction DR2. The initialization voltage line VIL may be disposed between the auxiliary line branched from each second gate line GL2 in the second direction DR2 and the vertical voltage line VVSL. The initialization voltage line VIL may supply an initialization voltage to the pixel circuits of the first pixel SP1 to the third pixel SP3. The initialization voltage line VIL may receive a sensing signal from the pixel circuits of the first pixel SP1 to the third pixel SP3, and supply the sensing signal to the display driver 520.

[0102] The vertical voltage line VVSL may extend in the second direction DR2. The vertical voltage line VVSL may be disposed on the left side of the initialization voltage line VIL. The vertical voltage line VVSL may be connected between the power supply 550 and the second voltage line VSL. The vertical voltage line VVSL may supply the second voltage line VSL with a low potential voltage received from the power supply 550.

[0103] The second voltage line VSL may extend in the first direction DR1. The second voltage line VSL may be disposed in the (k+1)th row ROW. k+1 The second voltage line VSL may supply the low potential voltage received from the vertical voltage line VVSL to the light emitting element layers EML (see FIG. 1 ) of the first pixel SP1 to the third pixel SP3. Figure 6 ).

[0104] The first gate line GL1 may extend in the first direction DR1. The first gate line GL1 may be disposed above the pixel circuit of the first pixel SP1. At least a portion of each of the first gate lines GL1 may extend in a direction opposite to the second direction DR2. For example, each of the plurality of first gate lines GL1 may include an auxiliary line branching to the right side of the first pixel SP1 to the third pixel SP3 and extending in a direction opposite to the second direction DR2. The auxiliary line of each of the plurality of first gate lines GL1 may be disposed on the right side of the pixel circuit of the first pixel SP1 to the third pixel SP3. Each of the plurality of first gate lines GL1 may supply the first gate signal received from the gate driver 560 to the pixel circuit of the first pixel SP1 to the third pixel SP3 through the auxiliary line extending in a direction opposite to the second direction DR2.

[0105] The second gate line GL2 may extend in the first direction DR1. The second gate line GL2 may be disposed below the pixel circuit of the third pixel SP3. At least a portion of each second gate line GL2 may extend in the second direction DR2. For example, each of the plurality of second gate lines GL2 may include an auxiliary line branching to the left side of the first voltage line VDL and extending in the second direction DR2. The auxiliary line of each of the plurality of second gate lines GL2 may be disposed on the left side of the first voltage line VDL. Each of the plurality of second gate lines GL2 may supply the second gate signal received from the gate driver 560 to the pixel circuits of the first pixel SP1 to the third pixel SP3 through the auxiliary line extending in the second direction DR2.

[0106] The data lines DL may extend in the second direction DR2. The data lines DL may supply data voltages to the pixels SP. The data lines DL may include first to third data lines DL1 to DL3.

[0107] The second data line DL2 may extend in the second direction DR2. The second data line DL2 may be disposed on the right side of the auxiliary line of each first gate line GL1. The second data line DL2 may supply a data voltage received from the display driver 520 to a pixel circuit of the second pixel SP2.

[0108] The third data line DL3 may extend in the second direction DR2. The third data line DL3 may be disposed on the right side of the second data line DL2. The third data line DL3 may supply a data voltage received from the display driver 520 to a pixel circuit of the third pixel SP3.

[0109] The first data line DL1 may extend in the second direction DR2. The first data line DL1 may be disposed on the right side of the third data line DL3. The first data line DL1 may supply a data voltage received from the display driver 520 to a pixel circuit of the first pixel SP1.

[0110] Figure 5 is a schematic plan view of a portion of a display area DA of a display substrate 100 according to an embodiment.

[0111] Apart from Figure 1 and Figure 2 In addition, refer to Figure 5 , a plurality of emission areas LA and non-emission areas NLA may be defined in the display area DA of the display substrate 100. The emission area LA may be an area in which light generated by a light emitting element of the display substrate 100 is emitted to the outside of the display substrate 100, and the non-emission area NLA may be an area in which light is not emitted to the outside.

[0112] The emission area LA may include a first emission area LA1, a second emission area LA2, and a third emission area LA3.

[0113] The light emitted from the display substrate 100 to the color conversion substrate 200 in the emission area LA may be light of a third color. In an embodiment, the light of the third color may be blue light and may have a peak wavelength in the range of about 440 nm to about 480 nm. The peak wavelength may refer to a wavelength having a maximum intensity in a wavelength region. However, the present disclosure is not limited thereto, and the light emitted from the display substrate 100 to the color conversion substrate 200 in the emission area LA may also be light in an ultraviolet region.

[0114] The first emission area LA1, the second emission area LA2, and the third emission area LA3 may constitute a first pixel SP1, a second pixel SP2, and a third pixel SP3, respectively. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may be repeatedly disposed over the entire display area DA along the first direction DR1 and the second direction DR2. The first emission area LA1, the second emission area LA2, and the third emission area LA3 may constitute a unit color pixel.

[0115] The first to third emission areas LA1 to LA3 may be disposed in an oblique direction defined by the first direction DR1 and a direction opposite to the second direction DR2. For example, in one unit color pixel, the first emission area LA1 may be disposed approximately at the upper left corner in a plan view, the second emission area LA2 may be disposed approximately at the center in a plan view, and the third emission area LA3 may be disposed approximately at the lower right corner in a plan view.

[0116] However, the arrangement order of the first to third emission regions LA1 to LA3 is not limited thereto. In addition, in an embodiment, the first to third emission regions LA1 to LA3 may be arranged in an oblique direction defined by the first direction DR1 and the second direction DR2.

[0117] In an embodiment, the first emission area LA1 may be a polygon having a certain width in the first direction DR1 and the second direction DR2. In the drawings, a pentagon is shown as an example of the first emission area LA1. The second emission area LA2 may be a polygon having a certain width and extending in an oblique direction defined by the first direction DR1 and the second direction DR2. In the drawings, a polygon having steps at both ends is shown as an example of the second emission area LA2. The third emission area LA3 may be a polygon having a certain width in the first direction DR1 and the second direction DR2. In the drawings, a polygon including a portion protruding in a direction opposite to the first direction DR1 and in the second direction DR2 is shown as an example of the third emission area LA3.

[0118] As shown in the drawings, the widths and shapes of the first to third emission areas LA1 to LA3 may be different from each other. For example, the first emission area LA1 may have similar widths in the first direction DR1 and the second direction DR2. The second emission area LA2 may have a wide width in the oblique direction defined by the first direction DR1 and the second direction DR2, and may have a narrow width in the oblique direction defined by the first direction DR1 and the direction opposite to the second direction DR2. Therefore, the second emission area LA2 may be shaped as a polygon extending approximately in the oblique direction defined by the first direction DR1 and the second direction DR2. The third emission area LA3 may have similar widths in the first direction DR1 and the second direction DR2. However, the present disclosure is not limited thereto. In some embodiments, the first to third emission areas LA1 to LA3 may all have the same shape.

[0119] In the display device 10 according to the current embodiment, since the first to third emission areas LA1 to LA3 are arranged in the oblique direction, the difference in distribution of the emission areas LA between the upper, lower, left, and right parts of one unit color pixel can be reduced. Therefore, the color shift phenomenon of displaying a color other than white or black at the boundary between white and black can be minimized in the upper, lower, left, and right parts of one unit color pixel.

[0120] In addition, since the second emission area LA2 extends long in the oblique direction defined by the first direction DR1 and the second direction DR2, the difference in distribution of the emission area LA between the upper, lower, left and right parts of a unit color pixel can be further reduced, which correspondingly minimizes the color shift phenomenon in the upper, lower, left and right parts.

[0121] The non-emission area NLA may be located in the display area DA around the emission area LA of the display substrate 100. The non-emission area NLA may be located not only around the emission area LA but also between the first emission area LA1 and the second emission area LA2, between the second emission area LA2 and the third emission area LA3, and between the third emission area LA3 and the first emission area LA1.

[0122] In some embodiments, a boundary between the emission area LA and the non-emission area NLA may be formed by a pixel defining layer PDL (see FIG. Figure 6 ) and the outer wall surrounding the opening.

[0123] Light emitted from the emission area LA of the display substrate 100 may pass through the light-transmitting area of ​​the color conversion substrate 200 and may then be provided to the outside of the display device 10 .

[0124] Figure 6 It is along Figure 5 1 is a cross-sectional view of the display device 10 taken along line II-II′.

[0125] Apart from Figure 5 In addition, refer to Figure 6 , the display device 10 may include a display substrate 100 , a color conversion substrate 200 facing the display substrate 100 , and a filler 300 joining the display substrate 100 and the color conversion substrate 200 together.

[0126] The display substrate 100 may include a first substrate 110 , a circuit layer CCL, a light emitting element layer EML, and an encapsulation structure 170 .

[0127] The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass or quartz. The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto. The first substrate 110 may also include a plastic such as polyimide, and may have a flexible property so that the first substrate 110 can be bent, folded, or curled.

[0128] The circuit layer CCL (eg, a thin film transistor layer) may be disposed on the first substrate 110. Figure 8 etc. describe the circuit layer CCL in detail.

[0129] The light emitting element layer EML may be disposed on the circuit layer CCL. The light emitting element layer EML may include a pixel electrode PXE, a pixel defining layer PDL, a light emitting layer LEL, and a common electrode CME.

[0130] The pixel electrode PXE may be a first electrode, for example, an anode of a light emitting diode. The pixel electrode PXE may have a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) or a mixture thereof) and a stacked structure of a layer of a reflective material (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). The layer of the material with a high work function may be disposed on the layer of the reflective material so that the layer of the material with a high work function is positioned close to the light emitting layer LEL. The pixel electrode PXE may have (but is not limited to) ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure.

[0131] The pixel electrode PXE may include a first pixel electrode PXR, a second pixel electrode PXG, and a third pixel electrode PXB. The first pixel electrode PXR may overlap the first emission area LA1. The second pixel electrode PXG may overlap the second emission area LA2. The third pixel electrode PXB may overlap the third emission area LA3.

[0132] The pixel defining layer PDL may be disposed on the first substrate 110 along the boundary of the pixel SP, specifically, on the surface of the circuit layer CCL. The pixel defining layer PDL may be disposed on the pixel electrode PXE and may include an opening exposing the pixel electrode PXE. The emission area LA and the non-emission area NLA may be defined by the pixel defining layer PDL and the opening of the pixel defining layer PDL.

[0133] The pixel defining layer PDL may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). The pixel defining layer PDL may also include an inorganic material.

[0134] The light-emitting layer LEL may be disposed on the pixel electrode PXE exposed by the pixel defining layer PDL. The light-emitting layer LEL may contact not only the pixel electrode PXE but also the side surface and the upper surface of the pixel defining layer PDL. The light-emitting layer LEL may be connected without distinguishing between a plurality of emission areas LA and without distinguishing between a plurality of pixels SP. The light-emitting layer LEL may be disposed over the entire surface without distinguishing between a plurality of emission areas LA and without distinguishing between a plurality of pixels SP. Therefore, the light-emitting layers LEL of the emission areas LA1 to LA3 may emit light having the same wavelength. For example, the light-emitting layers LEL of the emission areas LA1 to LA3 may emit blue light or ultraviolet light, and the wavelength conversion layer WCL included in the color conversion substrate 200 to be described later may enable each pixel SP to display a corresponding color.

[0135] In an embodiment, the light emitting layers LEL may be respectively disposed in the emission areas LA1 to LA3 divided by the pixel defining layer PDL. In this case, the light emitting layers LEL of the emission areas LA1 to LA3 may emit light having the same wavelength.

[0136] In an embodiment in which the display device 10 is an organic light-emitting display device, the light-emitting layer LEL may include an organic layer including an organic material. The organic layer may include an organic light-emitting layer. In some cases, the organic layer may also include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer for assisting light emission. In an embodiment, when the display device 10 is a micro-LED display device or a nano-LED display device, the light-emitting layer LEL may include an inorganic material such as an inorganic semiconductor.

[0137] In some embodiments, the light emitting layer LEL may have a tandem structure including a plurality of organic light emitting layers overlapping each other in a thickness direction and a charge generating layer disposed therebetween. The organic light emitting layers overlapping each other may emit light of the same wavelength or may emit light of different wavelengths. At least some layers of the light emitting layer LEL of each pixel SP may be separated or connected to at least some layers of the light emitting layer LEL of an adjacent pixel SP by a pixel defining layer PDL.

[0138] The common electrode CME may be disposed on the light emitting layer LEL. The common electrode CME may be connected without distinguishing between a plurality of emission areas LA and a plurality of pixels SP. The common electrode CME may be a full-surface electrode disposed over the entire surface without distinguishing between a plurality of emission areas LA and a plurality of pixels SP. The common electrode CME may be a second electrode, for example, a cathode of a light emitting diode. The common electrode CME may include a material having a small work function (such as Li, Ca, LiF, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF 2 The common electrode CME may further include a transparent metal oxide layer disposed on the layer of the material having a small work function.

[0139] The pixel electrode PXE, the light emitting layer LEL, and the common electrode CME may constitute a light emitting element (eg, an organic light emitting diode). Light L emitted from the light emitting layer LEL may be output upward through the common electrode CME.

[0140] The encapsulation structure 170 may be disposed on the common electrode CME. The encapsulation structure 170 may include at least one thin film encapsulation layer. For example, the encapsulation structure 170 may include a first encapsulation inorganic layer 171 , an encapsulation organic layer 172 , and a second encapsulation inorganic layer 173 .

[0141] The first encapsulation inorganic layer 171 may be disposed on the light emitting element layer EML. The first encapsulation inorganic layer 171 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0142] Encapsulation organic layer 172 may be disposed on first encapsulation inorganic layer 171. Encapsulation organic layer 172 may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0143] The second encapsulation inorganic layer 173 may be disposed on the encapsulation organic layer 172. The second encapsulation inorganic layer 173 may include the same material as the first encapsulation inorganic layer 171 described above. For example, the second encapsulation inorganic layer 173 may include silicon nitride (SiN x ), silicon oxide (SiO x ) or silicon oxynitride (SiO x N y ).

[0144] In some embodiments, some layers of the encapsulation structure 170 or the entire encapsulation structure 170 may be omitted. When the encapsulation structure 170 is omitted, the filler 300, the sealing portion 400 (see Figure 1 ) and the color conversion substrate 200 may be directly disposed on the light emitting element layer EML and may directly perform an encapsulation function.

[0145] The color conversion substrate 200 may be disposed on the encapsulation structure 170 to face the display substrate 100. The color conversion substrate 200 may include a second substrate 210, a light blocking member BML, a color filter layer CFL, a first capping layer 220, a partition wall PTL, a wavelength conversion layer WCL, a light transmitting layer TPL, and a second capping layer 230.

[0146] The second substrate 210 may include a transparent material. The second substrate 210 may include a transparent insulating material such as glass or quartz. The second substrate 210 may be a rigid substrate. However, the second substrate 210 is not limited thereto. The second substrate 210 may also include a plastic such as polyimide, or may have a flexible property so that the second substrate 210 can be bent, folded, or curled.

[0147] The second substrate 210 may be the same substrate as the first substrate 110, but may have a different material, thickness, and transmittance from the first substrate 110. For example, the second substrate 210 may have a higher transmittance than the first substrate 110. The second substrate 210 may be thicker or thinner than the first substrate 110.

[0148] The light blocking member BML may be disposed on a surface of the second substrate 210 facing the first substrate 110 along the boundary of the pixel SP. The light blocking member BML may overlap the pixel defining layer PDL of the display substrate 100 and may be located in the non-emission area NLA. The light blocking member BML may include an opening exposing a surface of the second substrate 210 overlapping the emission area LA. The light blocking member BML may be formed in a lattice shape in a plan view.

[0149] The light blocking member BML may include an organic material. The light blocking member BML may reduce color distortion due to reflection of external light by absorbing external light. In addition, the light blocking member BML may prevent light L emitted from the light emitting layer LEL from intruding into adjacent pixels SP.

[0150] In an embodiment, the light blocking member BML may absorb all visible light wavelengths. The light blocking member BML may include a light absorbing material. For example, the light blocking member BML may be made of a material used as a black matrix of the display device 10.

[0151] In an embodiment, the light blocking member BML may absorb light of a specific wavelength among the visible light wavelengths and transmit light of another specific wavelength. For example, the light blocking member BML may include the same material as the color filter layer CFL. Specifically, the light blocking member BML may be made of the same material as the blue color filter layer. In some embodiments, the light blocking member BML may be formed integrally with the blue color filter layer. The light blocking member BML may also be omitted.

[0152] The color filter layer CFL may be disposed on the surface of the second substrate 210 on which the light blocking member BML is disposed. The color filter layer CFL may be disposed on the surface of the second substrate 210 exposed by the opening of the light blocking member BML. In addition, each of the plurality of color filter layers CFL may be disposed on a portion of an adjacent light blocking member BML.

[0153] The color filter layer CFL may include a first color filter layer CFL1 disposed in the first pixel SP1, a second color filter layer CFL2 disposed in the second pixel SP2, and a third color filter layer CFL3 disposed in the third pixel SP3. Each color filter layer CFL may include a colorant such as a dye or a pigment that absorbs wavelengths other than the corresponding color wavelength. The first color filter layer CFL1 may be a red (R) color filter layer, the second color filter layer CFL2 may be a green (G) color filter layer, and the third color filter layer CFL3 may be a blue (B) color filter layer. Although adjacent color filter layers CFL are spaced apart from each other on the light blocking member BML in the drawings, they may also at least partially overlap each other on the light blocking member BML.

[0154] The first cover layer 220 may be disposed on the color filter layer CFL and the light blocking member BML. The first cover layer 220 may prevent damage or contamination of the color filter layer CFL by preventing impurities such as moisture or air from penetrating into the color filter layer CFL from the outside.

[0155] The first cover layer 220 may directly contact the surface of the color filter layer CFL ( Figure 6 The first capping layer 220 may be made of an inorganic material. For example, the first capping layer 220 may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, or silicon oxynitride.

[0156] The partition wall PTL may be disposed on the first cover layer 220. The partition wall PTL may be located in the non-emission area NLA. The partition wall PTL may overlap the light blocking member BML. The partition wall PTL may include an opening exposing the color filter layer CFL. The partition wall PTL may include a photosensitive organic material, but the present disclosure is not limited thereto. The partition wall PTL may also include a light blocking material.

[0157] The wavelength conversion layer WCL or the light transmission layer TPL or both may be disposed in the space exposed by the opening of the partition wall PTL. The wavelength conversion layer WCL and the light transmission layer TPL may be formed by an inkjet process using the partition wall PTL as a bank, but the present disclosure is not limited thereto.

[0158] In an embodiment where the light emitting layer LEL of each pixel SP emits light of a third color, the wavelength conversion layer WCL may include a first wavelength conversion pattern WCL1 disposed in the first pixel SP1 and a second wavelength conversion pattern WCL2 disposed in the second pixel SP2. The light transmitting layer TPL may be disposed in the third pixel SP3.

[0159] The first wavelength conversion pattern WCL1 may include a first base resin BRS1 and a first wavelength conversion material WCP1 disposed in the first base resin BRS1. The second wavelength conversion pattern WCL2 may include a second base resin BRS2 and a second wavelength conversion material WCP2 disposed in the second base resin BRS2. The light transmitting layer TPL may include a third base resin BRS3 and a scatterer SCP disposed in the third base resin BRS3.

[0160] The first to third base resins BRS1 to BRS3 may include a light-transmitting organic material. For example, the first to third base resins BRS1 to BRS3 may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins BRS1 to BRS3 may all be made of the same material, but the present disclosure is not limited thereto.

[0161] The scatterers SCP may be metal oxide particles or organic particles. The metal oxide may be, for example, titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) or tin oxide (SnO 2 ), and the organic particulate material may be, for example, an acrylic resin or a urethane resin.

[0162] The first wavelength conversion material WCP1 may convert the third color into the first color, and the second wavelength conversion material WCP2 may convert the third color into the second color. The first wavelength conversion material WCP1 and the second wavelength conversion material WCP2 may be quantum dots, quantum rods, or phosphors. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI compound nanocrystals, or a combination thereof. The first wavelength conversion pattern WCL1 and the second wavelength conversion pattern WCL2 may further include a scatterer SCP to improve wavelength conversion efficiency.

[0163] The light-transmitting layer TPL disposed in the third pixel SP3 may transmit the third color light L emitted from the light-emitting layer LEL while maintaining the wavelength of the light L. The scatterer SCP of the light-transmitting layer TPL may control the emission path of the light emitted through the light-transmitting layer TPL. The light-transmitting layer TPL may not include a wavelength conversion material.

[0164] The second cover layer 230 may be disposed on the wavelength conversion layer WCL, the light-transmitting layer TPL, and the partition wall PTL. The second cover layer 230 may be made of an inorganic material. The second cover layer 230 may include a material selected from the materials listed as the materials of the first cover layer 220. The second cover layer 230 and the first cover layer 220 may be made of the same material, but the present disclosure is not limited thereto.

[0165] Filler 300 may be disposed between display substrate 100 and color conversion substrate 200. Filler 300 may fill the space between display substrate 100 and color conversion substrate 200, and may bond and couple them to each other. Filler 300 may be disposed between encapsulation structure 170 of display substrate 100 and second cover layer 230 of color conversion substrate 200. Filler 300 may be made of, but not limited to, Si-based organic material or epoxy-based organic material.

[0166] Figure 7 is a pixel SP of the display device 10 according to the embodiment (see Figure 3 ) circuit diagram.

[0167] Reference Figure 7 , each pixel SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a first gate line GL1 , a second gate line GL2 , and a vertical voltage line VVSL.

[0168] Each pixel SP may include a pixel circuit and a light emitting element ED. The pixel circuit of each pixel SP may include first to third transistors ST1 to ST3 and a capacitor CPT.

[0169] The first transistor ST1 may include an upper gate electrode UGE (see Figure 8), the lower gate electrode BGE (see Figure 8 ), drain electrode DE (see Figure 8 ) and the source electrode SE (see Figure 8 ). The first transistor ST1 may have an upper gate electrode UGE connected to the first node N1, a lower gate electrode BGE connected to the second node N2, a drain electrode DE connected to the first voltage line VDL, and a source electrode SE connected to the second node N2. The first transistor ST1 may control a drain-source current (or a driving current) based on a data voltage applied to the upper gate electrode UGE and the lower gate electrode BGE. The first transistor ST1 may be a driving transistor that drives the light emitting element ED.

[0170] The light emitting element ED may emit light in response to the received driving current. The amount of light emitted from the light emitting element ED or the brightness of the light emitting element ED may be proportional to the magnitude of the driving current. The light emitting element ED may be an organic light emitting diode including an organic light emitting layer, a quantum dot light emitting diode including a quantum dot light emitting layer, a micro light emitting diode, or an inorganic light emitting diode including an inorganic semiconductor.

[0171] A first electrode of the light emitting element ED may be connected to the second node N2, and a second electrode of the light emitting element ED may be connected to the vertical voltage line VVSL. The first electrode of the light emitting element ED may be connected to the source electrode SE of the first transistor ST1, the drain electrode of the third transistor ST3, and the second capacitor node CN2 of the capacitor CPT through the second node N2.

[0172] The second transistor ST2 may be turned on by the first gate signal of the first gate line GL1 to electrically connect the data line DL and the first node N1 as the upper gate electrode UGE of the first transistor ST1. The second transistor ST2 may be turned on based on the first gate signal to supply a data voltage to the first node N1. The second transistor ST2 may have a gate electrode connected to the first gate line GL1, a drain electrode connected to the data line DL, and a source electrode connected to the first node N1. The source electrode of the second transistor ST2 may be connected to the upper gate electrode UGE of the first transistor ST1 and the first capacitor node CN1 of the capacitor CPT through the first node N1. The second transistor ST2 may be a switching transistor that controls a current flowing through the first transistor ST1 and the light emitting element ED.

[0173] The third transistor ST3 may be turned on by the second gate signal of the second gate line GL2 to electrically connect the initialization voltage line VIL and the second node N2 as the source electrode SE of the first transistor ST1. The third transistor ST3 may be turned on based on the second gate signal to supply the initialization voltage to the second node N2. The third transistor ST3 may be turned on based on the second gate signal to supply the sensing signal to the initialization voltage line VIL. The third transistor ST3 may have a gate electrode connected to the second gate line GL2, a drain electrode connected to the second node N2, and a source electrode connected to the initialization voltage line VIL. The drain electrode of the third transistor ST3 may be connected to the source electrode SE of the first transistor ST1 and the first electrode of the light emitting element ED through the second node N2, and may be connected to the second capacitor node CN2 of the capacitor CPT. The third transistor ST3 may be a switching transistor that controls the current flowing through the first transistor ST1 and the light emitting element ED.

[0174] The capacitor CPT may include a first capacitor C1, a second capacitor C2, and a third capacitor C3. The first capacitor C1, the second capacitor C2, and the third capacitor C3 may be connected in parallel to each other through a first capacitor node CN1 and a second capacitor node CN2. Therefore, the total capacitance of the capacitor CPT may be equal to the sum of the respective capacitances of the first capacitor C1, the second capacitor C2, and the third capacitor C3.

[0175] One electrode of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be connected to the first node N1 through the first capacitor node CN1. The other electrode of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3 may be connected to the second node N2 through the second capacitor node CN2.

[0176] Figure 8 The display device 10 according to the embodiment (see Figure 7 ) is a cross-sectional view of the first transistor ST1 and the capacitor CPT. Fig. 9 yes Figure 8 Magnified view of area A.

[0177] Apart from Figure 7 In addition, refer to Figure 8 and Fig. 9 , the circuit layer CCL may be disposed on the first substrate 110. The circuit layer CCL (e.g., thin film transistor layer) may include a first metal layer MTL1, a buffer layer BF, an active layer ACTL, a gate insulating layer GI, a second metal layer MTL2, an interlayer insulating layer ILD, a third metal layer MTL3, a first passivation layer PVX1, a first via layer VIA1, a fourth metal layer MTL4, a second passivation layer PVX2, and a second via layer VIA2.

[0178] The first metal layer MTL1 may be disposed on the first substrate 110. The first metal layer MTL1 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In an embodiment, the first metal layer MTL1 may include a lower gate electrode BGE of the first transistor ST1 and a first capacitor electrode CPE1 of the capacitor CPT.

[0179] The buffer layer BF may be disposed on the first metal layer MTL1. The buffer layer BF may be made of an inorganic material such as silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide. Alternatively, the buffer layer BF may be a multilayer in which a plurality of layers selected from silicon nitride layers, silicon oxynitride layers, silicon oxide layers, titanium oxide layers, and aluminum oxide layers are alternately stacked.

[0180] The active layer ACTL may be disposed on the buffer layer BF. The active layer ACTL may be made of polysilicon, single crystal silicon, low temperature polysilicon, amorphous silicon or oxide semiconductor material. In an embodiment, the active layer ACTL may include an active region ACT, a drain electrode DE and a source electrode SE of the first transistor ST1.

[0181] The gate insulating layer GI may be disposed on the active layer ACTL. The gate insulating layer GI may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0182] The second metal layer MTL2 may be disposed on the gate insulating layer GI. The second metal layer MTL2 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In an embodiment, the second metal layer MTL2 may include an upper gate electrode UGE of the first transistor ST1 and a second capacitor electrode CPE2 of the capacitor CPT.

[0183] The interlayer insulating layer ILD may be disposed on the second metal layer MTL2. The interlayer insulating layer ILD may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The interlayer insulating layer ILD may include a plurality of inorganic layers.

[0184] The third metal layer MTL3 may be disposed on the interlayer insulating layer ILD. The third metal layer MTL3 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In an embodiment, the third metal layer MTL3 may include a first connection electrode CE1, a third connection electrode CE3, and a third capacitor electrode CPE3 of the capacitor CPT.

[0185] The first passivation layer PVX1 may be disposed on the third metal layer MTL3. The first passivation layer PVX1 may be made of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0186] The first via layer VIA1 may be disposed on the first passivation layer PVX1. The first via layer VIA1 may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0187] The fourth metal layer MTL4 may be disposed on the first via layer VIA1. The fourth metal layer MTL4 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In an embodiment, the fourth metal layer MTL4 may include the second connection electrode CE2 and the fourth capacitor electrode CPE4 of the capacitor CPT.

[0188] The second passivation layer PVX2 may be disposed on the fourth metal layer MTL4. The second passivation layer PVX2 may be made of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0189] The second via layer VIA2 may be disposed on the second passivation layer PVX2. The second via layer VIA2 may be made of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0190] The circuit layer CCL may include first to third transistors ST1 to ST3 and a capacitor CPT. Since the cross-sectional structures of the second and third transistors ST2 and ST3 are similar to that of the first transistor ST1, for ease of description, the first transistor ST1 is described as an example.

[0191] The first transistor ST1 may include an active region ACT, an upper gate electrode UGE, a lower gate electrode BGE, a drain electrode DE, and a source electrode SE.

[0192] The active region ACT may be disposed in the active layer ACTL. The active region ACT may overlap with the upper gate electrode UGE. The active region ACT may be a non-conductive portion of the active layer ACTL in a region overlapping with the upper gate electrode UGE.

[0193] The upper gate electrode UGE may be disposed in the second metal layer MTL2. Figure 7 As shown in , the upper gate electrode UGE may be connected to the first capacitor node CN1 of the capacitor CPT through the first node N1.

[0194] The lower gate electrode BGE may be disposed in the first metal layer MTL1. Figure 7 As shown in , the lower gate electrode BGE may be connected to the second capacitor node CN2 of the capacitor CPT through the second node N2.

[0195] In the drawings, the display device 10 is shown as including a dual-gate structure, wherein the upper gate electrode UGE and the lower gate electrode BGE are respectively disposed above and below the active area ACT. However, the present disclosure is not limited thereto. For example, by omitting any one of the upper gate electrode UGE and the lower gate electrode BGE, the display device 10 may also include a top gate structure or a bottom gate structure.

[0196] The drain electrode DE and the source electrode SE may be formed by making the active layer ACTL conductive through a heat treatment. The drain electrode DE and the source electrode SE may be made of an N-type semiconductor, but the present disclosure is not limited thereto.

[0197] like Figure 7 As shown in , the drain electrode DE may be electrically connected to the first voltage line VDL. Figure 8 As shown in FIG. 1 , the drain electrode DE may be connected to the third link electrode CE3. Although not shown in the drawings, the third link electrode CE3 may be connected to the first voltage line VDL. Therefore, the drain electrode DE may receive a driving voltage from the first voltage line VDL.

[0198] like Figure 7 As shown in , the source electrode SE can be connected to the light emitting element ED through the second node N2. Figure 8 As shown in FIG. 1 , the source electrode SE may be connected to the pixel electrode PXE through the first connection electrode CE1 and the second connection electrode CE2 . Therefore, the source electrode SE may supply a driving current to the light emitting element ED.

[0199] The capacitor CPT may include a first capacitor electrode CPE1 , a second capacitor electrode CPE2 , a third capacitor electrode CPE3 , and a fourth capacitor electrode CPE4 .

[0200] The first capacitor electrode CPE1 may be disposed in the first metal layer MTL1. The second capacitor electrode CPE2 may be disposed in the second metal layer MTL2. The third capacitor electrode CPE3 may be disposed in the third metal layer MTL3. The fourth capacitor electrode CPE4 may be disposed in the fourth metal layer MTL4.

[0201] The first capacitor C1 may include a first capacitor electrode CPE1 and a second capacitor electrode CPE2. For example, one electrode of the first capacitor C1 may be the first capacitor electrode CPE1, and the other electrode of the first capacitor C1 may be the second capacitor electrode CPE2. The first capacitor C1 may be formed in a first overlap region OLP1 where the first capacitor electrode CPE1 and the second capacitor electrode CPE2 overlap.

[0202] The second capacitor C2 may include a second capacitor electrode CPE2 and a third capacitor electrode CPE3. For example, one electrode of the second capacitor C2 may be the second capacitor electrode CPE2, and the other electrode of the second capacitor C2 may be the third capacitor electrode CPE3. The second capacitor C2 may be formed in a second overlapping region OLP2 where the second capacitor electrode CPE2 and the third capacitor electrode CPE3 overlap.

[0203] The third capacitor C3 may include a third capacitor electrode CPE3 and a fourth capacitor electrode CPE4. For example, one electrode of the third capacitor C3 may be the third capacitor electrode CPE3, and the other electrode of the third capacitor C3 may be the fourth capacitor electrode CPE4. The third capacitor C3 may be formed in a third overlapping region OLP3 where the third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 overlap.

[0204] In some embodiments, the second capacitor electrode CPE2 and the fourth capacitor electrode CPE4 may be connected to the first capacitor node CN1, and the first capacitor electrode CPE1 and the third capacitor electrode CPE3 may be connected to the second capacitor node CN2. Therefore, the second capacitor electrode CPE2 and the fourth capacitor electrode CPE4 may have the same potential as the upper gate electrode UGE of the first transistor ST1, and the first capacitor electrode CPE1 and the third capacitor electrode CPE3 may have the same potential as at least one of the source electrode SE and the lower gate electrode BGE of the first transistor ST1.

[0205] In the display device 10 according to the current embodiment, in a plan view, the area of ​​the first overlap region OLP1 may be smaller than the area of ​​the second overlap region OLP2. In addition, in a plan view, the area of ​​the second overlap region OLP2 may be smaller than the area of ​​the third overlap region OLP3. In the display device 10 according to the current embodiment, the area of ​​each of the first capacitor electrode CPE1 to the third capacitor electrode CPE3 of the capacitor CPT may be minimized, but the total capacitance of the capacitor CPT may be increased.

[0206] More specifically, the first capacitor electrode CPE1 may be disposed in the same first metal layer MTL1 as the lower gate electrode BGE of the first transistor ST1. Therefore, since the first capacitor electrode CPE1 must be disposed in consideration of the lower gate electrode BGE, it may not be easy to increase the area of ​​the first capacitor electrode CPE1. That is, it may not be easy to increase the area of ​​the first overlap region OLP1.

[0207] In addition, the second capacitor electrode CPE2 can be set in the same second metal layer MTL2 as the upper gate electrode UGE of the first transistor ST1. Therefore, since the second capacitor electrode CPE2 must be set in consideration of the upper gate electrode UGE, it is not easy to increase the area of ​​the second capacitor electrode CPE2. That is, it is not easy to increase the area of ​​the second overlapping region OLP2.

[0208] In the display device 10 according to the current embodiment, the third capacitor electrode CPE3 connected to the first capacitor electrode CPE1 may be disposed in the third metal layer MTL3, and the fourth capacitor electrode CPE4 connected to the second capacitor electrode CPE2 may be disposed in the fourth metal layer MTL4. Therefore, the capacitance of the capacitor CPT may be increased.

[0209] For example, the area of ​​the third overlap region OLP3 may be increased by increasing the area of ​​the third capacitor electrode CPE3 disposed in the third metal layer MTL3 and the area of ​​the fourth capacitor electrode CPE4 disposed in the fourth metal layer MTL4. Therefore, the capacitance of the third capacitor C3 may be increased, thereby increasing the total capacitance of the capacitor CPT.

[0210] In addition, since the third capacitor electrode CPE3 is disposed in the third metal layer MTL3 and the fourth capacitor electrode CPE4 is disposed in the fourth metal layer MTL4 , line resistance between wirings of the first transistor ST1 and the capacitor CPT may be reduced.

[0211] The display device 10 may include a fifth metal layer MTL5 disposed on the circuit layer CCL.

[0212] The fifth metal layer MTL5 may be disposed on the circuit layer CCL. For example, the fifth metal layer MTL5 may be disposed on the second via layer VIA2. In an embodiment, the fifth metal layer MTL5 may include a pixel electrode PXE.

[0213] In the display device 10 according to the current embodiment, the pixel electrode PXE may include a different material from at least one of the first capacitor electrode CPE1 to the fourth capacitor electrode CPE4. For example, the conductivity of at least one of the first capacitor electrode CPE1 to the fourth capacitor electrode CPE4 may be higher than the conductivity of the pixel electrode PXE. Therefore, the capacitance of the capacitor CPT may be increased.

[0214] For example, as described above, the pixel electrode PXE may include a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) or a mixture thereof) and a layer of a reflective material (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof). The layer of the material having a high work function may be disposed on the layer of the reflective material so that the layer of the material having a high work function is positioned close to the light emitting layer LEL (see Figure 6 ). The pixel electrode PXE may include (but not limited to) ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure.

[0215] Each of the first capacitor electrodes CPE1 to the fourth capacitor electrodes CPE4 respectively disposed in the first metal layer MTL1 to the fourth metal layer MTL4 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. In some embodiments, the first capacitor electrodes CPE1 to the fourth capacitor electrodes CPE4 may include the same material.

[0216] Fig.10 The display device 10 according to the embodiment (see Figure 7 ) is a schematic layout diagram of a portion of ). Figures 11 to 13 is a plan view of the first overlap region OLP1, the second overlap region OLP2, and the third overlap region OLP3 according to an embodiment. Fig.10 , the first voltage line VDL, the first transistor ST1, and the capacitor CPT are shown, and other elements are omitted.

[0217] Apart from Figure 8 and Fig. 9 In addition, refer to Figures 10 to 13 , the first voltage line VDL, the lower gate electrode BGE of the first transistor ST1, and the first capacitor electrode CPE1 of the capacitor CPT may be disposed in the first metal layer MTL1. The drain electrode DE, the active area ACT, and the source electrode SE of the first transistor ST1 may be disposed in the active layer ACTL. The upper gate electrode UGE of the first transistor ST1 and the second capacitor electrode CPE2 of the capacitor CPT may be disposed in the second metal layer MTL2. The third capacitor electrode CPE3 of the capacitor CPT may be disposed in the third metal layer MTL3. The fourth capacitor electrode CPE4 of the capacitor CPT may be disposed in the fourth metal layer MTL4.

[0218] In some embodiments, the first capacitor electrode CPE1 of the capacitor CPT may be a part of the lower gate electrode BGE of the first transistor ST1. For example, the first capacitor electrode CPE1 of the capacitor CPT may be formed integrally with the lower gate electrode BGE of the first transistor ST1. The first capacitor electrode CPE1 of the capacitor CPT and the lower gate electrode BGE of the first transistor ST1 may be physically connected to form a planar electrode.

[0219] In some embodiments, the second capacitor electrode CPE2 of the capacitor CPT may be a portion of the upper gate electrode UGE of the first transistor ST1. For example, the second capacitor electrode CPE2 of the capacitor CPT may be formed integrally with the upper gate electrode UGE of the first transistor ST1. The second capacitor electrode CPE2 of the capacitor CPT and the upper gate electrode UGE of the first transistor ST1 may be physically connected to form a planar electrode.

[0220] like Figures 10 to 13 As shown in , the first overlapping region OLP1 may be a region where the first capacitor electrode CPE1 and the second capacitor electrode CPE2 overlap. The second overlapping region OLP2 may be a region where the second capacitor electrode CPE2 and the third capacitor electrode CPE3 overlap. The third overlapping region OLP3 may be a region where the third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 overlap.

[0221] In the display device 10 according to the current embodiment, the area of ​​the third overlap region OLP3 may be greater than the area of ​​the second overlap region OLP2, and the area of ​​the second overlap region OLP2 may be greater than the area of ​​the first overlap region OLP1. Therefore, the area of ​​each of the first to third capacitor electrodes CPE1 to CPE3 of the capacitor CPT may be minimized, but the total capacitance of the capacitor CPT may be increased.

[0222] In some embodiments, Fig.12 and Fig.13 As shown in FIG. 1 , the entire first overlap region OLP1 may overlap the second overlap region OLP2, and the entire second overlap region OLP2 may overlap the third overlap region OLP3. Therefore, the display device 10 according to the current embodiment can increase the capacitor CPT even in a small area (see FIG. 1 ). Fig.10 ) capacitor.

[0223] In the following embodiments, the same elements as those of the above-described embodiments are identified by the same reference numerals, and any redundant description thereof will be omitted or briefly given, and differences will be mainly described.

[0224] Fig.14 The display device 10 according to the embodiment (see Figure 7 ) is a cross-sectional view of the first transistor ST1 and the capacitor CPT. Fig.15 yes Fig.14 Magnified view of area B.

[0225] Reference Fig.14 and Fig.15 The display device 10 according to the present embodiment is different from the display device 10 according to the reference Figure 8 The display device 10 of the embodiment described above is different in that the first via layer VIA1 includes an opening OP to form a peak CRS and a valley VAL.

[0226] More specifically, the first via layer VIA1 may include an opening OP. The opening OP may overlap the capacitor CPT in the third direction DR3. The first passivation layer PVX1 may be exposed through the opening OP of the first via layer VIA1.

[0227] The first via layer VIA1 may include a valley VAL which is the lowest portion (lowest surface) disposed within the opening OP and a peak CRS which is the highest portion (highest surface) disposed outside the opening OP. The valley VAL of the first via layer VIA1 may expose the upper surface of the first passivation layer PVX1.

[0228] The fourth capacitor electrode CPE4 may be disposed on the first passivation layer PVX1 exposed by the opening OP of the first via layer VIA1. The fourth capacitor electrode CPE4 may be disposed on the valley VAL of the first via layer VIA1. The second connection electrode CE2 may be disposed on the peak CRS of the first via layer VIA1. Therefore, the fourth capacitor electrode CPE4 may be located at a lower level than the second connection electrode CE2.

[0229] In an embodiment, a thickness TH1 of the first via layer VIA1 may be about 1 μm to about 3 μm. A height difference between the second connection electrode CE2 and the fourth capacitor electrode CPE4 in the third direction DR3 may be about 1 μm to about 3 μm.

[0230] In the display device 10 according to the current embodiment, since the first via layer VIA1 includes an opening OP, a peak CRS and a valley VAL may be formed. Therefore, a distance D1 between the third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 in the third direction DR3 may be minimized. Therefore, the capacitance of the third capacitor C3 may be increased, thereby increasing the total capacitance of the capacitor CPT.

[0231] Fig.16 The display device 10 according to the embodiment (see Figure 7 ) is a cross-sectional view of the first transistor ST1 and the capacitor CPT.

[0232] Reference Fig.16 The display device 10 according to the present embodiment is different from the display device 10 according to the reference Fig.14 The display device 10 of the embodiment described above is different in that the display device 10 according to the current embodiment further includes a fourth connection electrode CE4.

[0233] More specifically, the display device 10 according to the current embodiment may further include a fourth connection electrode CE4 disposed in the third metal layer MTL3. The fourth connection electrode CE4 may be disposed between the second capacitor electrode CPE2 and the fourth capacitor electrode CPE4. The fourth connection electrode CE4 may electrically connect the second capacitor electrode CPE2 and the fourth capacitor electrode CPE4.

[0234] Since the fourth connection electrode CE4 is disposed between the second capacitor electrode CPE2 and the fourth capacitor electrode CPE4 in the display device 10 according to the current embodiment, the reliability of the display device 10 may be improved.

[0235] For example, according to the reference Fig.14 In the display device 10 of the embodiment described in the example of FIG. 1 , a first contact hole CNT1 (see FIG. 1 ) may be formed. Fig.21 ) to pass through both the first passivation layer PVX1 and the interlayer insulating layer ILD so that the fourth capacitor electrode CPE4 is connected to the second capacitor electrode CPE2. As will be described later in the method S1 of manufacturing a display device (see Fig.18 ) operation S200 (see Fig.18 ), when the first contact hole CNT1 is formed (see Fig.21), a contact hole in which the second connection electrode CE2 connected to the first transistor ST1 is to be positioned may also be formed. Here, while the first contact hole CNT1 is formed by simultaneously etching the first passivation layer PVX1 and the interlayer insulating layer ILD, a contact hole in which the second connection electrode CE2 is to be positioned may be formed by etching only the first passivation layer PVX1. Since the display device 10 according to the current embodiment further includes the fourth connection electrode CE4, the difference in the degree of etching required may be eliminated. Therefore, the reliability of the display device 10 may be improved.

[0236] Fig.17 The display device 10 according to the embodiment (see Figure 7 ) is a cross-sectional view of the first transistor ST1 and the capacitor CPT.

[0237] Reference Fig.17 The display device 10 according to the present embodiment is different from the display device 10 according to the reference Fig.14 The display device 10 of the embodiment described above is different in that the first via layer VIA1 includes a groove GRV instead of an opening OP.

[0238] More specifically, the first via layer VIA1 may include a groove GRV. The groove GRV may overlap the capacitor CPT in the third direction DR3.

[0239] The first via layer VIA1 may include a valley VAL which is a lowest portion (lowest surface) disposed within the groove GRV and a peak CRS which is a highest portion (highest surface) disposed outside the groove GRV.

[0240] The fourth capacitor electrode CPE4 may be disposed on a valley VAL of the first via layer VIA1 disposed in the groove GRV of the first via layer VIA1. The fourth capacitor electrode CPE4 may be disposed on the valley VAL of the first via layer VIA1. The second connection electrode CE2 may be disposed on a peak CRS of the first via layer VIA1. Therefore, the fourth capacitor electrode CPE4 may be located at a lower level than the second connection electrode CE2.

[0241] In an embodiment, a thickness TH2 between the lower surface of the first via layer VIA1 and the peak CRS may be about 1.5 μm to about 4.5 μm. A thickness TH3 between the lower surface of the first via layer VIA1 and the valley VAL may be about 0.5 μm to about 1.5 μm.

[0242] When the method S1 (see FIG. 1 ) of manufacturing a display device to be described later is not performed Fig.18 ) operation S300 (see Fig.18) without reducing the thickness of the first via layer VIA1, the display device 10 according to the current embodiment can be formed. For example, when the fourth metal layer MTL4 is stacked while in operation S100 (see Fig.18 ) is maintained as it is, a display device shaped like the display device 10 according to the current embodiment can be formed. Therefore, since the ashing process is not performed, process efficiency can be improved.

[0243] A method for manufacturing a display device according to an embodiment will now be described. Fig.14 The method of the display device of the embodiment is taken as an example.

[0244] Fig.18 It shows the manufacturing basis Fig.14 A flow chart of a method S1 of a display device of an embodiment. Fig.19 and Fig. 20 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S100 . Fig.21 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S200 . Fig. 22 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S300 . Fig.23 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S400 . Fig.24 and Fig.25 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S500 . Fig.26 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S600 . Fig. 27 It is shown Fig.18 FIG. 5 is a cross-sectional view of operation S700 .

[0245] Reference Figures 18 to 27 , a method S1 of manufacturing a display device according to an embodiment may include: forming a groove in a first via layer using a halftone mask (operation S100); forming a first contact hole in a first passivation layer and an interlayer insulating layer using the first via layer as a mask (operation S200); forming an opening by reducing the thickness of the first via layer through an ashing process (operation S300); forming a fourth metal layer on the first via layer (operation S400); forming a second passivation layer and a second via layer on the fourth metal layer (operation S500); forming a second contact hole in the second passivation layer and the second via layer (operation S600); and forming a fifth metal layer on the second via layer (operation S700).

[0246] First, if Fig.19 and Fig. 20As shown in FIG. 1 , in forming a groove in the first via layer using a halftone mask (operation S100 ), a first via layer VIA1 may be formed on the first passivation layer PVX1 . The first via layer VIA1 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0247] Next, a groove GRV may be formed in the first via layer VIA1 by a photolithography process. A half-tone mask HFM may be used in the photolithography process. The half-tone mask HFM may be a mask in which regions with different transmittances exist in the mask. For example, the half-tone mask HFM may include a first region AR1, a second region AR2, and a third region AR3 with different transmittances.

[0248] When the halftone mask HFM uses a positive method, the transmittance may gradually increase in the order of the third area AR3, the second area AR2, and the first area AR1. When the halftone mask HFM uses a negative method, the transmittance may gradually increase in the order of the first area AR1, the second area AR2, and the third area AR3.

[0249] The thickness of the first via layer VIA1 may gradually increase in the order of the first area AR1, the second area AR2, and the third area AR3. A hole may be formed in the third area AR3 to expose the first passivation layer PVX1, and a groove GRV may be formed in the second area AR2 to form a valley VAL (see FIG. Fig.17 ).

[0250] Second, if Fig.21 As shown in, in forming a first contact hole in the first passivation layer and the interlayer insulating layer using the first via layer as a mask (operation S200), the first passivation layer PVX1 and the interlayer insulating layer ILD may be etched to form a contact hole exposing the second metal layer MTL2 and the third metal layer MTL3. In an embodiment, the first passivation layer PVX1 and the interlayer insulating layer ILD may be etched by dry etching, but the present disclosure is not limited thereto.

[0251] For example, a portion of the first passivation layer PVX1 may be etched to form a contact hole exposing the first connection electrode CE1 connected to the first transistor ST1. In addition, portions of the first passivation layer PVX1 and the interlayer insulating layer ILD may be etched to form an exposed capacitor CPT (see Fig.17 )'s first contact hole CNT1 of the second capacitor electrode CPE2.

[0252] In some embodiments, as described above with reference to Fig.16 As described above, when the fourth connection electrode CE4 (see Fig.16) is disposed in the third metal layer MTL3, the first contact hole CNT1 may pass through only the first passivation layer PVX1 and may not pass through the interlayer insulating layer ILD.

[0253] Third, if Fig. 22 As shown in FIG. 2 , in forming the opening by reducing the thickness of the first via layer through an ashing process (operation S300 ), the thickness of the first via layer VIA1 may be reduced through the ashing process.

[0254] As the thickness of the first via layer VIA1 decreases, the Fig. 20 ) in the groove GRV (see Fig.21 ) may be changed to the opening OP. A portion of the first passivation layer PVX1 may be exposed through the opening OP of the first via layer VIA1.

[0255] In some embodiments, as described above with reference to Fig.17 As described, the method for manufacturing a display device S1 (see Fig.18 ) in the process of omitting operation S300 (see Fig.18 ). In this case, as in Fig.17 The display device 10 of the embodiment (see Figure 7 ), the first via layer VIA1 may include a groove GRV instead of an opening OP.

[0256] Fourth, if Fig.23 As shown in , in forming the fourth metal layer on the first via layer (operation S400), a fourth metal layer MTL4 may be formed on the first via layer VIA1. The fourth metal layer MTL4 may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0257] The fourth metal layer MTL4 may include a second connection electrode CE2 connected to the first transistor ST1 and a capacitor CPT (see Fig.17 The second connection electrode CE2 may be disposed on the peak CRS of the first via layer VIA1, and the fourth capacitor electrode CPE4 may be disposed on the valley VAL located within the opening OP of the first via layer VIA1.

[0258] As in accordance with Fig.14 In the display device 10 of the embodiment of FIG. 1 , when the first via layer VIA1 includes an opening OP, the fourth capacitor electrode CPE4 may be disposed on the first passivation layer PVX1. Fig.17 In the display device 10 of the embodiment of the present invention, when the first via layer VIA1 includes the groove GRV, the fourth capacitor electrode CPE4 (see Fig.16 ) may be disposed on the first via layer VIA1.

[0259] Fifth, if Fig.24 and Fig.25 As shown in FIG. 1 , in forming a second passivation layer and a second via layer on a fourth metal layer (operation S500), a second passivation layer PVX2 may be formed on the fourth metal layer MTL4. The second passivation layer PVX2 may be made of an inorganic layer such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0260] The second via layer VIA2 may be formed on the second passivation layer PVX2. The second via layer VIA2 may be made of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0261] Sixth, if Fig.26 As shown in , in forming a second contact hole in the second passivation layer and the second via layer (operation S600), the second passivation layer PVX2 and the second via layer VIA2 may be etched to form a contact hole exposing the fourth metal layer MTL4. In an embodiment, the second passivation layer PVX2 and the second via layer VIA2 may be etched by dry etching, but the present disclosure is not limited thereto.

[0262] In an embodiment, as in operation S200 (see Fig.18 ), after the second via layer VIA2 is patterned by a photoresist process, the second passivation layer PVX2 may be etched using the patterned second via layer VIA2 as a mask.

[0263] Seventh, such as Fig. 27 As shown in FIG. 1 , in forming the fifth metal layer on the second via layer (operation S700), a fifth metal layer MTL5 may be formed on the second via layer VIA2. The fifth metal layer MTL5 may include a material having a high work function (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) or a mixture thereof and a stacked structure of a layer of a reflective material (such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof).

[0264] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed preferred embodiments of the present invention are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; A first metal layer is disposed on the substrate; An active layer, disposed on the first metal layer; A second metal layer is disposed on the active layer; a third metal layer, disposed on the second metal layer; a fourth metal layer, disposed on the third metal layer; and transistors and capacitors, disposed on the substrate, Wherein, the transistor comprises: a gate electrode disposed in at least one of the first metal layer and the second metal layer; and A drain electrode, a source electrode and an active region are provided in the active layer, and wherein the capacitor comprises: A first capacitor including a first electrode disposed in the first metal layer and a second electrode disposed in the second metal layer; a second capacitor including the second electrode and a third electrode disposed in the third metal layer; and The third capacitor includes the third electrode and a fourth electrode disposed in the fourth metal layer.

2. The display device according to claim 1, wherein: The display device further includes: a first connection electrode disposed in the fourth metal layer and electrically connected to any one of the drain electrode and the source electrode; and A light emitting element is disposed on the fourth metal layer and connected to the first connecting electrode.

3. The display device according to claim 2, wherein: The display device comprises: a first overlapping region, in which the first electrode overlaps with the second electrode; a second overlapping region, in which the second electrode overlaps the third electrode; and a third overlapping region, in which the third electrode overlaps with the fourth electrode, The area of ​​the third overlapping region is larger than each of the area of ​​the first overlapping region and the area of ​​the second overlapping region.

4. The display device according to claim 3, wherein: All of the first overlapping areas and all of the second overlapping areas overlap with the third overlapping area.

5. The display device according to claim 2, wherein: The light emitting element includes a pixel electrode connected to the first connection electrode, and The pixel electrode and at least one of the first to fourth electrodes include different materials.

6. The display device according to claim 5, wherein: The electrical conductivity of at least one of the first electrode to the fourth electrode is higher than the electrical conductivity of the pixel electrode.

7. The display device according to claim 5, wherein: The pixel electrode includes at least one of indium tin oxide, indium zinc oxide, zinc oxide, and indium oxide and at least one of silver, magnesium, aluminum, platinum, lead, gold, nickel, neodymium, iridium, chromium, lithium, and calcium, and At least one of the first to fourth electrodes includes at least one of molybdenum, aluminum, chromium, gold, titanium, nickel, neodymium, and copper.

8. The display device according to claim 2, wherein: The display device further includes a first via layer disposed between the third metal layer and the fourth metal layer, wherein: The first via layer includes an opening or a groove overlapping the capacitor, and The fourth electrode is disposed in the opening or the groove.

9. The display device according to claim 8, wherein: The fourth electrode is located at a lower level than the first connection electrode.

10. The display device according to claim 9, wherein: The display device further includes a second connection electrode that is disposed in the third metal layer and connects any one of the drain electrode and the source electrode to the first connection electrode. Wherein, in the thickness direction of the substrate, a distance between the third electrode and the fourth electrode is smaller than a distance between the first connecting electrode and the second connecting electrode.

11. The display device according to claim 8, wherein: The display device further includes a first passivation layer disposed between the first via layer and the third metal layer, wherein: The first via layer includes the opening, The first passivation layer is exposed through the opening, and The fourth electrode is disposed on the first passivation layer exposed through the opening.

12. The display device according to claim 8, wherein: The first via layer includes the groove, The first via layer includes a valley as the lowest surface disposed in the groove and a peak as the highest surface disposed outside the groove, and The fourth electrode is disposed on the valley.

13. The display device according to claim 8, wherein: The display device further includes a third connection electrode disposed in the third metal layer. Wherein, the third connecting electrode is arranged between the fourth electrode and the second electrode.

14. The display device according to claim 13, wherein: The third connection electrode electrically connects the fourth electrode and the second electrode to each other.

15. The display device according to claim 1, wherein: The second electrode and the fourth electrode are electrically connected to each other, and The first electrode and the third electrode are electrically connected to each other.

16. The display device according to claim 1, wherein: The gate electrode disposed in the first metal layer is a lower gate electrode, The gate electrode disposed in the second metal layer is an upper gate electrode, The first electrode and the third electrode have the same potential as at least one of the source electrode and the lower gate electrode, and The second electrode and the fourth electrode have the same potential as the upper gate electrode.

17. The display device according to claim 16, wherein: The second electrode is a portion of the upper gate electrode.

18. The display device according to claim 17, wherein: The first electrode is a portion of the lower gate electrode.

19. A display device, wherein: The display device comprises: substrate; A first metal layer is disposed on the substrate; A second metal layer, disposed on the first metal layer; a third metal layer, disposed on the second metal layer; a first via layer disposed on the third metal layer and comprising valleys and peaks; a fourth metal layer, disposed on the first via layer; and A capacitor is disposed on the substrate. Wherein, the capacitor comprises: A first electrode is disposed in the first metal layer; A second electrode is disposed in the second metal layer; A third electrode is disposed in the third metal layer; and a fourth electrode disposed in the fourth metal layer, and Wherein, the fourth electrode is arranged on the valley of the first via layer.

20. The display device according to claim 19, wherein: The second electrode and the fourth electrode are electrically connected to each other, and The first electrode and the third electrode are electrically connected to each other.

21. A method for manufacturing a display device, wherein: The display device includes a substrate, a first metal layer disposed on the substrate, a second metal layer disposed on the first metal layer, a third metal layer disposed on the second metal layer, a first via layer disposed on the third metal layer, and a capacitor disposed on the substrate, and the method includes: forming a groove in the first via layer using a half-tone mask; and forming a fourth metal layer on the first via layer, Wherein, the capacitor comprises: A first electrode is disposed in the first metal layer; A second electrode is disposed in the second metal layer; A third electrode is disposed in the third metal layer; and a fourth electrode disposed in the fourth metal layer, and The fourth electrode is formed in the groove.

22. The method according to claim 21, wherein: The method further comprises: after forming the groove, forming an opening by reducing the thickness of the first via layer, Wherein, in the forming of the fourth electrode, the fourth electrode is formed in the opening.

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