Mother substrate for display panel and display panel using same

Abstract

The invention discloses a mother substrate for a display panel and a display panel using the same. A mother substrate for a display panel includes: a plurality of display areas including a plurality of light emitting areas in which light emitting elements are to be disposed, a plurality of wirings, and a plurality of pads connected to the wirings; a conductive ring disposed in the non-display area outside the display area to surround each display area, and electrically connected to the pad; a photoresist pattern covering the display area and the non-display area; and a first metal layer covering the photoresist pattern. The conductive ring includes an electrostatic blocking region.

Description

Technical Field

[0001] The present disclosure relates to a mother substrate for a display panel and a display panel using the same. Background Art

[0002] Electroluminescent display devices may be roughly divided into organic light emitting display devices in which organic light emitting diodes (OLEDs) are provided in pixels and inorganic light emitting display devices in which inorganic light emitting diodes (hereinafter referred to as “LEDs”) are provided in pixels.

[0003] Since electroluminescent display devices use self-luminous elements to display images, they do not require a separate light source such as a backlight unit and can be implemented in a thin and diverse form. Electroluminescent display devices not only have excellent power consumption, response speed, brightness, and viewing angle, but also have excellent contrast and color reproduction rate because they can represent black grayscale as completely black.

[0004] Organic light emitting display devices need to be designed to prevent or reduce the penetration of oxygen and moisture, because the penetration of moisture and oxygen may cause oxidation between the organic light emitting layer and the electrode.

[0005] As an example of an inorganic light-emitting display device, a micro LED display device in which micro LEDs are arranged in pixels has attracted attention as a next-generation display device. Micro LEDs may be inorganic LEDs having a size of 100 μm or less. Micro LEDs are manufactured by a separate semiconductor process and are transferred to pixel positions on a substrate of a display panel for a display device so that they can be arranged in each sub-pixel of each color.

[0006] The description provided in this Background section should not be assumed to be prior art merely because it is mentioned in the Background section or associated with the Related Art section.The Background section may include information that describes one or more aspects of the subject technology. Summary of the invention

[0007] During the manufacturing process of the display panel, electrostatic discharge (ESD) may occur, which may cause problems such as dielectric breakdown or short circuits between thin film layers of the display panel.

[0008] Therefore, the inventors of the present disclosure recognized the above-mentioned problems and other limitations associated with the related art, and conducted various experiments to realize a mother substrate for a display panel and a display panel using the same, which substantially eliminates one or more problems caused by the limitations and disadvantages of the related art.

[0009] Therefore, embodiments of the present disclosure provide a mother substrate for a display panel capable of blocking electrostatic discharge affecting the display panel and a display panel using the same.

[0010] The problems of the present disclosure are not limited to the above-mentioned problems, and other unmentioned problems will be clearly understood by those skilled in the art from the following description.

[0011] One aspect of the present disclosure is to provide a mother substrate for a display panel, comprising: a plurality of display areas, including a plurality of light-emitting areas in which light-emitting elements are to be arranged, a plurality of wirings, and a plurality of pads connected to the wirings; a conductive ring, which is arranged in a non-display area outside the display area to surround each display area and is electrically connected to the pad; a photoresist pattern, which covers the display area and the non-display area; and a first metal layer, which covers the photoresist pattern. The conductive ring includes an electrostatic blocking area. The electrostatic blocking area includes a second metal layer spaced apart from the first metal layer, and the photoresist pattern is inserted therebetween. The light-emitting area includes a third metal layer spaced apart from the first metal layer, and the photoresist pattern is inserted therebetween. The first distance between the second metal layer and the first metal layer arranged in the electrostatic blocking area is less than the second distance between the third metal layer and the first metal layer arranged in the light-emitting area.

[0012] A display panel according to one embodiment of the present disclosure is separated from a mother substrate for a display panel and includes a display area without a photoresist pattern and a first metal layer.

[0013] In the present disclosure, the display panel and the conductive ring can be connected at the same potential on the mother substrate, and an electrostatic blocking area including a capacitor formed by utilizing the small spacing between metal layers can be provided in the conductive ring to prevent or reduce display panel defects caused by ESD caused in the manufacturing process of the display panel.

[0014] In the present disclosure, the yield of the display panel can be increased, the manufacturing process of the display panel can be optimized, and the production energy can be reduced.

[0015] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

[0016] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon review of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included in this specification, be within the scope of the present disclosure, and be protected by the appended claims. Nothing in this section shall be construed as limiting these claims. Other aspects and advantages are discussed below in conjunction with embodiments of the present disclosure.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which may be included to provide a further understanding of the disclosure and may be incorporated in and constitute a part of this disclosure, illustrate embodiments of the disclosure and together with the description serve to explain various principles of the disclosure.

[0019] The above and other objects, features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0020] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure;

[0021] Figure 2 The present invention is shown in the embodiment of the present invention. Figure 1 An enlarged view of region A;

[0022] Figure 3 is a diagram illustrating a local area of ​​a pixel according to an embodiment of the present disclosure;

[0023] Figure 4 According to the embodiment of the present disclosure, Figure 3 A cross-sectional view taken along line II′ in FIG.

[0024] Figure 5 According to the embodiment of the present disclosure, Figure 3 A cross-sectional view taken along line II-II′;

[0025] Figure 6 According to the embodiment of the present disclosure, Figure 3 A cross-sectional view taken along line III-III′ in FIG.

[0026] Figure 7 is a cross-sectional view illustrating an example in which a main light emitting element and a sub light emitting element are electrically connected to a pixel driving circuit according to an embodiment of the present disclosure;

[0027] Figure 8 is a diagram illustrating a display device according to another embodiment of the present disclosure;

[0028] Fig. 9 According to the embodiment of the present disclosure, Figure 8 A cross-sectional view taken along line IV-IV′ in FIG.

[0029] Fig.10 is a diagram illustrating two display panels disposed on a mother substrate according to an embodiment of the present disclosure;

[0030] Fig.11 According to one embodiment of the present disclosure Fig.10 An enlarged view of portion B is shown;

[0031] Fig.12 is a diagram showing a method of performing the following steps according to an embodiment of the present disclosure. Fig.11 A cross-sectional view of the cross-sectional structure of the electrostatic blocking region cut along line VV′ in FIG.

[0032] Fig.13 is a cross-sectional view showing a cross-sectional structure covered with a photoresist and a metal layer in a display area of ​​a display panel according to an embodiment of the present disclosure;

[0033] Fig.14 is a cross-sectional view illustrating an example in which the density of a metal layer is different between an electrostatic blocking region and a light emitting region on a mother substrate according to an embodiment of the present disclosure;

[0034] Fig.15 is a cross-sectional view illustrating an example in which the thickness of an insulating layer is different between an electrostatic blocking region and a light emitting region on a mother substrate according to an embodiment of the present disclosure;

[0035] Fig.16 According to another embodiment of the present disclosure Fig.10 an enlarged view of portion B as shown; and

[0036] Fig.17 According to the embodiment of the present disclosure, Fig.16 A cross-sectional view of the cross-sectional structure of the electrostatic blocking area cut along line VI-VI′ in FIG.

[0037] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0038] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when a detailed description of a well-known function or configuration associated with this document is determined to be unnecessary to obscure the gist of the inventive concept, its detailed description will be omitted. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein, and may be changed as known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals designate similar elements throughout the text. The names of the corresponding elements used in the following description may be selected only for the convenience of writing the specification, and therefore may be different from the names used in the actual product.

[0039] The advantages and features of the present disclosure and their implementation methods will be more clearly understood from the example embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following example embodiments, but can be implemented in various different forms. On the contrary, this example embodiment will make the disclosure of the present disclosure complete and help those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is defined only within the scope of the attached claims.

[0040] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings for describing various example embodiments of the present disclosure are given only by way of example, and the present disclosure is not limited thereto. Similar reference numerals generally refer to similar elements throughout the specification. In addition, when describing the present disclosure, a detailed description of known related technologies may be omitted or may be briefly provided to avoid unnecessarily obscuring the subject matter of the present disclosure. Any implementation described herein as an "example" is not necessarily to be interpreted as being preferred or advantageous over other implementations.

[0041] Terms such as "include," "comprising," "having," and "including" used herein are generally intended to allow the addition of other components unless these terms are used with a term such as "only." Elements described in the singular are intended to include plural elements and vice versa unless the context clearly indicates otherwise.

[0042] Even if not explicitly mentioned, the components are interpreted as including the ordinary error range.

[0043] When describing the position or interconnection relationship between two components, such as "on top", "above", "below", "beside", "connected or coupled", "crossed", "intersecting", etc., unless words such as "immediately", "directly" or "closely" are used, one or more other components may be interposed therebetween. For example, when a structure is described as being located "on", "above", "below", "over", "below", "below", "adjacent" to, "close to" or "adjacent to", "beside", or "next to" another structure, this description should be interpreted as including the case where the structures are in contact with each other and the case where a third structure is disposed or interposed therebetween. In addition, the terms "left", "right", "top", "bottom", "downward", "upward", "up", "down", etc. refer to an arbitrary reference system.

[0044] When describing a temporal relationship, such as "after", "after", "next", "before", etc., it may not be continuous in terms of time reference unless "only", "immediately" or "directly" is used.

[0045] Terms such as “first”, “second”, “A”, “B”, “(a)”, “(b)”, etc. may be used to distinguish elements from each other, but the function or structure of a component is not limited by the ordinal number preceding the component or the component name.

[0046] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first, second, and third items" means all combinations of items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless expressly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0048] The features in the various embodiments of the present disclosure may be partially or entirely connected or combined with each other, and may be technically interoperable and driven with each other in various ways, as can be fully understood by those skilled in the art. The embodiments of the present disclosure may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0049] Hereinafter, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, all components of each mother substrate and each display panel according to all embodiments of the present disclosure are operationally connected and configured. For ease of description, the scale of each element shown in the accompanying drawings is different from the actual scale and is therefore not limited to the scale shown in the drawings.

[0050] A display device according to an embodiment of the present specification includes: a display panel having a display area or screen on which an image is displayed, and a pixel driving circuit for driving pixels on the display panel. The display area includes a pixel area in which pixels are arranged. The pixel area includes a plurality of light-emitting areas. A light-emitting element is provided in each light-emitting area. The pixel driving circuit can be built into the display panel.

[0051] Figure 1 is a diagram illustrating a display device according to one embodiment of the present specification; Figure 2 yes Figure 1 An enlarged view of region A; Figure 3is a diagram illustrating a local area of ​​a pixel.

[0052] Reference Figure 1 and Figure 2 , a display device according to one embodiment of the present specification includes a display panel 100 that visually reproduces an input image. The display panel 100 may include a display area AA in which an image is displayed and a non-display area NA in which an image is not displayed. The non-display area NA may be adjacent to the display area AA, or may be disposed to at least partially surround the display area AA. In the non-display area NA, various wirings and driving circuits may be installed, and a pad portion PAD connected to an integrated circuit, a printed circuit, etc. may be disposed.

[0053] The plurality of light emitting elements 10 disposed in the display area AA to form the pixel PXL may be micro-sized inorganic light emitting elements. The inorganic light emitting elements may be grown on a silicon wafer and then attached to the display panel through a transfer process.

[0054] The transfer process of the light emitting element 10 may be performed for each pre-divided region. Figure 1 , the display area AA is divided into nine transfer areas ST, but the size or number of the division of the transfer area is not limited thereto. The transfer process may be performed sequentially or simultaneously on the first to ninth transfer areas ST. In the transfer areas ST, the blue light emitting element 10, the green light emitting element 10, and the red light emitting element 10 may be sequentially transferred, respectively.

[0055] In the non-display area NA, a data driving circuit or a gate driving circuit may be provided, and wiring for providing a control signal to control these driving circuits may be provided. Here, the control signal may include various timing signals including a clock signal, an input data enable signal, and a synchronization signal and may be received through the pad portion PAD.

[0056] The pixel PXL can be driven by a pixel driving circuit. The pixel driving circuit can receive a driving voltage, an image signal (digital signal), a synchronization signal synchronized with the image signal, etc., and output an anode voltage and a cathode voltage of the light-emitting element 10 to drive a plurality of pixels. The driving voltage can be a high potential voltage (EVDD). The cathode voltage can be a low potential voltage (EVSS) commonly applied to the pixel. The anode voltage can be a voltage corresponding to the pixel data value of the image signal. The pixel driving circuit can be arranged in the non-display area NA or in the lower part of the display area AA.

[0057] Each pixel PXL may include a plurality of sub-pixels, each sub-pixel having a different color (e.g., white, red, green, or blue, or cyan, magenta, or yellow, etc.). For example, the plurality of pixels may include a red sub-pixel in which a light emitting element 10 emitting red wavelength light is disposed, a green sub-pixel in which a light emitting element 10 emitting green wavelength light is disposed, and a blue sub-pixel in which a light emitting element 10 emitting blue wavelength light is disposed. The plurality of pixels may also include white pixels or white sub-pixels.

[0058] Reference Figure 2 and Figure 3 , a plurality of pixels PXL may be sequentially arranged in a first direction (X-axis direction) and a second direction (Y-axis direction). In a pixel of the display area AA, a plurality of sub-pixels of the same color may be arranged. For example, each of the plurality of pixels may include a first red sub-pixel in which a 1-1 light-emitting element 11a emitting light of a red wavelength is arranged, a second red sub-pixel in which a 1-2 light-emitting element 11b emitting light of a red wavelength is arranged, a first green sub-pixel in which a 2-1 light-emitting element 12a emitting light of a green wavelength is arranged, a second green sub-pixel in which a 2-2 light-emitting element 12b emitting light of a green wavelength is arranged, a first blue sub-pixel in which a 3-1 light-emitting element 13a emitting light of a blue wavelength is arranged, and a second blue sub-pixel in which a 3-2 light-emitting element 13b emitting light of a blue wavelength is arranged. The 1-1 light-emitting element 11a, the 2-1 light-emitting element 12a, and the 3-1 light-emitting element 13a may be interpreted as main light-emitting elements. The 1-2nd light emitting element 11b, the 2-2nd light emitting element 12b, and the 3-2nd light emitting element 13b may be interpreted as sub-light emitting elements. However, the present disclosure is not limited thereto. For example, the number of each of the main light emitting element and the sub-light emitting element may be changed in various ways.

[0059] One sub-pixel includes one or more light emitting elements, and if one light emitting element becomes defective, the brightness of another light emitting element can be increased to adjust the brightness of the sub-pixel. However, this is not necessarily limited to this, and one sub-pixel may include only one light emitting element.

[0060] Each of the plurality of first electrodes 161 may be disposed in the lower portion of the light emitting element 10, and may be selectively connected to the plurality of signal wirings TL1 to TL6 through the connection portion 161a. A high potential voltage may be applied to the pixel driving circuit through the signal wirings TL1 to TL6. The signal wirings TL1 to TL6 and the first electrodes 161 may be formed as an electrode pattern integrated in an electrode patterning process.

[0061] Exemplarily, the first signal wiring TL1 may be connected to the anode electrode of the first red sub-pixel, and the second signal wiring TL2 may be connected to the anode electrode of the second red sub-pixel. The third signal wiring TL3 may be connected to the anode electrode of the first green sub-pixel, and the fourth signal wiring TL4 may be connected to the anode electrode of the second green sub-pixel. The fifth signal wiring TL5 may be connected to the anode electrode of the first blue sub-pixel, and the sixth signal wiring TL6 may be connected to the anode electrode of the second blue sub-pixel. If one sub-pixel includes only one light-emitting element, the number of signal wirings TL may be reduced by half.

[0062] The second electrode 170 may be a cathode electrode arranged in each row to apply a cathode voltage to the light emitting elements 10 arranged continuously in the first direction (X-axis direction). A plurality of second electrodes 170 may be arranged to be spaced apart from each other in the second direction (Y-axis direction). A plurality of second electrodes 170 may be connected to the cathode voltage through the contact electrode 163. Each of the plurality of second electrodes 170 may be electrically connected to the contact electrode 163. However, this is not necessarily limited thereto, and the second electrode 170 may include one electrode layer instead of being divided into a plurality of electrodes to serve as a common electrode.

[0063] Figure 4 It is along Figure 3 A cross-sectional view taken along line II′ in FIG. Figure 5 It is along Figure 3 A cross-sectional view taken along line II-II′. Figure 6 It is along Figure 3 A cross-sectional view taken along line III-III′ in FIG. Figure 7 is a cross-sectional view showing an example in which two light emitting elements are connected to a pixel driving circuit.

[0064] Reference Figures 3 to 5 According to an embodiment, the display device includes a plurality of first electrodes 161 and a contact electrode 163 disposed on a substrate 110, a plurality of light emitting elements 10 disposed on the plurality of first electrodes 161, a first optical layer 141 disposed between the plurality of light emitting elements 10, and a second electrode 170 disposed on the plurality of light emitting elements 10.

[0065] The substrate 110 may be made of plastic having flexibility. For example, the substrate 110 may be a single-layer or multi-layer substrate made of one or more materials selected from the group consisting of polyimide, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyether sulfone, polyacrylate, polysulfone, and cyclic olefin copolymer, but is not limited thereto. For example, the substrate 110 may be a ceramic substrate or a glass substrate.

[0066] The pixel driving circuit 20 may be disposed in the display area AA on the substrate 110. The pixel driving circuit 20 may include a plurality of thin film transistors using an amorphous silicon semiconductor, a polysilicon semiconductor, or an oxide semiconductor.

[0067] The pixel driving circuit 20 may include at least one driving thin film transistor, at least one switching thin film transistor, and at least one storage capacitor. When the pixel driving circuit 20 includes a plurality of thin film transistors, it may be formed on the substrate 110 by a thin film transistor (TFT) manufacturing process. In an embodiment, the pixel driving circuit 20 may be a unified term for a plurality of thin film transistors electrically connected to the light emitting element 10.

[0068] The pixel driving circuit 20 may be a driver manufactured using a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process on a single crystal semiconductor substrate 110. The driver may include a plurality of pixel driving circuits driving a plurality of sub-pixels. When the pixel driving circuit 20 is implemented as a driver, after an adhesive layer is provided on the substrate 110, the driver may be mounted on the adhesive layer by a transfer process.

[0069] A buffer layer 121 covering the pixel driving circuit 20 may be disposed on the substrate 110. The buffer layer 121 may be made of an organic insulating material (eg, photosensitive photoacrylic or photosensitive polyimide), but is not limited thereto.

[0070] The buffer layer 121 may be formed by stacking an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO2), into multiple layers, and may be formed by stacking an organic insulating material and an inorganic insulating material into multiple layers.

[0071] The insulating layer 122 may be disposed on the buffer layer 121. The insulating layer 122 may be made of an organic insulating material (e.g., photosensitive photoacrylic or photosensitive polyimide), but is not limited thereto. The connection wirings RT1 and RT2 may be disposed on the buffer layer 121. The connection wirings RT1 and RT2 may be connected by corresponding signal wirings TL1 to TL6, or may be connected to the signal wirings TL1 to TL6. The connection wirings RT1 and RT2 may include a plurality of wiring patterns disposed on different layers, with one or more insulating layers interposed therebetween. The wiring patterns disposed on different layers may be electrically connected via contact holes passing through the insulating layers.

[0072] A plurality of bank patterns 130 may be disposed on the insulating layer 122. At least one light emitting element 10 may be disposed on each bank pattern 130. For example, a first light emitting element 11 may be disposed on the first bank pattern 130, a second light emitting element 12 may be disposed on the second bank pattern 130, and a third light emitting element 13 may be disposed on the third bank pattern 130.

[0073] The bank pattern 130 may be made of an organic insulating material (e.g., photosensitive acrylic or photosensitive polyimide), but is not limited thereto. As an example, the bank pattern 130 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin. Alternatively, the bank pattern 130 may include an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide or titanium oxide. The bank pattern 130 may guide the position to which the light-emitting element 10 is to be attached in the transfer process of the light-emitting element 10. The bank pattern 130 may be omitted.

[0074] The solder pattern 162 may be disposed on the first electrode 161. The solder pattern 162 may be made of indium (In), tin (Sn), or an alloy thereof, but is not limited thereto.

[0075] A plurality of light emitting elements 10 may be mounted on the solder pattern 162, respectively. One pixel may include three colors of light emitting elements 10. The first light emitting element 11 may be a red light emitting element, the second light emitting element 12 may be a green light emitting element, and the third light emitting element 13 may be a blue light emitting element. Two light emitting elements may be mounted in each sub-pixel.

[0076] The first optical layer 141 may cover the plurality of light emitting elements 10 and the bank pattern 130. Therefore, the first optical layer 141 may cover between the plurality of light emitting elements 10 and between the plurality of bank patterns 130. The first optical layer 141 may extend in the first direction (X) and be spaced apart in the second direction (Y) to separate between pixel rows.

[0077] The first optical layer 141 may include an organic insulating material in which fine metal particles such as titanium dioxide particles are dispersed. Light emitted from the plurality of light emitting elements 10 may be scattered by the fine metal particles dispersed in the first optical layer 141 to be emitted to the outside. In this case, the first optical layer 141 may be referred to as a light diffusion layer or a light scattering layer, and the present disclosure is not limited thereto.

[0078] The second electrode 170 may be disposed on a plurality of light emitting elements 10. The second electrode 170 may be connected in common to a plurality of pixels PXL. The second electrode 170 may be a thin electrode through which light is transmitted. The second electrode 170 may be a transparent electrode material (e.g., indium tin oxide (ITO)), but is not necessarily limited thereto. For example, the second electrode 170 may include a thin metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr and alloys thereof. Alternatively, the second electrode 170 may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0079] The second electrode 170 may extend in the first direction (X-axis direction) and be spaced apart in the second direction (Y-axis direction). The second electrode 170 may include a first region 171 disposed on the top surface of the light emitting element 10 and the top surface of the first optical layer 141, a second region 172 contacting the contact electrode 163 and electrically connected to the contact electrode 163, and a third region 173 disposed on the side of the first optical layer 141 and connecting the first region 171 and the second region 172.

[0080] On a plane, each of the plurality of second electrodes 170 may overlap the first optical layer 141 , and the second region 172 may cover a plane outside the first optical layer 141 .

[0081] The second optical layer 142 may be an organic insulating material surrounding the first optical layer 141. The second optical layer 142 may be disposed on the insulating layer 122 together with the first optical layer 141. The first optical layer 141 and the second optical layer 142 may include the same material (e.g., siloxane). For example, the first optical layer 141 may be siloxane containing titanium oxide (TiOx), and the second optical layer 142 may be siloxane not containing titanium oxide (TiOx). However, this is not necessarily limited thereto, and the first optical layer 141 and the second optical layer 142 may be formed of the same material, or may be formed of different materials.

[0082] According to an embodiment, since the second region 172 of the second electrode 170 is connected to the contact electrode 163 in an overall flat state, excessive stress does not concentrate at the connection point with the contact electrode 163. Therefore, cracks occurring in the second electrode 170 may be effectively prevented or reduced.

[0083] The second optical layer 142 may cover the second region 172 and the third region 173 of the second electrode 170. The top surface of the second optical layer 142 and the top surface of the first region 171 of the second electrode 170 may be coplanar. In other words, the first optical layer 141 and the second optical layer 142 may function as a planarization layer. As a result, since there is no step on the surface on which the black matrix 190 is formed, a pattern of the black matrix 190 may be easily formed on the first optical layer 141 and the second optical layer 142. However, this is not necessarily limited thereto, and the top surface of the second optical layer 142 and the top surface of the second electrode 170 may have different heights.

[0084] The black matrix 190 may be an organic insulating material to which a black pigment is added. Under the black matrix 190, the second electrode 170 may be in contact with the contact electrode 163. Transmission holes 191 may be formed between the patterns of the black matrix 190, and the light emitted from the light emitting element 10 is emitted to the outside through the transmission holes 191. Through the black matrix 190, the problem of light emitted from adjacent light emitting elements 10 mixing through the first optical layer 141 can be alleviated or eliminated.

[0085] The cover layer 180 may be an organic insulating material for covering the black matrix 190 and the second electrode 170. Figure 3 In the figure, the structures of the black matrix 190 and the cover layer 180 are omitted.

[0086] The contact electrode 163 is electrically connected to the first connection wiring RT1 provided on the lower portion thereof, and the first connection wiring RT1 may be connected to the pixel driving circuit 20. Therefore, the second electrode 170 may be applied with a cathode voltage through the contact electrode 163. The first electrode 161 may be electrically connected to the second connection wiring RT2. This will be described later.

[0087] Reference Figure 5 , the contact electrode 163 and the signal wirings TL1 to TL6 may be disposed on the same plane. The pixel driving circuit 20 may be disposed on the lower portion of the contact electrode 163 and the signal wirings TL1 to TL6. When the pixel driving circuit 20 is a driver, a plurality of drivers may be disposed in the display panel.

[0088] The passivation layer 133 may expose the contact electrode 163 so that the contact electrode 163 is electrically connected to the second electrode 170. In addition, the passivation layer 133 may insulate the signal wirings TL2 to TL5 from the second electrode 170. For example, the passivation layer 133, which is a dielectric (e.g., an inorganic dielectric), may be composed of a single layer or a multilayer thin film made of a silicon oxide (SiOx) film, a silicon nitride (SiNx) film, or a silicon oxynitride (SiOxNy) film.

[0089] Reference Figure 6 The connection portion 161 a of the first electrode 161 extends to one side surface 131 of the bank pattern 130 and is electrically connected to the connection wiring RT2 disposed on the buffer layer 121 .

[0090] The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wirings RT1 and RT2 may include a single layer or multiple layers of a metal layer selected from titanium (Ti), molybdenum (Mo) and aluminum (Al). The first electrode 161, the connection portion 161a, the signal wiring TL and / or the connection wirings RT1 and RT2 may be formed into a multilayer structure including a first layer ML1, a second layer ML2, a third layer ML3 and a fourth layer ML4.

[0091] The first layer ML1 and the third layer ML3 may include titanium (Ti) or molybdenum (Mo). The second layer ML2 may include aluminum (Al). The fourth layer ML4 may include a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO) having good adhesion to the solder pattern 162, corrosion resistance, and acid resistance.

[0092] The first layer ML1 , the second layer ML2 , the third layer ML3 , and the fourth layer ML4 may be sequentially deposited and then patterned by performing a photolithography process and an etching process.

[0093] The passivation layer 133 may be disposed on the first electrode 161 and the signal wiring TL, and may include an opening hole 133 a exposing the solder pattern 162 .

[0094] The light emitting element 10 may include a first conductive type semiconductor layer 10-1, an active layer 10-2 disposed on the first conductive type semiconductor layer 10-1, and a second conductive type semiconductor layer 10-3 disposed on the active layer 10-2. The first driving electrode 15 may be disposed on a lower portion of the first conductive type semiconductor layer 10-1, and the second driving electrode 14 may be disposed on an upper portion of the second conductive type semiconductor layer 10-3.

[0095] The light emitting element 10 can be formed on a silicon wafer using a method such as metal organic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), sputtering, etc.

[0096] The first conductive semiconductor layer 10-1 may be implemented as a compound semiconductor such as a III-V group, a II-VI group, etc., and may be doped with a first dopant. The first conductive semiconductor layer 10-1 may be formed of any one or more of semiconductor materials having a component formula of Alx1Iny1Ga(1-x1-y1)N(0≤x1≤1, 0≤y1≤1, 0≤x1+y1≤1), InAlGaN, AlGaAs, GaP, GaAs, and AlGaInP, but is not limited thereto. When the first dopant is an n-type dopant such as Si, Ge, Sn, Se, Te, etc., the first conductive semiconductor layer 10-1 may be an n-type nitride semiconductor layer. However, when the first dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc., the first conductive semiconductor layer 10-1 may be a p-type nitride semiconductor layer.

[0097] The active layer 10-2 is a layer where electrons (or holes) injected through the first conductive semiconductor layer 10-1 meet holes (or electrons) injected through the second conductive semiconductor layer 10-3. The active layer 10-2 can generate light that transitions to a lower energy level and has a corresponding wavelength as electrons and holes recombine.

[0098] The active layer 10-2 may have any one of a single well structure, a multi-well structure, a single quantum well structure, a multi-quantum well (MQW) structure, a quantum dot structure, or a quantum wire structure, and the structure of the active layer 10-2 is not limited thereto. The active layer 10-2 may generate light in a visible light wavelength band. Exemplarily, the active layer 10-2 may output light in any one of a blue wavelength band, a green wavelength band, and a red wavelength band.

[0099] The second conductive semiconductor layer 10-3 may be disposed on the active layer 10-2. The second conductive semiconductor layer 10-3 may be implemented as a compound semiconductor such as a III-V group, a II-VI group, etc., and the second conductive semiconductor layer 10-3 may be doped with a second dopant. The second conductive semiconductor layer 10-3 may be composed of a component having a molecular formula of In x2 Al y2 Ga 1-x-2+y2 The second conductive semiconductor layer 10-3 may be formed of a semiconductor material selected from the group consisting of AlInN, AlGaAs, GaP, GaAs, GaAsP, and AlGaInP. When the second dopant is a p-type dopant such as Mg, Zn, Ca, Sr, Ba, etc., the second conductive semiconductor layer 10-3 doped with the second dopant may be a p-type semiconductor layer. When the second dopant is an n-type dopant, the second conductive semiconductor layer 10-3 may be an n-type nitride semiconductor layer.

[0100] The reflective layer 16 may be disposed on the side surface and the lower portion of the light emitting element 10. The reflective layer 16 may have a structure in which a reflective material is dispersed in a resin layer, but is not necessarily limited thereto. Exemplarily, the reflective layer 16 may be manufactured as a reflector of various structures. The light emitted from the active layer 10-2 may be reflected upward by the reflective layer 16 to increase the light extraction efficiency.

[0101] Although the present embodiment is described as a vertical structure in which the driving electrodes 14 and 15 are provided on the upper and lower portions of the light emitting structure, the light emitting device may have a lateral structure or a flip chip structure in addition to the vertical structure.

[0102] Reference Figure 7, a main light emitting element 12a and a sub light emitting element 12b of a sub-pixel may be disposed on the bank pattern 130. The second light emitting element 12 will be exemplarily described, and the first light emitting element 11 and the third light emitting element 13 may be similarly configured. The 1-1st electrode 161-1 connected to the main light emitting element 12a may extend to one side surface of the bank pattern 130 to be electrically connected to the 2-1st connection wiring RT21 disposed on the lower portion thereof. The 1-2nd electrode 161-2 connected to the sub light emitting element 12b may extend to the other side surface of the bank pattern 130 to be electrically connected to the 2-2nd connection wiring RT22 disposed on the lower portion thereof.

[0103] The pixel driving circuit 20 can apply an anode voltage to the main light emitting element 12a through the 2-1st connection wiring RT21, and can apply an anode voltage to the sub light emitting element 12b through the 2-2nd connection wiring RT22. The pixel driving circuit 20 can apply a cathode voltage to the main light emitting element 12a and the sub light emitting element 12b through the first connection wiring RT1 and the second electrode 170.

[0104] The pixel driving circuit 20 can adjust the brightness by driving only the main light emitting element 12a, or can adjust the brightness by driving both the main light emitting element 12a and the sub-light emitting element 12b. If the main light emitting element 12a becomes dark, the brightness can be adjusted by driving only the sub-light emitting element 12b.

[0105] Figure 8 is a diagram illustrating a display device according to another embodiment of the present disclosure. Fig. 9 It is along Figure 8 A cross-sectional view taken along line IV-IV′ in FIG.

[0106] Reference Figure 8 and Fig. 9 , the second electrode 170 may be electrically connected to the contact electrode 163 through the contact hole TH1 formed in the second optical layer 142. The second optical layer 142 may include a contact hole TH1 exposing the contact electrode 163. The second electrode 170 may be inserted into the contact hole TH1 of the second optical layer 142 to contact the upper surface of the contact electrode 163. The contact hole TH1 may be formed in the outer region of the pixel. A portion 142a of the second optical layer 142 may be disposed between the contact hole TH1 and the first optical layer 141.

[0107] In the manufacturing process of the display panel, thin film layers of multiple display panels can be formed on a mother substrate at the same time, and then the display areas are separated in units of single display panels in a scribing process.

[0108] Fig.10 is a diagram illustrating two display panels provided on a mother substrate. Fig.11According to one embodiment of the present disclosure Fig.10 An enlarged view of portion B is shown in FIG.

[0109] Reference Fig.10 and Fig.11 The mother substrate 1100 includes a plurality of display panels. After the pixel driving circuit 20, the thin film layer and the light emitting element are disposed on the mother substrate and the inspection process is completed, each display panel is separated from the mother substrate along the scribing line SCL in the scribing process.

[0110] In the process of manufacturing the display panel, a large amount of charge may be generated in a thin film deposition process, for example, a process of depositing a metal layer to be patterned into the solder pattern 162. This amount of charge may generate ESD, thereby damaging the thin film of the display panel.

[0111] The conductive ring 300 is disposed in the non-display area of ​​the mother substrate 1100 so that the ESD generated in the process of manufacturing the display panel does not affect the display panel. The conductive ring 300 is electrically connected to the display panel to become equipotential with the display panel. The conductive ring 300 includes an electrostatic blocking area SBA. The conductive ring 300 includes a ring wiring pattern around the periphery of each display panel. Adjacent conductive rings 300 can be connected to each other by a connecting portion 320. The scribing line SCL can be disposed between the display area of ​​the display panel and the conductive ring 300.

[0112] The display panel includes a plurality of pads 200, which are arranged and exposed outside the display area AA in which the pixels are arranged. The pads 200 are electrically connected to the wiring pattern of the display area AA. The external host system can send signals, driving voltages, etc. required for driving the pixels to the pixel driving circuit through the pads 200. A flexible printed circuit film (e.g., a flexible printed circuit (FPC)) can be bonded to the pads 200 through an anisotropic conductive film (ACF). The mainboard of the host system can be connected to one end of the flexible circuit film, and the pads 200 of the display panel can be connected to the other end of the flexible circuit film.

[0113] The mother substrate 1100 includes a non-display area to be disposed outside the scribe line SCL to be removed. The pad 200 may be connected to a shorting bar 210 disposed in the non-display area of ​​the mother substrate 1100. The shorting bar 210 is connected to the conductive ring 300 through a connecting portion 220. The conductive ring 300, the connecting portion 220, the shorting bar 210, and the pad 200 may be formed as a metal pattern. In addition, as a metal wiring in which a wiring pattern disposed on different layers and an insulating layer interposed therebetween is connected through a contact hole, the conductive ring 300, the connecting portion 220, the shorting bar 210, and the pad 200 may be formed on the mother substrate 1100.

[0114] Through the connection structure of the conductive ring 300, the connection portions 220 and 320, the shorting bar 210, and the pad 200, the conductive ring 300 and the signal wiring of the display area AA may be at the same potential.

[0115] One or more electrostatic blocking areas SBA may be provided in the conductive ring 300. For example, Fig.10 As shown, the electrostatic blocking area SBA may be disposed at three portions of the conductive ring 300 including the left and right sides and the lower end except the portion where the pad 200 is disposed, but is not limited thereto. The electrostatic blocking area SBA may also be disposed at the corner of the conductive ring 300.

[0116] The electrostatic blocking area SBA may include a capacitor that bursts when ESD occurs. Since a large amount of charge is dissipated when the capacitor of the electrostatic blocking area SBA bursts, the amount of charge flowing to the display area AA when ESD occurs may be minimized or reduced.

[0117] A plurality of wiring patterns may be provided in the static electricity blocking area SBA, and at least two wiring patterns may overlap each other, but the present disclosure is not limited thereto. The static electricity blocking area SBA may include a plurality of openings 312, such as Fig.11 and Fig.12 As shown. The second metal layer 316 is exposed in each opening 312 of the electrostatic blocking area SBA. In the opening 312, the first metal layer 314 and the second metal layer 316 may be separated to have a step difference with each other by a photoresist pattern (PR) interposed therebetween. Fig.12 and Fig.17 As shown, the first metal layer 314 and the second metal layer 316 stepped in the opening 312 may be separated from each other or connected to each other according to the side shape of the photoresist pattern. In each opening 312, a capacitor may be formed by separating the first metal layer 314 and the second metal layer 316 from each other with an insulating layer (e.g., photoresist) interposed therebetween. Fig.11 312 is shown as a circular shape, but the present disclosure is not limited thereto. For example, the opening 312 may have a rectangular shape, an elliptical shape, an oval shape, or a quadrilateral shape, etc. In addition, although the opening 312 is Fig.11 The openings 312 are shown as being separated from each other, but the present disclosure is not limited thereto, and the openings 312 may be connected to each other to form one or more slits extending along the static electricity blocking area SBA.

[0118] A lift-off process may be used as a method of patterning the metal layers 314 and 316 on the mother substrate 1100. A photoresist is coated on the mother substrate 1100, and the photoresist pattern is retained on the mother substrate through an exposure process and a development process. When the metal layers 314 and 316 are deposited on the mother substrate on which the photoresist pattern is provided, the metal layers are separated by the photoresist pattern, and there is a step difference between the metal layers 314 and 316 by the height of the photoresist pattern. Subsequently, when the photoresist pattern is completely removed, the metal layer provided thereon is removed together with the photoresist pattern, and a metal pattern having a desired shape remains on the mother substrate 1100.

[0119] Fig.12 It is shown that by following Fig.11 A cross-sectional view of the cross-sectional structure of the electrostatic blocking region cut along line VV′ in FIG. Fig.13 is a cross-sectional view showing a cross-sectional structure of a display area of ​​a display panel covered with a photoresist and a metal layer.

[0120] Reference Fig.12 and Fig.13 , a photoresist is applied to the entire surface of the mother substrate 1100 to form a solder pattern 162 in the light emitting area EMA of the sub-pixel on the mother substrate 1100. The photoresist covers the display area AA on the mother substrate 1100 and the non-display area outside the display area AA. The photoresist is patterned by an exposure and development process. The photoresist pattern PR includes an opening 178 on the mother substrate 1100, and the solder pattern 162 of the display area AA is located in the opening 178; and a plurality of openings 312 located in the electrostatic blocking area SBA. The solder pattern 162 can be interpreted as a third metal layer.

[0121] In the display area AA and the non-display area outside the display area AA, the photoresist pattern PR may have an inverted tapered shape, for example, may become thicker toward the top. In this case, the opening 178 of the display area AA and the opening 312 of the non-display area on the mother substrate 1100 become narrower toward the top.

[0122] A metal layer is deposited on the entire surface of the mother substrate 1100 on which the photoresist pattern PR is formed. The metal layer includes a first metal layer 314 covering the photoresist pattern PR, a second metal layer 316 disposed inside the opening 312 of the static blocking area SBA, and a solder pattern 162 disposed inside the opening 178 of the display area AA. Therefore, in the process of manufacturing the display panel, the first metal layer 314, the second metal layer 316, and the solder pattern 162 can be formed simultaneously with the same material. For example, the first metal layer 314, the second metal layer 316, and the solder pattern 162 can be formed of the same material in the same process, but the present disclosure is not limited thereto.

[0123] When the photoresist pattern PR is removed in the strip process, the first metal layer 314 covering the photoresist pattern PR may also be removed.

[0124] On the mother substrate 1100, the first metal layer 314 and the second metal layer 316 disposed in the static blocking area SBA are spaced apart from each other, and air is interposed therebetween, and there is an air gap A. As a result, a capacitor C is formed in each opening 312 of the static blocking area SBA. Fig.13 As shown, the gap A between the first metal layer 314 and the second metal layer 316 is smaller than the gap B between the first metal layer 314 of the photoresist pattern PR covering the display area AA and the solder pattern 162 in the opening 178. Therefore, since the gap between the capacitor electrodes of the electrostatic blocking area SBA is smaller than the gap between the metal layers 314 and 162 of the display area AA, when ESD is generated in the deposition process of the first metal layer 314 and the second metal layer 316 and the charge moves along the conductive ring 300, the capacitor C of the electrostatic blocking area SBA can burst before the charge moves to the display area AA. In this case, most of the charge amount generated due to ESD disappears, and some of the remaining charge can be discharged through the wiring patterns M4 and M5. The wiring patterns M4 and M5 can be electrically connected to the base voltage source GND or the power wiring.

[0125] There is also a capacitor between the first metal layer 314 and the solder pattern 162 in the light emitting area EMA of the mother substrate, but the gap B between the metal layers 314 and 162 of the capacitor is larger than the gap A between the metal layers 314 and 316 of the capacitor C formed in the electrostatic blocking area SBA, so that when ESD occurs, the capacitor C of the electrostatic blocking area SBA bursts first. As a result, when ESD occurs, the charges flowing along the conductive ring 300 do not flow into the display area AA, and thus do not affect the pixels in the display area.

[0126] In order to reduce the distance A between the first metal layer 314 and the second metal layer 316 in the electrostatic blocking area SBA to be less than the distance B between the metal layers 162 and 314 disposed in the light emitting area EMA, the thickness tp2 of the photoresist pattern PR in the electrostatic blocking area SBA may be set to be less than the thickness tp1 in the display area. In another embodiment for achieving this, the thickness tb2 of the insulating layer used as the bank pattern BNK in the electrostatic blocking area SBA may be greater than the thickness tb1 in the display area.

[0127] By changing the density of the metal layer under the photoresist pattern PR, for example, the density of the stacked wiring patterns M1 to M5 between regions, the thicknesses tp1 and tp2 of the photoresist pattern PR can be different when the photoresist is coated. In the photoresist exposure process, by using a photomask as a halftone mask, the exposure amount of the photoresist can be different between the display area and the electrostatic blocking area of ​​the display panel, so that the thicknesses tp1 and tp2 of the photoresist pattern PR can be different. The density of the metal layer under the photoresist pattern PR may refer to the number of metal layers disposed under the photoresist pattern PR or be related to the number of metal layers disposed under the photoresist pattern PR, and the present disclosure is not limited thereto.

[0128] Fig.14 is a cross-sectional view illustrating an example in which a metal layer has different densities between an electrostatic blocking region and a light emitting region on a mother substrate.

[0129] Reference Fig.14 , a plurality of insulating layers INS1 to INS5 and a plurality of wiring patterns M1 to M5 separated from each other with the insulating layers INS1 to INS5 interposed therebetween may be included on the mother substrate 1100 .

[0130] N wiring patterns M1 to M5 (where N is a natural number equal to or greater than 2) may be disposed under the opening 312 of the electrostatic blocking area SBA. When viewed from a longitudinal cross section of the mother substrate 1100, the plurality of wiring patterns M1 to M5 overlap each other in the electrostatic blocking area 31, with an insulating layer interposed therebetween. In contrast, M wiring patterns M1, M4, and M5 (where M is a natural number less than N) are disposed under the opening 178 of the light emitting area EMA.

[0131] When the photoresist is coated on the mother substrate 1100, the photoresist flows downward from the electrostatic blocking area SBA having a high-density metal layer, so the thickness of the photoresist becomes thinner. In this case, in the light emitting area EMA having a low-density metal layer, the surface on which the photoresist is coated is relatively low, so the photoresist becomes thicker on the light emitting area EMA. As a result, since the thickness tp2 of the photoresist of the electrostatic blocking area SBA becomes smaller than the thickness tp1 of the photoresist formed in the light emitting area EMA, the distance A between the metal layers 314 and 316 forming the capacitor C in the electrostatic blocking area SBA becomes smaller than the distance B between the metal layers 162 and 314 in the light emitting area EMA.

[0132] Fig.15 is a cross-sectional view illustrating an example in which the thickness of the insulating layer is different between the electrostatic blocking region and the light emitting region on the mother substrate.

[0133] Reference Fig.15 , the bank pattern BNK disposed under the opening 312 of the electrostatic blocking area SBA may be formed to be thicker than the bank pattern BNK disposed under the opening 178 of the light emitting area EMA. In other words, the bank pattern thickness tb2 of the electrostatic blocking area SBA may be greater than the thickness tb1 of the bank pattern BNK of the light emitting area EMA. As a result, due to the difference in thickness of the bank pattern BNK, the gap A between the metal layers 314 and 316 forming the capacitor C in the electrostatic blocking area SBA may be smaller than the gap B between the metal layers 162 and 314 of the light emitting area EMA.

[0134] The bank pattern BNK may be formed of a photosensitive resin (e.g., photosensitive photoacrylic or photosensitive polyimide). In an exposure process for the photosensitive resin of the bank pattern, by using a photomask as a halftone mask, the exposure amount of the photosensitive resin is different between the static electricity blocking area SBA and the display area AA, and then, as shown in FIG. Fig.15 As shown, the thicknesses tp1 and tp2 of the bank pattern BNK may be different for each region.

[0135] Fig.16 In another embodiment of the present disclosure Fig.10 An enlarged view of portion B is shown. Fig.17 It is shown that by following Fig.16 A cross-sectional view of the cross-sectional structure of the electrostatic blocking area cut along line VI-VI′ in FIG.

[0136] Reference Fig.16 and Fig.17In the static electricity blocking area SBA, a metal layer (eg, a wiring pattern M5) is disposed on the bank pattern BNK. The photoresist pattern PR covers the insulating layer INS5 on which the wiring pattern M5 is disposed and the bank pattern BNK.

[0137] In the static electricity blocking area SBA, the photoresist pattern PR includes a plurality of grooves 318. The bank pattern BNK is disposed between adjacent grooves 318. Therefore, the metal layer (eg, the wiring pattern M5) is not exposed in the grooves 318 of the photoresist pattern PR.

[0138] In each groove 318 of the electrostatic blocking area SBA, the metal layer 314 and the wiring pattern M5 are separated and the photoresist pattern PR is interposed therebetween, and a capacitor is formed. The minimum distance D between the metal layer 314 and the wiring pattern M5 in the groove 318 is smaller than the distance C between the metal layer 314 and the wiring pattern M5 which are spaced apart from each other and between which the thick photoresist pattern PR is interposed in the portion without the groove 318. The distance C between the metal layer 314 and the wiring pattern M5 in the portion without the groove 318 is smaller than Fig.13 The minimum distance B between the metal layer 314 and the metal layer 162 in the light emitting area EMA is shown.

[0139] When ESD is generated in the deposition process of the metal layer 314 and the charge moves along the conductive ring 300, the capacitor connected to the groove 318 in the electrostatic blocking area SBA is first burst due to a large amount of charge. In this case, most of the charge generated due to ESD can be dissipated, and some remaining charges can be discharged through the wiring patterns M4 and M5. As a result, when ESD is generated, the charge flowing along the conductive ring 300 does not flow into the display panel, and thus does not affect the display area AA.

[0140] In addition, in the photoresist developing process, the metal layer is hardly etched by the developer. For this reason, when the metal layer exists below the opening 312 of the photoresist pattern PR, as shown in FIG. Fig.12 and Fig.13 As shown in FIG. 1 , more photoresist is removed from the lower end close to the metal layer, so that the side surface of the photoresist pattern PR has an inverted tapered shape, and thus the widths of the openings 178 and 312 become narrower as the widths of the openings 178 and 312 approach the first metal layer 314. In contrast, when there is no metal layer below the groove 318 of the photoresist pattern PR, as shown in FIG. Fig.17 As shown, since the photoresist is isotropically removed from the groove 318 by the developer, the photoresist pattern PR becomes tapered, for example, thicker toward the bottom. Fig.17The width of the groove 318 of the electrostatic blocking area SBA is shown to increase as it goes upward (eg, as it approaches the first metal layer 314 ).

[0141] exist Fig.17 In Fig.14 and Fig.15 As shown, the thicknesses of the photoresist pattern PR and the insulating layer of the bank pattern may vary for each region on the mother substrate 1100 .

[0142] According to one or more embodiments of the present disclosure, a mother substrate and a display panel using the mother substrate may be described as follows.

[0143] According to one or more embodiments of the present disclosure, a mother substrate for a display panel may include: a plurality of display areas, including a plurality of light-emitting areas in which light-emitting elements are to be placed, a plurality of wirings, and a plurality of pads connected to the wirings; a conductive ring disposed in a non-display area outside the display area to surround each display area and electrically connected to the pad; a photoresist pattern covering the display area and the non-display area; and a first metal layer covering the photoresist pattern. The conductive ring includes an electrostatic blocking area. The electrostatic blocking area includes a second metal layer spaced apart from the first metal layer, and the photoresist pattern is interposed therebetween. The light-emitting area includes a third metal layer spaced apart from the first metal layer, and the photoresist pattern is interposed therebetween. The first distance between the first metal layer and the second metal layer disposed in the electrostatic blocking area is less than the second distance between the first metal and the third metal layer disposed in the light-emitting area.

[0144] The mother substrate may further include a shorting bar disposed in the non-display area and connected to the pad. The conductive ring may be connected to the shorting bar.

[0145] Conductive rings adjacent to each other may be connected to each other.

[0146] The electrostatic blocking region may include a plurality of openings through which the second metal layer is exposed. The light emitting region may include an opening through which the third metal layer is exposed. In each opening of the electrostatic blocking region, the first metal layer and the second metal layer may be spaced apart from each other by a first distance and air is interposed therebetween. In the opening of the light emitting region, the first metal layer and the third metal layer may be spaced apart by a second distance and air is interposed therebetween.

[0147] The thickness of the photoresist pattern disposed in the static electricity blocking region may be smaller than the thickness of the photoresist pattern disposed in the light emitting region.

[0148] The electrostatic blocking region may include a plurality of metal layers disposed below the opening of the electrostatic blocking region. The light emitting region may include one or more metal layers disposed below the opening of the light emitting region. The density of the metal layer disposed below the opening of the electrostatic blocking region may be greater than the density of the metal layer disposed below the opening of the light emitting region.

[0149] When viewed from a longitudinal cross-section of the mother substrate, the metal layers placed under the opening of the static electricity blocking area may overlap each other.

[0150] The electrostatic blocking region may further include an insulating layer disposed under the second metal layer in each opening of the electrostatic blocking region. The light emitting region may further include an insulating layer disposed under the third metal layer in the opening of the light emitting region. The insulating layer in the electrostatic blocking region may be thicker than the insulating layer in the light emitting region.

[0151] The width of each of the opening of the electrostatic blocking region and the opening of the light emitting region may decrease as they approach the first metal layer.

[0152] The electrostatic blocking region may include a plurality of concave grooves. The second metal layer may be placed between adjacent grooves. The light emitting region may include an opening through which the third metal layer is exposed. The minimum distance between the first metal layer and the second metal layer in the electrostatic blocking region may be less than the minimum distance between the first metal layer and the third metal layer in the light emitting region.

[0153] The width of the groove of the electrostatic blocking region may increase as it approaches the first metal layer. The width of the opening of the light emitting region may decrease as it approaches the first metal layer.

[0154] According to one or more embodiments of the present disclosure, the display panel may be separated from the mother substrate. The display panel may include a display area without the photoresist pattern and the first metal layer.

[0155] According to one or more embodiments of the present disclosure, the display device may be applied to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a curved device, a sliding device, a variable device, an electronic notepad, an electronic book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation, a navigator, a vehicle navigation, a vehicle display device, a vehicle device, a theater device, a theater display device, a television, a wallpaper device, a sign device, a game device, a laptop computer, a display, a camera, a video camera, and a home appliance, etc. Additionally, the display device according to one or more embodiments of the present disclosure may be applied to an organic light emitting lighting device or an inorganic light emitting lighting device.

[0156] The above-mentioned objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure are not essential features of the specified claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure.

[0157] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are exemplary in all aspects and are not intended to limit the present disclosure.

[0158] CROSS-REFERENCE TO RELATED APPLICATIONS

[0159] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0090201 filed in Korea on July 12, 2023, the disclosure of which is incorporated herein by reference in its entirety for all purposes.

Claims

1. A mother substrate, comprising: a plurality of display areas, the plurality of display areas including a plurality of light emitting areas where light emitting elements are to be placed, a plurality of wirings, and a plurality of pads connected to the wirings; a conductive ring disposed in a non-display area outside the display area to surround each of the display areas and electrically connected to the pad; a photoresist pattern, wherein the photoresist pattern covers the display area and the non-display area; as well as a first metal layer, the first metal layer covering the photoresist pattern, Wherein, the conductive ring includes an electrostatic blocking area, The electrostatic blocking region includes a second metal layer spaced apart from the first metal layer and the photoresist pattern is interposed between the first metal layer and the second metal layer, The light emitting region includes a third metal layer spaced apart from the first metal layer and the photoresist pattern is interposed between the first metal layer and the third metal layer, and A first distance between the second metal layer disposed in the electrostatic blocking region and the first metal layer is smaller than a second distance between the third metal layer disposed in the light emitting region and the first metal layer.

2. The mother substrate according to claim 1, further comprising: a shorting bar disposed in the non-display area and connected to the pad, Wherein, the conductive ring is connected to the short-circuit bar.

3. The mother substrate according to claim 2, wherein: The conductive rings adjacent to each other are connected to each other.

4. The mother substrate according to claim 1, wherein: The electrostatic blocking region includes a plurality of openings, and the second metal layer is exposed through the plurality of openings. The light emitting region includes an opening, and the third metal layer is exposed through the opening, In each of the openings of the electrostatic blocking area, the first metal layer and the second metal layer are spaced apart from each other by the first distance and air is interposed between the first metal layer and the second metal layer, and In the opening of the light emitting area, the first metal layer and the third metal layer are spaced apart by the second distance and air is interposed between the first metal layer and the third metal layer.

5. The mother substrate according to claim 1, wherein: The thickness of the photoresist pattern disposed in the static electricity blocking region is smaller than the thickness of the photoresist pattern disposed in the light emitting region.

6. The mother substrate according to claim 4, wherein: The electrostatic blocking region includes a plurality of metal layers disposed below the opening of the electrostatic blocking region, The light emitting region includes one or more metal layers disposed below the opening of the light emitting region, and The density of the metal layer disposed under the opening of the electrostatic blocking area is greater than the density of the metal layer disposed under the opening of the light emitting area.

7. The mother substrate according to claim 6, wherein: The metal layers placed under the opening of the static electricity blocking area overlap each other when viewed from a longitudinal cross section of the mother substrate.

8. The mother substrate according to claim 4, wherein: The electrostatic blocking region further includes an insulating layer disposed below the second metal layer in each of the openings of the electrostatic blocking region, The light emitting region further includes an insulating layer disposed below the third metal layer in the opening of the light emitting region, and The insulating layer in the electrostatic blocking region is thicker than the insulating layer in the light emitting region.

9. The mother substrate according to any one of claims 4 to 8, wherein: A width of each of the opening of the electrostatic blocking area and the opening of the light emitting area decreases as they approach the first metal layer.

10. The mother substrate according to claim 1, wherein: The electrostatic blocking area includes a plurality of concave grooves, The second metal layer is placed between the grooves adjacent to each other, The light emitting region includes an opening through which the third metal layer is exposed, and A minimum distance between the second metal layer and the first metal layer in the electrostatic blocking area is smaller than a minimum distance between the third metal layer and the first metal layer in the light emitting area.

11. The mother substrate according to claim 10, wherein: The thickness of the photoresist pattern disposed in the static electricity blocking region is smaller than the thickness of the photoresist pattern disposed in the light emitting region.

12. The mother substrate according to claim 10, wherein: The electrostatic blocking region further includes an insulating layer disposed below the second metal layer in each of the openings of the electrostatic blocking region, The light emitting region further includes an insulating layer disposed below the third metal layer in the opening of the light emitting region, and The insulating layer in the electrostatic blocking region is thicker than the insulating layer in the light emitting region.

13. The mother substrate according to any one of claims 10 to 12, wherein: The width of the groove of the electrostatic blocking region increases as the groove approaches the first metal layer, and A width of the opening of the light emitting region decreases as the opening approaches the first metal layer.

14. The mother substrate according to claim 1, wherein: The first metal layer and the third metal layer are formed of the same material.

15. The mother substrate according to claim 1, wherein: The second metal layer is electrically connected to a base voltage source or power wiring.

16. A display panel separated from the mother substrate for a display panel according to any one of claims 1 to 15, the display panel comprising: The display area is free of the photoresist pattern and the first metal layer.

17. A mother substrate, comprising: a plurality of display areas, the plurality of display areas including a plurality of light emitting areas where light emitting elements are to be placed, a plurality of wirings, and a plurality of pads connected to the wirings; as well as a conductive ring disposed in a non-display area outside the display area to surround each of the display areas and electrically connected to the pad, Wherein, the conductive ring includes an electrostatic blocking area, The electrostatic blocking region includes a first metal layer electrically connected to a base voltage source or power wiring, The light emitting region includes a second metal layer disposed on the same layer as the first metal layer, and A height of a lower surface of the first metal layer is higher than a height of a lower surface of the second metal layer.

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