Memory error address detection method and device, electronic equipment and storage medium

Abstract

The invention provides a memory error address detection method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the primary access of at least one memory subspace of a memory, and obtaining the primary state information of the at least one memory subspace; wherein the primary state information is used for representing whether an access error occurs in the primary access; according to the primary state information, repeatedly performing at least one secondary access on the memory subspace with the access error to obtain secondary state information corresponding to the memory subspace with the access error; and determining a memory error address according to the secondary state information corresponding to the memory subspace with the access error. The memory address with the access error is determined by reducing the to-be-determined memory space range step by step, so that the memory address with the access error can be quickly determined from the memory. And therefore, the memory address with the error can be quickly processed, and the error data is prevented from being diffused.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a memory error address detection method, device, electronic device and storage medium. Background Art

[0002] In a computer system, the internal hardware must run at ultra-high speed to maintain smooth and stable operation of the computer system. Memory is a high-speed transfer station for data communication between the hard disk and the central processing unit in the computer. When the program is running, the hard disk will write the data to the memory, and then the central processing unit and the memory will communicate at high speed to achieve higher operating efficiency.

[0003] Memory is a volatile memory. Due to external electrical interference, such as infrared rays, WiFi signals, abnormal magnetic fields, etc., the data in the memory may be changed; or problems with the memory hardware itself may cause the data in the memory to be inaccurate, resulting in unstable computer operation, errors, etc. For servers or data centers with high precision requirements, a data error may cause the entire system to crash.

[0004] However, in some application scenarios, the system cannot accurately and promptly process erroneous memory addresses, which will cause the spread of erroneous data in the memory and cause adverse consequences. Summary of the invention

[0005] The present disclosure provides a memory error address detection method, device, electronic device and storage medium.

[0006] According to a first aspect of the present disclosure, a memory error address detection method is provided, wherein the memory includes multiple memory subspaces, and the method includes: performing primary access to at least one memory subspace of the memory to obtain primary status information of the at least one memory subspace; wherein the primary status information is used to indicate whether an access error occurs in the primary access; based on the primary status information, repeatedly performing at least one secondary access to the memory subspace where the access error occurs to obtain secondary status information corresponding to the memory subspace where the access error occurs; and determining the memory error address based on the secondary status information corresponding to the memory subspace where the access error occurs.

[0007] According to a second aspect of the present disclosure, a memory error address detection device is provided, wherein the memory includes multiple memory subspaces, and the device includes: a primary access unit, used to perform primary access to at least one memory subspace of the memory, and obtain primary status information of the at least one memory subspace; wherein the primary status information is used to indicate whether an access error occurs in the primary access; a secondary access unit, used to repeat at least one secondary access to the memory subspace where the access error occurs according to the primary status information, and obtain secondary status information corresponding to the memory subspace where the access error occurs; and a determination unit, used to determine the memory error address according to the secondary status information corresponding to the memory subspace where the access error occurs.

[0008] According to a third aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided in the first aspect.

[0009] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method provided in the first aspect.

[0010] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising: a computer program, wherein the computer program is stored in a readable storage medium, at least one processor of an electronic device can read the computer program from the readable storage medium, and the at least one processor executes the computer program so that the electronic device executes the method provided in the first aspect.

[0011] According to the memory error address detection method, device, electronic device and storage medium provided by the present disclosure, primary access is performed on at least one memory subspace of the memory to obtain primary state information of the at least one memory subspace; wherein the primary state information is used to indicate whether an access error occurs in the primary access; according to the primary state information, at least one secondary access is repeated on the memory subspace where the access error occurs to obtain the secondary state information corresponding to the memory subspace where the access error occurs; according to the secondary state information corresponding to the memory subspace where the access error occurs, the memory error address is determined, so that the primary access is first performed, and then at least one secondary access is repeated on the memory subspace where the access error occurs obtained by the primary access until the memory address where the error occurs is determined. Thus, the memory address where the access error occurs is determined by gradually narrowing the range of the memory space to be determined, which is conducive to quickly determining the memory address where the error occurs from the memory. This is further conducive to quickly processing the memory address where the error occurs to avoid the spread of erroneous data.

[0012] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0014] Figure 1 It is a schematic diagram of an application scenario of the memory error address detection disclosed in the present invention;

[0015] Figure 2 is a schematic diagram of an embodiment of a memory error address detection method provided by the present disclosure;

[0016] Figure 3 is a schematic diagram of another embodiment of a memory error address detection method provided by the present disclosure;

[0017] Figure 4 is a schematic diagram of a bitmap provided by the present disclosure;

[0018] Figure 5 is a principle flow chart of a memory error address detection method provided by the present disclosure;

[0019] Figure 6 is a schematic structural diagram of a memory error address detection device provided by the present disclosure;

[0020] Figure 7 is a schematic block diagram of an example electronic device that can be used to implement embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0022] ECC memory is a memory that uses error checking and correction technology (Error Checking and Correcting, ECC). In order to ensure the accuracy of memory data, error correction codes can be added to the data transmitted to the memory according to preset rules. When accessing data in the ECC memory, the ECC memory can recalculate the error correction code for the accessed data according to the above preset rules. If the error correction codes obtained by the two are the same, the data is error-free. If the error correction codes obtained by the two are different, the data stored in the ECC memory is erroneous. For single-point errors, the ECC memory can find the location of the single-point error and correct the single-point error. However, for multi-point errors, the current ECC memory does not have the ability to correct the errors. In other words, multi-point errors are uncorrectable errors in ECC memory.

[0023] When an uncorrectable error occurs, the ECC memory will notify the upper-layer operating system or driver by reporting an interrupt. In some application scenarios, the interrupt reported by the memory will include the physical address of the memory where the uncorrectable error occurred and the error type.

[0024] In order to prevent the memory with uncorrectable errors from being requested and accessed by different processes without the intervention of the operating system, the spread of uncorrectable errors will cause more computing services to be affected by the uncorrectable errors. After receiving the uncorrectable error interrupt, the operating system can obtain the physical address where the uncorrectable error occurred from the interrupt, mark the corresponding node on the operating system's physical memory allocator as a bad node (Posioned), and then mask the physical address where the uncorrectable error occurred, ensuring that the data in the physical address will no longer be allocated to any computing service in the future.

[0025] The shielding methods of the above operating systems are all based on the fact that when an uncorrectable error occurs, the reported error interrupt contains the physical address where the uncorrectable error occurs. In some application scenarios, if there is no address information in the interrupt reported by the memory, it is impossible to shield the corresponding node on the distributor. The operating system cannot mark the bad nodes of the nodes with errors in time, which will cause the spread of uncorrectable errors, resulting in more computing services being affected by uncorrectable errors.

[0026] In order to solve the above problems, after receiving an error interrupt, the embodiment of the present disclosure can parse the error type reported by the interrupt. If the error type is an uncorrectable error, the error address detection can be performed through the memory error address detection method provided by the present disclosure, so as to locate the error position in time and process the error position. The memory error address detection method provided by the present disclosure first performs a primary access, and then repeats at least one secondary access to the memory subspace where the access error occurs obtained by the primary access until the memory address where the error occurs is determined, thereby determining the memory address where the access error occurs in a step-by-step manner, which is conducive to quickly determining the memory address where the error occurs from the memory. In addition, the memory address where the error occurs can be quickly processed to avoid the spread of erroneous data, thereby ensuring the controllability of the impact of uncorrectable errors.

[0027] The execution subject of the memory error address detection method disclosed in the present invention can be a driver or an operating system. The above-mentioned driver can be a driver of the memory. The above-mentioned driver or operating system can run on a terminal device, such as a general-purpose central processing unit (CPU).

[0028] Please refer to Figure 1 , Figure 1 FIG. 1 shows an application scenario diagram of the memory error address detection method disclosed in the present invention. Figure 1 As shown, a memory can be installed on the electronic device 100 (such as a terminal device, a server, etc.). When the electronic device 100 runs a program or performs data calculations, the hard disk can write data into the memory. The above memory can be an ECC memory. When the ECC memory 101 in the electronic device 100 detects an error in the memory data, it sends an error message (such as an interrupt message) to the operating system 102 or a driver (the present disclosure uses the operating system as an example below for explanation), and the operating system 102 can determine the memory address where the error data appears in the memory based on the interrupt message, and then perform corresponding isolation and other processing operations on the memory address.

[0029] In one embodiment, the electronic device 100 may be formed by heterogeneous processors, for example, the electronic device 100 includes a general-purpose processor CPU and an artificial intelligence processor. The ECC memory 101 may refer to a memory with an ECC detection function on the artificial intelligence processor, and the operating system 102 or driver may run on the general-purpose processor CPU, and the operating system 102 or driver is used to drive and control the operation of the artificial intelligence processor.

[0030] Among them, the ECC memory 101 is a memory with error checking and correction functions. Specifically, the ECC memory 101 may include an ECC detection module, which is used for error detection and correction to detect whether the written data is correct. For single-point errors, the ECC memory can correct the single-point errors. When the ECC memory detects that the written data has multiple-point errors (the multi-point errors here can be errors in multiple bits of data in the data in the memory), the ECC memory cannot correct them. When the ECC memory detects that the error cannot be corrected, an interrupt message can be sent to the operating system. The interrupt message carries an indication that there is an error in the memory data. The ECC memory and the error correction function of the ECC memory in the present disclosure can refer to relevant materials and will not be repeated here.

[0031] Please refer to Figure 2 , Figure 2 FIG. 1 is a schematic diagram of an embodiment of a memory error address detection method provided by the present disclosure. Figure 2 As shown, the memory error address detection method provided by this embodiment includes:

[0032] S201. Perform primary access to at least one memory subspace of a memory to obtain primary state information of the at least one memory subspace.

[0033] The memory can be Figure 1 The ECC memory shown in the figure may include a plurality of memory subspaces, wherein the plurality of memory subspaces may be obtained by pre-dividing the memory.

[0034] The primary status information of the memory subspace is used to indicate whether an access error occurs in the primary access.

[0035] After receiving the interrupt information, if the execution subject determines that the interrupt information does not include the memory address where the erroneous data occurs, the execution subject may use the memory error address detection method provided in the present disclosure to determine the memory error address where the erroneous data occurs.

[0036] For each memory subspace in at least one memory subspace, the execution subject may perform primary access to the memory subspace, and during the primary access, the ECC detection module provided by the ECC memory may be called, and the ECC detection module verifies the data obtained by the primary access to obtain a verification result. The ECC detection module may store the verification result in a preset storage method.

[0037] The verification result indicates whether the error correction code originally stored in the memory subspace is consistent with the error correction code obtained in the primary access. In addition, if the error correction code originally stored in the memory subspace is inconsistent with the error correction code obtained in the primary access, the number of inconsistent bits can also be determined based on the verification result.

[0038] In one example, the preset storage method is to store the verification result in an error status register. In one example, the preset storage method is to store the verification result in a designated bit in the memory subspace. In an exemplary manner, 3 bytes with a total of 24 bits can be used to record the verification result.

[0039] After the execution subject calls the ECC detection module to verify the data in the memory subspace, the execution subject can read the verification result in the storage space indicated by the preset storage method.

[0040] For example, the execution subject can read the verification result of the data in the memory subspace from the error status register. As an implementation method, in the error status register, if the value of each bit recording the verification result is "0", it means that the data originally stored in the memory subspace is consistent with the data obtained by accessing the memory subspace this time. If the value of each bit recording the verification result is "1", it means that one bit of the data originally stored in the memory subspace is inconsistent with the data obtained by this access. If the value of each bit recording the verification result is data other than all "0" or all "1", it means that there are multiple bits of inconsistency between the data obtained by the primary access to the memory subspace this time and the data originally stored in the memory subspace.

[0041] For each memory subspace, when initially accessing the memory subspace, the execution subject may use the ECC detection module to determine the verification result of the memory subspace.

[0042] The execution subject may also generate primary status information according to the verification result. If the verification result indicates that the data obtained in the primary access is consistent with the data originally stored in the memory subspace, status information indicating that no access error occurred in the primary access may be generated. If the verification result indicates that the data obtained in the primary access is inconsistent with the data originally stored in the memory subspace, primary status information indicating that an access error occurred in the primary access may be generated. The primary status information may include any number, letter or symbol indicating that an access error occurred or did not occur.

[0043] Similarly, the primary state information corresponding to each memory subspace can be obtained. The above execution subject can also record the primary state information of each memory subspace.

[0044] S202: Repeat at least one secondary access to the memory subspace where the access error occurs according to the primary state information to obtain secondary state information corresponding to the memory subspace where the access error occurs.

[0045] After obtaining the primary state information of at least one memory subspace, the execution subject can determine the memory subspace where the primary access has an access error according to the primary state information. However, the memory subspace is usually relatively large, and in order to avoid wasting space caused by directly isolating the memory subspace, for each memory subspace where the primary access has an access error, at least one secondary access can be repeated to determine the memory error address in a more fine-grained manner.

[0046] Similarly, for each secondary access, the execution subject may call the ECC detection module of the memory, and the ECC detection module may verify the data of the secondary access. The execution subject may read the verification result corresponding to the secondary access, and generate the secondary state information of the memory subspace corresponding to the secondary access according to the verification result of the secondary access.

[0047] The secondary status information indicates whether there is erroneous data in the memory subspace accessed by the secondary level.

[0048] If the secondary verification result indicates that the data stored in the memory subspace corresponding to the secondary access is consistent with the data obtained by the secondary access, the above-mentioned execution subject can generate secondary status information indicating that there is no access error in the memory subspace of the secondary access. If the secondary verification result indicates that the data stored in the memory subspace corresponding to the secondary access is inconsistent with the data obtained by the secondary access, the above-mentioned execution subject can generate secondary status information indicating that there is an access error in the memory subspace of the secondary access. The secondary status information here may include any number, letter or symbol indicating that an access error occurred or did not occur.

[0049] S203: Determine a memory error address according to the secondary status information corresponding to the memory subspace where the access error occurs.

[0050] For a memory subspace in which an access error is indicated in the primary status information, the memory error address detection method disclosed in the present invention may perform at least one secondary access and record secondary status information obtained by the at least one secondary access.

[0051] The present disclosure can determine, from the recorded secondary status information, the memory subspace where the secondary status information indicates an access error, and use the memory address interval corresponding to the memory subspace as the memory error address.

[0052] In this embodiment, a primary access is performed on at least one memory subspace of the memory to obtain primary state information of at least one memory subspace; wherein the primary state information of the memory subspace is used to indicate whether an access error occurs in the primary access; according to the primary state information, at least one secondary access is repeated on the memory subspace where the access error occurs to obtain secondary state information corresponding to the memory subspace where the access error occurs; and the memory error address is determined according to the secondary state information corresponding to the memory subspace where the access error occurs. Thus, when performing memory error address detection, a primary access is first performed, and then at least one secondary access is repeated on the memory subspace where the access error occurs obtained by the primary access until a more accurate memory address where the error occurs is determined. By determining the memory address where the access error occurs by gradually narrowing the range, the memory address where the error occurs can be quickly determined from the memory. This is conducive to quickly processing the memory address where the error occurs, avoiding the spread of erroneous data, and thus controlling the adverse effects of uncorrectable erroneous data.

[0053] In some embodiments, the above-mentioned step S201 of performing primary access to the memory subspace of the memory and step S202 of repeating at least one secondary access to the memory subspace where the access error occurs based on the primary status information can utilize direct memory access hardware to perform primary access to the data of the memory subspace and read the verification result from the error status register.

[0054] Specifically, in step S201 and step S202, the execution subject may call the direct memory access (DMA) hardware to access the data of the memory subspace. The DMA hardware transmits the data to the ECC check module for verification. The DMA hardware may also read the check result generated by the ECC check module from the error status register corresponding to the ECC check module. The DMA hardware may feed back the read check result to the execution subject.

[0055] In these embodiments, by utilizing hardware with DMA function (DMA hardware for short) to access the memory subspace and returning the verification result in the error status register, the speed of determining the target memory address where the erroneous data occurs can be accelerated.

[0056] Please refer to Figure 3 , which shows a flowchart of another embodiment of the memory error address detection method provided by the present disclosure. Figure 3 As shown, the method comprises the following steps:

[0057] S301. Perform primary access to at least one memory subspace of the memory according to a first access step length to obtain primary status information of at least one memory subspace; wherein the primary status information is used to indicate whether an access error occurs in the primary access, and the first step length is an integer multiple of the detection granularity of the ECC detection module in the memory.

[0058] In this embodiment, the memory may be a memory with an ECC function, which includes an ECC detection module. The storage space outside the ECC detection module of the above memory may be pre-divided into at least one memory subspace.

[0059] In this embodiment, the execution subject may use the first access step length to access each of the memory subspaces.

[0060] The first step length here can be an integer multiple of the detection granularity supported by the ECC detection module in the memory. Schematically, the detection granularity supported by ECC is 128 bytes, and the first step length mentioned above can be an integer multiple of 128 bytes. The integer multiples here can include, for example, 10 times, 100 times, 10000 times, etc. The first step length here can be set according to the specific application scenario. It is understandable that when the memory subspace is larger, the first step length can also be larger. When the memory subspace is smaller, the first step length can also be smaller.

[0061] For each memory subspace, the execution subject may use the first step to traverse the memory subspace, and then obtain at least one primary state information corresponding to the memory subspace.

[0062] In some application scenarios, the size of the first step length may be equal to the size of the memory subspace. In this way, the first step length may be used to perform a primary access to a memory subspace once to complete the access to the memory subspace. In these application scenarios, the sizes of the memory subspaces in the memory storage space may be equal. For each memory subspace, when the execution subject uses the first step length to access the memory subspace, each time the memory subspace is accessed, the ECC detection module of the memory may be called to verify the data obtained from the access. The execution subject may generate primary status information according to the verification result corresponding to the access, and record the primary status information corresponding to the primary access. When recording the primary status information corresponding to the access, the location of the memory subspace (for example, including the starting address and the ending address) and the primary status information may be recorded.

[0063] S302. Repeat at least one secondary access to the memory subspace where the access error occurs according to the primary state information according to a second access step length, wherein the second step length is an integer multiple of the detection granularity of the ECC detection module; wherein the second step length is smaller than the first step length used for the primary access to the memory subspace.

[0064] S303: Determine a memory error address according to the secondary status information corresponding to the memory subspace where the access error occurs.

[0065] The present disclosure can read the primary status information corresponding to each memory subspace, and then search for the primary status information indicating the access error, and then determine the memory subspace corresponding to the primary status information indicating the access error.

[0066] In some embodiments, the execution subject may determine the memory subspace corresponding to the primary state information indicating the access error according to the starting address and offset address of the memory subspace corresponding to the primary state information indicating the access error. The offset address may be equal to the size of the first step length.

[0067] For the memory sub-interval where the access error occurs during the primary access, in order to narrow the scope and reduce the isolated memory space, the present disclosure also requires repeating at least one secondary access to the memory sub-interval where the access error occurs during the primary access (which can be regarded as the target memory sub-space).

[0068] For the memory subspace where the primary access has an access error, the execution subject may repeat at least one secondary access according to the second access step length. The second step length may be smaller than the first step length. The second step length may be an integer multiple of the detection granularity of the ECC detection module. The number of times the secondary access to the memory subspace is repeated at least once may be determined according to the size of the memory subspace.

[0069] Since the second access step length is smaller than the first access step length, for the memory sub-interval where an access error occurs in the primary access, the execution subject can traverse and access the memory sub-interval using the same second access step length to complete a secondary access to the memory interval.

[0070] When the second access step length is used to traverse the memory subspace, for each access, the execution subject may use the ECC detection module to verify the data obtained by the access and obtain the verification result corresponding to the access. The execution subject may generate the secondary state information corresponding to the access according to the verification result.

[0071] The secondary status information here may indicate whether an access error occurs in the memory subspace accessed by using the second access step length.

[0072] In some embodiments, the secondary access is repeated multiple times, and correspondingly the second access step includes multiple sub-steps, each sub-step corresponds to one secondary access; each sub-step is an integer multiple of the detection granularity of the ECC detection module; wherein the multiple sub-steps decrease in sequence according to the execution order of their corresponding secondary accesses, and the sub-step corresponding to the last secondary access is equal to the detection granularity of the ECC detection module.

[0073] In these embodiments, after performing a secondary access, the execution subject can determine the memory subspace where the access error occurred in the secondary access based on the secondary state information obtained in the secondary access. If the determined memory subspace where the access error occurred is still relatively large, the execution subject can continue to use a smaller sub-step size to perform the next secondary access to the memory subspace where the access error occurred, thereby achieving more fine-grained positioning.

[0074] Here, the sub-step length corresponding to each secondary access may be an integer multiple of the detection granularity of the ECC detection module.

[0075] It should be noted that the number of multiple secondary accesses and the size of each sub-step can be determined according to the size of the memory and the required accuracy of the memory error address.

[0076] In some embodiments, in the above-mentioned secondary access, the method also includes: reusing the ECC detection module to perform a secondary check on the data in the memory error address; if the secondary status information corresponding to the check result of the secondary check indicates an access error, the above-mentioned memory error address is determined as the memory error address where a data error occurs.

[0077] After the above-mentioned memory error address is found out based on at least one secondary access, in order to avoid misjudgment of the memory error address caused by errors in the above-mentioned verification process, the above-mentioned execution entity can use the ECC detection module again to perform a second verification on the data in the memory error address, thereby ensuring the accuracy of the final memory error address determined.

[0078] In the related art, in order to reduce the space waste caused by isolating the memory addresses where access errors occur, the traversal is performed in the order of the minimum step length during the traversal process, so as to obtain a memory error address with a smaller granularity. However, if the entire storage space of the memory is traversed in the order of the minimum step length, it will take a long time and occupy hardware resources for a long time. In the present solution, since each of the multiple secondary accesses is a more fine-grained secondary access to the memory subspace where the access error occurred in the previous secondary access, it is possible to determine the memory error address by gradually narrowing the access range. Compared with the above-mentioned method of traversing the memory space in the order of the minimum step length from the beginning, the present solution adopts the method of gradually narrowing the access range to locate the memory error address, which can save the time required to locate the memory error address, reduce the hardware resource occupation, and improve the efficiency of locating the memory error address.

[0079] In some embodiments, the secondary access is repeated once.

[0080] In these embodiments, for the memory subspace where the access error occurs as determined by the primary access, the execution subject may select a suitable second step length, and then use the second step length to perform a secondary access to the memory subspace. The second step length here may be a multiple of a smaller detection granularity of the ECC detection module, such as 1 times, 5 times, etc. Preferably, the selection of the second step length is consistent with the size of the isolated space acceptable to the user. This secondary access uses the second step length to traverse the memory subspace where the access error occurs.

[0081] In these embodiments, the memory address where the access error occurs is located through two-level access, the target space can be reduced by the primary state information obtained by the primary access, and the error address is located in the reduced target space using the second step length, which can improve the efficiency of determining the memory error address.

[0082] In some embodiments, the primary access to the memory subspace of the memory in step S301 and the secondary access to the memory subspace where an access error occurs in the primary access in step S302 can be accessed using direct memory access (DMA) hardware.

[0083] The direct memory access hardware can access the data in the memory subspace, and the DMA hardware transmits the data to the ECC check module for check. The DMA hardware can also read the check result generated by the ECC check module from the error status register corresponding to the ECC check module. The DMA hardware can feed back the read check result to the execution subject.

[0084] In these embodiments, DMA hardware is used to access a memory subspace, and state information of the accessed memory subspace is read and returned, thereby speeding up the determination of a memory error address.

[0085] In this embodiment, at least one memory subspace of the memory is accessed at a primary level according to a first access step length to obtain primary state information of at least one memory subspace; based on the primary state information, at least one secondary access is repeatedly performed on the memory subspace where an access error occurs according to a second access step length; wherein the second step length is smaller than the first step length used for the primary access to the memory subspace; and the memory error address is determined based on the secondary state information corresponding to the memory subspace where the access error occurs. Thus, when performing memory error address detection, primary state information is obtained through coarse-grained primary access, and then fine-grained secondary access is repeatedly performed using the second step length on the memory subspace where the primary state information indicates an access error occurs, so that the memory error address can be determined quickly and accurately, avoiding the waste of space caused by isolating the memory error address. This is conducive to quickly and accurately processing the memory address where the access error occurs, avoiding the spread of the adverse effects of the erroneous data.

[0086] exist Figure 2 and Figure 3 In some implementations of the memory error address detection method of the illustrated embodiment, the method further includes:

[0087] A bitmap is used to record the primary state information and the secondary state information corresponding to at least one secondary access. In the above bitmap, each bit can represent a memory subspace. A bitmap identifier representing the state information of the memory subspace is stored in the bit. By recording the bitmap identifier representing the state information of each memory subspace in the bitmap, the memory management can be facilitated.

[0088] The execution subject may establish a global bitmap of the memory, which may include a primary bitmap for recording primary status information of multiple memory subspaces and a secondary bitmap for recording secondary status information of multiple memory subspaces.

[0089] The primary bitmap may include a plurality of bits, and the memory subspaces corresponding to the plurality of bits of the primary bitmap may constitute the storage space of the ECC memory.

[0090] Each bit in the primary bitmap may record a primary bitmap identifier, which may represent primary state information of the memory subspace corresponding to the bit.

[0091] As an implementation method, before performing primary access to the ECC memory, the above-mentioned execution entity may create a global bitmap that only includes a primary bitmap, and then initialize the primary bitmap. An initial bitmap identifier may be recorded in each bit of the initialized primary bitmap. The initial bitmap identifier indicates the initial state information of the memory subspace corresponding to the bit. The above-mentioned initial state information may, for example, be state information indicating that no access error has occurred, and the above-mentioned initial bitmap identifier may be a bitmap identifier indicating state information that no access error has occurred, such as "0". In one example, in the above-mentioned primary bitmap created above, the size of the memory subspace corresponding to each bit may be equal to the size of the first step length.

[0092] After the execution subject receives the memory error address detection instruction sent by the operating system, the execution subject can traverse the memory subspace corresponding to the bit position (bit position) with the bitmap identifier of 0 in the global bitmap, that is, perform primary access to the memory subspace.

[0093] After primary access to a memory subspace, the execution subject may determine the primary bitmap identifier corresponding to the memory subspace according to the primary state information obtained by the primary access, and replace the initial bitmap identifier in the corresponding bit with the primary bitmap identifier.

[0094] In practice, if the primary state information obtained by primary access to a memory subspace is consistent with the initial state information, that is, the primary bitmap identifier corresponding to the memory subspace is consistent with the initial bitmap identifier, the above-mentioned execution entity may not replace the bitmap identifier recorded in the bit corresponding to the memory subspace.

[0095] If a primary access is performed on a memory subspace and the primary status information obtained indicates that an access error occurs in the memory subspace, the above-mentioned execution entity can generate a primary bitmap identifier of the access error, find the bit corresponding to the memory subspace in the bitmap, and use the primary bitmap identifier to replace the initial bitmap identifier of the bit.

[0096] The primary bitmap of the global memory subspace can be obtained in the above manner.

[0097] Specifically, when the execution subject uses the first step length to access the memory subspace [a, b] in the primary access, the first step length may be K×c. Here, c may be the detection granularity supported by the ECC detection module. K is a positive integer greater than 1. Wherein, a is the starting address of the memory subspace, and b is the ending address of the memory subspace.

[0098] When the above-mentioned execution subject uses the first step to access the memory subspace [a, b] for the first time, the actual access is to the [a, a+K×c] memory subspace. The above-mentioned execution subject can generate a corresponding primary bitmap identifier based on the primary status information obtained from the first access. Schematically, if the primary status information indicates that no access error has occurred, a primary bitmap identifier indicating that no access error has occurred is generated, such as "0". If the primary status information indicates that an access error has occurred, a primary bitmap identifier representing that an access error has occurred is generated, such as "1". The original initial bitmap identifier can be replaced with "1" in the bit corresponding to the memory subinterval [a, a+K×c] in the above-mentioned primary bitmap.

[0099] Then, when the execution subject uses the first step to perform primary access to the memory subspace [a, b] for the second time, the memory subspace [a+K×c+1, a+2K×c+1] is actually accessed. The execution subject can generate a corresponding primary bitmap identifier based on the primary state information obtained from the second primary access. If the primary bitmap identifier is consistent with the original bitmap identifier in the bit corresponding to the memory subspace [a+K×c+1, a+2K×c+1], it will not be replaced. If it is inconsistent, it will be replaced.

[0100] By analogy, after primary access to the memory traversal, the global primary bitmap corresponding to the memory can be obtained.

[0101] The memory subspace indicating that an access error occurred in the primary access may be read from the primary bitmap.

[0102] The following uses a secondary access as an example to illustrate the generation process of the secondary bitmap. For the memory subspace [e, f] (memory subspace [e, f] belongs to memory subspace [a, b]) indicated by the primary access, which indicates an access error, the above execution subject creates the secondary bitmap corresponding to the memory subspace [e, f] according to the second step length. e is the starting address of the memory subspace [e, f], and f is the ending address of the memory subspace [e, f].

[0103] The size of the memory subspace corresponding to each bit in the secondary bitmap may be equal to the second step size. Each bit in the secondary bitmap may correspond to an initial secondary bitmap identifier. The initial secondary bitmap identifier may indicate that no access error occurs in the memory subspace corresponding to each bit.

[0104] The execution subject may use the second access step to perform a secondary access to the memory subspace [e, f]. Where e is less than or equal to a; f is less than or equal to b. The size of the second step may be L×c, where L is a positive integer less than K.

[0105] The execution subject uses the second step length to access the memory subspace [e, f] for the first time, and the accessed subspace is [e, e+L×c]. Then the execution subject calls the ECC detection module to verify the data in this subspace and obtains the verification result. If the verification result indicates that the data originally stored in the subspace is consistent with the data accessed this time, the secondary state information of the subspace is that no access error occurs, and then the execution subject generates a secondary bitmap identifier corresponding to the secondary state information that no access error occurs, such as "0". If the verification result indicates that the data originally stored in the subspace is inconsistent with the data accessed this time, the secondary state information of the subspace is that an access error occurs, and then the execution subject generates a secondary bitmap identifier corresponding to the secondary state information that an access error occurs, such as "1". In the first bit of the secondary bitmap, the secondary bitmap identifier is used to replace the original initial secondary bitmap identifier.

[0106] After determining the secondary bitmap identifier corresponding to the memory subspace [e, e+L×c] and replacing it in the original secondary bitmap, the above-mentioned execution subject can continue to access the subspace [e+L×c+1, e+2L×c+1] using the second step length. Then the above-mentioned execution subject uses the ECC detection module to verify the accessed data. If the verification result indicates that the data originally stored in the subspace is consistent with the data accessed this time, the secondary state information of the subspace is that no access error occurs, and then the above-mentioned execution subject can generate a secondary bitmap identifier corresponding to the secondary state information that no access error occurs, such as "0". If the verification result indicates that the data originally stored in the subspace is inconsistent with the data accessed this time, the secondary state information of the subspace is that an access error occurs, and then the above-mentioned execution subject generates a secondary bitmap identifier corresponding to the secondary state information that an access error occurs, such as "1". In the second bit in the secondary bitmap, the above-mentioned secondary bitmap identifier is used to replace the original initial secondary bitmap identifier.

[0107] By analogy, using the second step length, the execution subject can sequentially perform secondary accesses to multiple memory subspaces belonging to the memory subspace [e, f], and then generate a secondary bitmap identifier corresponding to each access, indicating the presence or absence of an access error. For each access, if the secondary bitmap identifier corresponding to the access is a secondary bitmap identifier "1" indicating an access error, the execution subject can use the secondary bitmap identifier to replace the original secondary bitmap identifier in the bit corresponding to the access. Then, the secondary bitmap after the secondary access is completed is obtained.

[0108] That is, the memory subspace in the global memory space where the access error occurs can be determined based on the large step length scan. After performing the large step length global scan, the primary state information corresponding to the multiple memory subspaces can be obtained, and the execution subject can use the primary bitmap to record the primary state information corresponding to the multiple memory subspaces. In addition, for the memory subspace indicating the access error determined by the primary access, the execution subject can perform a fine-grained inspection based on the second step length.

[0109] Please refer to Figure 4 , which shows a schematic diagram of a bitmap. Figure 4 As shown, the global bitmap of the memory may include a primary bitmap and a secondary bitmap. Each box in the primary bitmap is a bit. One bit corresponds to a memory subspace. The number "0" or "1" in each bit is the primary bitmap identifier of the corresponding memory subspace. The primary bitmap identifier in each bit indicates whether an access error occurs in the primary access of the memory subspace corresponding to the bit. Among them, "1" indicates that an access error occurs in the primary access of the memory subspace. "0" indicates that no access error occurs in the primary access of the memory subspace.

[0110] In the process of determining the memory error address where the error data appears, each memory subspace in the memory can be accessed using the first step length (such as the size of the first step length is equal to the size of the memory subspace). If it is determined according to the primary access that a memory subspace has an access error, the primary bitmap flag of the bit in the primary bitmap corresponding to the memory subspace is set to 1. When the primary access determines that a memory subspace does not have an access error, the primary bitmap flag corresponding to the memory subspace remains 0. Figure 4 The memory subspaces corresponding to bits 401 and 402 in the primary bitmap respectively determine that access errors occur in the two memory subspaces through primary access, and the primary bitmap flags in bits 401 and 402 are set to 1. The remaining memory subspaces do not have access errors during primary access, and the primary bitmap flags of the remaining memory subspaces remain 0.

[0111] For the memory subspaces 401 and 402 where the primary access error occurs, the execution subject may use the second step size to perform a secondary access, and create a secondary bitmap corresponding to the memory subspace 401, such as the secondary bitmap shown by the mark 4010 in the figure, and a secondary bitmap corresponding to the memory subspace 402, such as the secondary bitmap shown by the mark 4020 in the figure. The size of the memory subspace corresponding to each bit in the secondary bitmaps 4010 and 4020 may be equal to the size of the second step size.

[0112] The execution body initializes each bit in the created secondary bitmap 4010 and the secondary bitmap 4020, for example, sets an initial secondary bitmap flag (such as 0) for each bit indicating that no access error occurs.

[0113] For the memory subspace 401, the above-mentioned execution subject uses the second step length to perform secondary access from the starting address of the memory subspace. The above-mentioned execution subject obtains data for each secondary access, and can use the ECC detection module to verify it, determine the secondary status information corresponding to the access based on the verification result, and generate a secondary bitmap identifier corresponding to the above-mentioned secondary status information. Similarly, the secondary bitmap identifier "0" indicates that there is no access error in the secondary access. The secondary bitmap identifier "1" indicates that there is an access error in the access. The secondary bitmap identifier in the corresponding bit of the secondary bitmap 4010 is updated using the secondary bitmap identifier obtained by the access.

[0114] Similarly, for the memory subspace 402, the execution subject uses the second step length to perform secondary access from the starting address of the memory subspace. The ECC check module is used to check each secondary access, and the execution subject generates secondary status information according to the check result, and generates a secondary bitmap identifier according to the secondary status information. The secondary bitmap identifier is used to update the secondary bitmap identifier of the corresponding bit of the secondary bitmap 4020.

[0115] From the secondary bitmaps 4010 and 4020 obtained through the secondary access, the execution subject can search for the secondary bitmap identifier 1 indicating an access error, and then the bits 4011, 4021, 4022, and 4023 corresponding to the secondary bitmap identifier 1. Then determine the address range indicated by these bits 4011 and 4021, 4022, and 4023. The address range indicated by 4011 and 4021, 4022, and 4023 can be reported as a memory error address.

[0116] For example, when the secondary bitmap flag corresponding to bit 4011 is detected as 1, the interrupt that the address interval corresponding to bit 4011 is the memory error address can be reported first. When the secondary bitmap flag corresponding to bit 4021 is detected as 1, the interrupt that the address interval corresponding to bit 4021 is the memory error address can be reported. And so on, the memory error addresses detected each time are reported one by one.

[0117] The memory is managed and abstracted by using a multi-level bitmap, and the memory error address detection is performed by sequentially traversing the bitmap. On the one hand, the memory address where the error data appears can be quickly verified, and when these addresses are isolated, excessive memory space will not be wasted. On the other hand, it can ensure that repeated access to the error address that has been verified will not be initiated during the traversal process, which will affect the accuracy of the memory error address detection.

[0118] In some embodiments, the execution subject may start the memory error address detection method after receiving interrupt information indicating that a memory data error has occurred. In these embodiments, the interrupt information may include information on the number of data errors.

[0119] In these embodiments, the execution subject may perform primary access to at least one memory subspace of the memory. If it is determined according to the primary access that access errors occur in the number of memory subspaces indicated by the quantity information, the execution subject repeats at least one secondary access to each memory subspace indicated by the primary access as having an access error.

[0120] If the number of memory subspaces with access errors determined according to the primary access is less than the number indicated by the quantity information, it is possible that there are more than two erroneous data in a single memory subspace. The execution subject may repeatedly access the memory subspace indicated by the primary access as having access errors using a second step length including multiple sub-step lengths.

[0121] In these instances, by using a second step size including multiple sub-step sizes to repeatedly perform secondary accesses on a memory subspace where a primary access indicates an access error, a more accurate memory error address can be obtained while avoiding omission of the memory error address.

[0122] In some embodiments, Figure 1 Steps S201 and S202 of the embodiment shown in FIG. Figure 3 Before step S301 of the illustrated embodiment, the method further includes:

[0123] In response to detecting an uncorrectable error in the memory, a memory error address detection process is initiated, and an interrupt for reporting an indication of a memory error is disabled during the memory error address detection process.

[0124] In these instances, in order to prevent an infinite loop caused by using the ECC detection module to verify the data in each memory sub-room and reporting the interrupt again during the process of detecting the memory error address based on the interrupt, the above-mentioned execution entity can turn off the function of the memory ECC detection module to issue an interrupt indicating a memory error when determining the memory address where the erroneous data appears based on the above-mentioned interrupt, so as to avoid falling into an infinite loop and effectively determine the memory error address.

[0125] In some embodiments, the method further comprises:

[0126] After the memory error address is determined, an interrupt carrying the memory error address is reported.

[0127] In these embodiments, the execution subject may report an interruption carrying the memory error address to the operating system connected to the memory, and the operating system may then isolate the memory error address according to the interruption, thereby preventing the spread of erroneous data in the memory error address.

[0128] In some embodiments, the method further comprises the steps of:

[0129] First, in response to detecting a memory error address of a memory subspace where an access error occurs, an interrupt carrying the memory error address is reported.

[0130] Secondly, after the interrupt carrying the memory error address is reported, the memory error address detection of the next memory subspace where the access error occurs continues until the memory error address detection of the memory is completed.

[0131] In these embodiments, after detecting a memory error address, the execution subject may report an interruption carrying the memory error address to the operating system connected to the memory in real time, so that the operating system isolates the memory error address in real time. If the interruption information indicating the memory error indicates that there are multiple memory errors, after reporting an interruption carrying the memory error address, the detection of the next memory error address may be continued until the detection of the multiple memory errors is completed.

[0132] The above-mentioned multiple memory error addresses may be distributed in one memory subspace or in different memory subspaces.

[0133] In these embodiments, by reporting an interrupt carrying a memory error address after detecting a memory error address, it is beneficial to isolate the memory error address in real time and reduce the diffusion range of the data in the memory error address.

[0134] Please refer to Figure 5 , which shows a principle flow chart of the memory error address detection method provided by the present disclosure. Figure 5 As shown, after receiving the memory error address detection instruction sent by the operating system, the above-mentioned execution subject can loop through the memory subspace 501 corresponding to the bit marked as 0 in the initialized primary bitmap (the global bitmap created for the first time can only include the primary bitmap, and the first traversal is to traverse the initialized primary bitmap) to perform primary access to the memory subspace corresponding to the bit marked as 0 in the bitmap.

[0135] Then the execution subject determines whether a memory error address is found from the primary bitmap obtained by the loop traversal primary access 502. Specifically, if the primary status information obtained by the primary access to a memory subspace indicates that an access error occurs in the memory subspace, the address interval of the memory subspace is the memory error address.

[0136] However, if the memory subspace corresponding to the address interval is large, in order to avoid wasting space caused by isolating the memory subspace, the execution entity also needs to perform fine-grained inspection on the memory subspace where the access error occurs as determined by the primary access.

[0137] For a memory subspace in which an access error occurs during primary access, the initial bitmap identifier "0" in the bit corresponding to the memory subspace may be updated to "1" 503, thereby implementing an update of the primary bitmap according to the primary access result.

[0138] The memory subspace where the primary access error occurs can be determined from the updated global primary bitmap, and then the execution subject creates a secondary bitmap for the memory subspace where the access error occurs, as shown in 504. The secondary bitmap may include multiple bits. The subspace size corresponding to each bit in the secondary bitmap is smaller than the subspace size corresponding to each bit in the primary bitmap. For the memory subspace where the access error occurs in the primary bitmap, the second step length can be used for access.

[0139] The size of the memory subspace corresponding to each bit in the secondary bitmap may be equal to the size of the second step. The initial state of each bit in the secondary bitmap created for the memory subspace may be a secondary bitmap flag indicating no access error, such as "0".

[0140] The above-mentioned execution subject can loop through the physical memory space 505 whose bit is 0 in the secondary bitmap. Each time a physical memory subspace with a bit of 0 is accessed, the above-mentioned execution subject can use the ECC detection module to verify the data stored in the physical memory subspace. The above-mentioned execution subject can determine the secondary status information of the physical memory subspace based on the verification result, and determine whether the memory error address 506 is found based on the secondary status information. If the secondary status information determined according to the verification result indicates that the physical memory subspace has no access error, the memory error address is not found in this secondary access. If the secondary status information determined according to the verification result indicates that the physical memory subspace has an access error, the memory error address is found in this secondary access.

[0141] Then the execution subject may check the memory error address twice 507. When checking the memory error address twice, the execution subject may call the ECC detection module to check the data of the memory error address. If the check result indicates that the data accessed this time is inconsistent with the data originally stored in the memory error address, then the memory error address is indeed a memory error address where a data error occurs. If the second check of the memory error address determines that a memory error actually occurs at the memory error address, the secondary bitmap identifier "0" of the corresponding bit in the secondary bitmap is updated to the secondary bitmap identifier "1" 508 used to represent the access error.

[0142] By analogy, the physical memory subspace with bit 0 in the secondary bitmap can be traversed according to the above loop to perform secondary access, and finally a secondary bitmap including multiple bits with secondary bitmap identifier 1 is obtained. The memory error address 509 corresponding to the bit with secondary bitmap identifier "1" is returned.

[0143] For interrupt information indicating multiple error addresses, if no memory error address is detected after primary access is performed on all memory subspaces with bits 0 in the primary bitmap, then it can be considered that the memory error address is in the physical memory space corresponding to the bit with the bitmap identifier 1 in the primary bitmap. Then the above-mentioned execution subject can loop through the memory subspace 510 corresponding to the secondary bitmap of the memory subspace with bits 1 in the primary bitmap. Afterwards, the above-mentioned execution subject loops through the physical memory subspace 505 corresponding to the bit with the secondary bitmap identifier 0 in the secondary bitmap. Specifically, the physical memory subspace corresponding to the bit with the bitmap identifier 0 in the secondary bitmap can be accessed, and then the accessed data is checked using the ECC detection module. Determine whether the physical memory subspace is a memory error address based on the check result. If so, the above-mentioned execution subject can double-check the data 507 in the memory error address. If it is determined according to the secondary verification result that an access error does occur at the memory error address, the execution entity sets the bitmap identifier of the bit corresponding to the physical memory subspace to "1" 508, and returns the address of the physical memory subspace with the bitmap identifier "1" to the operating system as the memory error address 509.

[0144] Please refer to Figure 6 , which shows a schematic diagram of the structure of a memory error address detection device. Figure 6 As shown, the memory error address detection device 60 includes: a primary access unit 601, a secondary access unit 602 and a determination unit 603. Among them:

[0145] A primary access unit 601 is used to perform primary access to at least one memory subspace of the memory and obtain primary state information of at least one memory subspace; wherein the primary state information is used to indicate whether an access error occurs in the primary access;

[0146] A secondary access unit 602 is used to repeatedly perform at least one secondary access to the memory subspace where the access error occurs according to the primary state information, so as to obtain secondary state information corresponding to the memory subspace where the access error occurs;

[0147] The determination unit is used to determine the memory error address according to the secondary state information corresponding to the memory subspace where the access error occurs.

[0148] In some embodiments, the primary access unit 601 is further used to: perform primary access to at least one memory subspace of the memory according to a first access step length, where the first step length is an integer multiple of the detection granularity of the ECC detection module in the memory.

[0149] In some embodiments, the secondary access unit 601 is further configured to:

[0150] Repeat at least one secondary access to the memory subspace where the access error occurs according to the second access step length, where the second step length is an integer multiple of the detection granularity of the ECC detection module; wherein,

[0151] The second step size is smaller than the first step size used for the primary access to the memory subspace.

[0152] In some embodiments, the secondary access is repeated multiple times, and accordingly the second access step includes multiple sub-steps, each sub-step corresponds to one secondary access; each sub-step is an integer multiple of the detection granularity of the ECC detection module;

[0153] The multiple sub-steps are reduced in sequence according to the execution order of the corresponding secondary accesses, and the sub-step corresponding to the last secondary access is equal to the detection granularity of the ECC detection module.

[0154] In some embodiments, the secondary access is repeated once.

[0155] In some embodiments, the device 60 further includes a recording unit (not shown in the figure). The recording unit is used to:

[0156] A bitmap is used to record the primary state information and the secondary state information corresponding to at least one secondary access.

[0157] In some embodiments, the apparatus 60 further includes a reporting unit (not shown in the figure). The reporting unit is used to: after determining the memory error address, report an interrupt carrying the memory error address.

[0158] In some embodiments, the reporting unit is further configured to:

[0159] In response to detecting a memory error address of a memory subspace where an access error occurs, reporting an interrupt carrying the memory error address;

[0160] After the interrupt carrying the memory error address is reported, the memory error address detection of the next memory subspace where the access error occurs continues until the memory error address detection of the memory is completed.

[0161] In some embodiments, the device 60 further includes an interruption closing unit (not shown in the figure), which is used to:

[0162] In response to detecting an uncorrectable error in the memory, a memory error address detection process is initiated, and an interrupt for reporting an indication of a memory error is disabled during the memory error address detection process.

[0163] refer to Figure 7 , which shows a schematic diagram of the structure of an electronic device 700 suitable for implementing the embodiment of the present disclosure, and the electronic device 700 may be a terminal device or a server. The terminal device may include but is not limited to mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (Portable Android Devices, PADs), portable multimedia players (PMPs), vehicle terminals (such as vehicle navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0164] like Figure 7 As shown, the electronic device 700 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 to a random access memory (RAM) 703. Various programs and data required for the operation of the electronic device 700 are also stored in the RAM 703. The processing device 701, the ROM 702, and the RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0165] Typically, the following devices may be connected to the I / O interface 705: input devices 706 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; output devices 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 708 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 709. The communication devices 709 may allow the electronic device 700 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 7 The electronic device 700 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0166] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device 709, or installed from a storage device 708, or installed from a ROM 702. When the computer program is executed by the processing device 701, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0167] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0168] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0169] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device executes the method shown in the above embodiment.

[0170] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0171] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0172] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0173] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0174] In a first aspect, according to one or more embodiments of the present disclosure, a method for detecting a memory error address is provided, the method comprising:

[0175] Performing primary access to at least one memory subspace of the memory to obtain primary state information of the at least one memory subspace; wherein the primary state information is used to indicate whether an access error occurs in the primary access;

[0176] According to the primary state information, repeatedly perform at least one secondary access to the memory subspace where the access error occurs, to obtain secondary state information corresponding to the memory subspace where the access error occurs;

[0177] A memory error address is determined according to secondary status information corresponding to the memory subspace where the access error occurs.

[0178] According to one or more embodiments of the present disclosure, primary access to at least one memory subspace of a memory includes:

[0179] A primary access is performed on at least one memory subspace of the memory according to a first access step length, wherein the first access step length is an integer multiple of a detection granularity of an ECC detection module in the memory.

[0180] According to one or more embodiments of the present disclosure, according to the primary state information, repeatedly performing at least one secondary access to the memory subspace where the access error occurs, includes:

[0181] Repeat at least one secondary access to the memory subspace where the access error occurs according to the second access step length, where the second step length is an integer multiple of the detection granularity of the ECC detection module; wherein,

[0182] The second step size is smaller than the first step size used for the primary access to the memory subspace.

[0183] According to one or more embodiments of the present disclosure, the secondary access is repeated multiple times, and accordingly the second access step includes multiple sub-steps, each sub-step corresponds to one secondary access; each sub-step is an integer multiple of the detection granularity of the ECC detection module;

[0184] The multiple sub-steps are reduced in sequence according to the execution order of the corresponding secondary accesses, and the sub-step corresponding to the last secondary access is equal to the detection granularity of the ECC detection module.

[0185] According to one or more embodiments of the present disclosure, the secondary access is repeated once.

[0186] According to one or more embodiments of the present disclosure, the method further includes:

[0187] A bitmap is used to record the primary state information and the secondary state information corresponding to at least one secondary access.

[0188] According to one or more embodiments of the present disclosure, the method further includes:

[0189] After the memory error address is determined, an interrupt carrying the memory error address is reported.

[0190] According to one or more embodiments of the present disclosure, the method further includes:

[0191] In response to detecting a memory error address of a memory subspace where an access error occurs, reporting an interrupt carrying the memory error address;

[0192] After the interrupt carrying the memory error address is reported, the memory error address detection of the next memory subspace where the access error occurs continues until the memory error address detection of the memory is completed.

[0193] According to one or more embodiments of the present disclosure, before performing primary access to at least one memory subspace of the memory to obtain primary state information of the at least one memory subspace, the method further includes:

[0194] In response to detecting an uncorrectable error in the memory, a memory error address detection process is initiated, and an interrupt for reporting an indication of a memory error is disabled during the memory error address detection process.

[0195] In a second aspect, according to one or more embodiments of the present disclosure, a memory error address detection device is provided, wherein the memory includes a plurality of memory subspaces, and the device includes:

[0196] A primary access unit is used to perform primary access to at least one memory subspace of the memory to obtain primary status information of the at least one memory subspace; wherein the primary status information is used to indicate whether an access error occurs in the primary access; a secondary access unit is used to repeat at least one secondary access to the memory subspace where the access error occurs according to the primary status information to obtain secondary status information corresponding to the memory subspace where the access error occurs;

[0197] The determination unit is used to determine the memory error address according to the secondary state information corresponding to the memory subspace where the access error occurs.

[0198] According to one or more embodiments of the present disclosure, the primary access unit is further used to: perform primary access to at least one memory subspace of the memory according to a first access step size, and the first step size is an integer multiple of the detection granularity of the ECC detection module in the memory.

[0199] According to one or more embodiments of the present disclosure, the secondary access unit is further configured to:

[0200] Repeat at least one secondary access to the memory subspace where the access error occurs according to the second access step length, where the second step length is an integer multiple of the detection granularity of the ECC detection module; wherein,

[0201] The second step size is smaller than the first step size used for the primary access to the memory subspace.

[0202] According to one or more embodiments of the present disclosure, the secondary access is repeated multiple times, and accordingly the second access step includes multiple sub-steps, each sub-step corresponds to one secondary access; each sub-step is an integer multiple of the detection granularity of the ECC detection module;

[0203] The multiple sub-steps are reduced in sequence according to the execution order of the corresponding secondary accesses, and the sub-step corresponding to the last secondary access is equal to the detection granularity of the ECC detection module.

[0204] According to one or more embodiments of the present disclosure, the secondary access is repeated once.

[0205] According to one or more embodiments of the present disclosure, the memory error address detection device further includes a recording unit. The recording unit is used to:

[0206] A bitmap is used to record the primary state information and the secondary state information corresponding to at least one secondary access.

[0207] According to one or more embodiments of the present disclosure, the memory error address detection device further includes a reporting unit. The reporting unit is used to: after determining the memory error address, report an interrupt carrying the memory error address.

[0208] According to one or more embodiments of the present disclosure, the reporting unit is further configured to:

[0209] In response to detecting a memory error address of a memory subspace where an access error occurs, reporting an interrupt carrying the memory error address;

[0210] After the interrupt carrying the memory error address is reported, the memory error address detection of the next memory subspace where the access error occurs continues until the memory error address detection of the memory is completed.

[0211] According to one or more embodiments of the present disclosure, the memory error address detection device further includes an interruption disabling unit, and the interruption disabling unit is used to:

[0212] In response to detecting an uncorrectable error in the memory, a memory error address detection process is initiated, and an interrupt for reporting an indication of a memory error is disabled during the memory error address detection process.

[0213] In a third aspect, according to one or more embodiments of the present disclosure, there is provided an electronic device, comprising: at least one processor and a memory;

[0214] Memory stores computer-executable instructions;

[0215] At least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the above first aspect and various possible methods of the first aspect.

[0216] In a fourth aspect, according to one or more embodiments of the present disclosure, a computer-readable storage medium is provided, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the first aspect and various possible methods of the first aspect are implemented.

[0217] In a fifth aspect, according to one or more embodiments of the present disclosure, a computer program product is provided, including a computer program, which implements the above first aspect and various possible methods of the first aspect when executed by a processor.

[0218] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A memory error address detection method, characterized in that: include: Performing primary access to at least one memory subspace of the memory to obtain primary state information of the at least one memory subspace; wherein the primary state information is used to indicate whether an access error occurs in the primary access; According to the primary state information, repeatedly perform at least one secondary access to the memory subspace where the access error occurs, to obtain secondary state information corresponding to the memory subspace where the access error occurs; A memory error address is determined according to the secondary status information corresponding to the memory subspace where the access error occurs.

2. The method according to claim 1, characterized in that The primary access to at least one memory subspace of the memory comprises: Primary access is performed on at least one memory subspace of the memory according to a first access step length, where the first access step length is an integer multiple of a detection granularity of an ECC detection module in the memory.

3. The method according to claim 1, characterized in that The step of repeatedly performing at least one secondary access to the memory subspace where the access error occurs according to the primary state information comprises: Repeat at least one secondary access to the memory subspace where the access error occurs according to the second access step length, wherein the second step length is an integer multiple of the detection granularity of the ECC detection module; wherein The second step size is smaller than the first step size used for primary access to the memory subspace.

4. The method according to claim 3, characterized in that The secondary access is repeated multiple times, and accordingly the second access step includes multiple sub-steps, each sub-step corresponds to one secondary access; each sub-step is an integer multiple of the detection granularity of the ECC detection module; The multiple sub-steps are reduced in sequence according to the execution order of the corresponding secondary accesses, and the sub-step corresponding to the last secondary access is equal to the detection granularity of the ECC detection module.

5. The method according to claim 3, characterized in that: The secondary access is repeated once.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: A bitmap is used to record the primary status information and the secondary status information corresponding to at least one secondary access.

7. The method according to claim 1, characterized in that The method further comprises: After determining the memory error address, an interrupt carrying the memory error address is reported.

8. The method according to claim 1, characterized in that The method further comprises: In response to detecting a memory error address of a memory subspace where an access error occurs, reporting an interrupt carrying the memory error address; After reporting the interrupt carrying the memory error address, continue detecting the memory error address of the next memory subspace where an access error occurs until the memory error address detection of the memory is completed.

9. The method according to claim 1, characterized in that: Before performing primary access to at least one memory subspace of the memory to obtain primary state information of the at least one memory subspace, the method further includes: In response to detecting that an uncorrectable error exists in the memory, a memory error address detection process is initiated, and during the memory error address detection process, an interrupt for reporting an indication of a memory error is disabled.

10. A memory error address detection device, characterized in that: The device comprises: A primary access unit, used to perform primary access to at least one memory subspace of the memory to obtain primary status information of the at least one memory subspace; wherein the primary status information is used to indicate whether an access error occurs in the primary access; A secondary access unit, configured to repeatedly perform at least one secondary access to the memory subspace where the access error occurs according to the primary state information, to obtain secondary state information corresponding to the memory subspace where the access error occurs; The determination unit is used to determine the memory error address according to the secondary status information corresponding to the memory subspace where the access error occurs.

11. An electronic device, characterized in that: include: Processor and memory; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory, so that the processor performs the memory error address detection method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions. When the processor executes the computer-executable instructions, the memory error address detection method according to any one of claims 1 to 9 is implemented.

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