Fault injection method, system and device of FPGA chip and medium

Abstract

The invention relates to the technical field of fault attacks, and discloses a fault injection method, system and device for an FPGA chip and a medium. The method comprises the following steps: acquiring actual power consumption data of an FPGA chip on a time sequence in a process of running a preset encryption algorithm by the FPGA chip; simulating the process of running the preset encryption algorithm by the FPGA chip to obtain simulation power consumption data of the FPGA chip on a time sequence; respectively carrying out multiplication operation and accumulation operation on data at corresponding moments in the actual power consumption data and the simulation power consumption data, and acquiring moments corresponding to the actual power consumption data and the simulation power consumption data when values obtained by the multiplication operation and the accumulation operation exceed a preset threshold value as fault injection moments of the FPGA chip; at the fault injection moment, the voltage drop is generated in the FPGA chip to complete fault injection of the FPGA chip, and the fault injection can be realized without changing the original circuit of the FPGA or triggering a signal.

Description

Technical Field

[0001] The present invention relates to the field of fault attack technology, and in particular to a fault injection method, system, device and medium for an FPGA chip. Background Art

[0002] At present, encryption algorithms are widely used, which play a vital role in ensuring the security of network communications, protecting the integrity of data storage, supporting the development of blockchain technology, and ensuring the security of electronic payments. Due to the reconfigurable and parallel computing characteristics of Field Programmable Gate Array (FPGA), FPGA is often used to implement hardware acceleration and customized logic of various algorithms in embedded systems, including encryption algorithms. However, the cryptographic algorithms implemented by FPGA are vulnerable to malicious attacks. Fault injection attacks (FIAs) are an attack method that can evaluate the security of cryptographic algorithms implemented by FPGA by injecting faults into FPGA chips. Traditional fault injection methods include voltage or clock glitch attacks, electromagnetic or laser attacks, and temperature attacks.

[0003] Among them, voltage glitches and clock glitches require changing the original circuit of the device (i.e., FPGA chip), and other attack methods also require obtaining a certain degree of physical permissions on the device. For example, in the process of fault injection, in order to complete the positioning of the fault injection interval, the target device is first required to provide a signal as a trigger. After capturing the signal, it is synchronized with the power consumption / electromagnetic trajectory to achieve accurate encryption and decryption interval positioning and fault injection. However, only the devices used in the experiment will reserve special trigger pins. In the devices actually used, the attacker needs to find an available trigger signal. When the attacker does not have physical permissions to the target device, there may be no available trigger signal, resulting in the failure of fault injection. Summary of the invention

[0004] The purpose of the present invention is to provide a fault injection method, system, device and medium for an FPGA chip, which can achieve fault injection without changing the original circuit of the FPGA and without requiring a trigger signal.

[0005] To solve the above technical problems, an embodiment of the present invention provides a fault injection method for an FPGA chip, comprising the following steps:

[0006] Obtain the actual power consumption data of the FPGA chip in timing when the FPGA chip runs the preset encryption algorithm;

[0007] The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip in timing;

[0008] Perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, respectively, and obtain the moments corresponding to the actual power consumption data and the simulated power consumption data when the values ​​obtained by the multiplication and accumulation operations exceed a preset threshold value as the fault injection moment of the FPGA chip;

[0009] At the moment of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip.

[0010] In some optional embodiments, the process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip in timing, including:

[0011] Get the total clock consumed by the FPGA chip to run the preset encryption algorithm;

[0012] According to the preset ideal clock for injecting faults into the FPGA chip, all clocks before the ideal clock in the total clock are obtained as the target clock;

[0013] The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock.

[0014] In some optional embodiments, before performing multiplication and accumulation operations on the actual power consumption data and the data at corresponding moments in the simulated power consumption data, the method further includes:

[0015] The simulated power consumption data is downsampled to the same sampling frequency as the actual power consumption data.

[0016] In some optional embodiments, the step of obtaining actual power consumption data in timing during the process of the FPGA chip running a preset encryption algorithm includes:

[0017] When the FPGA chip runs a preset encryption algorithm, the change of the combinational logic delay in the FPGA chip is obtained;

[0018] By changing the combinational logic delay in the FPGA chip, the change in the voltage drop of the FPGA chip is determined, and by the change in the voltage drop, the actual power consumption data of the FPGA chip is determined.

[0019] In some optional embodiments, generating a voltage drop in the FPGA chip to complete fault injection of the FPGA chip includes:

[0020] At the moment of fault injection, the operating voltage of each working circuit of the FPGA chip is reduced to below the preset operating voltage, and the delay of each working circuit is increased, so that each working circuit of the FPGA chip does not meet the preset timing, so as to complete the fault injection of the FPGA chip.

[0021] In some optional embodiments, the step of reducing the operating voltage of each working circuit of the FPGA chip to below a preset operating voltage includes:

[0022] The ring oscillator is used to reduce the operating voltage of each working circuit of the FPGA chip to below the preset operating voltage.

[0023] In some optional embodiments, there are multiple ring oscillators, and generating a voltage drop in the FPGA chip includes:

[0024] By adjusting the number of simultaneously enabled ring oscillators, the speed of the voltage drop, the holding time, and the range of the voltage drop can be adjusted.

[0025] An embodiment of the present invention further provides a fault injection system for an FPGA chip, comprising:

[0026] The first data acquisition module is used to acquire the actual power consumption data of the FPGA chip in timing when the FPGA chip runs a preset encryption algorithm;

[0027] The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing;

[0028] A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip;

[0029] The fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip.

[0030] An embodiment of the present invention also provides a computer device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned FPGA chip fault injection method.

[0031] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned fault injection method for the FPGA chip when executed by a processor.

[0032] The fault injection method of the FPGA chip provided by the present invention has at least the following beneficial effects:

[0033] By obtaining the actual power consumption data in the timing of the FPGA chip running the preset encryption algorithm, and simulating the process of the FPGA chip running the preset encryption algorithm, the simulated power consumption data of the FPGA chip in the timing is obtained, and the fault injection moment of the FPGA chip is determined by combining the actual power consumption data and the simulated power consumption data, that is, the data at the corresponding moment in the actual power consumption data and the simulated power consumption data are multiplied and accumulated respectively. If the value obtained by the multiplication and accumulation exceeds the preset threshold, it means that the actual power consumption data at this moment has the highest correlation with the simulated power consumption data, and the success rate of injecting faults at this time is the highest. Therefore, the present invention does not need to obtain any physical permissions of the FPGA chip (that is, it does not need to obtain the FPGA chip to give a trigger signal), but indirectly obtains the trigger signal by processing the power consumption information, so as to determine the fault injection moment of the FPGA chip, which has stronger concealment.

[0034] Furthermore, since all working circuits in the FPGA chip need to meet the setup time in terms of timing, the present invention generates a voltage drop in the FPGA chip at the time of fault injection, thereby reducing the working voltage of the circuit of the FPGA chip and making the circuit no longer meet the timing requirements for its normal operation, thereby completing the fault injection into the circuit (i.e., the FPGA chip).

[0035] Furthermore, this solution does not change the original circuit structure of the FPGA chip and is not easy to detect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] One or more embodiments are exemplarily described by the pictures in the corresponding drawings, and these exemplary descriptions do not constitute limitations on the embodiments.

[0037] Figure 1 A method for injecting faults into an FPGA chip according to an embodiment of the present invention is provided. Figure 1 ;

[0038] Figure 2 is a schematic diagram of a side information collection module provided according to an embodiment of the present invention;

[0039] Figure 3 is a waveform diagram of actual power consumption data provided according to an embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of power consumption data processing provided according to an embodiment of the present invention;

[0041] Figure 5 is a schematic diagram of a voltage drop provided according to an embodiment of the present invention;

[0042] Figure 6 A method for injecting faults into an FPGA chip according to an embodiment of the present invention is provided. Figure 2 . DETAILED DESCRIPTION

[0043] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are proposed in order to enable the reader to better understand the present invention. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present invention can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined and referenced with each other without contradiction.

[0044] An embodiment of the present invention relates to a fault injection method for an FPGA chip. The implementation details of the fault injection method for the FPGA chip of this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for implementing this solution.

[0045] The specific process of the fault injection method for the FPGA chip of this embodiment can be as follows: Figure 1 As shown, including:

[0046] Step 101, obtaining the actual power consumption data of the FPGA chip in timing when the FPGA chip runs a preset encryption algorithm.

[0047] Specifically, when the FPGA chip runs the preset encryption algorithm, the actual power consumption data in the timing can reveal the running status and operation mode of the FPGA chip. In a fault injection attack, the attacker may use the actual power consumption data in the timing to locate the attack time.

[0048] In the specific implementation, a side information collection module is deployed to collect the actual power consumption data inside the FPGA chip in real time. The side information collection module is composed of a hardware Trojan that can reflect power consumption leakage. The hardware Trojan can be used to obtain changes in the combinational logic delay in the FPGA chip. Through the changes in the combinational logic delay, the actual power consumption data of the FPGA chip can be obtained.

[0049] Among them, the working principle of the hardware Trojan is: in the hardware circuit, the power distribution network converts and distributes the power from the power supply to each circuit element. High switching activity often causes transient voltage drops in the power distribution network of the FPGA chip, so the voltage drop on the power distribution network reflects the power consumption. The voltage drop depends on the steady-state current consumption and the short transients caused by the switching logic of the chip on the FPGA. In a typical complementary metal oxide semiconductor (CMOS) circuit, the combinational logic delay can be modeled as inversely proportional to the voltage supplied to each gate. Therefore, the change in the combinational logic delay reflects the voltage drop, which in turn reflects the power consumption and switching activity of the circuit. This correlation between the combinational logic delay and power consumption can be used to build an on-chip power monitor on the FPGA chip. Build a circuit to measure the combinational path delay and use the delay to estimate the power consumption of other modules on the FPGA chip. For example, a voltmeter is built on the FPGA chip using a ring oscillator and a time-to-digital converter, where the design based on the ring oscillator is easier to implement and more universal, and the time-to-digital converter has an advantage in sampling resolution.

[0050] In one example, the design of the above-mentioned side information collection module is as follows: Figure 2 As shown, the whole is divided into four parts: delay chain, latch, counter and register. In the delay chain, the clock signal propagates through a series of buffers. Since the delay of these buffers depends on the supply voltage, the buffers can be monitored as a substitute for the supply voltage. The delay line is tapped by adding latches between these buffers. The latch is enabled with the same clock signal connected to the start of the delay line, so it can be shown how far the clock can propagate through the buffer in the time when the latch is enabled, that is, half a clock cycle. The tapped data outputs the number of 1s in the data chain after passing through a counter composed of combinational logic and is saved by the register. When any other circuit on the same PDN becomes active, power is consumed, causing the voltage to drop, slowing down the buffer of the delay line, resulting in a decrease in the value in the TDC output register. In order to save some area of ​​the sensor, usually only the last bit of the buffer chain is tapped, because the delay of the buffer will not change enough to affect the entire delay line. Therefore, only one part of the delay chain is observable, and the other part is the initial delay. In FPGA, the observable part is usually implemented using carry chain primitives, which provides the best resolution, while the initial delay is based on lookup tables (LUTs) and flip-flops with small area overhead but high latency. Finally, the power consumption waveform collected by the module can be as follows Figure 3 shown.

[0051] Step 102, simulating the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing.

[0052] In a specific implementation, the total clock consumed by the FPGA chip to run the preset encryption algorithm is obtained, and according to the preset ideal clock for injecting faults into the FPGA chip, all clocks before the ideal clock in the total clock are obtained as the target clock, and the process of the FPGA chip running the preset encryption algorithm is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock. For example, the total clock consumed by the FPGA chip to run the preset encryption algorithm is 4, and the preset ideal clock for injecting faults into the FPGA chip is the third clock. However, in actual operation, since it is unknown when the preset encryption algorithm starts to run, it is naturally unknown when the third clock of the preset encryption algorithm is, so all waveforms before the third clock are obtained in advance through simulation, that is, the simulated power consumption data of the FPGA chip within the target clock.

[0053] In one example, the simulated power consumption data of the FPGA chip within the target clock is obtained in the following manner: first, the simulation waveform of the FPGA chip running the preset encryption algorithm is obtained, and the (NM, N) time period is intercepted in the simulation waveform as the target time window, where N is the preset ideal time to inject a fault into the FPGA chip, and M is the length of the target time window. The larger M is, the more resources are consumed in the subsequent correlation coefficient calculation, and the accuracy of the subsequent Pearson correlation coefficient calculation is also higher, making it easier to obtain the correct fault injection time of the FPGA chip. Figure 4 As shown, (a) represents the waveform of the simulated power consumption data, (b) represents the waveform of the actual power consumption data, the dotted box portion is the waveform corresponding to the target time window, and (c) represents the waveform used to reflect the degree of correlation between the actual power consumption data at the corresponding moment and the simulated power consumption data when calculating the Pearson correlation coefficient between the simulated power consumption data corresponding to the target time window and the actual power consumption data at each moment.

[0054] Step 103, perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, respectively, and obtain the moments corresponding to the actual power consumption data and the simulated power consumption data when the values ​​obtained by the multiplication and accumulation operations exceed the preset threshold value as the fault injection moment of the FPGA chip.

[0055] Specifically, the time corresponding to the data whose correlation degree exceeds the preset threshold between the actual power consumption data and the above-mentioned simulated power consumption data is obtained, and multiplication and accumulation operations are performed on the actual power consumption data and the data at the corresponding time in the simulated power consumption data, respectively. This is equivalent to calculating the Pearson correlation coefficient between the simulated power consumption data corresponding to the target time window and the actual power consumption data at each moment. When the Pearson correlation coefficient exceeds the preset threshold, the moment corresponding to the simulated power consumption data and the actual power consumption data is the fault injection moment of the FPGA chip.

[0056] It is understandable that the accuracy level of the simulation in the simulation software used to simulate the FPGA chip running the preset encryption algorithm process can be determined according to the attacker's understanding of the FPGA chip. If the attacker knows the process of the FPGA chip in advance, the corresponding process library file can be selected to simulate it.

[0057] In one example, when simulating the process of running a preset encryption algorithm on an FPGA chip, the process of running the preset encryption algorithm on the FPGA chip within a target time window formed by all moments before an ideal moment can be simulated to directly obtain the simulated power consumption data corresponding to the above target time window.

[0058] In an example, before obtaining the moment corresponding to the data in the actual power consumption data and the simulated power consumption data whose correlation degree exceeds a preset threshold, it is first necessary to downsample the obtained simulated power consumption data of the FPGA chip in timing to a sampling frequency consistent with the actual power consumption data, and then store it in an on-chip register for subsequent calculations to ensure its accuracy.

[0059] In the specific implementation, a shift register is used to store the actual power consumption data in the most recent period. The depth of the shift register is equal to the length of the simulated power consumption data. At each new sampling moment, the actual power consumption data at the current moment is stored in the lowest bit of the shift register. At each moment, a Pearson correlation coefficient between the actual power consumption data and the simulated power consumption data is recalculated, and a reasonable threshold is set to determine whether the correlation value at that moment exceeds the threshold. If it exceeds the threshold, it means that this moment is the fault injection moment of the FPGA chip, and the fault injection trigger signal of one clock cycle is raised. If it does not exceed, wait for the next moment to update the actual power consumption data in the shift register.

[0060] Step 104 , at the time of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip.

[0061] Specifically, the hardware Trojan is composed of multiple ring oscillators, so it can generate a voltage drop in the FPGA chip through the ring oscillator at the time of fault injection. The speed, holding time and voltage drop range of the voltage drop are determined by the oscillation parameters of the ring oscillator, and the speed, holding time and voltage drop range of the generated voltage drop can be adjusted by changing the oscillation parameters of the ring oscillator. Among them, reducing the fan-out value of the enable signal can speed up the voltage drop speed, and increasing the number of ring oscillators can increase the voltage drop amplitude, but at the same time increase resource consumption, and the voltage drop holding time is controlled by the pull-up time of the enable signal.

[0062] In the specific implementation, when the trigger signal is pulled high, a single or multiple clock enable signal is generated according to the preset parameters. The enable signal drives the ring oscillator to perform a 0-1-0 conversion. If the voltage drop speed is accelerated, the enable signal is stored in N registers. In the next clock, each register drives M / N ROs, where M is the number of ring counters. The actual voltage drop is Figure 5 As shown, the voltage signal passes through a 30db amplifier, the number of ring counters is 10000, there is no fan-out reduction process, and the enable clock maintains one clock.

[0063] In one example, after completing the fault injection of the FPGA chip, the following method can be used to verify whether the fault injection of the FPGA chip is successful: assuming that the preset encryption algorithm is a digital signature verification algorithm, the digital signature verification algorithm is run in the FPGA chip, and the first hash value obtained by decrypting the digital signature of the digital signature verification algorithm and the original data of the digital signature verification algorithm, and the second hash value obtained by encrypting the hash algorithm are verified to be the same. If the first hash value is different from the second hash value, it is confirmed that the fault injection of the FPGA chip is successful, otherwise, the fault injection of the FPGA chip fails. At this time, the process of fault injection of the FPGA chip of this embodiment can be as follows: Figure 6 shown.

[0064] In this embodiment, by obtaining the actual power consumption data in the timing of the FPGA chip running the preset encryption algorithm, and simulating the process of the FPGA chip running the preset encryption algorithm, the simulated power consumption data of the FPGA chip in the timing is obtained, and the fault injection moment of the FPGA chip is determined by combining the actual power consumption data with the simulated power consumption data. The fault injection moment of the FPGA chip can be determined without obtaining any physical permissions of the FPGA chip. When the working voltage drops, the delay on the circuit will increase, which may cause the circuit to no longer meet the timing requirements. Therefore, for the FPGA chip, at the moment of fault injection, a voltage drop is generated in the FPGA chip, and the fault injection attack of the FPGA chip can be completed. In addition, this solution does not change the original circuit structure of the FPGA chip and is not easy to be detected.

[0065] The step division of the various methods above is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the protection scope of the present invention. Adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the protection scope of the invention.

[0066] Another embodiment of the present invention relates to a fault injection system for an FPGA chip. The implementation details of the fault injection system for the FPGA chip of this embodiment are specifically described below. The following content is only for the convenience of understanding the implementation details provided, and is not necessary for implementing this solution. The fault injection system for the FPGA chip of this embodiment includes:

[0067] The first data acquisition module is used to acquire the actual power consumption data of the FPGA chip in timing when the FPGA chip runs a preset encryption algorithm;

[0068] The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing;

[0069] A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip;

[0070] The fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip.

[0071] It is not difficult to find that this embodiment is a system embodiment corresponding to the above method embodiment, and this embodiment can be implemented in conjunction with the above method embodiment. The relevant technical details and technical effects mentioned in the above embodiment are still valid in this embodiment, and in order to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0072] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present invention, this embodiment does not introduce units that are not closely related to solving the technical problem proposed by the present invention, but this does not mean that there are no other units in this embodiment.

[0073] Another embodiment of the present invention relates to a computer device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the fault injection method of the FPGA chip in the above-mentioned embodiments.

[0074] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0075] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0076] Another embodiment of the present invention relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0077] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions for a device (which can be a single-chip microcomputer, chip, etc.) or a processor (processor) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as: ROM), random access memory (Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program codes.

[0078] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A fault injection method for an FPGA chip, characterized in that: The method comprises: Obtain the actual power consumption data of the FPGA chip in timing when the FPGA chip runs the preset encryption algorithm; The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip in timing; Perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, respectively, and obtain the moments corresponding to the actual power consumption data and the simulated power consumption data when the values ​​obtained by the multiplication and accumulation operations exceed a preset threshold value as the fault injection moment of the FPGA chip; At the moment of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip.

2. The fault injection method of the FPGA chip according to claim 1, characterized in that: The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip in timing, including: Get the total clock consumed by the FPGA chip to run the preset encryption algorithm; According to the preset ideal clock for injecting faults into the FPGA chip, all clocks before the ideal clock in the total clock are obtained as the target clock; The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock.

3. The fault injection method of the FPGA chip according to claim 2, characterized in that: Before performing multiplication and accumulation operations on the actual power consumption data and the data at corresponding moments in the simulated power consumption data, the method further includes: The simulated power consumption data is downsampled to the same sampling frequency as the actual power consumption data.

4. The fault injection method of the FPGA chip according to claim 1, characterized in that: The obtaining of actual power consumption data in timing during the process of the FPGA chip running the preset encryption algorithm includes: When the FPGA chip runs a preset encryption algorithm, the change of the combinational logic delay in the FPGA chip is obtained; By changing the combinational logic delay in the FPGA chip, the change in the voltage drop of the FPGA chip is determined, and by the change in the voltage drop, the actual power consumption data of the FPGA chip is determined.

5. The fault injection method of FPGA chip according to claim 1, characterized in that: The step of generating a voltage drop in the FPGA chip to complete the fault injection of the FPGA chip includes: At the moment of fault injection, the operating voltage of each working circuit of the FPGA chip is reduced to below the preset operating voltage, and the delay of each working circuit is increased, so that each working circuit of the FPGA chip does not meet the preset timing, so as to complete the fault injection of the FPGA chip.

6. The fault injection method of the FPGA chip according to claim 5, characterized in that: The step of reducing the operating voltage of each working circuit of the FPGA chip to below a preset operating voltage includes: The ring oscillator is used to reduce the operating voltage of each working circuit of the FPGA chip to below the preset operating voltage.

7. The fault injection method of the FPGA chip according to claim 6, characterized in that: There are multiple ring oscillators, and the voltage drop generated in the FPGA chip includes: By adjusting the number of simultaneously enabled ring oscillators, the speed of the voltage drop, the holding time, and the range of the voltage drop can be adjusted.

8. A fault injection system for an FPGA chip, characterized in that: The system comprises: The first data acquisition module is used to acquire the actual power consumption data of the FPGA chip in timing when the FPGA chip runs a preset encryption algorithm; The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing; A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip; The fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip.

9. A computer device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the fault injection method for the FPGA chip as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the fault injection method for an FPGA chip as described in any one of claims 1 to 7 is implemented.

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