Programmable memory and dynamic random access memory

Abstract

The invention provides a programmable memory and a dynamic random access memory. The programmable memory comprises a fuse array; the driving circuit at least comprises a plurality of first driving circuits; each first driving circuit is connected with one column selection transistor of the fuse array and is used for determining whether to provide driving voltage for the connected column selection transistor or not according to a column selection signal; the voltage adjusting circuit is connected with the driving circuit and is used for providing the adjusted working voltage for the driving circuit; the voltage regulation circuit comprises a plurality of output ports; the distances between the same first driving circuit and the plurality of output ports are different; and each first driving circuit in the plurality of first driving circuits is connected with the closest output port in the plurality of output ports.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a programmable memory and a dynamic random access memory. Background Art

[0002] Memory is an important component used to store data in various electronic devices. With the development of integrated circuit technology, the precision and complexity of memory are increasing. Various applications have also put forward higher and higher requirements on the reliability of memory to meet the needs of various application scenarios. Summary of the invention

[0003] In view of this, the main purpose of the present disclosure is to provide a programmable memory, a dynamic random access memory.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] The present disclosure provides a programmable memory, the programmable memory comprising:

[0006] Fuse array;

[0007] The driving circuit comprises at least a plurality of first driving circuits; each first driving circuit is connected to a column selection transistor of the fuse array and is used to determine whether to provide a driving voltage for the connected column selection transistor according to a column selection signal;

[0008] A voltage regulating circuit is connected to the driving circuit and is used to provide an adjusted working voltage for the driving circuit; the voltage regulating circuit includes multiple output ports; the same first driving circuit is at different distances from the multiple output ports; each of the multiple first driving circuits is connected to the output port that is closest to the multiple output ports.

[0009] In the above scheme, the working mode of the programmable memory includes a programming mode and a reading mode;

[0010] In the programming mode, the voltage adjustment circuit is specifically used to provide a first operating voltage for the driving circuit, and the driving circuit is specifically used to provide a first gate voltage for the column selection transistor to be selected under the first operating voltage, and the column selection transistor to be selected is turned on to a first degree;

[0011] In the read mode, the voltage adjustment circuit is specifically used to provide a second operating voltage to the driving circuit, and the driving circuit is specifically used to provide a second gate voltage to the column selection transistor to be selected under the second operating voltage, and the column selection transistor to be selected is turned on to a second degree;

[0012] The first operating voltage is greater than the second operating voltage, and the first level is greater than the second level.

[0013] The embodiment of the present disclosure also provides a dynamic random access memory, including the above-mentioned programmable memory.

[0014] An embodiment of the present disclosure provides a programmable memory, which includes: a fuse array; a driving circuit, including at least a plurality of first driving circuits; each of the first driving circuits is connected to a column selection transistor of the fuse array, and is used to determine whether to provide a driving voltage for the connected column selection transistor according to a column selection signal; a voltage adjustment circuit is connected to the driving circuit, and is used to provide an adjusted operating voltage to the driving circuit; the voltage adjustment circuit includes a plurality of output ports; the same first driving circuit is at different distances from the plurality of output ports; each of the plurality of first driving circuits is connected to an output port that is closest to the plurality of output ports.

[0015] In this way, by providing a one-to-one corresponding first driving circuit for the column selection transistors in the fuse array, the transmission path of the first driving circuit when providing the driving voltage to the corresponding column selection transistor is shortened, and the voltage loss caused by the resistance voltage drop effect can be reduced to ensure that the corresponding column selection transistor is fully turned on. At the same time, when the voltage adjustment circuit transmits the adjusted working voltage to the multiple first driving circuits through multiple output ports, the actual voltages received by the multiple first driving circuits are basically the same, so that when providing the driving voltage to the column selection transistors in the fuse array, the consistency of the opening degree of the column selection transistor can be ensured, so as to improve the reliability of the programmable memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of a fuse array in a programmable memory provided by an embodiment of the present disclosure;

[0017] Figure 2 A schematic diagram of the layout of a programmable memory provided by an embodiment of the present disclosure;

[0018] Figure 3 A schematic diagram of the connection relationship between a voltage adjustment circuit and a driving circuit provided in an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the structure of a voltage adjustment circuit provided in one embodiment of the present disclosure;

[0020] Figure 5 A schematic diagram of a layout of a programmable memory provided by another embodiment of the present disclosure;

[0021] Figure 6 A schematic diagram of the layout of a voltage adjustment circuit and a driving circuit provided in an embodiment of the present disclosure;

[0022] Figure 7A schematic diagram of the structure of a voltage adjustment circuit provided by another embodiment of the present disclosure;

[0023] Figure 8 A schematic diagram of the layout of a voltage adjustment circuit and a driving circuit provided in another embodiment of the present disclosure;

[0024] Fig. 9 A schematic diagram of a layout of a programmable memory provided in yet another embodiment of the present disclosure;

[0025] Fig.10 A schematic diagram of the layout of a programmable memory provided in accordance with yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0027] The present disclosure is described in more detail in the following paragraphs with reference to the accompanying drawings by way of example. The advantages and features of the present disclosure will become clearer from the following. It should be noted that the accompanying drawings are in a very simplified form and are not in exact proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0028] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0029] Programmable memory including fuse array has the characteristic that the storage state is not affected by power failure, and can be applied in various technical fields. For example, programmable memory is used in dynamic random access memory (DRAM) chips to store the address information of defective storage cells, thereby realizing redundant replacement; the programmable memory can also be programmed to realize precise adjustment of various parameters inside the chip (such as voltage, current and frequency).

[0030] Figure 1 A schematic diagram of the structure of a fuse array in a programmable memory provided by an embodiment of the present disclosure. Generally, the fuse storage units in the fuse array can be divided into two categories: anti-electrically programmable fuse (Anti-Efuse) storage units and electrical fuse (Efuse) storage units.

[0031] The gate oxide dielectric of the anti-fuse memory cell will break down after high voltage is applied, and the impedance of the path will decrease after the breakdown. The information stored in the anti-fuse memory cell can be read out by detecting the path resistance state after the breakdown. The initial resistance value of the electric fuse in the electric fuse memory cell is very small. When a large current passes through the electric fuse, the electric fuse is blown (programmed), and its resistance value doubles. The information stored in the electric fuse memory cell can be read out by detecting the path resistance state of the electric fuse memory cell.

[0032] It should be noted that Figure 1 The fuse storage unit in the fuse array is an anti-fuse storage unit as an example for explanation. However, based on the above principle, the electric fuse storage unit is still applicable. Figure 1 As shown, the fuse array 10 includes a plurality of bit lines BLn (n is the serial number of the corresponding bit line) arranged along the first direction and extending along the second direction, each bit line is connected to a plurality of anti-fuse storage units 101, and each bit line is connected to the first node N1 through a different column selection transistor 103, and the control end of the column selection transistor 103 receives a voltage signal Yn (Yn is the voltage signal received by the control end of the column selection transistor on the corresponding different bit lines).

[0033] In some embodiments, column select transistor 103 comprises an N-type transistor.

[0034] Each anti-fuse memory cell 101 includes an anti-fuse transistor 101-1 and a selection transistor 101-2. The selection transistor 101-2 is controlled by a word line WL_m (m is the number of the corresponding word line), and the anti-fuse transistor 101-1 is controlled by a programming line PGM_m (m is the number of the corresponding programming line). The first end of the anti-fuse transistor 101-1 is connected to the second end of the selection transistor 101-2, and the first end of the selection transistor 101-2 is connected to the bit line. Exemplarily, Figure 1 The fuse array is a 16*16 fuse array, that is, the fuse array includes 16 bit lines (BL) and 16 word lines (WL). Figure 1 In the illustrated embodiment, a total of 16 anti-fuse memory cells 101 are connected to each bit line.

[0035] In some embodiments, each bit line is connected to a precharge unit for providing a precharge voltage to the bit line in a programming mode to prevent unselected anti-fuse memory cells from being misprogrammed. The precharge unit includes a precharge switch 102, a first end of the precharge switch 102 is connected to the corresponding bit line, a second end of the precharge switch 102 is used to receive a precharge voltage VPRE, and a control end of the precharge switch 102 is used to receive a voltage signal Yn. It is understood that the voltage signal received by the column selection transistor 103 and the control end of the precharge switch 102 connected to the same bit line is the same.

[0036] The first terminal of the mode selection transistor 104 is grounded, the second terminal of the mode selection transistor 104 is connected to the first node N1, and the control terminal of the mode selection transistor 104 receives the working mode selection signal Z0. Figure 1 As shown, the working mode selection signal Z0 received by the control terminal of the mode selection transistor 104 is set to a high level, and the voltage signal Y0 received by the control terminal of the column selection transistor 103 corresponding to the bit line BL0 is set to a high level. In this way, the mode selection transistor 104 and the column selection transistor 103 are turned on, so that the programming path is opened. The word line WL_0 controls the selection transistor 101-2 to turn on, and a high voltage is applied to the control terminal of the target anti-fuse memory cell to be programmed to implement the programming operation of the anti-fuse memory cell. The programming current path of the target anti-fuse memory cell is shown as follows: Figure 1 As shown in path 1 ( Figure 1 It should be noted that, since the voltage signal Y0 received by the control terminal of the precharge switch 102 corresponding to the bit line BL0 is set to a high level before the programming operation, it is possible to prevent non-target anti-fuse memory cells from being misprogrammed.

[0037] Take the read mode as an example, Figure 1 As shown, the working mode selection signal Z0 received by the control end of the mode selection transistor 104 is set to a low level, and the voltage signal Y0 received by the control end of the column selection transistor 103 corresponding to the bit line BL0 is set to a high level. In this way, the mode selection transistor 104 is turned off, and the column selection transistor 103 is turned on, so that the read path is opened, and the word line WL_0 controls the selection transistor 101-2 to be turned on, and a read voltage is applied to the control end of the target anti-fuse storage unit to be read, and the voltage value at the first node N1 is compared with the reference voltage and the comparison result is output, which represents the 1-bit data stored in the target anti-fuse storage unit.

[0038] It is understandable that when programming or reading the target anti-fuse memory cell, the conduction of the relevant path is crucial. However, the voltage of the control end of the column selection transistor and the control end of the mode selection transistor usually comes from an external voltage such as a power supply voltage. The external voltage needs to pass through a certain distance of metal wiring to reach the control end of the column selection transistor and the mode selection transistor. However, if the metal wiring path is too long or the line width is insufficient, it will bring about a serious resistance drop (IR drop) effect, thereby slowing down the switching speed of the transistor or making the transistor not fully turned on, resulting in incomplete programming of the anti-fuse memory cell or inaccurate reading, etc., which has a great impact on the reliability of the entire programmable memory.

[0039] Therefore, how to improve the reliability of programmable memory has become a technical problem that needs to be solved urgently.

[0040] like Figure 2 As shown, an embodiment of the present disclosure provides a schematic diagram of the layout of a programmable memory. Figure 2 As shown, the programmable memory includes a fuse array 10, a drive circuit 20, a voltage adjustment circuit 30 and a logic control circuit 40. The specific structure of the fuse array 10 can be referred to Figure 1 Related description.

[0041] In some embodiments, Figure 2 As shown, the driving circuit 20 includes a plurality of first driving circuits 201, each of which is connected to a column selection transistor 103 of the fuse array 10, and is used to determine whether to provide a driving voltage for the connected column selection transistor 103 according to a column selection signal, and the driving voltage determines the voltage value of the voltage signal Y0-Y15 received by the control terminal of the column selection transistor 103. It should be noted that the column selection signal is a bit line selection signal, which is used to select a target bit line from a plurality of bit lines and turn on the column selection transistor connected to the target bit line.

[0042] The driving circuit 20 also includes a second driving circuit 202, which is connected to the mode selection transistor 104 and is used to provide a driving voltage to the mode selection transistor 104 in the programming mode. The driving voltage determines the voltage value of the working mode selection signal Z0 received by the control terminal of the mode selection transistor 104.

[0043] In some embodiments, the voltage adjustment circuit 30 is connected to the driving circuit 20 to provide the driving circuit 20 with an adjusted operating voltage to increase the driving voltage output by the driving circuit 20 in different operating modes, thereby improving the driving capability of the driving circuit 20 for the column selection transistor or the mode selection transistor, and alleviating the problem of slower transistor switching speed or insufficient transistor turn-on caused by the resistance voltage drop effect.

[0044] Specifically, Figure 3 As shown, each first driving circuit 201 is used to determine whether to provide a driving voltage for the connected column selection transistor 103 according to the column selection signal Yn CTRL. The second driving circuit 202 is used to determine whether to provide a driving voltage for the connected mode selection transistor 104 according to the mode selection signal Z0CTRL. It should be noted that Yn CTRL is a column selection signal received by the first driving circuit connected to the column selection transistor on different bit lines.

[0045] In some embodiments, if the gate thickness of the column selection transistor is less than or equal to the preset thickness, the voltage adjustment circuit includes a voltage adjustment circuit 30 including a low dropout regulator (LDO); if the gate thickness of the column selection transistor is greater than the preset thickness, the voltage adjustment circuit 30 includes a charge pump. The preset thickness is different in different products and process nodes.

[0046] In some embodiments, when the gate thickness of the column selection transistor is less than or equal to 2 nm, the voltage adjustment circuit 30 includes a low voltage drop linear voltage regulator circuit. The low voltage drop linear voltage regulator circuit has small output ripple and good stability, and can reduce the input voltage to adapt to the relatively thin gate thickness of the column selection transistor.

[0047] In some embodiments, when the gate thickness of the column selection transistor is greater than 4 nm, the voltage adjustment circuit 30 includes a charge pump. The charge pump has high efficiency and can quickly increase or decrease the input voltage.

[0048] Figure 4 FIG. 1 is a schematic diagram of a voltage adjustment circuit according to an embodiment of the present disclosure. Figure 4 As shown, the voltage adjustment circuit 30 includes: a comparator 301, a second transistor 302, a first variable resistor R1, and a second variable resistor R2. The inverting input terminal of the comparator 301 is connected to the reference voltage VREF, the non-inverting input terminal of the comparator 301 is connected to the second node N2, and the output terminal of the comparator 301 is connected to the third node N3. The second terminal of the second transistor 302 is connected to the power supply terminal V_in, the first terminal of the second transistor 302 is connected to the voltage output terminal V_out, and the control terminal of the second transistor 302 is connected to the third node N3. The first variable resistor R1 is connected between the first terminal of the second transistor 302 and the second node N2, and the second variable resistor R2 is connected between the second node N2 of the second transistor 302 and the ground terminal.

[0049] In the above voltage adjustment circuit, the comparator 301 amplifies the voltage difference between its non-inverting input terminal and its inverting input terminal and inputs it to the third node N3, and the third node N3 controls the second transistor 302 to output current, thereby providing the adjusted working voltage to the voltage output terminal V_out. In some embodiments, the second transistor 302 is a P-type transistor.

[0050] The voltage regulating circuit 30 may further include a capacitor C connected between the voltage output terminal V_out and the ground terminal. The capacitor C may make the output of the voltage regulating circuit 30 uniform, reduce the load requirement, and minimize the impedance.

[0051] The voltage adjustment circuit can provide an adjusted operating voltage to the driving circuit, so that the driving voltage provided by the driving circuit to the corresponding transistor can alleviate the problem of slow transistor switching speed or insufficient transistor opening caused by the resistance voltage drop effect.

[0052] In order to further shorten the distance between the voltage adjustment circuit and the second drive circuit and the plurality of first drive circuits in the drive circuit to alleviate the resistance voltage drop effect, and at the same time balance the magnitude of the actual voltage received by the second drive circuit and the plurality of first drive circuits from the output port of the voltage adjustment circuit, another embodiment of the present disclosure provides as follows Figure 5 The schematic diagram of the layout of the programmable memory is shown in FIG. Figure 5 As shown, the programmable memory includes: a fuse array 10; a driving circuit 20, including at least a plurality of first driving circuits 201; each first driving circuit 201 is connected to a column selection transistor 103 of the fuse array 10, and is used to determine whether to provide a driving voltage for the connected column selection transistor 103 according to a column selection signal; a voltage adjustment circuit 30, connected to the driving circuit 20, and is used to provide an adjusted working voltage for the driving circuit 20; the voltage adjustment circuit 30 includes a plurality of output ports; the same first driving circuit 201 is at different distances from the plurality of output ports; each of the plurality of first driving circuits 201 is connected to an output port that is closest to the plurality of output ports.

[0053] In some embodiments, each output port may correspond to a plurality of first driving circuits, that is, the number of output ports is less than the number of first driving circuits.

[0054] In some embodiments, each output port may also correspond to a first driving circuit one-to-one, that is, the number of output ports is the same as the number of first driving circuits.

[0055] For example, Figure 5As shown, the voltage adjustment circuit 30 includes four output ports, and the driving circuit 20 includes sixteen first driving circuits 201. The same output port is at different distances from the sixteen first driving circuits 201, and the same first driving circuit 201 is at different distances from the four output ports. Each of the multiple first driving circuits 201 is connected to the output port that is closest to the multiple output ports.

[0056] In some embodiments, Figure 5 As shown, the voltage regulating circuit 30 includes: a control subcircuit 310 and a plurality of driving subcircuits 320 , and the output ports of the plurality of driving subcircuits 320 serve as a plurality of output ports of the voltage regulating circuit 30 .

[0057] In this way, the distance at which the voltage adjustment circuit transmits the adjusted operating voltage to the multiple first drive circuits through the multiple output ports is basically the same, which can avoid the problem of inconsistent voltage loss caused by the large difference in distance from the voltage adjustment circuit, thereby ensuring that the actual voltages received by the multiple first drive circuits are basically the same, and can improve the reliability of programming and reading operations on the fuse storage unit.

[0058] In other embodiments, the voltage adjustment circuit 30 includes eight output ports, and the drive circuit 20 includes sixteen first drive circuits 201. Each output port is connected to two first drive circuits 201, and the two first drive circuits 201 are symmetrically arranged compared to the output port connected thereto, and illustratively, each output port is equidistant from the two first drive circuits 201 connected thereto. Preferably, the distance between any output port and the first drive circuit 201 connected thereto is equal to the distance between other output ports and the first drive circuit 201 connected thereto.

[0059] The same first driving circuit 201 has different distances from the eight output ports, and each of the multiple first driving circuits 201 is connected to the output port closest to the multiple output ports. In this way, the paths through which the voltage adjustment circuit transmits the adjusted working voltage to the multiple first driving circuits through the multiple output ports are equal, and the actual voltages received by the multiple first driving circuits are substantially the same, and the transmission paths are short, thereby reducing the resistance voltage drop effect and improving the reliability of performing programming and reading operations on the fuse storage unit.

[0060] In some embodiments, the driving circuit further includes a second driving circuit 202, and the second driving circuit 202 is connected to an output port closest to the plurality of output ports. Figure 5 As shown, the second driving circuit 202 is connected to the output port that is closest to the multiple output ports. In this way, the first driving circuit and the second driving circuit share the same output port to save circuit and layout area.

[0061] It should be noted that the number of output ports in the voltage adjustment circuit and the number of first drive circuits in the drive circuit shown in the embodiment of the present disclosure are only for illustration. In actual use, the number can be selected according to the number of fuse storage units in the fuse array. For example, if the fuse array is an 8*8 fuse array, the number of output ports is 4, and the number of first drive circuits is 8. Alternatively, the number of output ports is 8, and the number of first drive circuits is 8. The protection scope of the present disclosure should not be excessively limited here.

[0062] In some embodiments, the fuse array 10 includes a plurality of fuse storage units 101 arranged in rows and columns; the programmable memory also includes: a plurality of bit lines BLn, each bit line being connected to a fuse storage unit 101 located in the same column, each bit line being connected to a sensing node (first node N1) via a column selection transistor 103; the sensing node being connected to a ground voltage via a mode selection transistor 104.

[0063] It should be noted that Figure 5 The fuse array 10 shown is Figure 1 The fuse array shown differs in that Figure 5 The multiple bit lines of the fuse array 10 shown are arranged along the second direction and extend along the first direction. It can be understood that in the embodiment of the present disclosure, the row direction is the extension direction of the word line, and the column direction is the extension direction of the bit line. Figure 5 The column direction is the first direction, and the row direction is the second direction. For other specific structures, please refer to Figure 1 Related description.

[0064] In some embodiments, the operating mode of the programmable memory includes a programming mode and a reading mode; in the programming mode, the voltage adjustment circuit is specifically used to provide a first operating voltage to the driving circuit, and the driving circuit is specifically used to provide a first gate voltage to the column selection transistor to be selected at the first operating voltage, and the column selection transistor to be selected is turned on to a first degree; in the reading mode, the voltage adjustment circuit is specifically used to provide a second operating voltage to the driving circuit, and the driving circuit is specifically used to provide a second gate voltage to the column selection transistor to be selected at the second operating voltage, and the column selection transistor to be selected is turned on to a second degree; the first operating voltage is greater than the second operating voltage, and the first degree is greater than the second degree.

[0065] In some embodiments, the external power supply voltage received by the power supply terminal of the voltage adjustment circuit is in the range of 1.8V to 2.0V. In the programming mode, the driving circuit receives the first working voltage provided by the voltage adjustment circuit and provides a first gate voltage for the column selection transistor to be selected. Exemplarily, the first gate voltage is 1.5V, 1.6V or 1.7V. Under the action of the first gate voltage, the column transistor to be selected is turned on to a first degree, and the programming path is opened to realize programming of the target fuse storage unit.

[0066] In the read mode, the driving circuit receives the second operating voltage provided by the voltage adjustment circuit, and provides a second gate voltage for the column selection transistor to be selected. Exemplarily, the second gate voltage is 1.2 V or 1.3 V. Under the action of the second gate voltage, the column transistor to be selected is turned on to a second degree, which can ensure the reliability of the read operation of the fuse storage unit.

[0067] In the disclosed embodiment, the voltage adjustment circuit flexibly provides different operating voltages according to different operating modes of the programmable memory. In the programming mode, the column selection transistor corresponding to the target fuse storage fuse unit is fully turned on by using a larger first voltage, which can increase the voltage difference across the target fuse storage unit and improve the reliability of the programming operation on the fuse storage unit. At the same time, in the reading mode, no large current is generated, and the column selection transistor corresponding to the target fuse storage fuse unit is turned on by using a smaller second voltage, which can reduce power consumption and reduce the risk of column selection transistor breakdown.

[0068] In some embodiments, Figure 5 As shown, the voltage regulating circuit 30 includes: a control subcircuit 310 and a plurality of driving subcircuits 320, and the output ports of the plurality of driving subcircuits 320 serve as a plurality of output ports of the voltage regulating circuit 30; wherein,

[0069] The control subcircuit 310 is used to generate different operating voltages in different operating modes;

[0070] Each driving sub-circuit 320 is connected to the control sub-circuit 310 , and each driving sub-circuit 320 corresponds to at least one first driving circuit 201 , and is used to provide an operating voltage to the corresponding at least one first driving circuit 201 .

[0071] In some embodiments, the same control sub-circuit 310 controls multiple driving sub-circuits 320 .

[0072] In some embodiments, the plurality of control sub-circuits 310 respectively control the plurality of driving sub-circuits 320 . In order to save circuit area, the plurality of control sub-circuits 310 are integrated together.

[0073] In some embodiments, a plurality of first driving circuits 201 are correspondingly arranged at a plurality of positions in the first region; a plurality of driving sub-circuits 320 are arranged at a plurality of positions in the first region corresponding to the plurality of first driving circuits 201; a control sub-circuit 310 is arranged in the first region and the plurality of driving sub-circuits 320 are symmetrically arranged compared to the control sub-circuit 310. In this way, the plurality of driving sub-circuits are evenly arranged in a dispersed manner compared to the control sub-circuit, which is conducive to further reducing the difference between the operating voltages provided by the control sub-circuit to the first driving circuit via the driving sub-circuit.

[0074] In some embodiments, Figure 5 As shown, the fuse array 10 is arranged in the second area; the first area and the second area are arranged in parallel along the first direction; multiple first driving circuits 320 are arranged in parallel along the second direction; the first direction is perpendicular to the second direction; and multiple driving sub-circuits 320 are symmetrically arranged along the second direction compared to the control sub-circuit 310.

[0075] In some embodiments, the programmable memory also includes: a logic control circuit 40, the logic control circuit 40 is used to control the read and write operations of the fuse array 10, and the logic control circuit 40 can also be used to control the switching between different operating modes; the logic control circuit 40 is set in the third area; the first area is located between the second area and the third area.

[0076] Figure 6 FIG. 1 is a schematic diagram of the layout of a voltage adjustment circuit and a driving circuit provided in an embodiment of the present disclosure. Figure 6 As shown, multiple first driving circuits 201 in the driving circuit are correspondingly arranged at multiple positions in the first area; multiple driving sub-circuits 320 in the voltage adjustment circuit are arranged at multiple positions in the first area corresponding to the multiple first driving circuits 201, and the control sub-circuit 310 in the voltage adjustment circuit is arranged in the first area and the multiple driving sub-circuits 320 are symmetrically arranged compared to the control sub-circuit 310. The multiple first driving circuits 201 are symmetrically arranged compared to the driving sub-circuits 320 correspondingly connected thereto. The same control sub-circuit 310 controls the multiple driving sub-circuits 320. In this way, the multiple driving sub-circuits are evenly arranged in a dispersed manner compared to the control sub-circuit, which is conducive to further reducing the difference between the working voltages provided by the control sub-circuit to the first driving circuit via the driving sub-circuit. Figure 7 This is a schematic diagram of the structure of a voltage adjustment circuit provided by another embodiment of the present disclosure. Taking LDO as an example, Figure 7 As shown, the voltage adjustment circuit includes a control subcircuit 310 and a plurality of driving subcircuits 320 . Through layout design, the plurality of driving subcircuits 320 are symmetrically arranged along the second direction compared to the control subcircuit 310 .

[0077] The control subcircuit 310 includes a comparator, a first variable resistor R1 and a second variable resistor R2. The inverting input terminal of the comparator is connected to the reference voltage VREF, the non-inverting input terminal of the comparator is connected to the second node N2, and the output terminal of the comparator is connected to the third node N3.

[0078] The control terminals of all the driving sub-circuits 320 are connected to the third node N3, and the second terminals (output ports) of all the driving sub-circuits 320 are connected to the fourth node N4, which is connected to the voltage output terminal V_out. It can be understood that all the driving sub-circuits 320 are connected in parallel between the third node N3 and the fourth node N4.

[0079] In some embodiments, the first terminals of all driving sub-circuits 320 are connected to the power supply terminal V_in. In some embodiments, the voltage signals output by all power supply terminals V_in are the same. In other embodiments, according to the voltage requirements of different bit lines and different layout positions, the voltage amplitudes input from the power supply terminal V_in to each driving sub-circuit can be different to further balance the voltage losses caused by the paths at different positions.

[0080] In a specific embodiment, the number of the driving sub-circuits 320 is four.

[0081] In the above voltage adjustment circuit, the comparator amplifies the voltage difference between its non-inverting input terminal and its inverting input terminal and inputs it to the third node N3. The third node N3 controls the drive sub-circuit 320 to output current, thereby providing the adjusted working voltage to the voltage output terminal V_out. The output ports of the multiple drive sub-circuits 320 serve as the multiple output ports of the voltage adjustment circuit 30.

[0082] The voltage regulating circuit may further include a capacitor C, which is connected between the voltage output terminal V_out and the ground terminal. The capacitor C may make the output of the voltage regulating circuit 30 uniform, reduce the load requirement, and minimize the impedance.

[0083] In practical applications, a charge pump may be used as a voltage adjustment circuit as required to implement the layout of the control subcircuit and the drive subcircuit in the voltage adjustment circuit in the above embodiment.

[0084] Figure 8 FIG. 1 is a schematic diagram of the layout of a voltage adjustment circuit and a driving circuit provided by another embodiment of the present disclosure. Figure 8 As shown, the multiple control subcircuits 310 respectively control the multiple driving subcircuits 320, and each control subcircuit 310 correspondingly adjusts the magnitude of the adjusted working voltage output by the driving subcircuit 320. The multiple control subcircuits 310 are integrated together to save circuit area, and the driving subcircuits 320 corresponding to each control subcircuit 310 are evenly dispersed.

[0085] Fig. 9 A schematic diagram of the layout of a programmable memory provided by another embodiment of the present disclosure. Fig. 9 As shown, the programmable memory includes a fuse array. In some embodiments, the fuse array includes multiple fuse sub-arrays; the multiple fuse sub-arrays are respectively arranged in multiple second areas, and the multiple second areas are arranged at intervals along the second direction; the multiple first driving circuits 201 corresponding to each fuse sub-array are arranged in parallel along the first direction; the first direction is perpendicular to the second direction; the first area is located between two adjacent second areas.

[0086] Exemplarily, the fuse array includes a first fuse sub-array 10-1 and a second fuse sub-array 10-2, and the first fuse sub-array 10-1 and the second fuse sub-array 10-2 are respectively arranged in two second areas. A plurality of first drive circuits 201 in the drive circuit 20 corresponding to the first fuse sub-array 10-1 are arranged in parallel along the first direction, and a plurality of first drive circuits 201 in the drive circuit 20 corresponding to the second fuse sub-array 10-2 are arranged in parallel along the first direction. The specific structures of the first fuse sub-array 10-1 and the second fuse sub-array 10-2 can be referred to Figure 1 The relevant description of the fuse array 10 is shown.

[0087] In some embodiments, the programmable memory further includes a voltage adjustment circuit 30 , and a plurality of driving sub-circuits 320 in the voltage adjustment circuit 30 are symmetrically arranged along the first direction compared to the control sub-circuit 310 .

[0088] In some embodiments, the programmable memory further includes: a logic control circuit 40. The logic control circuit 40 is disposed in the third region; the third region is located on the same side of the first region and the plurality of second regions.

[0089] like Fig. 9 As shown, in some embodiments, the driving circuit further includes a second driving circuit 202, which is connected to the mode selection transistor and is used to provide a driving voltage to the mode selection transistor in the programming mode.

[0090] In other embodiments, in the read mode, the second driving circuit 202 can be turned on or off. Preferably, the second driving circuit 202 is used to stop providing a driving voltage to the mode selection transistor in the read mode to save power consumption.

[0091] In some embodiments, the voltage adjustment circuit includes: a first voltage adjustment circuit and a second voltage adjustment circuit; the first voltage adjustment circuit is used to provide an adjusted operating voltage to the first driving circuit; the second voltage adjustment circuit is used to provide an adjusted operating voltage to the second driving circuit.

[0092] In some embodiments, if the gate thickness of the column selection transistor is less than or equal to a preset thickness, the voltage adjustment circuit includes a low voltage drop linear regulator circuit; if the gate thickness of the column selection transistor is greater than the preset thickness, the voltage adjustment circuit includes a charge pump.

[0093] Fig.10 A schematic diagram of the layout of a programmable memory provided by another embodiment of the present disclosure. Fig.10 As shown, the multiple control subcircuits 310 respectively control the multiple driving subcircuits 320, and each control subcircuit 310 correspondingly adjusts the magnitude of the adjusted working voltage output by the driving subcircuit 320. The multiple control subcircuits 310 are integrated together to save circuit area, and the driving subcircuits 320 corresponding to each control subcircuit 310 are evenly dispersed.

[0094] The disclosed embodiment provides a one-to-one corresponding first driving circuit for the column selection transistors in the fuse array, thereby shortening the transmission path of the first driving circuit when providing the driving voltage to the corresponding column selection transistor, and can reduce the voltage loss caused by the resistance voltage drop effect to ensure that the corresponding column selection transistor is fully turned on. At the same time, when the voltage adjustment circuit transmits the adjusted working voltage to the multiple first driving circuits through multiple output ports, the actual voltages received by the multiple first driving circuits are basically the same, so that when providing the driving voltage to the column selection transistors in the fuse array, the consistency of the opening degree of the column selection transistors can be ensured, so as to improve the reliability of the programmable memory.

[0095] The embodiments of the present disclosure also provide a dynamic random access memory, including the programmable memory disclosed in the embodiments of the present disclosure. The dynamic random access memory is composed of a plurality of memory cells, each of which generally includes a transistor and a capacitor, and the word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor. The fuse data is stored in the memory to achieve redundant replacement or precise adjustment of various parameters (such as voltage, current and frequency) inside the dynamic random access memory.

[0096] It should be noted that the embodiments of the present disclosure are not limited to DRAM, but also include other memories including programmable memories, such as static random-access memory (SRAM), NAND memory, etc.

[0097] It should be understood that "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in some embodiments" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0098] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A programmable memory, characterized in that: The programmable memory comprises: Fuse array; The driving circuit comprises at least a plurality of first driving circuits; each of the first driving circuits is connected to a column selection transistor of the fuse array and is used to determine whether to provide a driving voltage for the connected column selection transistor according to a column selection signal; A voltage adjustment circuit is connected to the driving circuit and is used to provide an adjusted working voltage for the driving circuit; the voltage adjustment circuit includes multiple output ports; the same first driving circuit is at different distances from the multiple output ports; each of the multiple first driving circuits is connected to the output port that is closest to the multiple output ports.

2. The programmable memory according to claim 1, characterized in that: The working modes of the programmable memory include a programming mode and a reading mode; In the programming mode, the voltage adjustment circuit is specifically used to provide a first operating voltage for the driving circuit, and the driving circuit is specifically used to provide a first gate voltage for the column selection transistor to be selected under the first operating voltage, and the column selection transistor to be selected is turned on to a first degree; In the read mode, the voltage adjustment circuit is specifically used to provide a second operating voltage for the drive circuit, and the drive circuit is specifically used to provide a second gate voltage for the column selection transistor to be selected under the second operating voltage, and the column selection transistor to be selected is turned on to a second degree; The first operating voltage is greater than the second operating voltage, and the first level is greater than the second level.

3. The programmable memory according to claim 1, characterized in that: The voltage regulating circuit comprises: a control subcircuit and a plurality of driving subcircuits, wherein the output ports of the plurality of driving subcircuits serve as a plurality of output ports of the voltage regulating circuit; wherein, The control subcircuit is used to generate different operating voltages in different operating modes; Each of the driving sub-circuit is connected to the control sub-circuit, and each of the driving sub-circuit corresponds to at least one first driving circuit, and is used to provide the operating voltage to the corresponding at least one first driving circuit.

4. The programmable memory according to claim 3, characterized in that: The multiple first driving circuits are arranged at multiple positions in the first area; the multiple driving sub-circuits are arranged at multiple positions in the first area corresponding to the multiple first driving circuits, the control sub-circuit is arranged in the first area and the multiple driving sub-circuits are symmetrically arranged compared to the control sub-circuit.

5. The programmable memory according to claim 4, characterized in that: The fuse array is arranged in the second area; The first area and the second area are arranged side by side along a first direction; The plurality of first driving circuits are arranged in parallel along a second direction; the first direction is perpendicular to the second direction; The plurality of driving sub-circuits are symmetrically arranged along the second direction compared to the control sub-circuit.

6. The programmable memory according to claim 5, characterized in that: The programmable memory further comprises: a logic control circuit, the logic control circuit being used to control the read and write operations of the fuse array; The logic control circuit is arranged in the third area; and the first area is located between the second area and the third area.

7. The programmable memory according to claim 4, characterized in that: The fuse array includes a plurality of fuse sub-arrays; The plurality of fuse sub-arrays are respectively arranged in a plurality of second regions, and the plurality of second regions are arranged at intervals along a second direction; the plurality of first driving circuits corresponding to each of the fuse sub-arrays are arranged in parallel along a first direction; and the first direction is perpendicular to the second direction; The first area is located between two adjacent second areas; The plurality of driving sub-circuits are symmetrically arranged along the first direction compared to the control sub-circuit.

8. The programmable memory according to claim 1, characterized in that: The fuse array includes a plurality of fuse storage units arranged in row and column directions; The programmable memory further comprises: a plurality of bit lines, each of which is connected to the fuse storage unit in the same column, each of which is connected to a sensing node via a column selection transistor; and the sensing node is connected to a ground voltage via a mode selection transistor.

9. The programmable memory according to claim 8, characterized in that: The driving circuit further comprises a second driving circuit, the second driving circuit being connected to the mode selection transistor and being used for providing a driving voltage to the mode selection transistor in a programming mode; The voltage regulating circuit includes: a first voltage regulating circuit and a second voltage regulating circuit; the first voltage regulating circuit is used to provide an adjusted working voltage for the first driving circuit; the second voltage regulating circuit is used to provide an adjusted working voltage for the second driving circuit.

10. The programmable memory according to claim 1, characterized in that: If the gate thickness of the column selection transistor is less than or equal to a preset thickness, the voltage adjustment circuit includes a low voltage drop linear voltage regulator circuit; If the gate thickness of the column selection transistor is greater than a predetermined thickness, the voltage adjustment circuit includes a charge pump.

11. A dynamic random access memory, characterized in that: Comprising a programmable memory as claimed in any one of claims 1 to 10.

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