Preparation method of diode integrated chip, diode integrated chip and application

Abstract

The invention provides a preparation method of a diode integrated chip, the diode integrated chip and application. The method comprises the following steps: preparing materials including a ceramic tube shell, a diode bare chip and a molybdenum copper plate; carrying out plasma cleaning to remove surface pollutants and increase the surface roughness; a molybdenum copper plate is placed on the positive electrode welding island, and a diode bare chip is placed on the negative electrode welding island; fixing is carried out in an eutectic mode; performing plasma cleaning again; bonding the anodes of the diode bare chips and the molybdenum copper plates one by one by using gold wires; the opening of the cavity of the ceramic tube shell is sealed by a ceramic tube cap; filling an insulating medium into the closed cavity of the ceramic tube shell; and sealing a cap. According to the method, a plurality of PIN diode units can be integrated into a whole, the occupied space is optimized, devices in a chip can be well combined, and each PIN diode unit has good consistency parameter performance.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated chips, and more specifically, to a preparation method of a diode integrated chip, a diode integrated chip and applications. Background Art

[0002] At present, conventional frequency hopping filters use a large number of PIN diodes. Figure 1 For example: if it is a two-stage, ten-group PIN diode resonant capacitor array, the number of PIN diodes required is 20; if it is a three-stage, twelve-group PIN diode resonant capacitor array, the number of PIN diodes required is 36, and so on. For this reason, the number and size of PIN diodes have become the main limiting factors for the size of frequency hopping filter products.

[0003] Most of the old PIN diodes are square or cylindrical leadless metal ceramic tubes with hermetic packaging, which are widely used in surface mounting technology. Taking the MA-COM-1072 package as an example, the size of a single PIN diode is about 3.4mm×2.4mm×2.4mm. Considering the electrical clearance of welding and other assemblies, the space occupied by multiple PIN diodes arranged in parallel is often very large, especially the frequency hopping filter uses a large number of PIN diodes, which makes it difficult to reduce the size of the frequency hopping filter and other equipment systems. Due to the size limitations of the inherent packaging of the current PIN diode, it is difficult to achieve further miniaturization.

[0004] As electronic packaging technology gradually develops towards miniaturization and integration, more and more electronic systems have put forward the demand for miniaturization and lightweight. Therefore, it is urgent to improve the preparation method and structure of PIN diodes to meet the demand for miniaturization and lightweight of electronic equipment. Summary of the invention

[0005] In order to overcome the shortcomings and deficiencies in the prior art, the purpose of the present invention is to provide a method for preparing a diode integrated chip, a diode integrated chip and its application; this method can integrate multiple PIN diode units into one, optimize the occupied space, the internal devices of the chip can be well combined, and each PIN diode unit has good consistency parameter performance.

[0006] In order to achieve the above object, the present invention is implemented by the following technical solution: a method for preparing a diode integrated chip, comprising the following steps: S1. Prepare materials; the materials include: a ceramic tube shell, a diode bare chip and a molybdenum copper plate; the ceramic tube shell is provided with a cavity for arranging the diode bare chip and the molybdenum copper plate; a plurality of positive electrode welding islands matching the size of the molybdenum copper plate and a plurality of negative electrode welding islands matching the size of the diode bare chip and having the same number as the positive electrode welding island are provided on the wall of the ceramic tube shell cavity; the number of positive electrode welding islands and negative electrode welding islands is set according to the number of PIN diode units required to be integrated in the diode integrated chip; S2, plasma cleaning the ceramic tube shell, the diode bare chip and the molybdenum copper plate respectively to remove surface pollutants and increase surface roughness; S3, placing the molybdenum copper plate on the positive electrode welding island, placing the diode bare chip on the negative electrode welding island, and attaching the negative electrode of the diode bare chip to the negative electrode welding island; and fixing them by adopting a eutectic method; S4, using plasma cleaning to clean the diode bare chip and the surface of the molybdenum copper plate after eutectic treatment; S5, using two ends of the gold wire to bond the positive electrode of the diode bare chip and the molybdenum copper plate one-to-one to form each PIN diode unit; S6. Using a ceramic tube cap to seal the opening of the ceramic tube shell cavity; filling the sealed ceramic tube shell cavity with an insulating medium to improve insulation performance; S7. Use sealant to fix the ceramic tube cap to the ceramic tube shell to achieve capping.

[0007] Preferably, in step S2, plasma cleaning is performed using a plasma argon cleaning device; the process gas of the plasma argon cleaning device is argon, the vacuum degree is set to 30 Pa, and the power is 180 W; the plasma cleaning time is 300 s to 500 s.

[0008] Preferably, in step S3, the eutectic method refers to: using Au80Sn20 solder for manual eutectic or vacuum sintering furnace eutectic; the eutectic treatment reaches tin overflow around the edges of the diode bare chip and the molybdenum copper plate, and the distance from the overflow edge is ≤0.2mm; the Au80Sn20 solder stacking height is ≤2 / 3 of the height of the diode bare chip, and the void ratio is ≤5%.

[0009] Preferably, in step S5, an automatic bonding machine is used for bonding; the bonding pressure of the automatic bonding machine is set to 80 g, the welding ultrasound is set to 110 LSB, and the welding time is set to 90 ms.

[0010] Preferably, in step S6, filling with insulating medium refers to filling with inert gas or filling with insulating gel.

[0011] Preferably, all positive electrode welding islands are arranged in one row; all negative electrode welding islands are arranged in another row; each positive electrode welding island and each negative electrode welding island are positioned opposite to each other one by one. This arrangement enables the side-by-side modular arrangement of each PIN diode unit, thereby improving the consistency of the performance of each PIN diode unit.

[0012] Preferably, an electrical gap N is left between adjacent positive electrode welding islands and between adjacent negative electrode welding islands; an electrical gap M is left between opposite positive electrode welding islands and negative electrode welding islands; M≥0.4mm; N≥0.4mm. The electrical gaps set can meet the electrical performance and insulation performance.

[0013] Preferably, the diode bare chip refers to a high-voltage silicon PIN diode bare chip with a circular positive electrode, a square negative electrode, and a platform shape as a whole.

[0014] A diode integrated chip is manufactured using the method for manufacturing the diode integrated chip.

[0015] An application of the diode integrated chip is used in electronic equipment.

[0016] Compared with the prior art, the present invention has the following advantages and beneficial effects: 1. The method of the present invention can integrate multiple PIN diode units into one, and the internal devices can be well combined; each PIN diode unit has good consistency parameter performance; when applied to a circuit using multiple PIN diodes, the space size occupied by the PIN diode in the circuit can be greatly optimized, thereby helping to reduce the size and weight of the device; 2. The method of the present invention has the advantage of miniaturization of micro-assembly. The bonding gold wire is micron-level, short and thin. The end face of the diode bare chip does not need to be supported by a molybdenum copper cylinder to connect to the package electrode like the conventional PIN diode. Therefore, the distributed capacitance generated by the diode integrated chip made by the method of the present invention and the ceramic tube shell in the package is very small, thereby reducing the junction capacitance; 3. The diode integrated chip of the present invention is reflowed as a single integrated device, which takes less time and is more efficient than reflowing multiple independently packaged diodes; the present invention better meets the current market demand for miniaturization, lightweight and high efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of the method for preparing the diode integrated chip of the present invention; Figure 2 This is one of the structural schematic diagrams of a diode integrated chip made by the method for making a diode integrated chip of the present invention; Figure 3 This is the second structural schematic diagram of the diode integrated chip made by the method for making the diode integrated chip of the present invention; Figure 4 This is one of the internal structure schematic diagrams of a diode integrated chip made by the method for making a diode integrated chip of the present invention; Figure 5 This is the second schematic diagram of the internal structure of the diode integrated chip made by the method for making the diode integrated chip of the present invention; Figure 6 The diagram is a schematic diagram of the internal structure of another type of diode integrated chip manufactured by the method for manufacturing the diode integrated chip of the present invention.

[0018] Among them, 1 is a ceramic tube shell, 2 is a molybdenum copper plate, 3 is a diode bare chip, 4 is a gold wire, 5 is a ceramic tube cap, and 6 is a welding island. DETAILED DESCRIPTION

[0019] The present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0020] Example This embodiment provides a method for preparing a diode integrated chip, the process is as follows Figure 1 As shown, the following steps are included: S1. Prepare materials; the materials include: a ceramic tube shell 1, a diode bare chip 3 and a molybdenum copper plate 2; the ceramic tube shell 1 is provided with a cavity for arranging the diode bare chip 3 and the molybdenum copper plate 2.

[0021] The diode bare chip 3 refers to a high-voltage silicon PIN diode bare chip with a circular positive electrode, a square negative electrode, and a platform shape as a whole.

[0022] A plurality of welding islands 6 are arranged on the cavity wall of the ceramic tube shell 1; the welding islands 6 include positive electrode welding islands matching the size of the molybdenum copper plate 2, and negative electrode welding islands matching the size of the diode bare chip 3 and having the same number as the positive electrode welding islands; the molybdenum copper plate 2 has the same length and width as the diode bare chip 3; the number of positive electrode welding islands and negative electrode welding islands is set according to the number of PIN diode units integrated in the diode integrated chip. The preferred solution is: all positive electrode welding islands are arranged in one row; all negative electrode welding islands are arranged in another row; each positive electrode welding island and negative electrode welding island are respectively positioned one-to-one.

[0023] An electrical gap N is left between adjacent positive electrode welding islands and between adjacent negative electrode welding islands; an electrical gap M is left between the positive electrode welding island and the negative electrode welding island that are opposite to each other; M≥0.4mm; N≥0.4mm. The electrical gap set can meet the electrical performance and insulation performance.

[0024] S2, plasma cleaning the ceramic tube shell 1, the diode bare chip 3 and the molybdenum copper plate 2 respectively to remove surface pollutants and increase surface roughness.

[0025] Plasma cleaning is performed using plasma argon cleaning equipment; the process gas of the plasma argon cleaning equipment uses argon, the vacuum degree is set to 30Pa, and the power is 180W; the plasma cleaning time is 300s to 500s.

[0026] By utilizing the inert gas characteristics of argon, it will not chemically react with ceramic tube shells, diode bare chips, and molybdenum copper plates. It removes surface pollutants through physical bombardment, increases surface roughness, improves surface adhesion and wettability, and improves the bonding strength of subsequent welding processes.

[0027] S3, placing the molybdenum copper plate 2 on the positive electrode welding island, placing the diode bare chip 3 on the negative electrode welding island and attaching the negative electrode of the diode bare chip to the negative electrode welding island; and fixing them by adopting a eutectic method.

[0028] The eutectic method means: using Au80Sn20 solder for manual eutectic or vacuum sintering furnace eutectic; the eutectic treatment reaches tin overflow around the edges of the diode bare chip and the molybdenum copper plate, and the distance from the overflow edge is ≤0.2mm; the Au80Sn20 solder accumulation height is ≤2 / 3 of the height of the diode bare chip, and the void rate is ≤5%.

[0029] The manual eutectic temperature is 300℃, and the time is controlled within 10S. The eutectic curve for the vacuum sintering furnace can be set according to the recommended setting curve in the solder specification.

[0030] Use Au80Sn20 solder eutectic. Au80Sn20 solder has a melting point of 280°C and a thermal conductivity of 57W / mK. It has good wettability and oxidation resistance. The higher melting point makes it easier to use conventional solder in the subsequent process without causing tin melting inside the device.

[0031] S4. Use plasma cleaning to clean the diode bare chip and molybdenum copper plate surface after eutectic treatment; ensure that the bonding surface is clean.

[0032] S5. Use the two ends of the gold wire 4 to bond the positive electrode of the diode bare chip and the molybdenum copper plate one-to-one to form each PIN diode unit. The negative electrode welding island where the diode bare chip 3 is located forms the negative electrode, and the positive electrode welding island where the molybdenum copper plate 2 is located forms the positive electrode; check the bonding quality.

[0033] An automatic bonding machine is preferably used for bonding; the bonding pressure of the automatic bonding machine is set to 80 g, the welding ultrasound is set to 110 LSB, and the welding time is set to 90 ms.

[0034] Inspection of bonding quality includes: the shape of the solder joint after bonding is a flat oval, length: 1.5D≤L≤6D, width: 1.2D≤W≤2D (D is the diameter of the gold wire), the non-destructive test strength of 25μm gold wire is 0.03N, and the destructive test strength is ≥0.06N.

[0035] S6. Use the ceramic tube cap 5 to seal the opening of the cavity of the ceramic tube shell 1; and fill the sealed cavity of the ceramic tube shell 1 with an insulating medium to improve the insulation performance.

[0036] Filling with insulating medium means filling with inert gas or filling with insulating gel. After filling with insulating medium, refer to GJB548B method 1014.2 sealing, GJB360B method 107 temperature shock test air medium method condition B-3, GJB548B method 2001.1 constant acceleration test condition B, and require the leakage rate to be less than 5mPa.cm 3 .s -1 .

[0037] S7. Use sealant to fix the ceramic tube cap 5 and the ceramic tube shell 1 to achieve capping.

[0038] The diode integrated chip manufactured by the method for manufacturing the diode integrated chip of this embodiment has a structure as shown in FIG. Figures 2 to 5 As shown, it comprises a ceramic tube shell 1, a ceramic tube cap 5 and more than two PIN diode units. Each PIN diode unit comprises: a diode bare chip 3, a molybdenum copper plate 2 and a gold wire 4.

[0039] The ceramic tube shell 1 is provided with a cavity, and the ceramic tube cap 5 is provided at the opening of the cavity to achieve the closure of the cavity. The diode bare chip 3, the molybdenum copper plate 2 and the gold wire 4 are respectively located in the cavity. A plurality of welding islands 6 are provided on the cavity wall; the welding islands 6 include a positive electrode welding island whose size matches that of the molybdenum copper plate 2, and a negative electrode welding island whose size matches that of the diode bare chip 3 and whose number is the same as that of the positive electrode welding island. Figures 2 to 5 In the embodiment, the number of PIN diode units is five; in practical applications, the number of PIN diode units can also be two or three (e.g. Figure 6 shown), four, six, seven, or even more.

[0040] All positive electrode welding islands are arranged in one row; all negative electrode welding islands are arranged in another row; each positive electrode welding island and each negative electrode welding island are positioned opposite to each other one by one. The molybdenum copper plate 2 is arranged on the positive electrode welding island, and the diode bare chip 3 is arranged on the negative electrode welding island. The negative electrode of the diode bare chip 3 is attached to the negative electrode welding island; the positive electrode of the diode bare chip 3 is bonded to the molybdenum copper plate 2 through a gold wire. Using the molybdenum copper plate 2 as a packaging electrode can improve the heat dissipation effect.

[0041] The diode bare chip 3 may adopt an existing high-voltage silicon PIN diode bare chip, and the electrical parameters at room temperature are shown in Table 1.

[0042] Table 1 Electrical parameters of high voltage silicon PIN diode bare chip at room temperature The following is a comparison of the space occupied by a diode integrated chip with five PIN diode units in this embodiment and five independent PIN diodes of model MA4P506-1072T assembled side by side: In this embodiment, the following dimensions are taken as an example: the width of the molybdenum copper plate 2, the diode bare chip 3 and the welding island 6 is 0.7mm, the electrical gap N is 0.8mm, M is 1.2mm, the distance L between the outermost welding island and the edge is 0.5mm, and the welding island size is 0.7mm×0.9mm; the size of the diode integrated chip in this embodiment: length = 0.7×5+0.8×4+0.5×2=7.7mm, width = 0.9×2+1.2=3mm, height = 2.5mm.

[0043] The space occupied by five PIN diodes of model MA4P506-1072T assembled side by side is: the size of a single diode is 3.4mm×2.4mm×2.4mm, and the space occupied is calculated based on the electrical clearance of 0.8mm: length = (2.4×5+0.8×4) = 15.2mm, width 3.4mm, height 2.4mm. In comparison, the space occupied by the diode integrated chip in this embodiment is reduced by about 50%, which greatly optimizes the space occupied by the diode in the system.

[0044] The diode integrated chip made by the method of the present invention integrates multiple PIN diode units into one; when applied to a circuit using multiple PIN diodes, compared with independently packaged diodes, the present invention can greatly optimize the space size occupied by the diodes in the circuit, thereby facilitating the reduction of the volume and weight of the equipment; and the diode integrated chip of the present invention is reflow soldered as a single integrated device, which takes less time and is more efficient than reflow soldering multiple independently packaged diodes; the present invention better meets the current market demand for miniaturization, lightweight and high efficiency.

[0045] In addition, the diode integrated chip made by the method of the present invention utilizes the natural advantages of micro-assembly miniaturization, and the molybdenum copper sheet 2 is used as the packaging electrode, and is bonded to the positive electrode of the diode bare chip by gold wire; the bonded gold wire is micron-level, short and thin, and the end face of the diode bare chip does not need to be supported by a molybdenum copper cylinder to connect to the packaging electrode like a traditional conventional diode, so it can effectively reduce the influence of parameters such as distributed capacitance, so that the junction capacitance Ct of the PIN diode is very small compared with the junction capacitance Cj of the diode bare chip, and the requirements of low series resistance Rs and small junction capacitance Ct of the PIN diode are effectively met. The performance index comparison of the diode integrated chip made by the method of the present invention and the existing PIN diode model MA4P506-1072T is shown in Table 2.

[0046] Table 2 Comparison of performance parameters between the diode integrated chip of the present invention and MA4P506-1072T It can be seen from Table 2 that the diode integrated chip of the present invention can not only greatly optimize the space size occupied by the PIN diode in the circuit, but also effectively reduce the distributed capacitance generated by the PIN diode in the package and the ceramic tube shell, thereby reducing the junction capacitance.

[0047] This embodiment also provides an application of the above-mentioned diode integrated chip, which is used in electronic devices, such as frequency hopping filters, and can be used as a PIN diode in a PIN diode resonant capacitor array of a frequency hopping filter; in addition, it can also be applied to other electronic devices that use a large number of PIN diodes.

[0048] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. A method for preparing a diode integrated chip, characterized in that: The steps include: S1. Prepare materials; the materials include: a ceramic tube shell, a diode bare chip and a molybdenum copper plate; the ceramic tube shell is provided with a cavity for arranging the diode bare chip and the molybdenum copper plate; a plurality of positive electrode welding islands matching the size of the molybdenum copper plate and a plurality of negative electrode welding islands matching the size of the diode bare chip and having the same number as the positive electrode welding island are provided on the wall of the ceramic tube shell cavity; the number of positive electrode welding islands and negative electrode welding islands is set according to the number of PIN diode units required to be integrated in the diode integrated chip; S2, plasma cleaning the ceramic tube shell, the diode bare chip and the molybdenum copper plate respectively to remove surface pollutants and increase surface roughness; S3, placing the molybdenum copper plate on the positive electrode welding island, placing the diode bare chip on the negative electrode welding island, and attaching the negative electrode of the diode bare chip to the negative electrode welding island; and fixing them by adopting a eutectic method; S4, using plasma cleaning to clean the diode bare chip and the surface of the molybdenum copper plate after eutectic treatment; S5, using two ends of the gold wire to bond the positive electrode of the diode bare chip and the molybdenum copper plate one-to-one to form each PIN diode unit; S6. Using a ceramic tube cap to seal the opening of the ceramic tube shell cavity; filling the sealed ceramic tube shell cavity with an insulating medium to improve insulation performance; S7. Use sealant to fix the ceramic tube cap to the ceramic tube shell to achieve capping.

2. The method for preparing a diode integrated chip according to claim 1, characterized in that: In the step S2, plasma cleaning is performed using a plasma argon cleaning device; the process gas of the plasma argon cleaning device is argon, the vacuum degree is set to 30 Pa, and the power is 180 W; the plasma cleaning time is 300 s to 500 s.

3. The method for preparing a diode integrated chip according to claim 1, characterized in that: The step S3, using the eutectic method means: using Au80Sn20 solder for manual eutectic or vacuum sintering furnace eutectic; the eutectic treatment reaches tin overflow around the edges of the diode bare chip and the molybdenum copper plate, and the overflow edge distance is ≤0.2mm; the Au80Sn20 solder stacking height is ≤2 / 3 of the diode bare chip height, and the void ratio is ≤5%.

4. The method for preparing a diode integrated chip according to claim 1, characterized in that: In the step S5, an automatic bonding machine is used for bonding; the bonding pressure of the automatic bonding machine is set to 80 g, the welding ultrasound is set to 110 LSB, and the welding time is set to 90 ms.

5. The method for preparing a diode integrated chip according to claim 1, characterized in that: The step S6, filling with insulating medium refers to filling with inert gas or filling with insulating gel.

6. The method for preparing a diode integrated chip according to claim 1, characterized in that: All positive electrode welding islands are arranged in one row; all negative electrode welding islands are arranged in another row; and each positive electrode welding island and each negative electrode welding island are positioned opposite to each other one by one.

7. The method for preparing a diode integrated chip according to claim 6, characterized in that: An electrical gap N is left between adjacent positive electrode welding islands and between adjacent negative electrode welding islands; an electrical gap M is left between the positive electrode welding island and the negative electrode welding island that are opposite to each other; M≥0.4mm; N≥0.4mm.

8. The method for preparing a diode integrated chip according to claim 1, characterized in that: The diode bare chip refers to a high-voltage silicon PIN diode bare chip with a round positive pole, a square negative pole, and a platform shape as a whole.

9. A diode integrated chip, characterized in that: The diode integrated chip is manufactured using the method for manufacturing a diode integrated chip according to any one of claims 1 to 8.

10. An application of the diode integrated chip according to claim 9, characterized in that: Used in electronic equipment.

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