Chip packaging structure and method for manufacturing the same

Abstract

The chip packaging structure preparation method and the chip packaging structure provided by the embodiments of the present disclosure comprise: a first chip, a second protective layer, a second chip and a third protective layer which are sequentially stacked, and a first conductive connection structure, a second conductive connection structure and a polyimide layer; the second protective layer is located on the side of the first chip close to the second chip, the third protective layer is located on the side of the second chip away from the first chip, and the polyimide layer is formed on the side wall of the first chip; the first conductive connection structure is arranged in the first opening, the second chip is electrically connected with the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, part of the second conductive connection structure is exposed by the third protective layer, and the first chip outputs or receives an electrical signal through the second conductive connection structure. The overall volume of the chip packaging structure prepared and formed is smaller, and the integration degree is higher.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology and related technical fields, in particular, to a preparation method of a chip packaging structure and the chip packaging structure. BACKGROUND

[0002] Wafer Level Chip Scale Packaging (WLCSP), namely wafer level chip packaging, is a new technology that performs packaging and testing on a whole wafer first, and then cuts the wafer into individual IC particles, so that the volume of the packaged IC is equal to the original size of the IC wafer.

[0003] In the traditional CSP packaging, the original chip is only molded, and the electrical connection between the chip and the PCB is realized through the Bonding Pad, so that the integration degree is relatively low, and the overall volume of the prepared chip is large. In addition, since the prepared semiconductor chip is the original molded chip, the cutting path between two adjacent chips is wide, and the number of chips accommodated on a wafer is small. SUMMARY

[0004] The embodiments described herein provide a preparation method of a chip packaging structure and the chip packaging structure, which have a high integration degree.

[0005] In a first aspect, according to the content of the present disclosure, a preparation method of a chip packaging structure is provided, comprising:

[0006] forming a second protective layer on a wafer having a plurality of first chips, wherein the second protective layer comprises a first opening and a second opening;

[0007] forming a first conductive connection structure in the first opening of the second protective layer, and then flip-chip connecting a second chip with the first chip on the wafer through the first conductive connection structure;

[0008] forming a second conductive connection structure at the position of the second opening of the second protective layer;

[0009] forming a third protective layer on the side of the second conductive connection structure and the second chip away from the second protective layer;

[0010] cutting the wafer to form a cutting path at the position between two adjacent first chips on the side of the wafer away from the second protective layer, and spraying polyimide on the cutting path to form a polyimide layer on the surface of the cutting path;

[0011] processing the third protective layer so that part of the second conductive connection structure is exposed outside the third protective layer;

[0012] The positions of the cutting streets are cut again to obtain a plurality of separated chip packaging structures.

[0013] In some embodiments of the present disclosure, forming a second conductive connection structure at the second opening position of the second protective layer includes:

[0014] forming a mask layer on a side of the second protective layer away from the wafer, wherein the mask layer comprises a third opening, and a vertical projection of the third opening on the wafer covers a vertical projection of the second opening on the wafer;

[0015] After forming a second conductive connection structure at the second opening position of the second protection layer, the mask layer is removed.

[0016] In some embodiments of the present disclosure, the wafer is cut from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a scribe line, and polyimide is sprayed on the scribe line. Before the polyimide layer is formed on the surface of the scribe line, the method further includes:

[0017] performing a thinning process on the wafer at a side of the wafer away from the second protective layer;

[0018] A first protective layer is formed on a side of the wafer away from the second protective layer.

[0019] In some embodiments of the present disclosure, before forming the first protective layer on the side of the wafer away from the second protective layer, the method further includes:

[0020] A metal layer is formed on a side of the wafer away from the second protective layer.

[0021] In some embodiments of the present disclosure, the materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

[0022] In some embodiments of the present disclosure, before processing the third protective layer so that part of the second conductive connection structure is exposed outside the third protective layer, the method further includes:

[0023] Disposing a support layer on a side of the wafer away from the second protective layer;

[0024] After the positions of the cutting streets are cut again to obtain a plurality of separated chip packaging structures, the method further includes:

[0025] The prepared chip packaging structure is separated from the supporting layer.

[0026] In a second aspect, according to the present disclosure, a chip packaging structure is provided, comprising: a first chip, a second protective layer, a second chip and a third protective layer which are sequentially stacked, and a first conductive connection structure, a second conductive connection structure and a polyimide layer;

[0027] The second protective layer is located on the side of the first chip close to the second chip, the third protective layer is located on the side of the second chip away from the first chip, and the polyimide layer is formed on the side wall of the first chip.

[0028] The second protective layer comprises a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second chip is flip-chip connected with the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, part of the second conductive connection structure is exposed by the third protective layer, and the first chip outputs or receives an electrical signal through the second conductive connection structure.

[0029] In some embodiments of the present disclosure, the thickness of the third protective layer is H1, the thickness of the second chip is H2, and the thickness of the second conductive connection structure is H3, and H1, H2 and H3 satisfy: H2 < H1 < H3.

[0030] The thickness of the third protective layer satisfies:

[0031] In some embodiments of the present disclosure, a first protective layer and a metal layer are further included, the metal layer is located on the side of the first chip away from the second chip, and the first protective layer is located on the side of the metal layer away from the first chip.

[0032] In some embodiments of the present disclosure, the materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a tin ball.

[0033] The chip packaging structure provided by the embodiment of the present disclosure is prepared by the method, and the chip packaging structure prepared by the method comprises a first chip, a second protective layer, a second chip and a third protective layer which are sequentially stacked, and a first conductive connection structure, a second conductive connection structure and a polyimide layer. The second chip is electrically connected with an external PCB circuit board through the first conductive connection structure, the first chip and the second conductive connection structure, so as to realize output or reception of electrical signals. Compared with the prior art in which different functional modules of electrical signals are received or output by one chip, the integration of the chip packaging structure prepared by the embodiment of the present disclosure is higher. In addition, after the first protective layer and the first chip are cut to form a cutting channel, the polyimide layer is prepared on the surface of the cutting channel. Based on the properties of the polyimide layer material, the polyimide particles are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, in the process of preparing the cutting channel, the width of the cutting channel is relatively narrow. Compared with the prior art in which the cutting channel can only be formed by plastic packaging material in the process of preparing the chip packaging structure, since the plastic packaging material is an epoxy resin material, the particles of the epoxy resin material are generally large, and the thickness of the formed epoxy resin is relatively thick. Therefore, the width of the cutting channel is relatively wide. In the method for preparing the chip packaging structure provided by the embodiment of the present disclosure, the cutting channel between the two adjacent first chips is narrower. Therefore, the number of chips that can be accommodated on one wafer is more than that of the prior art.

[0034] The above description is only a summary of the technical solutions of the embodiments of the present application. In order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure. Among them:

[0036] Figure 1 is a structural schematic diagram of a chip packaging structure provided by the embodiment of the present disclosure;

[0037] Figure 2 is a structural schematic diagram of another chip packaging structure provided by the embodiment of the present disclosure;

[0038] Figure 3 is a flowchart of a method for preparing a chip packaging structure provided by the embodiment of the present disclosure;

[0039] Figures 4A-4K is a process schematic diagram of a method for preparing a chip packaging structure provided by the embodiment of the present disclosure;

[0040] Figures 5A-5D FIG. 8 is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present disclosure.

[0041] 10, a first protective layer; 20, a first chip; 21, a wafer; 30, a second protective layer; 40, a second chip; 50, a third protective layer; 60, a first conductive connection structure; 70, a second conductive connection structure; 31, a first opening; 32, a second opening; 80, a metal layer.

[0042] In the drawings, reference numbers of the last two digits that are the same, correspond to elements that are the same. It is to be noted that the elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0043] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort also belong to the scope of protection of the present disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present subject matter belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. As used herein, the statement that two or more parts are "connected" or "coupled" together refer to an indirect or direct connection or coupling.

[0045] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase "in an embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. A person of ordinary skill in the art will readily recognize from the disclosure herein, given the total volume of this application that one or more preceding and / or following embodiments can be combined, interchanged or removed.

[0046] The term "and / or" herein is merely used to describe associated objects, indicating that there can be three relationships, for example, A and / or B, which can represent three cases of existence of A, existence of A and B, and existence of B. In addition, the character " / " herein generally represents an "or" relationship between the front and rear associated objects.

[0047] In addition, in all embodiments of the present disclosure, terms such as "first" and "second" are only used to distinguish one component (or part of a component) from another component (or another part of a component).

[0048] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more (including two), and similarly, "a plurality of groups" means two or more groups (including two groups).

[0049] In order for those skilled in the art to better understand the scheme of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings.

[0050] Based on the problems existing in the prior art, the chip packaging structure provided by the embodiments of the present disclosure, Figure 1 is a structural schematic diagram of the chip packaging structure provided by the embodiments of the present disclosure, as Figure 1 shown, the chip packaging structure comprises: first chip 20, second protective layer 30, second chip 40 and third protective layer 50 which are sequentially stacked, and first conductive connection structure 60, second conductive connection structure 70 and polyimide layer 90; the second protective layer 30 is located on the side of the first chip 20 close to the second chip 40, the third protective layer 50 is located on the side of the second chip 40 away from the first chip 20, and the polyimide layer 90 is formed on the side wall of the first chip 20; the second protective layer 30 comprises a first opening 31 and a second opening 32, the first conductive connection structure 60 is arranged in the first opening 31, the second chip 40 is flip-chip connected with the first chip 20 through the first conductive connection structure 60, the second conductive connection structure 70 is arranged at the second opening 32, the third protective layer 50 exposes part of the second conductive connection structure 70, and the first chip 20 outputs or receives electrical signals through the second conductive connection structure 70.

[0051] In a specific embodiment, in combination with Figure 1 In the embodiments of the present disclosure, the chip packaging structure prepared comprises a first chip 20 and a second chip 40, wherein the first chip 20 is a WLCSP chip, the second chip 40 is a flip-chip, the second chip 40 is a master chip in the chip packaging structure provided by the embodiments of the present disclosure, the control logic of different functional modules in the first chip 20 is integrated on the second chip 40, the first chip 20 receives or outputs electrical signals through the second chip 40, specifically, the second chip realizes electrical connection with an external PCB circuit board through the first conductive connection structure, the first chip and the second conductive connection structure, realizes output or reception of electrical signals, compared with the prior art in which one chip realizes reception or output of electrical signals of different functional modules, the integration degree of the chip packaging structure provided by the embodiments of the present disclosure is higher.

[0052] In a specific embodiment, the chip packaging structure in the present disclosure is based on the specific structure of the chip packaging structure obtained in the preparation process, as shown in Figure 1 The chip packaging structure includes a first chip 20 and a second chip 40. The second chip 40 is flip-chip connected to the first chip 20 through a first conductive connection structure 60 of a first opening 31. The second chip 40 is smaller in volume than the first chip 20. The first chip 20 is electrically connected to an external PCB circuit board through a second conductive connection structure 70 of a second opening 32. The first chip 20 receives an electrical signal transmitted by the PCB circuit board through the second conductive connection structure 70 and sends the electrical signal to the second chip 40 through the first conductive connection structure 60. Alternatively, the second chip 40 outputs an electrical signal to the first chip 20 through the first conductive connection structure 60. The first chip 20 transmits the electrical signal output by the second chip 40 to the PCB circuit board through the second conductive connection structure 70.

[0053] In addition, in the process of preparing the chip packaging structure, after cutting the cutting position of the adjacent two chip packaging structures on one side of the first protective layer through a cutting process, a polyimide layer 90 is formed on the sidewall of the first chip 20 after cutting through a spraying process or the like. The sidewall of the first chip 20 after cutting is prevented from directly contacting the outside.

[0054] In a specific embodiment, the second protective layer 30 is located on the side of the first chip 20 close to the second chip 40. The second protective layer 30 serves as an insulating layer between the first chip 20 and the second chip 40.

[0055] In a specific embodiment, the third protective layer 50 is arranged on the side of the second chip 30 away from the first chip 20. On the one hand, the third protective layer 50 is a plastic package frame of the chip packaging structure. On the other hand, the third protective layer 50 can protect the second chip 40.

[0056] In a specific embodiment, the third protective layer 50 exposes part of the second conductive connection structure 70, thereby realizing electrical connection between the exposed part of the second conductive connection structure 70 and the external PCB circuit board.

[0057] The chip packaging structure provided by the embodiments of the present disclosure is characterized in that the first chip, the second protective layer, the second chip, and the third protective layer are sequentially stacked, and the first conductive connection structure and the second conductive connection structure are arranged. The second chip is electrically connected to the external PCB circuit board through the first conductive connection structure, the first chip, and the second conductive connection structure, thereby realizing the output or reception of electrical signals. Compared with the prior art in which a chip is used to realize the reception or output of electrical signals of different functional modules, the integration of the chip packaging structure prepared by the embodiments of the present disclosure is higher. In addition, after the first chip is cut to form a cutting channel, a polyimide layer is prepared on the side surface of the cutting channel. Based on the properties of the polyimide layer material, the polyimide particles are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, during the preparation of the cutting channel, the width of the cutting channel is relatively narrow. Compared with the prior art in which the cutting channel is formed of plastic packaging material during the preparation of the chip packaging structure, the cutting channel formed of the epoxy resin material has a relatively wide width because the epoxy resin material generally has relatively large particles and a relatively thick thickness. In the chip packaging structure provided by the embodiments of the present disclosure, the cutting channel between the two adjacent first chips is narrower, and therefore, the number of chips that can be accommodated on one chip is more than that in the prior art.

[0058] In a specific embodiment, the thickness of the third protective layer 50 is H1, the thickness of the second chip 40 is H2, and the thickness of the second conductive connection structure 70 is H3. H1, H2, and H3 satisfy: H2 < H1 < H3.

[0059] In combination with Figure 1 , if the thickness of the third protective layer 50 is H1, the thickness of the second chip 40 is H2, and the thickness of the second conductive connection structure 70 is H3, H1, H2, and H3 need to satisfy: H2 < H1 < H3. On the basis of ensuring that the third protective layer 50 protects the second chip, the third protective layer 50 exposes part of the second conductive connection structure 70, thereby facilitating the subsequent electrical connection between the first chip and the external PCB circuit board through the second conductive connection structure 70.

[0060] As a preferred embodiment, the thickness of the third protective layer 50 satisfies:

[0061] In a specific embodiment, after the second conductive connection structure 70 is prepared, the third protective layer 50 is first prepared on the side of the second chip 40 away from the first chip 20. The third protective layer 50 completely covers the second conductive connection structure 70 and the second chip 40. Then, the third protective layer 50 is treated by a chemical process, so that the third protective layer 50 exposes part of the second conductive connection structure 70 and covers the second chip 40.

[0062] In a specific embodiment, the third protective layer 50 is processed by a chemical process to expose part of the second conductive connection structure and cover the second chip, and the processing of the third protective layer is stopped when the third protective layer 50 is ground based on the chemical process to make the thickness of the remaining third protective layer greater than or equal to one-third of the thickness of the second conductive connection structure and less than or equal to one-half of the thickness of the second conductive connection structure.

[0063] In a specific embodiment, the second conductive connection structure 70 includes a spherical structure.

[0064] In a specific embodiment, the spherical second conductive connection structure 70 covers the vertical projection of the second opening 32 on the vertical projection of the first chip 20.

[0065] In a specific embodiment, the second conductive connection structure is a tin ball.

[0066] In a specific embodiment, after the second chip 40 is flipped onto the first chip 20, a mask plate is arranged to form the second conductive connection structure 70 at the position of the second opening 32, so that the second conductive connection structure 70 is electrically connected to the first chip 20 at the position of the second opening 32, and the thickness of the second conductive connection structure 70 needs to be greater than the thickness of the third protective layer 50 because the second conductive connection structure 70 serves as a transmission conductor for receiving or outputting electrical signals.

[0067] In a preferred embodiment, during the process of preparing the second conductive connection structure 70, a mask plate including a circular opening at the position of the second opening 32 is selected, so that the second conductive connection structure 70 formed at the position of the second opening 32 is spherical. After the second conductive connection structure 70 is formed and the mask plate is removed, the spherical second conductive connection structure 70 will undergo a certain reflow, thereby completely filling the second opening 32 and improving the electrical connection performance of the second conductive connection structure 70 and the first chip 20.

[0068] During the preparation of the spherical second conductive connection structure 70, the spherical second conductive connection structure 70 will undergo a certain reflow, so the circular opening included in the mask plate at the position of the second opening is selected to be larger than the second opening, that is, the vertical projection of the spherical second conductive connection structure 70 covers the vertical projection of the second opening 32 on the vertical projection of the first chip 20.

[0069] In a specific embodiment, the second chip is electrically connected to the first chip through the first conductive connection structure in the first opening, that is, the second chip and the first chip are electrically connected through a Bonding Pad, which is the first conductive connection structure.

[0070] On the basis of the above embodiments, Figure 2is a structural schematic diagram of another chip packaging structure provided by the embodiment of the disclosure, as shown in Figure 2 The chip packaging structure further includes a first protective layer 10 and a metal layer 80. The metal layer 80 is located on the side of the first chip 20 away from the second chip 40, and the first protective layer 10 is located on the side of the metal layer 80 away from the first chip 20.

[0071] Specifically, referring to Figure 2 By arranging the metal layer 80 between the first protective layer 10 and the first chip 20, the metal layer serves as a heat conduction layer to dissipate the heat generated by the first chip 20.

[0072] In addition, the first protective layer 10 is arranged on the side of the metal layer 80 away from the first chip 20. The first protective layer 10 is used to avoid the direct contact of the surface of the metal layer 80 with the outside, which may cause damage to the first chip 20.

[0073] In a specific embodiment, the first protective layer 10, the second protective layer 30, and the third protective layer 50 are all insulating materials. In addition, the first protective layer 10 serves as the packaging structure on the side of the first chip 20 away from the second chip 40, and the third protective layer 50 serves as the packaging structure on the side of the second chip 40 away from the first chip 20.

[0074] It should be noted that in the above embodiment, the material of the first protective layer and the third protective layer has larger particles and higher hardness than the material of the second protective layer.

[0075] Further, in the above embodiment, the material of the first protective layer and the third protective layer is epoxy resin, and the material of the second protective layer is polyimide.

[0076] On the basis of the above embodiment, the embodiment of the disclosure further provides a preparation method of a chip packaging structure, Figure 3 is a flowchart of the preparation method of the chip packaging structure provided by the embodiment of the disclosure, Figures 4A-4I The process for preparing the chip packaging structure provided by the embodiment of the disclosure combines Figure 3 and Figures 4A-4I The preparation method of the chip packaging structure includes the following steps.

[0077] S110, a second protective layer is prepared on a wafer with a plurality of first chips.

[0078] The second protective layer includes a first opening and a second opening.

[0079] In a specific embodiment, the preparation method of the chip packaging structure combines Figure 4AFirst, a second protective layer 30 is prepared on a wafer 21 having a plurality of first chips 20, and then a first opening 31 and a second opening 32 are prepared on the second protective layer 30 by a mask process or the like, wherein the first opening 31 is located at a position where the first chip 20 and the second chip 40 are electrically connected through a bonding pad, and the second opening 32 is located at a position where the first chip 20 and an external PCB circuit board are electrically connected.

[0080] S120, after forming the first conductive connection structure in the first opening of the second protective layer, flip-chip connecting the second chip and the first chip on the wafer through the first conductive connection structure.

[0081] After forming the first opening 31 and the second opening 32 on the second protective layer 30, as shown in Figure 4B , a second metal layer 301 (the material of the second metal layer is copper) is first formed on the second protective layer 30, and the second metal layer 301 includes an opening at the position corresponding to the first opening 31, and then tin paste is brushed at the position corresponding to the first opening, as shown in Figure 4C , to realize the preparation of the first conductive connection structure 60 in the first opening 31, and then the second metal layer 301 is removed, as shown in Figure 4D .

[0082] After forming the first conductive connection structure 60 in the first opening 31, the second chip 40 is flip-chip connected at the first conductive connection structure 60, as shown in Figure 4E .

[0083] S130, forming a second conductive connection structure at the position of the second opening of the second protective layer.

[0084] In a specific embodiment, forming the second conductive connection structure at the position of the second opening of the second protective layer includes: preparing a mask layer on the side of the second protective layer away from the wafer, wherein the mask layer includes a third opening, and the vertical projection of the third opening on the wafer covers the vertical projection of the second opening on the wafer; after forming the second conductive connection structure at the position of the second opening of the second protective layer, removing the mask layer.

[0085] Specifically, as shown in Figure 4F , the mask layer prepared on the side of the second protective layer 30 away from the wafer 21 can be a ball leakage net made of a metal material, and after the ball leakage net is prepared, a spherical second conductive connection structure 70 is formed at the opening of the ball leakage net, and then the ball leakage net is removed. After removing the ball leakage net, the spherical second conductive connection structure 70 will undergo a certain reflow, thereby completely filling the second opening 32 and improving the conductive connection performance of the second conductive connection structure 70 and the first chip 20, as shown in Figure 4J .

[0086] S140, forming a third protective layer on the side of the second conductive connection structure and the second chip away from the second protective layer.

[0087] After the second conductive connection structure 70 is prepared, the third protective layer 50 is prepared, as shown in Figure 4H , the third protective layer 50 formed completely covers the second conductive connection structure 70 and the second chip 40.

[0088] S150, from the side of the wafer away from the second protective layer, cutting the wafer to form a cutting path at the position between the two adjacent first chips, and spraying polyimide on the cutting path to form a polyimide layer on the surface of the cutting path.

[0089] After the structure shown in Figure 4H is prepared, the wafer is first flipped by a flipping process, that is, the side of the first chip away from the second chip is upward, and then the wafer 21 is cut to form a cutting path between the two adjacent first chips by a cutting process, and a polyimide layer is formed on the surface of the cutting path by a spraying process, as shown in Figure 4I .

[0090] Specifically, in the process of cutting the wafer to form a cutting path at the position between the two adjacent first chips, the wafer is cut by a laser cutting process.

[0091] S160, processing the third protective layer so that part of the second conductive connection structure is exposed outside the third protective layer.

[0092] After the structure shown in Figure 4I is prepared, the wafer is again flipped by a flipping process, that is, the side of the third protective layer is upward, and since the second conductive connection structure is electrically connected to the external PCB circuit board, the third protective layer 50 can be processed by a chemical grinding process so that part of the second conductive connection structure 70 is exposed, as shown in Figure 4G , realizing that the chip packaging structure prepared is electrically connected to the external PCB circuit board through the second conductive connection structure 70.

[0093] S170, re-cutting the position of the cutting path to obtain a plurality of separated chip packaging structures.

[0094] Finally, the wafer is re-cut at the cutting path position between the two adjacent first chips on the side of the third protective layer 50 away from the second protective layer 30 to obtain a plurality of separated chip packaging structures, as shown in Figure 4K .

[0095] In a specific embodiment, the position of the cutting groove is further cut at a position between two adjacent first chips on a side of the third protective layer away from the second protective layer, and the position of the cutting groove is further cut by a physical cutting process. After the position of the cutting groove is further cut, the entire second chip is cleaned by a cleaning process to obtain a chip packaging structure.

[0096] It should be noted that in the above embodiment, during the process of cutting the wafer to form a cutting groove at a position between two adjacent first chips on a side of the wafer away from the second protective layer, the second protective layer will be cut based on the laser cutting process, but during the process of forming a polyimide layer on the surface of the cutting groove (the polyimide layer formed is the same material as the second protective layer), a polyimide layer will also be formed on the second protective layer in the cutting groove. Therefore, when the position of the cutting groove is further cut to obtain a plurality of separated chip packaging structures, the third protective layer and the polyimide layer need to be cut again.

[0097] The chip packaging structure provided by the method for preparing a chip packaging structure provided by the embodiments of the present disclosure includes a first chip, a second protective layer, a second chip, and a third protective layer, which are sequentially stacked, as well as a first conductive connection structure, a second conductive connection structure, and a polyimide layer. The second chip is electrically connected to an external PCB circuit board through the first conductive connection structure, the first chip, and the second conductive connection structure to realize the output or reception of electrical signals. Compared with the prior art, in which a chip is used to realize the reception or output of electrical signals of different functional modules, the integration of the chip packaging structure prepared by the embodiments of the present disclosure is higher. In addition, after the first chip is cut to form a cutting groove, a polyimide layer is prepared on the surface of the cutting groove. Based on the properties of the polyimide layer material, the polyimide particles are relatively small, and the thickness of the prepared polyimide layer is relatively thin. Therefore, during the preparation of the cutting groove, the width of the cutting groove is relatively narrow. Compared with the prior art, in which a cutting groove is formed by a plastic packaging material during the preparation of a chip packaging structure, the cutting groove formed by the plastic packaging material is relatively wide due to the relatively large particles and the relatively thick thickness of the epoxy resin material. In the method for preparing a chip packaging structure provided by the embodiments of the present disclosure, the cutting groove between two adjacent first chips is narrower, and therefore, the number of chips that can be accommodated on a single chip is more than that in the prior art.

[0098] On the basis of the above embodiment, before step S150 is performed, the wafer is thinned on a side of the wafer away from the second protective layer, and a first protective layer is prepared on a side of the wafer away from the second protective layer.

[0099] Specifically, first, the wafer 21 is thinned on the side far from the second protective layer 30, so as to reduce the overall volume of the chip packaging structure finally manufactured, and then a first protective layer 10 is prepared to protect the wafer 21, so as to avoid scratching the wafer 21, as shown in Figure 5A At this time, in the process of performing step S150, the first protective layer and the wafer are cut to form a cutting path at the position between the two adjacent first chips on the side of the wafer far from the second protective layer, and polyimide is sprayed on the cutting path to form a polyimide layer on the surface of the cutting path.

[0100] In addition, in the above embodiment, before the first protective layer is prepared on the side of the wafer far from the second protective layer, it further includes: preparing a metal layer on the side of the wafer far from the second protective layer.

[0101] The metal layer 80 is prepared on the side of the wafer 21 far from the second protective layer 30, and the metal layer 80 serves as a heat dissipation layer of the chip packaging structure, as shown in Figure 5B and 5C After the metal layer is prepared, steps S150-S170 are performed, at this time, in the process of performing step S150, the first protective layer, the metal layer and the wafer are cut to form a cutting path at the position between the two adjacent first chips on the side of the wafer far from the second protective layer, and polyimide is sprayed on the cutting path to form a polyimide layer on the surface of the cutting path.

[0102] Through the above steps, the chip packaging structure formed is a six-surface WLCSP chip packaging structure.

[0103] On the basis of the above embodiment, before step S160 is performed, it further includes: preparing a support layer on the side of the wafer far from the second protective layer.

[0104] After the wafer is cut to form a cutting path at the position between the two adjacent first chips on the side of the wafer far from the second protective layer, and polyimide is sprayed on the cutting path to form a polyimide layer on the surface of the cutting path, first, a support layer 90 is prepared on the side of the wafer 21 far from the second protective layer 30, the support layer 90 is transparent glue, and the support layer 90 is bonded with the first chip in the uncut part, so as to avoid deformation of the chip packaging structure to be cut, as shown in Figure 5D After the support layer 90 is prepared, steps S160-S170 are performed.

[0105] Specifically, the material of the support layer is a high-molecular synthetic material.

[0106] In a specific embodiment, when the support layer is prepared on the side of the wafer away from the second protective layer before step S160 is performed, the prepared chip package structure is separated from the support layer after step S170 is performed.

[0107] Specifically, the chip package structure formed by cutting is sucked from the support layer by the suction nozzle to obtain the final chip package structure.

[0108] On the basis of the above-mentioned embodiments, an electronic device is also provided by the embodiments of the present disclosure. The electronic device includes the chip package structure according to the embodiments of the present disclosure. The electronic device is, for example, an automotive electronic product or a smart terminal device, such as a tablet computer, a smart phone, and the like.

[0109] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0110] It should be understood that all statements herein reciting "one embodiment" or "an embodiment", that a certain feature, structure, or characteristic being "included in" an embodiment, that a certain feature, structure, or characteristic "being" an embodiment, and the like, are intended to mean that the feature, structure, or characteristic is included in at least one embodiment of the present application. Therefore, these phrases or similar phrases in various places throughout the specification are not necessarily referring to the same embodiment. Further, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the steps / processes recited in various embodiments of the present application does not mean that the execution order is prior or posterior, and the execution order of the steps / processes should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. Moreover, the sequence number of the above-mentioned embodiments of the present application is only for description, not representing the advantages or disadvantages of the embodiments.

[0111] It should be noted that the terms "first", "second", and the like used in the specification and claims of the present application and the above-described drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a prior or posterior sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product, or device including a series of steps or units does not necessarily limit to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0112] The above only is the preferred embodiment of the present disclosure, and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure can have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a chip packaging structure, characterized in that: include: Forming a second protective layer on a wafer having a plurality of first chips, wherein the second protective layer includes a first opening and a second opening; After forming a first conductive connection structure in the first opening of the second protective layer, flip-chip connecting the second chip to the first chip on the wafer through the first conductive connection structure; forming a second conductive connection structure at a second opening position of the second protective layer; forming a third protective layer on a side of the second conductive connection structure and the second chip away from the second protective layer; Cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a dicing street, and spraying polyimide on the dicing street to form a polyimide layer on a surface of the dicing street; Processing the third protective layer so that a portion of the second conductive connection structure is exposed outside the third protective layer; The positions of the cutting streets are cut again to obtain a plurality of separated chip packaging structures.

2. The method according to claim 1, characterized in that The forming of a second conductive connection structure at the second opening position of the second protective layer includes: forming a mask layer on a side of the second protective layer away from the wafer, wherein the mask layer comprises a third opening, and a vertical projection of the third opening on the wafer covers a vertical projection of the second opening on the wafer; After forming a second conductive connection structure at the second opening position of the second protection layer, the mask layer is removed.

3. The method according to claim 1, characterized in that Cutting the wafer from a side of the wafer away from the second protective layer at a position between two adjacent first chips to form a dicing street, and spraying polyimide on the dicing street. Before forming the polyimide layer on the surface of the dicing street, the method further includes: performing a thinning process on the wafer at a side of the wafer away from the second protective layer; A first protective layer is formed on a side of the wafer away from the second protective layer.

4. The method according to claim 3, characterized in that Before forming the first protective layer on the side of the wafer away from the second protective layer, the method further includes: A metal layer is formed on a side of the wafer away from the second protective layer.

5. The method according to claim 3, characterized in that The materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

6. The method according to claim 1, characterized in that Before processing the third protective layer so that a portion of the second conductive connection structure is exposed outside the third protective layer, the method further includes: Disposing a support layer on a side of the wafer away from the second protective layer; After the positions of the cutting streets are cut again to obtain a plurality of separated chip packaging structures, the method further includes: The prepared chip packaging structure is separated from the supporting layer.

7. A chip packaging structure, characterized in that: include: A first chip, a second protective layer, a second chip, a third protective layer, a first conductive connection structure, a second conductive connection structure, and a polyimide layer are sequentially stacked; The second protective layer is located on a side of the first chip close to the second chip, the third protective layer is located on a side of the second chip away from the first chip, and the polyimide layer is formed on a sidewall of the first chip; The second protective layer includes a first opening and a second opening, the first conductive connection structure is arranged in the first opening, the second chip is flip-chip connected to the first chip through the first conductive connection structure, the second conductive connection structure is arranged at the second opening, the third protective layer exposes part of the second conductive connection structure, and the first chip outputs or receives electrical signals through the second conductive connection structure.

8. The chip packaging structure according to claim 7, wherein: The thickness of the third protective layer is H1, the thickness of the second chip is H2, and the thickness of the second conductive connection structure is H3. Then H1, H2 and H3 satisfy: H2 <H1<H3; The thickness of the third protective layer satisfies:

9. The chip packaging structure according to claim 7, wherein: It also includes a first protective layer and a metal layer. The metal layer is located on a side of the first chip away from the second chip, and the first protective layer is located on a side of the metal layer away from the first chip.

10. The chip packaging structure according to claim 9, wherein: The materials of the first protective layer and the third protective layer are epoxy resin, the material of the second protective layer is polyimide, and the second conductive connection structure is a solder ball.

Images