Surge and static dual protection circuit and dynamic power supply clamping circuit

Abstract

The invention relates to a surge and static dual protection circuit and a dynamic power supply clamping circuit, and designs the surge and static dual protection circuit which comprises a surge detection branch circuit, a static detection branch circuit, a discharge control branch circuit and a current discharge branch circuit which are arranged between a power supply and the ground. According to the invention, before the surge voltage rises to the reverse conduction threshold voltage of the transient voltage suppression diode, intervention is carried out in advance through the electrostatic detection branch circuit, so that the circuit is protected from being damaged; and meanwhile, an MOS transistor is added to the electrostatic detection branch, so that the discharge time of electrostatic impact current is prolonged, and the requirements of the protection circuit for quick response to electrostatic impact and full discharge are met.

Description

Technical Field

[0001] The invention belongs to the field of circuit design, and in particular relates to a surge and static electricity dual protection circuit and a dynamic power clamp circuit. Background Art

[0002] Surge and static electricity can cause irreversible damage to integrated circuits. Surge shock or static electricity shock may occur during the production, manufacturing, development and use, such as when switching power states, plugging and unplugging chips, or human contact, manufacturing and transportation, etc. With the continuous improvement of semiconductor technology, the size of transistors is being made smaller and smaller to integrate more transistors per unit area, but their voltage resistance is also getting lower and lower, so surge and static electricity protection circuits play a very critical role in chips.

[0003] Traditional surge protection circuits use a transient voltage suppression diode that is reversely connected between the power supply and the ground as a means of discharging surge current. When the surge voltage reaches the threshold of the transient voltage suppression diode's reverse conduction, it conducts to discharge the surge current. Since the surge voltage rise time is relatively long, generally in the microsecond range, and to avoid false triggering of power supply noise, its threshold is usually set high. If a surge occurs on the power supply, the long rise time of the voltage before reaching the conduction threshold may damage the protected circuit.

[0004] The traditional electrostatic protection circuit uses an RC circuit composed of a capacitor and a resistor in series to detect electrostatic shock on the power supply. Although the larger time constant RC can meet the circuit's need for sufficient discharge of electrostatic current, it also reduces the sensitivity of electrostatic shock detection. Therefore, the traditional electrostatic protection circuit cannot simultaneously meet the needs of rapid detection and sufficient discharge of electrostatic shock.

[0005] Therefore, traditional protection circuits use independent surge and electrostatic protection circuits, which occupy a large area; and traditional surge protection circuits based on transient voltage suppression diodes cannot protect the circuit before the voltage reaches its reverse conduction threshold, and the voltage rise time in microseconds may cause damage to the circuit; traditional electrostatic protection circuits based on RC detection circuits have two identical time parameters for response time and discharge time to electrostatic shocks, which makes it difficult to simultaneously meet the protection circuit's requirements for rapid response and sufficient discharge of electrostatic shocks. Summary of the invention

[0006] The present application intervenes in advance through the electrostatic detection branch before the surge voltage rises to the threshold voltage of the transient voltage suppression diode for reverse conduction, thereby protecting the circuit from damage; at the same time, a MOS transistor is added to the electrostatic detection branch design to extend the discharge time of the electrostatic shock current, thereby meeting the requirements of the protection circuit for rapid response to electrostatic shocks and sufficient discharge.

[0007] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0008] To achieve one, part, or all of the above purposes or other purposes, the present invention provides a surge and static electricity dual protection circuit and a dynamic power clamp circuit.

[0009] A surge and static electricity dual protection circuit is arranged between a power supply and a ground, and is characterized by comprising: a surge detection branch, a static electricity detection branch, a discharge control branch, and a current discharge branch; The electrostatic detection branch includes a resistor and a capacitor connected in series and a PMOS transistor, and when an electrostatic shock is detected in the power supply, a response signal is output to the discharge control branch; The surge detection branch includes a transient voltage suppression diode and a resistor and capacitor device. When a surge impact is detected on the power supply, the transient voltage suppression diode conducts in reverse and outputs a response signal to the discharge control branch; The discharge control branch converts the response signal into a control signal of the current discharge branch through a pair of complementary MOS transistors; The current discharge branch includes a MOS transistor, and the control signal controls the MOS transistor to be turned on to discharge the impact current.

[0010] The electrostatic detection branch includes resistor-capacitor devices connected in series in sequence, and the resistor-capacitor devices include at least two capacitors and at least one resistor. The source of the PMOS transistor is connected to the power supply, the gate is connected to the output end of the discharge control branch, and the drain is connected between the two capacitors.

[0011] The electrostatic detection branch includes a capacitor C1, a capacitor C2 and a resistor R4 connected in series in sequence; One end of the capacitor C1 is connected to the power supply, and the other end is connected to the capacitor C2; the other end of the capacitor C2 is connected to the resistor R4, and the other end of the resistor R4 is grounded; The drain of the PMOS transistor P3 is connected to the node J2 between the capacitor C1 and the capacitor C2, the source is connected to the power supply, and the gate is connected to the output end of the discharge control branch through the node J3; The electrostatic detection branch is connected to the input end of the discharge control branch via a node J1 between the capacitor C2 and the resistor R4, and outputs a response signal to the discharge control branch.

[0012] When an electrostatic shock is detected in the power supply, the node J1 is kept at a low level, the node J3 is kept at a high level, the source and the drain of the PMOS transistor P3 are kept closed, the capacitors C1 and C2 start to charge, the equivalent capacitance is 1 / C1+1 / C2, the node J1 forms a high level, and outputs a response signal to the discharge control branch; The discharge control branch converts the response signal into a control signal and outputs it to the current discharge branch. A low level is formed at the node J3. At this time, the source and drain of the PMOS transistor P3 are turned on, the capacitor C1 is short-circuited, the capacitor C2 continues to charge, the equivalent capacitor is C2, the node J1 continues to maintain a high level, and continuously outputs a response signal to the discharge control branch, thereby extending the discharge time of the electrostatic shock current.

[0013] The surge detection branch includes a transient voltage suppression diode and a resistor R3 connected in series in sequence; The cathode of the transient voltage suppression diode is connected to the power supply, and the anode is connected to the resistor R3 and connected to the node J1 between the capacitor C2 and the resistor R4; the other end of the resistor R3 is grounded.

[0014] When a surge occurs to the power supply and the voltage of the power supply exceeds the threshold voltage of the transient voltage suppression diode, the transient voltage suppression diode conducts in the reverse direction, a high level is formed at the node J1, and is output to the discharge control branch; When the power supply has no surge impact, the transient voltage suppression diode remains in a cut-off state, the node J1 forms a low level and is output to the discharge control branch.

[0015] When a surge occurs to the power supply but the voltage of the power supply does not exceed the threshold voltage of the transient voltage suppression diode, the capacitors C1 and C2 of the electrostatic detection branch begin to charge, and the node J1 forms a high level and is output to the discharge control branch.

[0016] The discharge control branch includes at least one PMOS transistor P1 and at least one NMOS transistor N1; The source of the PMOS transistor P1 is connected to the power supply, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are connected to the node J1, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are connected to the node J3, and the source of the NMOS transistor N1 is grounded.

[0017] When the node J1 is at a low level, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the node J3 forms a high level and is output to the current discharge branch; When the node J1 is at a high level, the PMOS transistor P1 is in a cut-off state, the NMOS transistor N1 is turned on, and the node J3 forms a low level and is output to the current discharge branch.

[0018] The current discharge branch includes a PMOS transistor P4, the source of the PMOS transistor P4 is connected to the power supply, the drain is grounded, the gate is connected to the node J3, and receives the control signal output by the discharge control branch; When the node J3 is at a low level, the source and drain of the PMOS transistor P4 are in a conducting state, and the low-resistance discharge channel between the power supply and the ground is opened, discharging the surge impact current and the electrostatic impact current to the ground; When the node J3 is at a high level, the source and drain of the PMOS transistor P4 are in a cut-off state, and the low-resistance discharge channel between the power supply and the ground is closed.

[0019] A dynamic power clamp circuit uses the above-mentioned surge and electrostatic dual protection circuit, including: An input port protection branch, the input port protection branch is connected between the input port and the core circuit, and includes at least one pair of reversely connected diodes, which discharge the impact current to the power supply end or the ground end; The input port transmits the input signal to the core circuit through a current limiting device; An output port protection branch, the output port protection branch is connected between the output port and the core circuit, and includes at least one pair of reversely connected diodes, providing a discharge path for discharging the surge current to the power supply terminal or the ground terminal; An input / output port protection module, wherein the input / output port protection module is connected between the input / output terminal and the input / output port on the other side of the core circuit, and provides a discharge path for discharging the impact current to the power supply terminal or the ground terminal; IO power surge and electrostatic shock protection module, including a surge and electrostatic dual protection circuit connected between the IO power supply and the ground; and a core power surge and electrostatic shock protection module, including a surge and electrostatic double protection circuit connected between the core power supply and ground.

[0020] The input / output port protection module includes at least two surge current discharge paths, which are respectively connected to the input / output end on the other side of the core circuit; The inrush current discharge path is composed of at least two reversely connected diodes, through which the inrush current is discharged to the power supply terminal or the ground terminal; A current limiting device is also connected between the input end on the other side of the core circuit and the input / output port.

[0021] The input port protection branch includes a first diode and a second diode; The cathode of the first diode is connected to the power supply terminal, the anode is connected to the cathode of the second diode, and the anode of the second diode is grounded; The current limiting device is a resistor.

[0022] The input port protection branch includes a PMOS transistor and an NMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, and the source of the NMOS transistor is grounded.

[0023] Compared with the prior art, the beneficial effects of the present invention mainly include: The present application intervenes in advance through the electrostatic detection branch before the surge voltage rises to the threshold voltage of the transient voltage suppression diode for reverse conduction, thereby protecting the circuit from damage; at the same time, a MOS transistor is added to the electrostatic detection branch design, and the RC constant of the electrostatic detection branch is dynamically adjusted through the MOS transistor to extend the discharge time of the electrostatic shock current, thereby meeting the requirements of the protection circuit for rapid response to electrostatic shock and sufficient discharge.

[0024] In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 Schematic diagram of the surge and static electricity dual protection circuit provided in Example 1 of the present application.

[0027] Figure 2 Schematic diagram of the input port protection branch provided in Example 2 of the present application.

[0028] Figure 3 A schematic diagram of the output port protection branch provided in Example 2 of the present application.

[0029] Figure 4 Schematic diagram of the input / output port protection module provided in Example 2 of the present application.

[0030] Figure 5 Schematic diagram of the dynamic power clamp circuit provided in Example 2 of the present application. DETAILED DESCRIPTION

[0031] The above and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0032] The present application intervenes in advance through the electrostatic detection branch before the surge voltage rises to the threshold voltage of the transient voltage suppression diode for reverse conduction, thereby protecting the circuit from damage; at the same time, a MOS transistor is added to the electrostatic detection branch design, and the RC constant of the electrostatic detection branch is dynamically adjusted through the MOS transistor to extend the discharge time of the electrostatic shock current, thereby meeting the requirements of the protection circuit for rapid response to electrostatic shock and sufficient discharge.

[0033] The following will describe the various embodiments of the present application in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present application, many technical details are provided in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solution claimed in the present application can be implemented.

[0034] Figure 1 Shown is a schematic diagram of a surge and electrostatic dual protection circuit provided in Example 1 of the present application.

[0035] like Figure 1 As shown, a surge and static electricity dual protection circuit is arranged between a power supply and a ground, comprising: a surge detection branch, a static electricity detection branch, a discharge control branch and a current discharge branch; The electrostatic detection branch includes a resistor and a capacitor connected in series and a PMOS transistor, and when an electrostatic shock is detected in the power supply, a response signal is output to the discharge control branch; The surge detection branch includes a transient voltage suppression diode and a resistor and capacitor device. When a surge impact is detected on the power supply, the transient voltage suppression diode conducts in the reverse direction and outputs a response signal to the discharge control branch. The discharge control branch converts the response signal into a control signal of the current discharge branch through a pair of complementary MOS transistors; The current discharge branch includes a MOS transistor, and a control signal controls the MOS transistor to be turned on to discharge the impact current.

[0036] like Figure 1 As shown, the electrostatic detection branch includes resistor-capacitor devices connected in series, the resistor-capacitor devices include at least two capacitors and at least one resistor, the source of the PMOS transistor is connected to the power supply, the gate is connected to the output end of the discharge control branch, and the drain is connected between the two capacitors.

[0037] Specifically, the electrostatic detection branch includes a capacitor C1, a capacitor C2 and a resistor R4 connected in series in sequence; one end of the capacitor C1 is connected to the power supply, and the other end is connected to the capacitor C2; the other end of the capacitor C2 is connected to the resistor R4, and the other end of the resistor R4 is grounded; the drain of the PMOS transistor P3 is connected to the node J2 between the capacitor C1 and the capacitor C2, the source is connected to the power supply, and the gate is connected to the output end of the discharge control branch through the node J3; the electrostatic detection branch is connected to the input end of the discharge control branch through the node J1 between the capacitor C2 and the resistor R4, and outputs a response signal to the discharge control branch.

[0038] When the power supply VCC is detected to have an electrostatic shock, the node J1 remains at a low level, the node J3 remains at a high level, the source and the drain of the PMOS transistor P3 remain closed, the capacitors C1 and C2 begin to charge, the equivalent capacitance is 1 / C1+1 / C2, the node J1 forms a high level, and outputs a response signal to the discharge control branch; The discharge control branch converts the response signal into a control signal and outputs it to the current discharge branch. A low level is formed at the node J3. At this time, the source and drain of the PMOS transistor P3 are turned on, the capacitor C1 is short-circuited, the capacitor C2 continues to charge, the equivalent capacitor is C2, the node J1 continues to maintain a high level, and the RC constant of the discharge control branch is relatively large at this time. The response signal is continuously output to the discharge control branch, thereby extending the discharge time of the electrostatic shock current.

[0039] like Figure 1 As shown, the surge detection branch includes a transient voltage suppression diode TVS1 and a resistor R3 connected in series in sequence; the cathode of the transient voltage suppression diode TVS1 is connected to the power supply, the anode is connected to the resistor R3, and is connected to the node J1 between the capacitor C2 and the resistor R4; the other end of the resistor R3 is grounded.

[0040] Specifically, when a surge occurs in the power supply and the voltage of the power supply exceeds the threshold voltage of the transient voltage suppression diode TVS1, the transient voltage suppression diode TVS1 conducts in the reverse direction at a speed of picoseconds, and the node J1 forms a high level and is output to the discharge control branch; When there is no surge impact on the power supply, the transient voltage suppression diode TVS1 remains in the cut-off state, the node J1 forms a low level and is output to the discharge control branch; When a surge occurs in the power supply, the surge voltage continues to rise within microseconds. Before the surge voltage reaches the threshold voltage of the transient voltage suppression diode TVS1, the electrostatic detection branch detects the surge, capacitors C1 and C2 begin to charge, node J1 forms a high level, and is output to the discharge control branch.

[0041] like Figure 1As shown, the discharge control branch includes at least one PMOS transistor P1 and at least one NMOS transistor N1; the source of the PMOS transistor P1 is connected to the power supply, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are connected to the node J1, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are connected to the node J3, and the source of the NMOS transistor N1 is grounded.

[0042] Specifically, when the node J1 is at a low level, the PMOS transistor P1 is turned on, the NMOS transistor N1 is in the off state, the node J3 forms a high level, and is output to the current discharge branch; when the node J1 is at a high level, the PMOS transistor P1 is in the off state, the NMOS transistor N1 is turned on, the node J3 forms a low level, and is output to the current discharge branch.

[0043] like Figure 1 As shown, the current discharge branch includes a PMOS transistor P4, the source of the PMOS transistor P4 is connected to the power supply, the drain is grounded, the gate is connected to the node J3, and receives the control signal output by the discharge control branch; Specifically, when a low level appears at the node J3, the source and drain of the PMOS transistor P4 are in an on state, and the low-resistance discharge channel between the power supply and the ground is opened, and the surge impact current and the electrostatic impact current are discharged into the ground; when a high level appears at the node J3, the source and drain of the PMOS transistor P4 are in an off state, and the low-resistance discharge channel between the power supply and the ground is closed.

[0044] Figure 2 Shown is a schematic diagram of the input port protection branch provided in Example 2 of the present application.

[0045] like Figure 2 As shown, the input port protection branch is composed of a first diode D1, a second diode D2 and a first current limiting resistor R1; the anode of the first diode D1 is connected to the input port IPAD1, the cathode of the second diode D2 and one end of the first current limiting resistor R1; the cathode of the first diode D1 is connected to the power supply VCC; the anode of the second diode D2 is connected to the ground GND; the other end of the first current limiting resistor R1 is connected to the input terminal DATA_I1 of the core circuit; When a surge or electrostatic discharge occurs at the input port IPAD1, the first diode D1 and the second diode D2 provide a discharge channel for discharging the current to the power supply VCC or the ground GND; When there is no discharge at the input port IPAD1, the input signal enters the core circuit through the first resistor R1.

[0046] As a preferred embodiment of the present invention, the first diode D1 and the second diode D2 in this embodiment are both large-size diodes.

[0047] As a preferred embodiment of the present invention, the D1 diode in this embodiment can be replaced by a PMOS transistor, the D2 diode can be replaced by an NMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, and the source of the NMOS transistor is grounded.

[0048] Figure 3 Shown is a schematic diagram of the output port protection branch provided in Example 2 of the present application.

[0049] like Figure 3 As shown, the output port protection branch is composed of a third diode D3 and a fourth diode D4; the anode of the third diode D3 is connected to the output port OPAD1, the cathode of the fourth diode D4 and the output end DATA_O1 of the core circuit; the cathode of the third diode D3 is connected to the power supply VCC; the anode of the fourth diode D4 is connected to the ground GND.

[0050] When a surge or electrostatic discharge occurs at the output port OPAD1 , the third diode D3 and the fourth diode D4 provide a discharge channel for discharging the current to the power source VCC or the ground GND.

[0051] When there is no discharge at the input port OPAD1, the output signal is output normally from the core circuit.

[0052] As a preferred embodiment of the present invention, the third diode D3 and the fourth diode D4 in this embodiment are both large-size diodes.

[0053] As a preferred embodiment of the present invention, the D3 diode in this embodiment can be replaced by a PMOS transistor, the D4 diode can be replaced by an NMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, and the source of the NMOS transistor is grounded.

[0054] Figure 4 Shown is a schematic diagram of the input / output port protection module provided in Example 2 of the present application.

[0055] The input / output port protection module includes both input port protection and output port protection functions, and is mainly used for bidirectional IO ports, such as configurable IO ports in programmable devices such as FPGA.

[0056] like Figure 4As shown, the input / output port protection module is composed of a fifth diode D5, a sixth diode D6, a seventh diode D7, an eighth diode D8 and a second current limiting resistor R2; the anode of the fifth diode D5 is connected to the bidirectional port IOPAD1, the anode of the seventh diode D7, the cathode of the sixth diode D6, the cathode of the eighth diode D8, the output end DATA_O2 of the core circuit and one end of the second current limiting resistor R2; the cathode of the fifth diode D5 is connected to the power supply VCC; the anode of the sixth diode D6 is connected to the ground GND; the cathode of the seventh diode D7 is connected to the power supply VCC; the anode of the eighth diode D8 is connected to the ground GND; the other end of the second current limiting resistor R2 is connected to the input end DATA_I2 of the core circuit.

[0057] When the input / output port is configured in input mode, when a surge or electrostatic discharge occurs at the input / output port IOPAD1, the seventh diode D7 and the eighth diode D8 provide a discharge channel for discharging the current to the IO power supply VCCIO or the ground GND; when no discharge occurs at the input / output port IOPAD1, the input signal enters the core circuit through the second current limiting resistor R2.

[0058] When the input / output port is configured in output mode, when a surge or electrostatic discharge occurs at the input / output port IOPAD1, the fifth diode D5 and the sixth diode D6 provide a discharge channel for discharging the current to the IO power supply VCCIO or the ground GND; when no discharge occurs at the input / output port IOPAD1, the output signal is output normally from the core circuit.

[0059] Figure 5 Shown is a schematic diagram of a dynamic power clamp circuit provided in Example 2 of the present application.

[0060] like Figure 5 As shown, a dynamic power clamp circuit comprises: An input port protection branch, the input port protection branch is connected between the input port and the core circuit, and includes at least one pair of reversely connected diodes, which discharges the impact current to a discharge path of a power supply terminal or a ground terminal; The input port transmits the input signal to the core circuit through the current limiting device; An output port protection branch, the output port protection branch is connected between the output port and the core circuit, and includes at least one pair of reversely connected diodes, providing a discharge path for discharging the surge current to the power supply end or the ground end; An input / output port protection module, the input / output port protection module is connected between the input / output terminal and the input / output port on the other side of the core circuit, and provides a discharge path for discharging the impact current to the power supply terminal or the ground terminal; IO power surge and electrostatic shock protection module, including a surge and electrostatic dual protection circuit connected between the IO power supply and the ground; and a core power surge and electrostatic shock protection module, including a surge and electrostatic double protection circuit connected between the core power supply and ground.

[0061] Specifically, in the surge and electrostatic shock protection module of the IO power supply, in the normal power-on state: the first transient voltage suppression diode TVS11 is reversely cut off, and the node J11 remains at a low level; the capacitor C11 and the capacitor C12 begin to charge, but since the voltage rise during the power-on process requires milliseconds, the node J11 continues to remain at a low level, the source and drain of the PMOS tube P11 are turned on, the node J13 remains at a high level, the source and drain of the PMOS tube P12 are turned off, C11 continues to maintain a charging state, and at the same time, the source and drain of the PMOS tube P13 are turned off, and the circuit is powered on and operates normally.

[0062] Specifically, in the electrostatic shock state: when an electrostatic shock occurs at the input port IPAD11, the diode D11 is forward-conducted to discharge the electrostatic current to the IO power supply VCCIO; the capacitor C11 and the capacitor C12 begin to charge, a high level appears at the node J11, the source and drain of the PMOS tube P11 are turned off, the source and drain of the NMOS tube N11 are turned on, a low level appears at the node J13, the source and drain of the PMOS tube P13 are turned on, and a short discharge path is formed between the IO power supply VCCIO and the ground GND; at the same time, the source and drain of the PMOS tube P12 are turned on, the capacitor C11 is short-circuited, the equivalent capacitance formed by the capacitor C11 and the capacitor C12 increases, the time constant RC increases, the opening time of the discharge path is extended, and the electrostatic current on the IO power supply VCCIO is fully discharged.

[0063] When an electrostatic shock occurs at the output port OPAD11, the diode D13 is forward-conducted, discharging the surge current to the IO power supply VCCIO. The subsequent process is the same as when a surge shock occurs at the input port IPAD11. When an electrostatic shock occurs to the input / output port IOPAD11, the diode D15 and the diode D17 are forward-conducted to discharge the surge current to the IO power supply VCCIO, and the subsequent process is the same as when a surge shock occurs to the input port IPAD11.

[0064] Specifically, in the surge impact state: when a surge impact occurs at the input port IPAD11, the diode D11 is forward-conducted to discharge the surge current to the IO power supply VCCIO; before the surge voltage reaches the reverse conduction threshold voltage of the transient voltage suppression tube TVS11, the capacitors C11 and C12 begin to charge, a high level appears at the node J11, the source and drain of the PMOS tube P11 are turned off, the source and drain of the NMOS tube N11 are turned on, a low level appears at the node J13, and the source and drain of the PMOS tube P13 are turned off. The electrode is turned on, forming a short discharge path between the IO power supply VCCIO and the ground GND; at the same time, the source and drain of the PMOS tube P12 are turned on, the capacitor C11 is short-circuited, the equivalent capacitance composed of the capacitors C11 and C12 increases, the RC time constant increases, and the opening time of the discharge path is extended; after the surge voltage exceeds the reverse conduction threshold voltage of the transient voltage suppression tube TVS11, the node continues to maintain a high level, and the opening time of the discharge path is further extended until the voltage of the IO power supply VCCIO falls back to the normal range.

[0065] When a surge occurs at the output port OPAD11, the diode D13 is forward-conducted to discharge the surge current to the IO power supply VCCIO. The subsequent process is the same as when a surge occurs at the input port IPAD11. When a surge occurs at the input / output port IOPAD11, the diode D15 and the diode D17 are forward-conducted to discharge the surge current to the IO power supply VCCIO, and the subsequent process is the same as when a surge occurs at the input port IPAD11.

[0066] In the surge and electrostatic shock protection module of the core power supply, in the normal power-on state: the second transient voltage suppression diode TVS21 is reversely cut off, and the node J21 remains at a low level; the capacitors C21 and C22 begin to charge, but since the voltage rise during the power-on process takes milliseconds, the node J21 continues to remain at a low level, the source and drain of the PMOS tube P21 are turned on, the node J23 remains at a high level, the source and drain of the PMOS tube P22 are turned off, C21 continues to maintain a charging state, and the source and drain of the PMOS tube P23 are turned off, and the circuit is powered on and runs normally; In the electrostatic shock state: when an electrostatic shock occurs on the core power supply VCCINT, capacitors C21 and C22 begin to charge, a high level appears at node J21, the source and drain of the PMOS tube P21 are turned off, the source and drain of the NMOS tube N21 are turned on, a low level appears at node J23, the source and drain of the PMOS tube P23 are turned on, and a short discharge path is formed between the core power supply VCCINT and the ground GND; at the same time, the source and drain of the PMOS tube P22 are turned on, capacitor C21 is short-circuited, the equivalent capacitance formed by capacitors C21 and C22 increases, the time constant RC increases, the opening time of the discharge path is extended, and the electrostatic current on the core power supply VCCINT is fully discharged; In the surge state: when a surge occurs on the core power supply VCCINT port, before the surge voltage reaches the reverse conduction threshold voltage of the transient voltage suppressor TVS21, capacitors C21 and C22 begin to charge, a high level appears at the node J21, the source and drain of the PMOS tube P21 are turned off, the source and drain of the NMOS tube N21 are turned on, a low level appears at the node J23, the source and drain of the PMOS tube P23 are turned on, and a short discharge path is formed between the core power supply VCCINT and the ground GND; at the same time, the source and drain of the PMOS tube P22 are turned on, capacitor C21 is short-circuited, the equivalent capacitance composed of capacitors C21 and C22 increases, the RC time constant increases, and the opening time of the discharge path is extended; after the surge voltage exceeds the reverse conduction threshold voltage of the transient voltage suppressor TVS21, the node continues to maintain a high level, and the opening time of the discharge path is further extended until the voltage of the core power supply VCCINT falls back to the normal range.

[0067] The present application intervenes in advance through the electrostatic detection branch before the surge voltage rises to the threshold voltage of the transient voltage suppression diode for reverse conduction, thereby protecting the circuit from damage; at the same time, a MOS transistor is added to the electrostatic detection branch design, and the RC constant of the electrostatic detection branch is dynamically adjusted through the MOS transistor to extend the discharge time of the electrostatic shock current, thereby meeting the requirements of the protection circuit for rapid response to electrostatic shock and sufficient discharge.

[0068] In order to facilitate the description, some common English nouns or letters used in the present invention are only used for exemplary reference rather than restrictive interpretation or specific usage, and the protection scope of the present invention should not be limited by their possible Chinese translations or specific letters.

[0069] It should also be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

Claims

1. A surge and static electricity dual protection circuit, arranged between a power source and a ground, characterized in that: include: Surge detection branch, static detection branch, discharge control branch and current discharge branch; The electrostatic detection branch includes a resistor and a capacitor and a PMOS transistor connected in series in sequence, and when an electrostatic shock is detected in the power supply, a response signal is output to the discharge control branch; The surge detection branch includes a transient voltage suppression diode and a resistor and capacitor device. When a surge impact is detected on the power supply, the transient voltage suppression diode conducts in reverse and outputs a response signal to the discharge control branch; The discharge control branch converts the response signal into a control signal of the current discharge branch through a pair of complementary MOS transistors; The current discharge branch includes a MOS transistor, and the control signal controls the MOS transistor to be turned on to discharge the impact current.

2. A surge and static electricity dual protection circuit according to claim 1, characterized in that: The electrostatic detection branch includes resistor-capacitor devices connected in series in sequence, and the resistor-capacitor devices include at least two capacitors and at least one resistor. The source of the PMOS transistor is connected to the power supply, the gate is connected to the output end of the discharge control branch, and the drain is connected between the two capacitors.

3. The surge and static electricity dual protection circuit according to claim 1, characterized in that: The electrostatic detection branch includes a capacitor C1, a capacitor C2 and a resistor R4 connected in series in sequence; One end of the capacitor C1 is connected to the power supply, and the other end is connected to the capacitor C2; the other end of the capacitor C2 is connected to the resistor R4, and the other end of the resistor R4 is grounded; The drain of the PMOS transistor P3 is connected to the node J2 between the capacitor C1 and the capacitor C2, the source is connected to the power supply, and the gate is connected to the output end of the discharge control branch through the node J3; The electrostatic detection branch is connected to the input end of the discharge control branch via a node J1 between the capacitor C2 and the resistor R4, and outputs a response signal to the discharge control branch.

4. The surge and static electricity dual protection circuit according to claim 3, characterized in that: When an electrostatic shock is detected in the power supply, the node J1 is kept at a low level, the node J3 is kept at a high level, the source and the drain of the PMOS transistor P3 are kept closed, the capacitors C1 and C2 start to charge, the equivalent capacitance is 1 / C1+1 / C2, the node J1 forms a high level, and outputs a response signal to the discharge control branch; The discharge control branch converts the response signal into a control signal and outputs it to the current discharge branch. A low level is formed at the node J3. At this time, the source and drain of the PMOS transistor P3 are turned on, the capacitor C1 is short-circuited, the capacitor C2 continues to charge, the equivalent capacitor is C2, the node J1 continues to maintain a high level, and continuously outputs a response signal to the discharge control branch, thereby extending the discharge time of the electrostatic shock current.

5. The surge and static electricity dual protection circuit according to claim 3, characterized in that: The surge detection branch includes a transient voltage suppression diode and a resistor R3 connected in series in sequence; The cathode of the transient voltage suppression diode is connected to the power supply, and the anode is connected to the resistor R3 and connected to the node J1 between the capacitor C2 and the resistor R4; the other end of the resistor R3 is grounded.

6. The surge and static electricity dual protection circuit according to claim 5, characterized in that: When a surge occurs to the power supply and the voltage of the power supply exceeds the threshold voltage of the transient voltage suppression diode, the transient voltage suppression diode conducts in the reverse direction, a high level is formed at the node J1, and is output to the discharge control branch; When the power supply has no surge impact, the transient voltage suppression diode remains in a cut-off state, the node J1 forms a low level and is output to the discharge control branch.

7. The surge and static electricity dual protection circuit according to claim 6, characterized in that: When a surge occurs to the power supply but the voltage of the power supply does not exceed the threshold voltage of the transient voltage suppression diode, the capacitors C1 and C2 of the electrostatic detection branch begin to charge, and the node J1 forms a high level and is output to the discharge control branch.

8. The surge and static electricity dual protection circuit according to claim 3, characterized in that: The discharge control branch includes at least one PMOS transistor P1 and at least one NMOS transistor N1; The source of the PMOS transistor P1 is connected to the power supply, the gate of the PMOS transistor P1 and the gate of the NMOS transistor N1 are connected to the node J1, the drain of the PMOS transistor P1 and the drain of the NMOS transistor N1 are connected to the node J3, and the source of the NMOS transistor N1 is grounded.

9. The surge and static electricity dual protection circuit according to claim 8, characterized in that: When the node J1 is at a low level, the PMOS transistor P1 is turned on, the NMOS transistor N1 is turned off, the node J3 forms a high level and is output to the current discharge branch; When the node J1 is at a high level, the PMOS transistor P1 is in a cut-off state, the NMOS transistor N1 is turned on, and the node J3 forms a low level and is output to the current discharge branch.

10. The surge and static electricity dual protection circuit according to claim 3, characterized in that: The current discharge branch includes a PMOS transistor P4, the source of the PMOS transistor P4 is connected to the power supply, the drain is grounded, the gate is connected to the node J3, and receives the control signal output by the discharge control branch; When the node J3 is at a low level, the source and drain of the PMOS transistor P4 are in a conducting state, and the low-resistance discharge channel between the power supply and the ground is opened, discharging the surge impact current and the electrostatic impact current to the ground; When the node J3 is at a high level, the source and drain of the PMOS transistor P4 are in a cut-off state, and the low-resistance discharge channel between the power supply and the ground is closed.

11. A dynamic power clamp circuit, characterized in that: The surge and electrostatic dual protection circuit according to any one of claims 1 to 10 comprises: An input port protection branch, the input port protection branch is connected between the input port and the core circuit, and includes at least one pair of reversely connected diodes, which discharge the impact current to the power supply end or the ground end; The input port transmits the input signal to the core circuit through a current limiting device; An output port protection branch, the output port protection branch is connected between the output port and the core circuit, and includes at least one pair of reversely connected diodes, providing a discharge path for discharging the surge current to the power supply terminal or the ground terminal; An input / output port protection module, wherein the input / output port protection module is connected between the input / output terminal and the input / output port on the other side of the core circuit, and provides a discharge path for discharging the impact current to the power supply terminal or the ground terminal; IO power surge and electrostatic shock protection module, including a surge and electrostatic dual protection circuit connected between the IO power supply and the ground; and a core power surge and electrostatic shock protection module, including a surge and electrostatic double protection circuit connected between the core power supply and ground.

12. A dynamic power clamp circuit according to claim 11, characterized in that: The input / output port protection module includes at least two surge current discharge paths, which are respectively connected to the input / output end on the other side of the core circuit; The inrush current discharge path is composed of at least two reversely connected diodes, through which the inrush current is discharged to the power supply terminal or the ground terminal; A current limiting device is also connected between the input end on the other side of the core circuit and the input / output port.

13. The dynamic power clamp circuit according to claim 11, characterized in that: The input port protection branch includes a first diode and a second diode; The cathode of the first diode is connected to the power supply terminal, the anode is connected to the cathode of the second diode, and the anode of the second diode is grounded; The current limiting device is a resistor.

14. The dynamic power clamp circuit according to claim 11, characterized in that: The input port protection branch includes a PMOS transistor and an NMOS transistor, the source of the PMOS transistor is connected to the power supply terminal, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, and the source of the NMOS transistor is grounded.

Images