Power amplifier

Abstract

A power amplification device is provided with: a power amplification transistor; a voltage detection circuit; a bias circuit that supplies a bias current to the power amplifier transistor; a bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit; a plurality of current generation modes for controlling the bias circuit and the bias power supply circuit include: a weak limit mode in which, if the notified power supply voltage is equal to or greater than a first threshold value, the bias power supply current is reduced compared to when the notified power supply voltage is less than the first threshold value, and the bias power supply current is reduced compared to when the notified power supply voltage is less than the first threshold value; the bias circuit operates in either an ON mode in which a bias power supply current generated by the bias power supply circuit is supplied as a bias current to the power amplifier transistor, or an OFF mode in which the supply is performed or stopped by lowering the level of the bias current compared to the ON mode. When the bias control circuit is notified that the power supply voltage is greater than or equal to a second threshold value that is greater than the first threshold value, the bias control circuit can operate the bias circuit in the off mode.

Description

Technical Field

[0001] The invention relates to a power amplifying device. Background Art

[0002] Patent document 1 discloses a high-frequency signal power amplifier circuit having an overcurrent or overvoltage protection function. In the power amplifier circuit disclosed in Patent document 1, the level of the power supply current supplied to the collector of the power amplifier transistor is limited so as to avoid the breakdown of the power amplifier transistor when an overcurrent or overvoltage occurs. In addition, when an overcurrent or overvoltage occurs, the operation of the power amplifier transistor is stopped by blocking the current supplied to the base of the bias transistor for supplying a bias current to the power amplifier transistor. Thus, the breakdown of the amplifier transistor is avoided.

[0003] Prior Art Literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2020 / 080332 Summary of the invention

[0006] Problem that the invention aims to solve

[0007] Depending on various internal and external factors and the characteristics of the power amplifier circuit, it is necessary to limit the level of the power supply current for preventing the breakdown of the power amplifier transistor and change the conditions for stopping the operation. The object of the present invention is to provide a power amplifier device that can meet various requirements for preventing the breakdown of the power amplifier transistor.

[0008] Technical solutions to solve problems

[0009] According to one aspect of the present invention, there is provided a power amplifier device, comprising:

[0010] Power amplifier transistor, which amplifies the power of high-frequency signals;

[0011] a voltage detection circuit that outputs a first detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a first threshold value, and a second detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a second threshold value that is greater than the first threshold value;

[0012] A bias circuit supplies a bias current to the power amplifier transistor;

[0013] a bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit; and

[0014] a bias control circuit, controlling the bias circuit,

[0015] The bias power supply circuit operates in any current generation mode among a plurality of current generation modes for generating the bias power supply current at different levels.

[0016] The plurality of current generation modes include a weak limiting mode, in which, when the power supply voltage is notified by the first detection signal to be above the first threshold, the bias power supply current is reduced compared to when the power supply voltage is notified to be below the first threshold,

[0017] The bias circuit receives control from the bias control circuit and operates in either an on mode or an off mode. In the on mode, the bias power supply current generated by the bias power supply circuit is supplied to the power amplifier transistor as the bias current. In the off mode, the bias current is supplied or stopped by reducing the level of the bias current compared to the on mode.

[0018] The bias control circuit can operate the bias circuit in the shutdown mode when the bias control circuit is informed by the second detection signal that the power supply voltage is equal to or higher than the second threshold value.

[0019] Effects of the Invention

[0020] By selecting a mode from a plurality of current generation modes, the level of the bias power supply current can be changed. If the level of the bias power supply current is reduced, the bias current of the power amplifier transistor is reduced, and as a result, the power supply current flowing into the collector is reduced. By reducing the power supply current, the breakdown of the power amplifier transistor can be suppressed. By selecting a mode from a plurality of current generation modes, various requirements for suppressing the breakdown of the power amplifier transistor can be flexibly responded to. By operating the bias circuit in the shutdown mode, the amplification operation of the power amplifier transistor can be stopped, and the breakdown of the power amplifier transistor can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a block diagram of a power amplifier circuit according to the first embodiment.

[0022] Figure 2 It is the equivalent circuit diagram of the voltage selection circuit.

[0023] Figure 3 This is an equivalent circuit diagram of the first voltage-current conversion circuit of the bias power supply circuit.

[0024] Figure 4 : is a graph showing the relationship between the first detection signal det1 , the first mode selection signals p3 , p4 , and the current generation mode.

[0025] Figure 5This is an equivalent circuit diagram of the second voltage-current conversion circuit of the bias control circuit.

[0026] Figure 6 : is a graph showing the relationship between the second detection signal det2, the second mode selection signals p1, p2, and the operation mode of the bias circuit.

[0027] Figure 7 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit operates in the limit mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit operates in the strong shutdown mode.

[0028] Figure 8 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit operates in the limit mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit operates in the weak shutdown mode.

[0029] Fig. 9 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit operates in the unrestricted mode, and the second mode selection signal p1 is set to H level, p2 is set to L level, and the bias circuit operates in the strong shutdown mode.

[0030] Fig.10 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit operates in the unrestricted mode, and the second mode selection signal p1 is set to L level, p2 is set to H level, and the bias circuit operates in the weak shutdown mode.

[0031] Fig.11 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the L level, p4 is set to the H level, the bias power supply circuit operates in the strong limit mode, and the second mode selection signals p1 and p2 are both set to the L level and the bias circuit operates in the on mode.

[0032] Fig.12It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level and the bias power supply circuit operates in the unrestricted mode, and when the second mode selection signals p1 and p2 are both set to L level and the bias circuit operates in the on mode.

[0033] Fig.13 This is an equivalent circuit diagram of a bias power supply circuit of a power amplifier circuit according to a modified example of the first embodiment.

[0034] Fig.14 This is a block diagram of a power amplifier device according to the second embodiment.

[0035] Fig.15 This is an equivalent circuit diagram of the first voltage-current conversion circuit of the power amplifier device according to the second embodiment.

[0036] Fig.16 This is a graph showing the relationship between the first mode selection signals p3, p4, and p5, the bias power supply current IeC, and the current generation mode of the bias power supply circuit in the power amplifier circuit according to the second embodiment.

[0037] Fig.17 The first mode selection signal p3 and p4 are both set to L level, p5 is set to H level, and the bias power supply circuit operates in the variable limit mode, and the second mode selection signal p1 is set to H level, p2 is set to L level, and the bias circuit operates in the strong shutdown mode ( Figure 6 ) is a curve diagram showing the relationship between the power supply voltage Vcc and the power supply current Icc when operating under .

[0038] Fig.18 The first mode selection signal p3 and p4 are both set to L level, p5 is set to H level, and the bias power supply circuit operates in the variable limit mode, and the second mode selection signal p1 is set to L level, p2 is set to H level, and the bias circuit operates in the weak shutdown mode ( Figure 6 ) is a curve diagram showing the relationship between the power supply voltage Vcc and the power supply current Icc when operating under .

[0039] Description of Reference Numerals

[0040] 10: Voltage detection circuit

[0041] 11: 1st comparator

[0042] 12: Second comparator

[0043] 13: Voltage divider circuit

[0044] 14: Voltage selection circuit

[0045] 15: Multi-level voltage divider circuit

[0046] 16: Switch

[0047] 30: Bias circuit

[0048] 31: Bias transistor

[0049] 32: Resistor

[0050] 33: Diode circuit

[0051] 50: Bias power supply circuit

[0052] 51: The first voltage-current conversion circuit

[0053] 52: Decoder No. 1

[0054] 53: Operational Amplifier

[0055] 54: n-channel MOSFET

[0056] 55: Resistor

[0057] 56: Switch

[0058] 57: No. 1 constant current source

[0059] 58: 1st Current Mirror

[0060] 60: Breakdown area

[0061] 70: Bias control circuit

[0062] 71: Second voltage-current conversion circuit

[0063] 72: Decoder No. 2

[0064] 73: Operational Amplifier

[0065] 75: Resistor

[0066] 76: Switch

[0067] 77: Second constant current source

[0068] 78: Second Current Mirror

[0069] 80: Differential current generation circuit

[0070] 81: Operational Amplifier No. 3

[0071] 82: Operational Amplifier No. 4

[0072] 83: Transistor

[0073] 84: Resistor

[0074] 85, 86: switch

[0075] 87: Transistor

[0076] 90: Power amplifier transistor

[0077] 91: Choke Coil

[0078] 92: DC cut-off capacitor. DETAILED DESCRIPTION

[0079] [First embodiment]

[0080] Reference Figures 1 to 12 The power amplifier device based on the first embodiment is described with reference to the accompanying drawings.

[0081] Figure 1 1 is a block diagram of a power amplifier circuit according to the first embodiment. The power amplifier circuit according to the first embodiment includes a power amplifier transistor 90 , a voltage detection circuit 10 , a bias circuit 30 , a bias power supply circuit 50 , and a bias control circuit 70 .

[0082] As the power amplifier transistor 90, for example, a heterojunction bipolar transistor can be used. A high-frequency signal RFin is input to the base of the power amplifier transistor 90 via a DC cutoff capacitor 92. A power supply voltage Vcc is applied to the collector of the power amplifier transistor 90 via a choke coil 91. Thus, a DC power supply current Icc is supplied to the collector of the power amplifier transistor 90. An amplified high-frequency signal RFout is output from the collector of the power amplifier transistor 90. In addition, in the following embodiments, field effect transistors can also be used as each transistor including the power amplifier transistor 90. In this case, the structure of each embodiment can be understood by replacing the base of each transistor with a gate, replacing the collector with a drain, and replacing the emitter with a source.

[0083] Next, the configuration and function of the voltage detection circuit 10 will be described.

[0084] The voltage detection circuit 10 includes a first comparator 11, a second comparator 12, a voltage divider circuit 13, and a voltage selection circuit 14. A reference voltage Vref3 and selection signals sel1 and sel2 are input to the voltage selection circuit 14. The voltage selection circuit 14 divides the reference voltage Vref3 according to each of the selection signals sel1 and sel2 to generate a first voltage Vd1 and a second voltage Vd2. The second voltage Vd2 is higher than the first voltage Vd1.

[0085] The voltage divider circuit 13 divides the power supply voltage Vcc to generate a voltage divider value Vccd. The first comparator 11 compares the voltage divider value Vccd with the first voltage Vd1 and outputs the comparison result as a first detection signal det1. The second comparator 12 compares the voltage divider value Vccd with the second voltage Vd2 and outputs the comparison result as a second detection signal det2. The first comparator 11 substantially compares the power supply voltage Vcc before the voltage divider value Vccd (at Figure 1 , indicated in brackets) and a first threshold value Vth1 (in Figure 1 The second comparator 12 is substantially the same as comparing the power supply voltage Vcc with the second threshold value Vth2 (in Figure 1 The second threshold value Vth2 is higher than the first threshold value Vth1.

[0086] That is, the voltage detection circuit 10 detects whether the power supply voltage Vcc is above the first threshold value Vth1, and outputs the detection result as the first detection signal det1, and detects whether the power supply voltage Vcc is above the second threshold value Vth2, and outputs the detection result as the second detection signal det2. As an example, the first comparator 11 sets the first detection signal det1 to the L level when the power supply voltage Vcc is less than the first threshold value Vth1, and sets the first detection signal det1 to the H level when the power supply voltage Vcc becomes above the first threshold value Vth1. The second comparator 12 sets the second detection signal det2 to the L level when the power supply voltage Vcc is less than the second threshold value Vth2, and sets the second detection signal det2 to the H level when the power supply voltage Vcc becomes above the second threshold value Vth2. In addition, it is preferable that the first comparator 11 and the second comparator 12 have hysteresis characteristics.

[0087] Next, refer to Figure 2 The detailed structure of the voltage selection circuit 14 will be described.

[0088] Figure 2 : is an equivalent circuit diagram of the voltage selection circuit 14. The voltage selection circuit 14 includes a multi-stage voltage divider circuit 15 in which a plurality of resistor elements are connected in multiple stages, and a plurality of switches 16 respectively connected to a plurality of voltage extraction nodes of the multi-stage voltage divider circuit 15. One of the plurality of switches 16 is selected and turned on by a selection signal se11. As a result, the voltage of the voltage extraction node connected to the switch 16 in the turned-on state (equivalent to the first voltage Vd1) is input to an input node of the first comparator 11. A divided voltage value Vccd of the power supply voltage Vcc generated by the voltage divider circuit 13 is input to the other input node of the first comparator 11. The second voltage Vd2 ( Figure 1 ) is also the same as the circuit for generating the first voltage Vd1, and one of the plurality of switches is selected by the selection signal sel2.

[0089] Next, the bias circuit 30 will be described.

[0090] like Figure 1 As shown in FIG. 1 , the bias circuit 30 includes a bias transistor 31, a resistor element 32, and a diode circuit 33. As the bias transistor 31, for example, a heterojunction bipolar transistor can be used. The diode circuit 33 includes two heterojunction bipolar transistors connected in diode connection, and the two heterojunction bipolar transistors are connected in series. The bias power supply current IeC input from the bias power supply circuit 50 is supplied to the collector of the bias transistor 31. The emitter current of the bias transistor 31 is supplied to the base of the power amplifier transistor 90 as the bias current Ibb.

[0091] The bias control current IB input from the bias control circuit 70 is supplied to the base of the bias transistor 31 via the resistor 32. A part of the bias control current IB flows to the ground via the diode circuit 33. The base current (control current) of the bias transistor 31 is controlled by the bias control current IB.

[0092] The bias circuit 30 receives the bias control current IB from the bias control circuit 70 and can operate in any operation mode of "on mode" and "off mode". In the on mode, the bias power supply current IeC is supplied to the power amplifier transistor 90 as the bias current Ibb. In the off mode, the level of the bias current Ibb is lowered compared to the on mode and supplied to the power amplifier transistor 90 or the supply is stopped. The mode in which the level of the bias current Ibb is lowered compared to the on mode and supplied to the power amplifier transistor 90 is called "weak off mode", and the mode in which the supply of the bias current Ibb is stopped is called "strong off mode". In the weak off mode, the level of the bias current Ibb is low, so the power amplifier transistor 90 does not substantially perform an amplification operation. In other words, in the weak off mode, the power amplifier transistor 90 does not perform an amplification operation with a positive gain.

[0093] Next, the bias power supply circuit 50 will be described.

[0094] The bias power supply circuit 50 includes a first voltage-current conversion circuit 51 and a first decoder 52. The first voltage-current conversion circuit 51 generates a bias power supply current IeC by converting a reference voltage Vref1 into a current according to a command from the first decoder 52. The generated bias power supply current IeC is supplied to the bias circuit 30. The first decoder 52 provides a command to the first voltage-current conversion circuit 51 based on the first mode selection signals p3 and p4, the first control signal cnt1, and the first detection signal det1.

[0095] The level of the bias power supply current IeC changes according to the first detection signal det1 from the voltage detection circuit 10 as will be described later. Figure 3 as well as Figure 4 To explain.

[0096] Next, the bias control circuit 70 will be described.

[0097] The bias control circuit 70 includes a second voltage-current conversion circuit 71 and a second decoder 72. The second voltage-current conversion circuit 71 generates a bias control current IB by converting a reference voltage Vref2 into a current according to a command from the second decoder 72. The generated bias control current IB is supplied to the bias circuit 30. The second decoder 72 provides a command to the second voltage-current conversion circuit 71 based on the second mode selection signals p1 and p2, the second control signal cnt2, and the second detection signal det2.

[0098] The level of the bias control current IB changes according to the second detection signal det2 from the voltage detection circuit 10 as will be described later. Figure 5 as well as Figure 6 To explain.

[0099] Next, refer to Figure 3 as well as Figure 4 , the structure and operation of the bias power supply circuit 50 are described.

[0100] Figure 3: is an equivalent circuit diagram of the first voltage-current conversion circuit 51 of the bias power supply circuit 50. The first constant current source 57 is composed of an operational amplifier 53, an n-channel MOSFET 54, three resistor elements 55, and three switches 56. A reference voltage Vref1 is applied to the non-inverting input node of the operational amplifier 53. The three resistor elements 55 have different resistance values. Switches 56 are connected in series to the three resistor elements 55, respectively. Three series circuits including the resistor elements 55 and the switches 56 are connected in parallel. The switches 56 are turned on and off according to the instructions from the first decoder 52. If one switch 56 is selected from the three switches 56 and turned on, the first constant current source 57 generates a current of a fixed level corresponding to the resistance value of the resistor element 55 connected to the turned-on switch 56.

[0101] In addition, Figure 3 In FIG. 1 , a structure using three resistor elements 55 and three switches 56 to switch the resistance value is shown, but the method of switching the resistance value is not limited to this. For example, instead of Figure 3 As shown in the figure, a structure in which a plurality of resistor elements with different resistance values ​​are set to the number of resistance values ​​to be achieved is set as follows: a resistor element group including a plurality of resistor elements with the same resistance value and a plurality of switches for switching the connection between these plurality of resistor elements is set, and the combined resistance value of the resistor element group is switched.

[0102] The two p-channel MOSFETs form a first current mirror 58. The battery voltage VBAT is applied to the sources of the two p-channel MOSFETs. The drain current of the n-channel MOSFET 54 (the current generated by the first constant current source 57) is set to K times by the first current mirror 58 including the two p-channel MOSFETs, thereby generating a bias power supply current IeC. The bias power supply current IeC is supplied to the bias circuit 30.

[0103] The first decoder 52 receives a first control signal cnt1, a first detection signal det1, and first mode selection signals p3 and p4. The first control signal cnt1 stops the operation of the first voltage-current conversion circuit 51 and adjusts the current amount by switching the resistance value of the circuit including the three resistors 55.

[0104] The bias power supply circuit 50 can operate in any of a plurality of current generation modes for generating bias power supply currents IeC at different levels. Figure 4 When the table shown in FIG. 1 is stored in the first decoder 52, the bias power supply circuit 50 can be operated in any current generation mode among a plurality of current generation modes for generating bias power supply currents IeC having different levels. Figure 4, the relationship between the first detection signal det1, the first mode selection signals p3, p4, and the current generation mode will be described.

[0105] Figure 4 1 is a graph showing the relationship between the first detection signal det1, the first mode selection signals p3 and p4, and the current generation mode. When the first detection signal det1 is at an L level, that is, when the power supply voltage Vcc is less than the first threshold value Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC to IeC1 regardless of the values ​​of the first mode selection signals p3 and p4.

[0106] When the first detection signal det1 is at the H level, that is, when the power supply voltage Vcc is above the first threshold value Vth1, the bias power supply circuit 50 sets the level of the bias power supply current IeC according to the values ​​of the first mode selection signals p3 and p4. When the first mode selection signals p3 and p4 are both at the L level, the level of the bias power supply current IeC is set to IeC1. If the bias current Ibb at the level IeC1 is supplied to the power amplifier transistor 90 ( Figure 1 ), the power amplifier transistor 90 performs a normal amplification operation. The current generation mode in which the level of the bias power supply current IeC is set to IeC1 is referred to as a "non-limiting mode".

[0107] When the first mode selection signal p3 is at the L level and p4 is at the H level, the level of the bias power supply current IeC is set to IeCL. The level IeCL is such that even if the bias current Ibb of this level is supplied to the power amplifier transistor 90 ( Figure 1 ), the power amplifier transistor 90 does not substantially perform an amplification operation. The current generation mode in which the level of the bias power supply current IeC is set to IeCL is referred to as a "strong limit mode".

[0108] When the first mode selection signal p3 is at the H level and p4 is at the L level, the level of the bias power supply current IeC is set to a fixed level IeC2 lower than IeC1. In this state, the bias current Ibb supplied to the power amplifier transistor 90 is reduced compared to the non-limited mode. The power amplifier transistor 90 performs an amplification operation in a state where the operating point is changed. The current generation mode in which the level of the bias power supply current IeC is set to IeC2 is called a "weak limit mode". In addition, since the limited level IeC2 is a fixed value, it is sometimes called a "fixed limit mode".

[0109] Next, refer to Figure 5 as well as Figure 6 , the structure and operation of the bias control circuit 70 are described.

[0110] Figure 57 is an equivalent circuit diagram of the second voltage-current conversion circuit 71 of the bias control circuit 70. The basic circuit structure of the second voltage-current conversion circuit 71 is the same as that of the first voltage-current conversion circuit 51, and includes a second constant current source 77 and a second current mirror 78.

[0111] The second constant current source 77 includes an operational amplifier 73, an n-channel MOSFET 74, two resistor elements 75, and two switches 76. A reference voltage Vref2 is applied to the non-inverting input node of the operational amplifier 73. The resistance values ​​of the two resistor elements 75 are different from each other. The switch 76 is turned on and off according to the instruction from the second decoder 72. If one of the two switches 76 is selected and turned on, the second constant current source 77 generates a current of a fixed level corresponding to the resistance value of the resistor element 75 connected to the turned-on switch 76.

[0112] The drain current of the n-channel MOSFET 74 (the current generated by the second constant current source 77) is multiplied by K by the second current mirror 78, thereby generating the bias control current IB. In addition, usually, the current multiplication factor of the second current mirror 78 is the same as that of the first current mirror 58 ( Figure 3 The bias control current IB is supplied to the bias circuit 30.

[0113] The second decoder 72 receives the second control signal cnt2, the second detection signal det2, and the second mode selection signals p1 and p2. The second control signal cnt2 stops the operation of the second voltage-current conversion circuit 71 and adjusts the current amount. The bias control circuit 70 switches the operation mode of the bias circuit 30 between the on mode and the off mode by generating the bias control current IB of different levels. Figure 6 , the relationship between the second detection signal det2, the second mode selection signals p1, p2, and the operation mode of the bias circuit 30 will be described.

[0114] Figure 6 is a graph showing the relationship between the second detection signal det2, the second mode selection signals p1, p2, and the operation mode of the bias circuit 30. For example, in the case of Figure 6 When the table shown is stored in the second decoder 72, the bias circuit 30 can be operated in any of the plurality of operation modes, or the bias control circuit 70 can cause the bias circuit 30 to operate in any of the plurality of operation modes. When the second detection signal det2 is at an L level, that is, when the power supply voltage Vcc is lower than the second threshold value Vth2, the bias control circuit 70 sets the level of the bias control current IB to the normal level Lon regardless of the values ​​of the second mode selection signals p1 and p2.

[0115] When the second detection signal det2 is at the H level, that is, when the power supply voltage Vcc is equal to or higher than the second threshold value Vth2, the bias control circuit 70 sets the level of the bias control current IB according to the values ​​of the second mode selection signals p1 and p2.

[0116] When the second mode selection signals p1 and p2 are both at L level, the level of the bias control current IB is set to the normal level Lon. If the bias control current IB at the normal level Lon is supplied to the bias circuit 30 ( Figure 1 ), the bias current Ibb supplied to the power amplifier transistor 90 becomes substantially the same level as the bias power supply current IeC. The operation mode of the bias circuit 30 when the level of the bias control current IB is set to the normal level Lon is referred to as the "on mode".

[0117] When the second mode selection signal p1 is at the L level and p2 is at the H level, the level of the bias control current IB is set to the low level Llow. If the bias control current IB of the low level Llow is supplied to the bias circuit 30 ( Figure 1 ), the bias current Ibb supplied to the power amplifier transistor 90 is reduced compared to the bias current Ibb in the on mode. In this state, the power amplifier transistor 90 does not substantially perform an amplification operation. The operation mode of the bias circuit 30 when the level of the bias control current IB is set to the low level Llow is referred to as the "weak off mode".

[0118] When the second mode selection signal p1 is at the H level and p2 is at the L level, the level of the bias control current IB is set to the off level Loff. Specifically, the supply of the bias control current IB is stopped. At this time, the bias current Ibb is no longer supplied to the power amplifier transistor 90, and the amplification operation of the power amplifier transistor 90 is stopped. The operation mode of the bias circuit 30 when the level of the bias control current IB is set to the off level Loff is referred to as a "strong off mode".

[0119] Next, refer to Figures 7 to 12 The relationship between the power supply voltage Vcc and the power supply current Icc of the power amplifier transistor 90 is described with reference to the accompanying drawings. Figures 7 to 12 The accompanying drawing is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc of the power amplifier transistor 90. The horizontal axis represents the power supply voltage Vcc, and the vertical axis represents the power supply current Icc. The approximate breakdown region 60 of the power amplifier transistor 90 is represented by a hatched figure.

[0120] Figure 7It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit 50 operates in the limit mode, and the second mode selection signal p1 is set to the H level, p2 is set to the L level, and the bias circuit 30 operates in the strong shutdown mode.

[0121] When the power supply voltage Vcc is lower than the first threshold value Vth1 (the first detection signal det1 is at an L level), the level of the bias power supply current IeC becomes IeC1. When the power supply voltage Vcc is higher than the first threshold value Vth1 (the first detection signal det1 is at an H level), the level of the bias power supply current IeC becomes IeC2 which is lower than IeC1. When the power supply voltage Vcc is lower than the second threshold value Vth2 (the second detection signal det2 is at an L level), the bias control current IB becomes a normal level Lon, and the bias circuit 30 ( Figure 1 ) operates in the on mode.

[0122] When the bias circuit 30 operates in the on mode, the power supply current Icc is proportional to the bias power supply current IeC. Specifically, the level of the power supply current Icc is substantially equal to the value obtained by multiplying the bias power supply current IeC by the current amplification factor hfe of the power amplifier transistor 90. For example, when the level of the bias power supply current IeC is IeC1, the level Icc1 of the power supply current Icc is equal to hfe×IeC1. When the level of the bias power supply current IeC is IeC2, the level Icc2 of the power supply current Icc is equal to hfe×IeC2.

[0123] When the power supply voltage Vcc becomes equal to or higher than the second threshold value Vth2 (the second detection signal det2 becomes the off-level Loff), the bias control current IB becomes the off-level Loff, and the bias circuit 30 operates in the strong off-mode. As a result, the power supply current Icc becomes substantially 0. That is, the power supply current Icc decreases in two steps as the power supply voltage Vcc increases.

[0124] When an excessive voltage (a voltage greater than or equal to the second threshold value Vth2) is applied to the power amplifier transistor 90, the amplification operation of the power amplifier transistor 90 is stopped, thereby suppressing the breakdown of the power amplifier transistor 90. As the power supply voltage Vcc increases, the power supply current Icc decreases in two steps, so that the safe operation region of the power amplifier transistor 90 can be effectively used.

[0125] Figure 8It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the H level, p4 is set to the L level, the bias power supply circuit 50 operates in the limit mode, and the second mode selection signal p1 is set to the L level, p2 is set to the H level, and the bias circuit 30 operates in the weak shutdown mode.

[0126] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold value Vth2 is Figure 7 The relationship shown in FIG. 1 is the same as that shown in FIG. 1 . When the power supply voltage Vcc becomes equal to or higher than the second threshold value Vth2 (the second detection signal det2 becomes H level), the bias control circuit 70 sets the bias control current IB to the low level Llow. As a result, the operation mode of the bias circuit 30 becomes the weak shutdown mode, and the level of the power supply current Icc drops to IccL. At this level IccL, the power amplifier transistor 90 does not substantially perform an amplification operation.

[0127] Since the supply of the bias power supply current IeC is not completely stopped even when the power supply voltage Vcc becomes equal to or higher than the second threshold value Vth2 (ie, the supply of the bias current Ibb is not completely stopped), the recovery time is shorter than when the supply of the bias power supply current IeC is completely stopped.

[0128] Fig. 9 It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit 50 operates in the unrestricted mode, and the second mode selection signal p1 is set to H level, p2 is set to L level, and the bias circuit 30 operates in the strong shutdown mode.

[0129] Since the bias power supply circuit 50 operates in the non-limiting mode, the level of the bias power supply current IeC is set to IeC1 regardless of whether the power supply voltage Vcc is greater than the first threshold value Vth1. When the power supply voltage Vcc is less than the second threshold value Vth2 (the second detection signal det2 is at the L level), the bias control current IB is set to the normal level Lon, so the level of the power supply current Icc becomes Icc1 (hfe×IeC1).

[0130] When the power supply voltage Vcc becomes equal to or higher than the second threshold value Vth2 (the second detection signal det2 becomes H level), the bias control current IB is set to the off level Loff. Figure 7 In the same manner as in the case of , the power supply current Icc becomes substantially 0. That is, when the power supply voltage Vcc increases, the power supply current Icc decreases in a one-step manner.

[0131] Fig.10It is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level, the bias power supply circuit 50 operates in the unrestricted mode, and the second mode selection signal p1 is set to L level, p2 is set to H level, and the bias circuit 30 operates in the weak shutdown mode.

[0132] The level of the power supply current Icc when the power supply voltage Vcc is less than the second threshold value Vth2 (the second detection signal det2 is at the L level) is Fig. 9 If the power supply voltage Vcc becomes higher than the second threshold value Vth2 (the second detection signal det2 becomes H level), then Figure 8 In the same manner as in the case of , the level of the power supply current Icc drops to IccL. That is, if the power supply voltage Vcc increases, the power supply current Icc drops in a one-step manner.

[0133] Fig.11 1 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signal p3 is set to the L level, p4 is set to the H level, the bias power supply circuit 50 operates in the strong limit mode, and the second mode selection signals p1 and p2 are both set to the L level, and the bias circuit 30 operates in the on mode. The level of the bias control current IB is set to the normal level Lon regardless of the power supply voltage Vcc.

[0134] When the power supply voltage Vcc is less than the first threshold value Vth1 (the first detection signal det1 is at the L level), the level of the bias power supply current IeC is set to IeC1, and the level of the power supply current Icc becomes Icc1 (hfe×IeC1). When the power supply voltage Vcc becomes higher than the first threshold value Vth1 (the first detection signal det1 becomes the H level), the level of the bias power supply current IeC is set to IeCL, and the level of the power supply current Icc decreases to IccL (hfe×IeCL). That is, when the power supply voltage Vcc increases, the power supply current Icc decreases in a one-step manner.

[0135] Fig.12 1 is a graph showing the relationship between the power supply voltage Vcc and the power supply current Icc when the first mode selection signals p3 and p4 are both set to L level and the bias power supply circuit 50 operates in the non-limiting mode, and the second mode selection signals p1 and p2 are both set to L level and the bias circuit 30 operates in the on mode. Regardless of the power supply voltage Vcc, the level of the bias control current IB is set to the normal level Lon, and the level of the bias power supply current IeC is set to IeC1.

[0136] Therefore, the level of the power supply current Icc becomes a fixed value Icc1 (hfe×IeC1) regardless of the power supply voltage Vcc.

[0137] Next, the excellent effects of the first embodiment will be described.

[0138] In the first embodiment, Figure 4 as well as Figure 6 As shown in FIG. 1 , the level of the bias power supply current IeC and the operation mode of the bias circuit 30 can be changed by setting the second mode selection signals p1 and p2 and the first mode selection signals p3 and p4. Figure 7 , Figure 8 As shown in FIG. 1 , as the power supply voltage Vcc increases, the power supply current Icc of the power amplifier transistor 90 can be reduced in two steps. Fig. 9 , Fig.10 , Fig.11 As shown in FIG. 1 , the power supply current Icc of the power amplifier transistor 90 can be decreased in a step-like manner. Fig.12 As shown, the power supply current Icc of the power amplifier transistor 90 can be maintained substantially constant regardless of the power supply voltage Vcc.

[0139] In this way, the power supply current Icc can be flexibly reduced according to the characteristics of the power amplifier transistor 90, and the amplification operation can be substantially stopped.

[0140] Next, refer to Fig.13 , a bias power supply circuit for a power amplifier circuit according to a variation of the first embodiment is described.

[0141] Fig.13 1 is an equivalent circuit diagram of a bias power supply circuit 50 of a power amplifier circuit according to a modified example of the first embodiment. Figure 3 ), the level of the bias power supply current IeC is changed by changing the level of the current generated by the first constant current source 57. Fig.13 In the illustrated modification, the level of the current generated by the first constant current source 57 is fixed. In this modification, the level of the bias power supply current IeC is changed by changing the current multiplication factor of the first current mirror 58 according to the output of the first decoder 52.

[0142] Specifically, the circuit on the output side of the first current mirror 58 is composed of a parallel circuit of a plurality of transistors. The gate of at least one of the plurality of transistors constituting the parallel circuit is connected to the gate of the transistor on the input side via a switch 59. The conduction and non-conduction of the switch 59 are switched according to the output of the first decoder 52. By switching the conduction and non-conduction of the switch 59, the current multiplication factor of the first current mirror 58 can be changed.

[0143] The second voltage-current conversion circuit 71 ( Figure 5 ), or Fig.13 Similarly, the first voltage-current conversion circuit 51 shown in FIG. 1 does not connect the switch 76 and sets the resistor element 75 ( Figure 5 ) is set to a fixed value, so that the second current mirror 78 ( Figure 5 ) can be used with variable current multiplier.

[0144] Next, other modified examples of the first embodiment will be described.

[0145] In the first embodiment, a bipolar transistor is used as the bias transistor 31, but a MOSFET may also be used. In this case, the bias power supply current IeC is supplied to the drain of the MOSFET. The bias control circuit 70 controls the gate bias of the MOSFET to perform Figure 6 The bias circuit 30 shown switches between the on mode, the weak off mode, and the strong off mode.

[0146] [Second embodiment]

[0147] Next, refer to Figures 14 to 18 The power amplifier device according to the second embodiment is described with reference to the accompanying drawings. Figures 1 to 12 The accompanying drawings illustrate the common structure of the power amplifier device of the first embodiment, and the description is omitted.

[0148] Fig.14 This is a block diagram of a power amplifier device based on the second embodiment. Figure 1 ), the output of the first decoder 52 and the reference voltage Vref1 are input to the first voltage-current conversion circuit 51. In the second embodiment, the divided voltage value Vccd of the power supply voltage Vcc generated by the voltage divider circuit 13 and the first voltage Vd1 generated by the voltage selection circuit 14 are also input to the first voltage-current conversion circuit 51. Furthermore, in addition to the first mode selection signals p3 and p4, the third first mode selection signal p5 is also input to the first decoder 52.

[0149] The first voltage-current conversion circuit 51 changes the level of the bias power supply current IeC based on the difference between the divided voltage value Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold value Vth1 ).

[0150] Fig.15: is an equivalent circuit diagram of the first voltage-current conversion circuit 51. The first voltage-current conversion circuit 51 of the power amplifier device according to this embodiment includes, in addition to the first constant current source 57 and the first current mirror 58, a differential current generating circuit 80. The differential current generating circuit 80 generates a differential current Idif of a level corresponding to the difference between the power supply voltage Vcc and the first threshold value Vth1.

[0151] Next, the configuration and operation of the differential current generating circuit 80 will be described.

[0152] A current source is constituted by the third operational amplifier 81, the transistor 83, two resistors 84 connected in parallel, a switch 85 connected in series to each of the resistors 84, and the fourth operational amplifier 82. The switch 85 is turned on and off in accordance with the output of the first decoder 52.

[0153] A voltage corresponding to the difference between the divided voltage value Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold value Vth1) is applied to both ends of the resistor element 84. A current having a magnitude determined by the voltage corresponding to the difference between the divided voltage value Vccd of the power supply voltage Vcc and the first voltage Vd1 (corresponding to the first threshold value Vth1) (hereinafter referred to as the differential voltage) and the resistance value of the resistor element 84 flows through the transistor 83.

[0154] Transistors 83 and 87 form a current mirror. If switch 86 is turned on, the current mirror is activated and current flows to transistor 87. Switch 86 is controlled to be on and off according to the output of the first decoder 52. The current flowing through transistor 87 is output to the outside as a differential current Idif. The level of the differential current Idif increases linearly with respect to the differential voltage. In addition, the rate of change of the differential current Idif with respect to the differential voltage decreases as the resistance value of the resistor element 84 increases.

[0155] The differential current Idif acts to reduce the current generated by the first constant current source 57. Therefore, the level of the bias power supply current IeC decreases in accordance with the differential voltage. That is, as the differential voltage increases, the amount of decrease in the bias power supply current IeC increases.

[0156] Fig.16 1 is a graph showing the relationship between the first mode selection signals p3, p4, and p5, the bias power supply current IeC, and the current generation mode of the bias power supply circuit 50. When the first mode selection signal p5 is at an L level, the switch 86 becomes non-conductive and the differential current Idif does not flow. Therefore, the operation of the bias power supply circuit 50 is similar to that of the first embodiment ( Figure 4 ) is the same.

[0157] When the first mode selection signal p5 is at an H level and the first mode selection signals p3 and p4 are both at an L level, if the first detection signal det1 becomes an H level, the first decoder 52 turns on at least one of the switches 85 and 86. As a result, the level IeC2 of the bias power supply current IeC decreases in accordance with the differential voltage. This current generation mode is referred to as a "weak limit mode". In addition, in order to be consistent with the fixed limit mode ( Figure 4 ) and is sometimes called variable restriction mode.

[0158] Fig.17 The first mode selection signal p3 and p4 are both set to L level, p5 is set to H level, and the bias power supply circuit 50 operates in the variable limit mode, and the second mode selection signal p1 is set to H level, p2 is set to L level, and the bias circuit 30 is in the strong shutdown mode ( Figure 6 ) is a curve diagram showing the relationship between the power supply voltage Vcc and the power supply current Icc when operating under .

[0159] In the first embodiment Figure 7 In the example shown, when the power supply voltage Vcc is equal to or higher than the first threshold value Vth1, the level of the bias power supply current IeC drops to IeC2, which is a fixed value. Fig.17 In the example shown, when the power supply voltage Vcc becomes equal to or higher than the first threshold value Vth1 (the first detection signal det1 becomes H level), the level IeC2 of the bias power supply current IeC gradually and continuously decreases as the power supply voltage Vcc increases. The level Icc2 (hfe×IeC2) of the power supply current Icc also gradually and continuously decreases, for example, linearly.

[0160] When the power supply voltage Vcc further rises and becomes equal to or higher than the second threshold value Vth2 (the second detection signal det2 becomes H level), the bias control current IB becomes the off level Loff, and the supply of the bias power supply current IeC is stopped. Figure 1 ) stops zooming in.

[0161] Fig.18 The first mode selection signal p3 and p4 are both set to L level, p5 is set to H level, and the bias power supply circuit 50 operates in the variable limit mode, and the second mode selection signal p1 is set to L level, p2 is set to H level, and the bias circuit 30 is in the weak shutdown mode ( Figure 6 ) is a curve diagram showing the relationship between the power supply voltage Vcc and the power supply current Icc when operating under .

[0162] The relationship between the power supply voltage Vcc and the power supply current Icc when the power supply voltage Vcc is less than the second threshold value Vth2 is Fig.17When the power supply voltage Vcc becomes equal to or higher than the second threshold value Vth2 (the second detection signal det2 becomes H level), the bias control current IB becomes the low level Llow, and thus the level of the bias power supply current IeC drops to IccL.

[0163] Next, the excellent effects of the second embodiment will be described. In the second embodiment, as in the first embodiment, the power supply current Icc can be flexibly reduced and the amplification operation can be substantially stopped according to the characteristics of the power amplifier transistor 90. Furthermore, in the second embodiment, the bias power supply current Icc is gradually reduced as the power supply voltage Vcc rises, so that the safe operation region of the power amplifier transistor 90 can be used more effectively.

[0164] The above-mentioned embodiments are illustrative, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. The same effects brought about by the same structure of multiple embodiments are not mentioned one by one in each embodiment. Furthermore, the present invention is not limited to the above-mentioned embodiments. For example, various changes, improvements, combinations, etc. can be performed, which is obvious to those skilled in the art.

[0165] Based on the above-described embodiments described in this specification, the following inventions are disclosed.

[0166] <1>

[0167] A power amplifier device, comprising:

[0168] Power amplifier transistor, which amplifies the power of high-frequency signals;

[0169] a voltage detection circuit that outputs a first detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a first threshold value, and a second detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a second threshold value that is greater than the first threshold value;

[0170] A bias circuit supplies a bias current to the power amplifier transistor;

[0171] a bias power supply circuit that generates a bias power supply current to be supplied to the bias circuit; and

[0172] a bias control circuit, controlling the bias circuit,

[0173] The bias power supply circuit operates in any current generation mode among a plurality of current generation modes for generating the bias power supply current at different levels.

[0174] The plurality of current generation modes include a weak limiting mode, in which, when the power supply voltage is notified by the first detection signal to be above the first threshold, the bias power supply current is reduced compared to when the power supply voltage is notified to be below the first threshold,

[0175] The bias circuit receives control from the bias control circuit and operates in either an on mode or an off mode. In the on mode, the bias power supply current generated by the bias power supply circuit is supplied to the power amplifier transistor as the bias current. In the off mode, the bias current is supplied or stopped by reducing the level of the bias current compared to the on mode.

[0176] The bias control circuit can operate the bias circuit in the shutdown mode when the bias control circuit is informed by the second detection signal that the power supply voltage is equal to or higher than the second threshold value.

[0177] <2>

[0178] according to <1> The power amplifier device, wherein:

[0179] The weak limiting mode includes a fixed limiting mode in which the bias power supply current is reduced to a fixed level lower than the level of the bias power supply current when it is notified that the power supply voltage is lower than the first threshold value.

[0180] <3>

[0181] according to <1> or <2> The power amplifier device, wherein:

[0182] The weak limiting mode includes a variable limiting mode in which, as the power supply voltage increases, the amount of decrease in the level of the bias power supply current relative to the level of the bias power supply current when it is notified that the power supply voltage is less than the first threshold value is increased.

[0183] <4>

[0184] according to <2> The power amplifier device, wherein:

[0185] The bias power supply circuit comprises:

[0186] a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal;

[0187] a first constant current source that changes the level of a generated current according to the output from the first decoder; and

[0188] The first current mirror outputs the current generated by the first constant current source as the bias power supply current.

[0189] <5>

[0190] according to <2> The power amplifier device, wherein:

[0191] The bias power supply circuit comprises:

[0192] a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal;

[0193] A first constant current source; and

[0194] The first current mirror changes a magnification according to an output from the first decoder, and outputs the current generated by the first constant current source as the bias power supply current.

[0195] <6>

[0196] according to <2> The power amplifier device, wherein:

[0197] The bias power supply circuit comprises:

[0198] a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal;

[0199] A first constant current source; and

[0200] The first current mirror changes a magnification according to an output from the first decoder, and outputs the current generated by the first constant current source as the bias power supply current.

[0201] <7>

[0202] according to <3> The power amplifier device, wherein:

[0203] The bias power supply circuit comprises:

[0204] a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal;

[0205] a current source that changes a level of a generated current according to an output from the first decoder and a difference between the power supply voltage and the first threshold value; and

[0206] The first current mirror outputs the current generated by the current source as the bias power supply current.

[0207] <8>

[0208] according to <1> to <7> The power amplifier device according to any one of the preceding claims, wherein:

[0209] The plurality of current generation modes further include a non-limiting mode in which the bias power supply current is maintained at a fixed value regardless of a state of the first detection signal.

[0210] <9>

[0211] according to <1> to <8> The power amplifier device according to any one of the preceding claims, wherein:

[0212] The multiple current generation modes also include a strong limiting mode. In the strong limiting mode, if it is notified by the first detection signal that the power supply voltage is above the first threshold, the level of the bias power supply current is reduced to a level such that the power amplifier transistor does not perform an amplification operation.

[0213] <10>

[0214] according to <1> to <9> The power amplifier device according to any one of the preceding claims, wherein:

[0215] When the bias control circuit operates the bias circuit in the shutdown mode, the bias control circuit can operate the bias circuit in a strong shutdown mode in which supply of the bias current to the power amplifier transistor is stopped.

[0216] <11>

[0217] according to <1> to <10> The power amplifier device according to any one of the preceding claims, wherein:

[0218] When the bias control circuit causes the bias circuit to operate in the shutdown mode, the bias control circuit can cause the bias circuit to operate in a weak shutdown mode, in which the bias current after the level of the bias power supply current is reduced is supplied from the bias circuit to the power amplifier transistor.

[0219] <12>

[0220] according to <1> to <11> The power amplifier device according to any one of the preceding claims, wherein:

[0221] The voltage detection circuit comprises:

[0222] a first comparator that compares the power supply voltage with the first threshold value and outputs a comparison result as the first detection signal; and

[0223] The second comparator compares the power supply voltage with the second threshold value and outputs a comparison result as the second detection signal.

[0224] <13>

[0225] according to <1> to <12> The power amplifier device according to any one of the preceding claims, wherein:

[0226] The bias circuit includes: a bias transistor for supplying the bias current to the power amplifier transistor;

[0227] The emitter or source of the bias transistor is connected to the base or gate of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit.

[0228] <14>

[0229] according to <1> to <13> The power amplifier device according to any one of the preceding claims, wherein:

[0230] The bias control circuit comprises:

[0231] a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal;

[0232] a second constant current source that changes the level of a generated current according to the output from the second decoder; and

[0233] The second current mirror supplies the current generated by the second constant current source to the bias circuit.

[0234] <15>

[0235] according to <1> to <13> The power amplifier device according to any one of the preceding claims, wherein:

[0236] The bias control circuit comprises:

[0237] a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal;

[0238] a second constant current source; and

[0239] The second current mirror changes a magnification according to an output from the second decoder, and supplies the current generated by the second constant current source to the bias circuit.

Claims

1. A power amplifier device, comprising: Power amplifier transistor, which amplifies the power of high-frequency signals; a voltage detection circuit that outputs a first detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a first threshold value, and a second detection signal for notifying whether the power supply voltage applied to the power amplifier transistor is equal to or greater than a second threshold value that is greater than the first threshold value; A bias circuit supplies a bias current to the power amplifier transistor; a bias power supply circuit for generating a bias power supply current supplied to the bias circuit; and a bias control circuit, controlling the bias circuit, The bias power supply circuit operates in any current generation mode among a plurality of current generation modes for generating the bias power supply current at different levels. The plurality of current generation modes include a weak limiting mode, in which, when the power supply voltage is notified by the first detection signal to be above the first threshold, the bias power supply current is reduced compared to when the power supply voltage is notified to be below the first threshold, The bias circuit receives control from the bias control circuit and operates in either an on mode or an off mode. In the on mode, the bias power supply current generated by the bias power supply circuit is supplied to the power amplifier transistor as the bias current. In the off mode, the bias current is supplied or stopped by reducing the level of the bias current compared to the on mode. The bias control circuit can operate the bias circuit in the shutdown mode when the bias control circuit is informed by the second detection signal that the power supply voltage is equal to or higher than the second threshold value.

2. The power amplification device according to claim 1, wherein: The weak limiting mode includes a fixed limiting mode in which the bias power supply current is reduced to a fixed level lower than the level of the bias power supply current when it is notified that the power supply voltage is lower than the first threshold value.

3. The power amplifier device according to claim 1 or 2, wherein: The weak limiting mode includes a variable limiting mode in which, as the power supply voltage increases, the amount of decrease in the level of the bias power supply current relative to the level of the bias power supply current when it is notified that the power supply voltage is less than the first threshold value is increased.

4. The power amplifying device according to claim 2, wherein: The bias power supply circuit comprises: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; a first constant current source that changes the level of a generated current according to the output from the first decoder; and The first current mirror outputs the current generated by the first constant current source as the bias power supply current.

5. The power amplifying device according to claim 2, wherein: The bias power supply circuit comprises: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; A first constant current source; and The first current mirror changes a magnification according to an output from the first decoder, and outputs the current generated by the first constant current source as the bias power supply current.

6. The power amplifying device according to claim 3, wherein: The bias power supply circuit comprises: a first decoder for decoding a first mode selection signal for selecting the current generation mode and the first detection signal; a current source that changes a level of a generated current according to an output from the first decoder and a difference between the power supply voltage and the first threshold value; and The first current mirror outputs the current generated by the current source as the bias power supply current.

7. The power amplification device according to any one of claims 1 to 6, wherein: The plurality of current generation modes further include a non-limiting mode in which the bias power supply current is maintained at a fixed value regardless of a state of the first detection signal.

8. The power amplification device according to any one of claims 1 to 7, wherein: The multiple current generation modes also include a strong limiting mode. In the strong limiting mode, if it is notified by the first detection signal that the power supply voltage is above the first threshold, the level of the bias power supply current is reduced to a level such that the power amplifier transistor does not perform an amplification operation.

9. The power amplification device according to any one of claims 1 to 8, wherein: When the bias control circuit operates the bias circuit in the shutdown mode, the bias control circuit can operate the bias circuit in a strong shutdown mode in which supply of the bias current to the power amplifier transistor is stopped.

10. The power amplification device according to any one of claims 1 to 9, wherein: When the bias control circuit causes the bias circuit to operate in the shutdown mode, the bias control circuit can cause the bias circuit to operate in a weak shutdown mode, in which the bias current after the level of the bias power supply current is reduced is supplied from the bias circuit to the power amplifier transistor.

11. The power amplification device according to any one of claims 1 to 10, wherein: The voltage detection circuit comprises: a first comparator that compares the power supply voltage with the first threshold value and outputs a comparison result as the first detection signal; and The second comparator compares the power supply voltage with the second threshold value and outputs a comparison result as the second detection signal.

12. The power amplification device according to any one of claims 1 to 11, wherein: The bias circuit includes: a bias transistor for supplying the bias current to the power amplifier transistor; The emitter or source of the bias transistor is connected to the base or gate of the power amplifier transistor, the bias power supply current is supplied to the collector or drain of the bias transistor, and the control current of the bias transistor is controlled by the bias control circuit.

13. The power amplification device according to any one of claims 1 to 12, wherein: The bias control circuit comprises: a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal; a second constant current source that changes the level of a generated current according to the output from the second decoder; and The second current mirror supplies the current generated by the second constant current source to the bias circuit.

14. The power amplification device according to any one of claims 1 to 12, wherein: The bias control circuit comprises: a second decoder for decoding a second mode selection signal for selecting the operation mode of the bias circuit and the second detection signal; a second constant current source; and The second current mirror changes a magnification according to an output from the second decoder, and supplies the current generated by the second constant current source to the bias circuit.

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