DLL circuit to suppress clock jitter

Abstract

The present invention discloses a DLL circuit for suppressing clock jitter. To suppress clock jitter, the DLL circuit of the present invention includes a phase detector, a filter, a pulse generator and a delay line, wherein the delay line includes a first delay line and a second delay line; the pulse generator receives a reference clock, and when the pulse generator is enabled, generates an injection pulse and transmits it to the second delay line; the second delay line includes a first PMOS, a second PMOS and n PMOS connected in parallel, and the second delay line also includes a first NMOS, a second NMOS and n NMOS connected in parallel, where n is a positive integer; the second control code is used to control n PMOS or / and n NMOS; the gate of the first PMOS is connected to a common ground terminal voltage, and the gate of the first NMOS is connected to a device operating voltage; the gate of the second NMOS receives the injection pulse, and the gate of the second PMOS receives the inverted signal of the injection pulse. The present invention can suppress clock jitter and improve the quality of clock signals. The present invention is applicable to the field of integrated circuits.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a DLL circuit for suppressing clock jitter. Background Art

[0002] In some communication systems, there may be a phase error between the data sampling clock and the phase locked loop (PLL) output clock, which will result in insufficient margin of the sampling circuit during data sampling. In addition, the jitter of the sampling clock will be amplified during transmission.

[0003] In order to ensure the timing window during data sampling, a delay locked loop (DLL) is generally added between the PLL output clock and the sampling clock to adjust the phase of the sampling clock in real time to align it with the PLL output clock.

[0004] As a circuit for clock synchronization and phase adjustment, the delay-locked loop plays an important role in high-speed communication, memory interface, image processing and other fields. The delay-locked loop is a circuit for clock synchronization and phase adjustment. Similar to the phase-locked loop, the DLL is also used to achieve phase alignment of the clock signal, but its working principle and application scenarios are different.

[0005] DLL mainly adjusts the phase of the clock signal through a delay line, which includes a delay line, a phase detector and a control unit. For the delay line, the input clock signal passes through a series of adjustable delay units to generate a set of clock signals with different phases. For the phase detector, the phase difference between the input clock signal and the delay line output signal is compared. For the control unit, according to the comparison result of the phase detector, the delay amount of the delay line is adjusted to align the phase of the clock signal output by the delay line with the input clock signal.

[0006] Although traditional analog DLL can achieve good performance, it introduces large filter capacitors and occupies a large chip area, thus limiting its application in certain circuit scenarios.

[0007] Figure 1 The timing diagram of clock jitter is shown. In DLL, after the reference clock and the second clock are compared in phase, the edges of the second clock and the reference clock are aligned. However, there are still some non-ideal factors that cause clock jitter. The so-called clock jitter is the deviation of the actual clock from the ideal clock edge that does not accumulate over time and sometimes leads to or lags behind. This is called clock jitter. Figure 1 As shown.

[0008] In recent years, all-digital DLL circuits have gradually attracted the attention of researchers. However, due to power supply voltage fluctuations, the delay line in the all-digital DLL circuit will introduce large jitter, namely power supply induced jitter (PSIJ). Large jitter will affect the signal quality of the DLL output sampling clock, and then affect the eye diagram of the signal.

[0009] Therefore, it is very important to design a low-jitter DLL circuit. Summary of the invention

[0010] In order to alleviate or partially alleviate the above technical problems, the solution of the present invention is as follows:

[0011] A DLL circuit for suppressing clock jitter comprises a phase detector, a filter, a pulse generator and a delay line, wherein the delay line comprises a first delay line and a second delay line; the phase detector receives a reference clock and a second clock, and inputs the phase detection result to the filter, the filter outputs a first control code to the first delay line, and the filter also outputs a second control code to the second delay line; the pulse generator receives the reference clock, and when the pulse generator is enabled, generates an injection pulse and transmits it to the second delay line; the first delay line receives the first clock and outputs a third clock, and the second delay line receives the third clock and outputs the second clock; and the second delay line comprises a first PMOS, a second PMOS and n PMOS connected in parallel, and the second delay line further comprises a first NMOS, a second NMOS and n NMOS connected in parallel, wherein n is a positive integer; the second control code is used to control the n PMOS or / and the n NMOS; the gate of the first PMOS is connected to a common ground terminal voltage, and the gate of the first NMOS is connected to a device operating voltage; the gate of the second NMOS receives the injection pulse, and the gate of the second PMOS receives an inverted signal of the injection pulse.

[0012] Furthermore, the second delay line also includes a third NMOS and a third PMOS; the sources of the first PMOS, the second PMOS and the n PMOS in parallel are connected to the device operating voltage; the drains of the first PMOS, the second PMOS and the n PMOS in parallel are connected to the source of the third PMOS; the sources of the first NMOS, the second NMOS and the n NMOS in parallel are grounded; the drains of the first NMOS, the second NMOS and the n NMOS in parallel are connected to the source of the third NMOS; the drains of the third PMOS and the third NMOS are connected to the output node, and the output node outputs the second clock.

[0013] Furthermore, the third clock is connected to the gate of the third PMOS and the gate of the third NMOS.

[0014] Furthermore, the gate control signals of the n PMOS and the gate control signals of the n NMOS are inverted signals.

[0015] Further, the output node is connected to a first end of a capacitor, and a second end of the capacitor is grounded.

[0016] Further, the filter outputs an enable signal to the pulse generator.

[0017] Further, after receiving the enable signal, the pulse generator generates an injection pulse or does not block the injection pulse from being transmitted to the second delay line.

[0018] Furthermore, the pulse width of the injected pulse is smaller than the pulse width of the reference clock.

[0019] Further, the pulse generator generates the injection pulse according to a reference clock.

[0020] Further, when the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulse is at a high level.

[0021] The technical solution of the present invention has one or more of the following beneficial technical effects:

[0022] (1) Clock jitter can be suppressed.

[0023] (2) It avoids the use of high-precision phase detection circuits in traditional solutions, thereby saving circuit power consumption.

[0024] In addition, other beneficial effects of the present invention will be mentioned in the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a timing diagram of clock jitter;

[0026] Figure 2 It is a block diagram of a DLL circuit for suppressing clock jitter of the present invention;

[0027] Figure 3 is a circuit diagram of a second delay line of the present invention;

[0028] Figure 4 It is a timing diagram of eliminating clock jitter according to the present invention. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same or similar items with substantially the same functions and effects. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0031] Figure 2 The block diagram of the DLL circuit for suppressing clock jitter of the present invention is shown. The phase detector receives the reference clock and the second clock as inputs, and transmits the phase detection result of the reference clock and the second clock to the filter. The filter outputs a first control code to control the delay of the first delay line; the filter outputs a second control code to control the delay of the second delay line.

[0032] The delay line in the DLL circuit includes the first delay line and the second delay line. The delay line receives the first clock and outputs the second clock. The first delay line receives the first clock and outputs the third clock, and the second delay line receives the third clock and outputs the second clock.

[0033] In addition, the DLL circuit further includes a pulse generator, which receives a reference clock and outputs an injection pulse.

[0034] Preferably, the pulse generator further receives an enabling signal output by the filter, so that the pulse generator generates the injection pulse or does not block the injection pulse from being transmitted to the second delay line.

[0035] Furthermore, the first delay line is a coarse-tuning delay line, and the second delay line is a fine-tuning delay line.

[0036] Figure 3 The circuit diagram of the second delay line of the present invention is shown, which is a circuit structure with the function of eliminating burrs. The second delay line includes a plurality of N-channel Metal Oxide Semiconductors (NMOS) and a plurality of P-channel Metal Oxide Semiconductors (PMOS). The plurality of PMOS include a first PMOS, a second PMOS and a third PMOS; the plurality of NMOS include a first NMOS, a second NMOS and a third NMOS.

[0037] The second control code includes d <0> and its inverted signal d_n <0> d <1> and its inverted signal d_n <1> d <2> and its inverted signal d_n <2> ……、d <n>and its inverted signal d_n <n>. Where n is a positive integer.

[0038] Alternatively, the second control code includes d <0> d <1> d <2> ...and d <n>. The inverting signal d_n <0> , inverted signal d_n <1> ...and the inverted signal d_n <n>, can be respectively based on d through the inverter <0> d <1> ...and d <n>And obtained.

[0039] For example, the second delay line includes a first PMOS, a second PMOS and n PMOS connected in parallel, and the second delay line also includes a first NMOS, a second NMOS and n NMOS. The second control code is used to control the n PMOS and / or the n NMOS.

[0040] The gate of the first PMOS is connected to a common ground voltage (Voltage Source-to-Source, VSS). The gate of the first NMOS is connected to a device operating voltage (Voltage Drain-to-Drain, VDD).

[0041] In addition, n PMOSs among the plurality of PMOSs receive d <0> d <1> d <2> ...and d <n>. n NMOS in a plurality of NMOSs receive the inverted signal d_n respectively <0> , inverted signal d_n <1> ...and the inverted signal d_n <n>.

[0042] The gate of the second PMOS receives an inverted signal of the injection pulse, and the gate of the second NMOS receives the injection pulse.

[0043] Specifically, the first PMOS, the second PMOS and the n PMOS are connected in parallel, their sources are all connected to VDD, and their drains are all connected to the source of the third PMOS.

[0044] The first NMOS, the second NMOS and the n NMOS are connected in parallel, their sources are all grounded, and their drains are all connected to the source of the third NMOS.

[0045] The third clock is connected to the gates of the third PMOS and the third NMOS. The drain of the third PMOS and the drain of the third NMOS are connected to the output node, and the output node outputs the second clock.

[0046] In addition, the output node is also connected to a first end of the capacitor, and a second end of the capacitor is grounded.

[0047] Figure 4 The timing diagram of eliminating clock jitter of the present invention is shown. Before the injection pulse, the second clock has a relatively severe jitter. After the injection pulse, the clock jitter eventually gradually approaches 0, achieving the technical purpose of the present invention.

[0048] Further, the pulse generator may generate the injection pulse according to the reference clock.

[0049] Furthermore, the pulse width of the injected pulse is smaller than the pulse width of the reference clock.

[0050] Further, when the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulse is at a high level.

[0051] The first delay line is used to cover the delay required by the DLL, and the second delay line includes a circuit module for eliminating burrs in the clock signal. This embodiment helps to improve the quality of the second clock.

[0052] The present invention generates periodic injection pulses from a reference signal with low jitter and injects them into the control end of the delay unit in the second delay line, thereby suppressing the jitter caused by the power supply on the delay line and achieving a second clock output by the DLL with smaller jitter.

[0053] The relationship between the delay of the delay line and the power supply voltage is: t=Q / I=CU / I, where I is the current in the circuit, Q is the charge, t is the duration, C is the capacitance, and U is the voltage on the capacitor.

[0054] If the number of delay lines is larger, the delay variation caused by power supply ripple will also become larger.

[0055] In the present invention, the injected pulse is transmitted to the last stage in the delay line, thereby suppressing the influence of the power supply ripple on the jitter of the second clock to the greatest extent.

[0056] In the present invention, the normally-on first PMOS and the first NMOS can avoid glitches in the second clock when the second control code does not change synchronously.

[0057] The injection pulse is also injected into the gate of the second PMOS and the gate of the second NMOS at the same time, thereby generating an increase in the instantaneous charge amount to compensate for the delay variation caused by power supply fluctuation.

[0058] The present invention is suitable for application scenarios requiring zero-delay clock buffers such as double data rate synchronous dynamic random access memory (DDR SDRAM), serializer / deserializer (Serdes) circuits, and can also be applied to certain clock distribution systems requiring low jitter and systems requiring adjustment of fixed delays.

[0059] In order to better illustrate the present invention, numerous specific details are provided in the above specific embodiments. It should be understood by those skilled in the art that the present invention can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present invention.

[0060] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.< / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

1. A DLL circuit for suppressing clock jitter, characterized in that: comprising a phase detector, a filter, a pulse generator and a delay line, wherein the delay line comprises a first delay line and a second delay line; The phase detector receives a reference clock and a second clock, and inputs a phase detection result to the filter, the filter outputs a first control code to the first delay line, and the filter also outputs a second control code to the second delay line; The pulse generator receives a reference clock and generates an injection pulse and transmits it to the second delay line when the pulse generator is enabled; The first delay line receives the first clock and outputs the third clock, the second delay line receives the third clock and outputs the second clock; and, The second delay line includes a first PMOS, a second PMOS and n PMOS connected in parallel, and the second delay line also includes a first NMOS, a second NMOS and n NMOS connected in parallel, where n is a positive integer; The second control code is used to control the n PMOS and / or the n NMOS; The gate of the first PMOS is connected to a common ground voltage, and the gate of the first NMOS is connected to a device operating voltage; A gate of the second NMOS receives the injection pulse, and a gate of the second PMOS receives an inverted signal of the injection pulse.

2. The DLL circuit for suppressing clock jitter according to claim 1, characterized in that: The second delay line further includes a third NMOS and a third PMOS; The sources of the first PMOS, the second PMOS and the n PMOS connected in parallel are connected to the device operating voltage; The drains of the first PMOS, the second PMOS and the n PMOS connected in parallel are connected to the source of the third PMOS; The sources of the first NMOS, the second NMOS and the n NMOS connected in parallel are grounded; The drains of the first NMOS, the second NMOS and the n NMOS connected in parallel are connected to the source of the third NMOS; The drain of the third PMOS and the drain of the third NMOS are connected to an output node, and the output node outputs a second clock.

3. The DLL circuit for suppressing clock jitter according to claim 2, characterized in that: The third clock is connected to the gate of the third PMOS and the gate of the third NMOS.

4. The DLL circuit for suppressing clock jitter according to claim 3, characterized in that: The gate control signals of the n PMOS and the gate control signals of the n NMOS are inverted signals.

5. The DLL circuit for suppressing clock jitter according to claim 4, characterized in that: The output node is connected to a first end of the capacitor, and a second end of the capacitor is grounded.

6. The DLL circuit for suppressing clock jitter according to claim 5, characterized in that: The filter outputs an enable signal to the pulse generator.

7. The DLL circuit for suppressing clock jitter according to claim 6, characterized in that: After receiving the enabling signal, the pulse generator generates an injection pulse or does not block the injection pulse from being transmitted to the second delay line.

8. The DLL circuit for suppressing clock jitter according to claim 7, characterized in that: The pulse width of the injected pulse is smaller than the pulse width of the reference clock.

9. The DLL circuit for suppressing clock jitter according to claim 8, characterized in that: The pulse generator generates an injection pulse according to a reference clock.

10. The DLL circuit for suppressing clock jitter according to claim 9, characterized in that: When the rising edge of the reference clock and the rising edge of the second clock appear, the injection pulse is at a high level.

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