Semiconductor memory device

Abstract

The invention relates to a semiconductor memory device. The semiconductor memory device includes: a substrate including a peripheral circuit; a gate stack structure disposed on the substrate and including a cell array region and a step region extending from the cell array region; a channel structure passing through the cell array region of the gate stack structure; a memory layer surrounding sidewalls of the channel structure; a first contact plug passing through the step region of the gate stack structure; and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202010710334.3 (application date: July 22, 2020, invention name: semiconductor memory device and method for manufacturing the semiconductor memory device). Technical Field

[0002] Various embodiments generally relate to a semiconductor memory device and a method for manufacturing the semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device and a method for manufacturing the three-dimensional semiconductor memory device. Background Art

[0003] A semiconductor memory device may include a memory cell array and a peripheral circuit coupled to the memory cell array. The memory cell array may include a plurality of memory cells, and the peripheral circuit may be configured to perform various operations of the memory cells.

[0004] A plurality of memory cells may be arranged three-dimensionally to form a three-dimensional semiconductor memory device. In the three-dimensional semiconductor memory device, the gates of the memory cells may be connected to a plurality of word lines stacked on a substrate. In order to increase the integration density of the three-dimensional semiconductor memory device, the number of word lines stacked on top of each other may be increased. The more word lines stacked on top of each other, the more complicated the manufacturing process of the semiconductor memory device may become. Summary of the invention

[0005] According to one embodiment, a semiconductor memory device may include: a substrate including a peripheral circuit; a gate stack structure disposed on the substrate and including a cell array region and a stepped region extending from the cell array region; a channel structure passing through the cell array region of the gate stack structure; a memory layer surrounding a side wall of the channel structure; a first contact plug passing through the stepped region of the gate stack structure; and an insulating structure surrounding a side wall of the first contact plug to insulate the first contact plug from the gate stack structure.

[0006] According to one embodiment, a method for manufacturing a semiconductor memory device may include the following steps: forming a preliminary structure including a first semiconductor pattern and a second semiconductor pattern separated from each other by an insulating layer; forming a stacked structure on the preliminary structure, the stacked structure including an interlayer insulating layer and a sacrificial layer alternately stacked on each other; forming a channel hole and a first contact hole passing through the stacked structure; forming a memory layer on a surface of each of the channel hole and the first contact hole; filling the channel hole with a channel structure; forming a first contact plug in the first contact hole; and replacing the sacrificial layer with a conductive pattern. The channel hole may overlap with the first semiconductor pattern, and the first contact hole may overlap with the second semiconductor pattern. The first contact plug may pass through the memory layer and the second semiconductor pattern in the first contact hole. The conductive pattern may surround the channel structure and the first contact plug, and interpose the memory layer between each conductive pattern and each of the channel structure and the first contact plug. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram showing a configuration of a semiconductor memory device according to an embodiment;

[0008] Figure 2 is a diagram showing a cell array region and a step region of a semiconductor memory device according to one embodiment;

[0009] FIG. 3A to FIG. 3C is along Figure 2 Cross-sectional views taken along lines II-I', II-II' and III-III' are shown;

[0010] Figure 4 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment;

[0011] Figure 5A is a diagram showing a memory string according to one embodiment, and Figure 5B is a diagram showing a memory layer according to one embodiment;

[0012] Figure 6 is a cross-sectional view showing a lower structure of a semiconductor memory device according to an embodiment;

[0013] Figure 7 is a flow chart schematically illustrating a method of manufacturing a semiconductor memory device according to one embodiment;

[0014] FIG. 8A to FIG. 8C Is to show about Figure 7 A cross-sectional view of an embodiment of step ST1 is shown;

[0015] FIG. 9A to FIG. 9J Is to show about Figure 7A cross-sectional view of an embodiment of step ST3 is shown;

[0016] FIG. 10A to FIG. 10K Is to show about Figure 7 A cross-sectional view of an embodiment of step ST5 is shown;

[0017] FIG. 11A to FIG. 11C Is to show about Figure 7 A cross-sectional view of an embodiment of step ST7 is shown;

[0018] Fig. 12A , Fig. 12B , Fig.13 , Fig.14A and Fig. 14B Is to show about Figure 7 A cross-sectional view of one embodiment of a process performed after step ST7 is shown;

[0019] Fig.15 is a block diagram showing a configuration of a memory system according to one embodiment; and

[0020] Fig.16 is a block diagram showing a configuration of a computing system according to one embodiment. DETAILED DESCRIPTION

[0021] The specific structural description or functional description disclosed herein is only exemplary for describing the embodiments of the concepts according to the present disclosure. The embodiments can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0022] Various embodiments relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device capable of simplifying a manufacturing process of the semiconductor memory device.

[0023] Figure 1 is a schematic diagram showing a configuration of a semiconductor memory device according to an embodiment.

[0024] Reference Figure 1 , the semiconductor memory device may include a Figure 6 The peripheral circuit and memory cell array on the substrate 201 shown in the figure include a first area A1 and a second area A2. The first area A1 can be defined as an area overlapping with the gate stack structure GST forming the memory cell array. The second area A2 can be defined as an area not overlapping with the gate stack structure GST.

[0025] although Figure 1Although not shown in the figure, the peripheral circuit may include a row decoder, a page buffer, a control logic, etc. The row decoder, the page buffer, and the control logic may include a transistor TR. A first group of transistors in the transistor TR included in the peripheral circuit may be disposed in the second area A2 of the substrate. A second group of transistors in the transistor TR included in the peripheral circuit may be disposed in the first area A1 of the substrate and may overlap with the gate stack structure GST. The gate 213 of each transistor TR may be disposed in an active area ACT defined in the substrate. Figure 6 The illustrated junctions JN serving as the source and drain of each transistor TR may be formed in the active region ACT at opposite sides of the gate 213 .

[0026] The gate stack structures GST may be separated from each other by slits SI. Each gate stack structure GST may include a cell array region CAR and a step region STA. The step region STA may extend from the cell array region CAR. According to one embodiment, each gate stack structure GST may include two or more cell array regions CAR and a step structure STA disposed between adjacent cell array regions CAR. However, the embodiment is not limited thereto. For example, the step structure STA of each gate stack structure GST may be disposed at an edge of the gate stack structure GST corresponding to the step structure STA.

[0027] The stair structure STA may include a first contact region CA1 and a second contact region CA2. The stair structure of the gate stack structure GST may be connected to Figure 2 The gate contact plug GCT shown is disposed in the first contact region CA1 corresponding to the staircase structure. The staircase structure of the gate stack structure GST may be Figure 2 The first contact plug PCT1 shown penetrates and is disposed in the second contact area CA2 corresponding to the stepped structure.

[0028] The cell array region CAR may include a Figure 5A The multiple word lines WL and Figure 5A The memory strings may be coupled to bit lines BL disposed on the gate stack structure GST.

[0029] According to one embodiment, the transistor TR disposed in the second area A2 may overlap with a dummy stack structure disposed at the same level as the gate stack structure GST. According to one embodiment, the dummy stack structure may be omitted.

[0030] Figure 2 is a diagram showing a cell array region CAR and a step region STA of a semiconductor memory device according to an embodiment.

[0031] Reference Figure 2 , the channel structure CH may penetrate the cell array region CAR of the gate stack structure GST. The cell array region CAR of the gate stack structure GST may extend in the first direction D1 and the second direction D2. The channel structure CH may extend in a third direction D3 orthogonal to a plane extending in the first direction D1 and the second direction D2. According to one embodiment, the first direction D1, the second direction D2, and the third direction D3 may correspond to the x-axis, the y-axis, and the z-axis of a Cartesian coordinate system.

[0032] The memory layer 81 may surround the sidewalls of each channel structure CH. The channel structure CH may be disposed in a gate stack structure GST corresponding to the channel structure. The channel structure CH may be arranged in a zigzag shape. The array of the channel structure is not limited thereto. In one embodiment, the array of the channel structure CH may form a matrix structure. Each channel structure CH may have one of various cross-sectional shapes including but not limited to a circular, elliptical, polygonal or square.

[0033] The channel structure CH may be disposed at opposite sides of the upper slit USI formed in the gate stack structure GST. The upper slit USI and the slit SI may extend in the first direction D1 and the third direction D3.

[0034] The stepped structure STA of the gate stack structure GST may include a first contact region CA1 coupled to the gate contact plug GCT and a second contact region CA2 penetrated by the first contact plug PCT1, as shown in FIG. Figure 1 The semiconductor memory device may further include a supporting pillar SP passing through the step area STA of the gate stack structure GST.

[0035] Each of the gate contact plug GCT, the support pillar SP, and the first contact plug PCT1 may have one of various cross-sectional shapes including but not limited to an ellipse, a polygon, or a square. The arrangement of the gate contact plug GCT, the support pillar SP, and the first contact plug PCT1 is not limited to Figure 2 In the plane extending along the first direction D1 and the second direction D2, an area of ​​each of the support pillars SP and the first contact plugs PCT1 may be greater than an area of ​​each of the channel structures CH.

[0036] The gate contact plug GCT may overlap the step area STA and may extend in the third direction D3. The first insulating structure IS1 may surround the sidewall of each first contact plug PCT1. Each first contact plug PCT1 may be insulated from the gate stack structure GST by the first insulating structure IS1. The first dummy memory layer 81d1 may surround the sidewall of each support pillar SP. The first dummy memory layer 81d1 may include the same material as the memory layer 81.

[0037] FIG. 3A to FIG. 3C is along Figure 2 Cross-sectional views taken along lines II', II-II' and III-III' are shown.

[0038] Reference FIG. 3A to FIG. 3C , the gate stack structure GST may include interlayer insulating layers 41 and 63 and conductive patterns CP1 to CPn alternately stacked on each other, where n is a natural number. The conductive patterns CP1 to CPn may be stacked to be separated from each other in the third direction D3 by the interlayer insulating layer 41 or 63 disposed therebetween. The conductive patterns CP1 to CPn may include various conductive materials, such as doped semiconductors, metals, and conductive metal nitrides. Each of the conductive patterns CP1 to CPn may include one conductive material or two or more conductive materials. The interlayer insulating layers 41 and 63 may include a silicon oxide layer.

[0039] Each channel structure CH passing through the gate stack structure GST may be separated from the conductive patterns CP1 to CPn by the memory layer 81. Each support pillar SP passing through the gate stack structure GST may be separated from the conductive patterns CP1 to CPn by the first dummy memory layer 81d1.

[0040] Each support column SP may include the same material as that of each channel structure CH. According to one embodiment, each of the channel structure CH and the support column SP may include a channel layer 83, a core insulation pattern 85 and a capping pattern 91. The channel layer 83 may be formed on the memory layer 81 or the first dummy memory layer 81d1 corresponding to the channel layer 83, and may include a semiconductor material. For example, the channel layer 83 may include silicon. The channel layer 83 of each channel structure CH may be used as a channel of a memory string. The core insulation pattern 85 and the capping pattern 91 may fill the central area of ​​the channel layer 83. The core insulation pattern 85 may include an oxide. The capping pattern 91 may be disposed on the core insulation pattern 85 and may have a sidewall surrounded by the upper end of the channel layer 83. The capping pattern 91 may include a doped semiconductor layer including at least one of an n-type impurity and a p-type impurity. For example, the capping pattern 91 may include a doped silicon layer. According to one embodiment, the core insulation pattern 85 may be omitted, and the channel layer 83 may fill a central region of the memory layer 81 or the first dummy memory layer 81 d 1 corresponding to the channel layer 83 .

[0041] A gate stack structure GST may be separated from another gate stack structure GST adjacent thereto by a slit SI. In the third direction D3, the depth of the upper slit USI passing through the upper portion of the gate stack structure GST may be less than the depth of the slit SI. According to one embodiment, the upper slit USI may be deep enough to pass through at least the uppermost conductive pattern CPn among the conductive patterns CP1 to CPn. However, the embodiment is not limited thereto. For example, the upper slit USI may pass through one or more conductive patterns successively arranged below the nth conductive pattern CPn. The conductive patterns (e.g., CPn) penetrated by the upper slit USI may be divided into selection lines. Used as Figure 5A The conductive pattern of the word line WL shown may not be penetrated by the upper slit USI.

[0042] The first contact plug PCT1 may pass through the stepped structure of the gate stack structure GST. The first insulating structure IS1 surrounding each of the first contact plugs PCT1 may include a second dummy memory layer 81d2 including the same material as the memory layer 81. The first insulating structure IS1 may further include an oxide layer 95 disposed between the second dummy memory layer 81d2 and the first contact plug PCT1 corresponding to the second dummy memory layer 81d2.

[0043] Each of the channel structure CH, the support pillar SP and the first contact plug PCT1 may be formed in a hole passing through the gate stack structure GST. According to one embodiment, the hole may have a structure in which a lower hole and an upper hole are coupled together. The lower hole may be defined as a portion of the first stack structure G1 passing through the lower portion of the gate stack structure GST, and the upper hole may be defined as a portion of the second stack structure G2 passing through the upper portion of the gate stack structure GST. The interlayer insulating layers 41 and 63 may be divided into a first interlayer insulating layer 41 included in the first stack structure G1 and a second interlayer insulating layer 63 included in the second stack structure G2. The conductive patterns CP1 to CPn may include a first group of conductive patterns (CP1 to CPk) included in the first stack structure G1 and a second group of conductive patterns (CPk+1 to CPn) included in the second stack structure G2, where k is a natural number less than n. The lower hole may be deep enough to pass through the first stack structure G1, and the upper hole may be deep enough to pass through the second stack structure G2. The etching process for forming each of the lower hole and the upper hole may be easier than the etching process for forming a hole having a depth passing through both the first stack structure G1 and the second stack structure G2. When the lower hole and the upper hole are formed separately as described above, an undercut region may be defined at a boundary between the lower hole and the upper hole. The embodiment is not limited to the structure in which the undercut region is defined at the boundary between the lower hole and the upper hole, and the sidewall of each of the channel structure CH, the support pillar SP, and the first contact plug PCT1 may be substantially flat.

[0044] The conductive patterns CP1 to CPn of the gate stack structure GST may be coupled to the gate contact plugs GCT. The gate contact plugs GCT may be respectively coupled to portions of the conductive patterns CP1 to CPn forming the step structure, and may extend in the third direction D3.

[0045] The rise defined by the step structure may be covered by a gap-filling insulating structure. The gap-filling insulating structure may include a first gap-filling insulating layer 50 covering the rise defined by the first stacked structure G1 and a second gap-filling insulating layer 68 covering the rise defined by the second stacked structure G2. The gap-filling insulating structure and the gate stacked structure GST may be covered by an upper insulating layer 99. The channel structure CH may extend through the upper insulating layer 99. Each of the support pillar SP, the gate contact plug GCT, and the first contact plug PCT1 may pass through the upper insulating layer 99 and the first gap-filling insulating layer 50 and the second gap-filling insulating layer 68 of the gap-filling insulating structure.

[0046] The gate stack structure GST may be disposed on the semiconductor patterns 20A and 20B separated from each other by the insulating layer 35. The semiconductor patterns 20A and 20B may include a first semiconductor pattern 20A and a second semiconductor pattern 20B.

[0047] Each of the first semiconductor pattern 20A and the second semiconductor pattern 20B may include a first semiconductor layer 21 and a second semiconductor layer 29. The second semiconductor layer 29 may be spaced apart from the first semiconductor layer 21 and may extend along the bottom surface of the gate stack structure GST. The first semiconductor pattern 20A may include a channel coupling pattern 121 disposed between the first semiconductor layer 21 and the second semiconductor layer 29 corresponding to the first semiconductor pattern 20A, and each of the second semiconductor patterns 20B may include a sacrificial stack structure SA disposed between the first semiconductor layer 21 and the second semiconductor layer 29. The sacrificial stack structure SA may include a first protective layer 23, a sacrificial layer 25, and a second protective layer 27 sequentially stacked on the first semiconductor layer 21.

[0048] The first semiconductor layer 21 and the channel coupling pattern 121 may include n-type or p-type impurities. According to one embodiment, the channel coupling pattern 121 and the first semiconductor layer 21 including n-type impurities may be used for a GIDL erase method that performs an erase operation by using gate induced drain leakage (GIDL). According to one embodiment, the channel coupling pattern 121 and the first semiconductor layer 21 including p-type impurities may be used for a well erase method that performs an erase operation by supplying holes. The second semiconductor layer 29 may be an undoped semiconductor layer or a doped semiconductor layer including the same type of impurities as the first semiconductor layer 21 and the channel coupling pattern 121. The sacrificial layer 25 may include a material having a different etching rate from the first protective layer 23 and the second protective layer 27 to selectively etch the sacrificial layer 25. For example, the sacrificial layer 25 may include an undoped silicon layer. Each of the first protective layer 23 and the second protective layer 27 may include an oxide layer.

[0049] The first semiconductor pattern 20A may extend to overlap the slit SI and the channel structure CH. The slit SI may pass through the second semiconductor layer 29 of the first semiconductor pattern 20A. An oxide layer 125 may be formed between the slit SI and the first semiconductor pattern 20A.

[0050] The first semiconductor pattern 20A may extend to overlap the support pillar SP. The first semiconductor pattern 20A may overlap a portion of the step structure penetrated by the support pillar SP.

[0051] The channel structure CH and the support pillars SP may extend into the first semiconductor pattern 20A. According to one embodiment, the channel structure CH and the support pillars SP may extend into the first semiconductor layer 21 of the first semiconductor pattern 20A.

[0052] The memory layer 81 may be divided into a first memory pattern P1 and a second memory pattern P2. The first memory pattern P1 may be disposed between a channel structure CH corresponding to the first memory pattern P1 and the first semiconductor layer 21 of the first semiconductor pattern 20A, and the second memory pattern P2 may be disposed between the channel structure CH corresponding to the second memory pattern P2 and the gate stack structure GST.

[0053] The first dummy memory layer 81d1 may be divided into a first dummy pattern P1d and a second dummy pattern P2d. The first dummy pattern P1d may be disposed between a support pillar SP corresponding to the first dummy pattern P1d and the first semiconductor layer 21 of the first semiconductor pattern 20A, and the second dummy pattern P2d may be disposed between the support pillar SP corresponding to the second dummy pattern P2d and the gate stack structure GST.

[0054] The first semiconductor layer 21 of the first semiconductor pattern 20A may surround the lower portion of each channel structure CH and the lower portion of each support pillar SP. The second semiconductor layer 29 of the first semiconductor pattern 20A may extend along the bottom surface of the gate stack structure GST to surround the channel structure CH and the support pillar SP. The channel coupling pattern 121 may extend between the first memory pattern P1 and the second memory pattern P2 to contact the channel structure CH. The channel coupling pattern 121 may extend between the first dummy pattern P1d and the second dummy pattern P2d to contact the support pillar SP.

[0055] The first contact plug PCT1 may penetrate the second semiconductor pattern 20B. The width of each second semiconductor pattern 20B may be greater than the width of the first contact plug PCT1. The first semiconductor layer 21, the first protective layer 23, the sacrificial layer 25, the second protective layer 27, and the second semiconductor layer 29 of each second semiconductor pattern 20B may surround the first contact plug PCT1. Each first contact plug PCT1 may pass through the first insulating structure IS1 and may extend further than the first insulating structure IS1.

[0056] A first vertically doped semiconductor pattern 31A may be formed on a sidewall of the first semiconductor pattern 20A, and a second vertically doped semiconductor pattern 31B may be formed on a sidewall of each second semiconductor pattern 20B. The first vertically doped semiconductor pattern 31A and the second vertically doped semiconductor pattern 31B may include n-type or p-type impurities. According to one embodiment, the first vertically doped semiconductor pattern 31A and the second vertically doped semiconductor pattern 31B may include the same type of impurities as the first semiconductor layer 21.

[0057] The semiconductor patterns 20A and 20B may be disposed on the lower insulating layer 10 penetrated by the lower contact plugs 11A and 11B. The lower contact plugs 11A and 11B may include a first lower contact plug 11A coupled to the first semiconductor pattern 20A and a second lower contact plug 11B coupled to the first contact plug PCT1.

[0058] The first semiconductor pattern 20A and the first vertically doped semiconductor pattern 31A may overlap the first lower contact plug 11A, and each first contact plug PCT1 and each second semiconductor pattern 20B may overlap the second lower contact plug 11B. Each first contact plug PCT1 may pass through the second semiconductor pattern 20B to contact the second lower contact plug 11B.

[0059] Figure 4 is a cross-sectional view showing a portion of a semiconductor memory device according to an embodiment. Figure 4 The portion of the semiconductor memory device shown may be Figure 1 The second area A2 is shown overlapping.

[0060] Reference Figure 4 , refer to FIG. 3A to FIG. 3C The lower insulating layer 10 and the insulating layer 35 described above may be extended to the same Figure 1 The second area A2 described overlaps.

[0061] The lower contact plugs passing through the lower insulating layer 10 may further include third lower contact plugs 11C. The semiconductor patterns divided by the insulating layer 35 may further include third semiconductor patterns 20C.

[0062] The third semiconductor pattern 20C may be Figure 3BThe second semiconductor pattern 20B shown includes the same material. The third semiconductor pattern 20C may include a first semiconductor layer 21, a first protective layer 23, a sacrificial layer 25, a second protective layer 27, and a second semiconductor layer 29 sequentially stacked on each other. The third semiconductor pattern 20C may overlap with the third lower contact plug 11C. The third vertically doped semiconductor pattern 31C may be formed on the sidewall of the third semiconductor pattern 20C. The third vertically doped semiconductor pattern 31C may include the same type of impurities as the first semiconductor layer 21.

[0063] The third semiconductor pattern 20C and the third vertical doped semiconductor pattern 31C may be covered by a dummy stack structure DST. The dummy stack structure DST may include dummy interlayer insulating layers 41d and 63d and sacrificial layers 43 and 61 alternately stacked on the third semiconductor pattern 20C and the third vertical doped semiconductor pattern 31C. The dummy interlayer insulating layers 41d and 63d may be overlapped with the reference Figures 3A to 3C The interlayer insulating layers 41 and 63 described above include the same material, and the dummy interlayer insulating layer 41d may be disposed at the same level as the interlayer insulating layer 41, and the dummy interlayer insulating layer 63d may be disposed at the same level as the interlayer insulating layer 63. The sacrificial layers 43 and 61 may be disposed at the same level as the reference layers 41 and 63, respectively. FIG. 3A to FIG. 3C The sacrificial layers 43 and 61 may include a material having a different etching rate from the dummy interlayer insulating layers 41d and 63d to selectively etch the sacrificial layers 43 and 61. For example, each of the sacrificial layers 43 and 61 may include a nitride layer.

[0064] The second contact plug PCT2 may penetrate the dummy stack structure DST and the third semiconductor pattern 20C. The second contact plug PCT2 may extend to contact the third lower contact plug 11C.

[0065] The second insulating structure IS2 may surround the sidewall of the second contact plug PCT2. Figure 3B The first insulating structure IS1 described above includes the same material. According to one embodiment, the second insulating structure IS2 may include Figure 3A and Figure 3B The illustrated memory layer 81 has a third dummy memory layer 81d3 of the same material, and an oxide layer 95 disposed between the third dummy memory layer 81d3 and the second contact plug PCT2.

[0066] The second contact plug PCT2 may be formed in a hole passing through the dummy stack structure DST. The hole may be formed by a lower hole forming process passing through the lower stack structure 40 forming the lower portion of the dummy stack structure DST and by an upper hole forming process passing through the upper stack structure 60 forming the upper portion of the dummy stack structure DST. According to the embodiment, an undercut region may be defined at a boundary between the lower hole and the upper hole. The embodiment is not limited to a structure in which the undercut region is defined at a boundary between the lower hole and the upper hole, and the sidewall of the second contact plug PCT2 may be substantially flat. The embodiment is not limited to a method of manufacturing a hole by a lower hole forming process and an upper hole forming process.

[0067] Reference FIG. 3A to FIG. 3C The depicted upper insulating layer 99 may extend to cover the dummy stack structure DST, and may be penetrated by the second contact plug PCT2. The width of the third semiconductor pattern 20C may be greater than the width of the second contact plug PCT2.

[0068] FIG. 3A to FIG. 3C and Figure 4 The illustrated first, second, and third lower contact plugs 11A, 11B, and 11C and the first and second contact plugs PCT1 and PCT2 may include various conductive materials capable of transmitting electrical signals.

[0069] Figure 5A is a diagram showing a memory string according to one embodiment, and Figure 5B is a diagram showing a memory layer according to one embodiment.

[0070] Reference Figure 5A , the memory string may be connected to a plurality of word lines WL and selection lines SSL and DSL. The selection lines SSL and DSL may include at least one source selection line SSL and at least one drain selection line DSL. The word line WL may be disposed between the source selection line SSL and the drain selection line DSL. The source selection line SSL may be connected to the gate of the source selection transistor, the drain selection line DSL may be connected to the gate of the drain selection transistor, and the word line WL may be connected to the gate of the memory cell.

[0071] Reference FIG. 3A to FIG. 3CThe described conductive patterns CP1 to CPn may form a source selection line SSL, a word line WL, and a drain selection line DSL. According to one embodiment, among the conductive patterns CP1 to CPn, the first conductive pattern CP1 adjacent to the first semiconductor pattern 20A may be used as a source selection line SSL, and the nth conductive pattern CPn disposed farthest from the first semiconductor pattern 20A may be used as a drain selection line DSL. The conductive pattern between the source selection line SSL and the drain selection line DSL may be used as a word line WL. According to one embodiment, one or more conductive patterns successively disposed above the first conductive pattern CP1 may be used as another source selection line, and one or more conductive patterns successively disposed below the nth conductive pattern CPn may be used as another drain selection line.

[0072] According to the above structure, a drain selection transistor may be formed at the intersection of the drain selection line DSL and the channel structure CH, a source selection transistor may be formed at the intersection of the source selection line SSL and the channel structure CH, and a memory cell may be formed at the intersection of the word line WL and the channel structure CH. The memory cell may be connected in series between the source selection transistor and the drain selection transistor through the channel layer 83 of the channel structure CH. The source selection transistor may be connected to the channel connection pattern 121 of the first semiconductor pattern 20A through the channel layer 83. The capping pattern 91 of the channel structure CH may serve as a junction of the drain selection transistor.

[0073] The memory layer 81 may extend between each of the first semiconductor layer 21 and the second semiconductor layer 29 of the first semiconductor pattern 20A and the channel structure CH. Figure 5B As shown, each of the first memory pattern P1 and the second memory pattern P2 of the memory layer 81 may include a tunneling insulating layer TI, a data storage layer DL, and a blocking insulating layer BI.

[0074] Figure 5B A cross section of the memory layer 81 surrounding the channel layer 83 is shown.

[0075] Reference Figure 5B , the central area of ​​the memory layer 81 may be filled with Figure 5A The channel layer 83, the core insulation pattern 85 and the capping pattern 91 are shown. The tunneling insulation layer TI of the memory layer 81 may surround the channel layer 83, the data storage layer DL of the memory layer 81 may surround the tunneling insulation layer TI, and the blocking insulation layer BI of the memory layer 81 may surround the data storage layer DL.

[0076] The data storage layer DL may include a material layer capable of storing data changed by using Fowler-Nordheim tunneling. The data storage layer DL may include various materials, such as a charge trapping layer. The charge trapping layer may include a nitride layer. The embodiment is not limited thereto, and the data storage layer DL may include a phase change material or nanodots, etc. The blocking insulating layer BI may include an oxide layer capable of blocking charges. The tunneling insulating layer TI may include a silicon oxide layer that enables charge tunneling.

[0077] Figure 3A The first dummy memory layer 81d1, Figure 3B The second dummy memory layer 81d2 and Figure 4 Each of the illustrated third dummy memory layers 81d3 may include the same material layer as the above-described tunneling insulating layer TI, the data storage layer DL, and the blocking insulating layer BI.

[0078] Figure 6 is a cross-sectional view showing a lower structure LS of a semiconductor memory device according to an embodiment.

[0079] Reference Figure 6 , the lower structure LS may be disposed between the substrate 201 including the first area A1 and the second area A2 and the lower insulating layer 10 penetrated by the first lower contact plug 11A, the second lower contact plug 11B, and the third lower contact plug 11C.

[0080] The lower structure LS may include a plurality of transistors TR, a discharge impurity region DCI, and an interconnection structure 221. The plurality of transistors TR may be formed on an active region. The active region and the discharge impurity region DCI may be separated from each other by an isolation layer 203 formed in a substrate 201. The interconnection structure 221 may be connected to the transistor TR and the discharge impurity region DCI. The discharge impurity region DCI and the transistor TR may be covered by an insulating layer stacking structure 220 in which two or more insulating layers are stacked, and the interconnection structure 221 may pass through the insulating layer stacking structure 220.

[0081] A discharge impurity region DCI may be formed in the substrate 201. The discharge impurity region DCI may be connected to the first lower contact plug 11A via an interconnection structure 221 corresponding to the discharge impurity region DCI. The discharge impurity region DCI may be provided to discharge charges accumulated in the first semiconductor pattern 20A.

[0082] Each transistor TR may include a gate insulating layer 211, a gate 213, and a junction JN. The gate insulating layer 211 and the gate 213 of each transistor TR may be stacked on the active region. The junction JN of the transistor TR may be formed by implanting n-type or p-type impurities into the active region protruding on opposite sides of the corresponding gate 213.

[0083] Each of the first contact plugs PCT1 passing through the step area STA of the gate stack structure GST may be connected to the transistor TR via the second lower contact plug 11B and the interconnection structure 221 .

[0084] The transistors disposed in the second region A2 among the transistors TR may be connected to the second contact plug PCT2 passing through the dummy stack structure DST via the interconnection structure 221 corresponding to the transistors disposed in the second region A2 and the third lower contact plug 11C.

[0085] Figure 7 is a flowchart schematically illustrating a method of manufacturing a semiconductor memory device according to one embodiment.

[0086] Reference Figure 7 , the method of manufacturing a semiconductor memory device may include a step ST1 of forming a preliminary structure, a step ST3 of forming a stacked structure, a step ST5 of forming a channel structure, a support pillar, and a contact plug, and a step ST7 of forming a channel connection pattern.

[0087] A substrate including a lower structure and a lower contact plug may be formed before performing step ST1. The lower structure may include reference Figure 6 The lower structure LS described above and the lower contact plug may include reference FIG. 3A to FIG. 3C , Figure 4 and Figure 6 The first lower contact plug 11A, the second lower contact plug 11B, and the third lower contact plug 11C are described. In step ST1, a preliminary structure may be formed on a substrate including a lower structure and lower contact plugs.

[0088] In step ST3, the stacked structure may be formed to have a stepped structure and may be penetrated by channel holes, dummy holes, and contact holes. According to one embodiment, step ST3 may include forming a first stepped structure and forming a second stepped structure, the first stepped structure forming the lower portion of the stacked structure, and the second stepped structure forming the upper portion of the stacked structure. However, the embodiment is not limited thereto. According to one embodiment, step ST3 may include stacking a plurality of material layers as high as the height of the target stacked structure, and forming the stepped structure by etching the plurality of material layers.

[0089] Step ST5 may include forming a memory layer on the sidewall of each of the channel hole, the dummy hole, and the contact hole, forming a channel structure and a support column in the channel hole and the dummy hole, respectively, and forming a contact plug in the contact hole. Therefore, each of the channel structure, the support column, and the contact plug may be surrounded by the memory layer.

[0090] Step ST7 may include partially exposing the sidewalls of the channel structure, and forming a channel coupling pattern contacting the exposed sidewalls of the channel structure.

[0091] In the following, reference is made to FIG. 8A to FIG. 8C , FIG. 9A to FIG. 9J , FIG. 10A to FIG. 10K , FIG. 11A to FIG. 11C , Fig. 12A , Fig. 12B , Fig.13 , Fig.14A and Fig. 14B The following figures are cross-sectional views of the structure according to the manufacturing steps. The following figures are cross-sectional views taken along the line II', the line II-II' and the line III-III' and corresponding to the second area A2. The following figures show the manufacturing method including FIG. 3A to FIG. 3C and Figure 4 One embodiment of a method for a semiconductor memory device having a structure shown is shown.

[0092] FIG. 8A to FIG. 8C Is to show about Figure 7 A cross-sectional view of one embodiment of step ST1 is shown.

[0093] Reference Fig. 8A Before performing step ST1, lower contact plugs 311A, 311B, and 311C passing through the lower insulating layer 300 may be formed in the region including Figure 6 The lower structure LS is shown on the substrate 201. The lower contact plugs 311A, 311B and 311C may include various conductive materials capable of transmitting electrical signals.

[0094] The lower contact plugs 311A, 311B, and 311C may include a first lower contact plug 311A, a second lower contact plug 311B, and a third lower contact plug 311C. The first lower contact plug 311A ​​may be connected to the Figure 6 The second lower contact plug 311B and the third lower contact plug 311C may be connected to the discharge impurity region DCI, respectively. Figure 6 The corresponding transistor in the transistor TR of the peripheral circuit shown.

[0095] Reference Figure 8B , step ST1 may include forming a preliminary first semiconductor pattern 320A1 , a second semiconductor pattern 320B, and a third semiconductor pattern 320C that are separated from each other.

[0096] The preliminary first semiconductor pattern 320A1 may overlap the first lower contact plug 311A, the second semiconductor pattern 320B may overlap the second lower contact plug 311B, and the third semiconductor pattern 320C may overlap the third lower contact plug 311C. An edge of the preliminary first semiconductor pattern 320A1 may overlap the first lower contact plug 311A. The width of the second semiconductor pattern 320B may be greater than the width of the second lower contact plug 311B, and the second semiconductor pattern 320B may protrude to opposite sides of the second lower contact plug 311B. The width of the third semiconductor pattern 320C may be greater than the width of the third lower contact plug 311C, and the third semiconductor pattern 320C may protrude to opposite sides of the third lower contact plug 311C.

[0097] The steps of forming a preliminary first semiconductor pattern 320A1, a second semiconductor pattern 320B and a third semiconductor pattern 320C may include: sequentially stacking a first semiconductor layer 321, a sacrificial stack structure 305 and a second semiconductor layer 329 on the lower insulating layer 300 to cover the first lower contact plug 311A, the second lower contact plug 311B and the third lower contact plug 311C; and etching the first semiconductor layer 321, the sacrificial stack structure 305 and the second semiconductor layer 329.

[0098] The first semiconductor layer 321 may include n-type or p-type impurities. The sacrificial stack structure 305 may include a first protective layer 323, a sacrificial layer 325, and a second protective layer 327 sequentially stacked on each other. The sacrificial layer 325 may include a material having a different etching rate from the first protective layer 323 and the second protective layer 327 to selectively etch the sacrificial layer 325, and the first protective layer 323 and the second protective layer 327 may include a material capable of protecting the first semiconductor layer 321 and the second semiconductor layer 329 when the sacrificial layer 325 is etched. For example, the sacrificial layer 325 may include an undoped silicon layer. Each of the first protective layer 323 and the second protective layer 327 may include an oxide layer. The second semiconductor layer 329 may include an undoped semiconductor layer or a doped semiconductor layer including n-type or p-type impurities. At least one of the first protective layer 323, the second protective layer 327, and the second semiconductor layer 329 may be omitted.

[0099] Reference Figure 8C , step ST1 may include forming a first vertically doped semiconductor pattern 331A, a second vertically doped semiconductor pattern 331B, and a third vertically doped semiconductor pattern 331C on sidewalls of the preliminary first semiconductor pattern 320A1, the second semiconductor pattern 320B, and the third semiconductor pattern 320C, respectively. The first vertically doped semiconductor pattern 331A, the second vertically doped semiconductor pattern 331B, and the third vertically doped semiconductor pattern 331C may be formed with reference to Figure 8BThe described first semiconductor layer 321 includes the same impurities.

[0100] Step ST1 may include filling spaces between the preliminary first semiconductor pattern 320A1 , the second semiconductor pattern 320B, and the third semiconductor pattern 320C with an insulating layer 335 .

[0101] The above reference FIG. 8A to FIG. 8C The described processes form a preliminary structure including a preliminary first semiconductor pattern 320A1 , a second semiconductor pattern 320B, and a third semiconductor pattern 320C respectively overlapping the first lower contact plug 311A, the second lower contact plug 311B, and the third lower contact plug 311C and separated from each other by the insulating layer 335 .

[0102] FIG. 9A to FIG. 9J Is to show about Figure 7 FIG. 1 is a cross-sectional view of an embodiment of step ST3.

[0103] Reference Fig. 9A , step ST3 may include forming a first stacked structure 340 on the preliminary structure. The first stacked structure 340 may include a first interlayer insulating layer 341 and a first sacrificial layer 343 alternately stacked on each other. The first interlayer insulating layer 341 may include a first material layer, and the first sacrificial layer 343 may include a second material layer. The second material layer may include an insulating material having a different etching rate from the first material layer to selectively etch the second material layer. For example, the first material layer may include an oxide layer, and the second material layer may include a nitride layer.

[0104] Reference Fig. 9B , step ST3 may include etching the first stack structure 340 to form a first stepped structure SW1 .

[0105] Reference Fig. 9C Step ST3 may include forming a covering Fig. 9B The first gap-filling insulating layer 350 of the first stepped structure SW1 is shown. The ridges defined by the first stepped structure SW1 may be covered by the first gap-filling insulating layer 350.

[0106] Reference Fig.9D , step ST3 may include forming lower holes 351A to 351D. The lower holes 351A to 351D may be formed simultaneously. The lower holes 351A to 351D may include a first lower hole 351A, a second lower hole 351B, a third lower hole 351C, and a fourth lower hole 351D.

[0107] The first lower hole 351A may pass through the first stack structure 340 and may extend into the preliminary first semiconductor pattern 320A1. The first lower hole 351A may pass through the second semiconductor layer 329, the second protection layer 327, the sacrificial layer 325, and the first protection layer 323 of the preliminary first semiconductor pattern 320A1 and may extend into the first semiconductor layer 321.

[0108] The second lower hole 351B may pass through the cover Fig. 9B The second lower hole 351B may pass through the second semiconductor layer 329, the second protection layer 327, the sacrificial layer 325, and the first protection layer 323 of the preliminary first semiconductor pattern 320A1, and may extend into the first semiconductor layer 321.

[0109] The third lower hole 351C may pass through a portion of the first stack structure 340 overlapping the second semiconductor pattern 320B. The third lower hole 351C may pass through Fig. 9B A portion of the first stepped structure SW1 and the first gap-filling insulating layer 350 on the portion of the first stepped structure SW1 are shown. The third lower hole 351C may pass through the second semiconductor layer 329, the second protective layer 327, the sacrificial layer 325, and the first protective layer 323 of the second semiconductor pattern 320B, and may extend into the first semiconductor layer 321. The width of the third lower hole 351C may be less than the width of the second semiconductor pattern 320B.

[0110] The fourth lower hole 351D may pass through a portion of the first stack structure 340 overlapping the third semiconductor pattern 320C. The fourth lower hole 351D may pass through the second semiconductor layer 329, the second protection layer 327, the sacrificial layer 325, and the first protection layer 323 of the third semiconductor pattern 320C, and may extend into the first semiconductor layer 321. The width of the fourth lower hole 351 may be smaller than the width of the third semiconductor pattern 320.

[0111] Each of the preliminary first, second, and third semiconductor patterns 320A1 , 320B, and 320C may serve as an etch stop layer when performing an etching process to form the first, second, third, and fourth lower holes 351A, 351B, 351C, and 351D.

[0112] Reference Fig.9EStep ST3 may include filling the first lower hole 351A, the second lower hole 351B, the third lower hole 351C, and the fourth lower hole 351D with a vertical sacrificial layer 353. The vertical sacrificial layer 353 may include the same as that described above. Fig. 9A The first material layer and the second material layer are described as having materials with different etching rates to selectively remove the vertical sacrificial layer 353. According to one embodiment, the vertical sacrificial layer 353 may include a metal, such as tungsten.

[0113] Reference Fig.9F Step ST3 may include forming a second stacked structure 360 ​​on the first stacked structure 340 having a first stepped structure penetrated by the vertical sacrificial layer 353 and covered by the first gap-filling insulating layer 350. The second stacked structure 360 ​​may include second sacrificial layers 363 and second interlayer insulating layers 361 alternately stacked on each other. The second interlayer insulating layer 361 may include reference Fig. 9A The first material layer described, and the second sacrificial layer 363 may include reference Fig. 9A A second material layer is described.

[0114] Reference Figure 9G Step ST3 may include etching the second stacked structure 360 ​​to form a second stepped structure SW2. Portions of the second stacked structure 360 ​​overlapping the first stepped structure SW1 may be removed, and the first stepped structure SW1 may not overlap the second stacked structure 360 ​​having the second stepped structure SW2.

[0115] Reference Figure 9H Step ST3 may include forming a covering Figure 9G The second gap-filling insulating layer 368 of the second stepped structure SW2 is shown. The ridges defined by the second stepped structure SW2 may be covered by the second gap-filling insulating layer 368. Subsequently, a first mask layer 371 may be formed to cover the second gap-filling insulating layer 368 and the second stack structure 360. The first mask layer 371 may include a nitride layer.

[0116] Reference Fig.9I , step ST3 may include forming upper holes 373A to 373D. The upper holes 373A to 373D may be formed simultaneously. The upper holes 373A to 373D may include a first upper hole 373A coupled to the first lower hole 351A, a second upper hole 373B coupled to the second lower hole 351B, a third upper hole 373C coupled to the third lower hole 351C, and a fourth upper hole 373D coupled to the fourth lower hole 351D.

[0117] The first upper hole 373A, the second upper hole 373B, the third upper hole 373C, and the fourth upper hole 373D may be formed by etching the first mask layer 371, the second stack structure 360, and the second gap-filling insulating layer 368 to expose the vertical sacrificial layer 353. The first upper hole 373A may pass through the second stack structure 360. The second upper hole 373B may pass through Figure 9G The second stepped structure SW2 shown in FIG. Figure 9G The third upper hole 373C may pass through the second stepped structure of the second stacked structure 360 ​​overlapping the third lower hole 351C, or may pass through the second gap-filling insulating layer 368 overlapping the third lower hole 351C. The fourth upper hole 373D may pass through a portion of the second stacked structure 360 ​​overlapping the fourth lower hole 351D.

[0118] Reference Figure 9J , step ST3 may include Fig.9I The first upper hole 373A, the second upper hole 373B, the third upper hole 373C and the fourth upper hole 373D are removed. Fig.9I The vertical sacrificial layer 353 is shown. Therefore, the channel hole HA, the dummy hole HB, the first contact hole HC and the second contact hole HD can be opened.

[0119] By connecting the first lower hole 351A to Fig.9I The first upper hole 373A shown in FIG. 1 defines a channel hole HA and may expose the first semiconductor layer 321 of the preliminary first semiconductor pattern 320A1. The second lower hole 351B may be connected to the Fig.9I The second upper hole 373B shown in FIG. 1 defines a dummy hole HB and may expose the first semiconductor layer 321 of the preliminary first semiconductor pattern 320A1. The third lower hole 351C may be connected to the Fig.9I The third upper hole 373C shown in FIG. 1 defines a first contact hole HC and may expose the first semiconductor layer 321 of the second semiconductor pattern 320B. The fourth lower hole 351D may be connected to the Fig.9I The fourth upper hole 373D is shown to define a second contact hole HD, and may expose the first semiconductor layer 321 of the third semiconductor pattern 320C.

[0120] The above reference FIG. 9A to FIG. 9JThe step stack structure 379 having a step structure and penetrated by the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD is formed by the process described above. The channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD may be formed such that the channel hole HA and the dummy hole HB overlap the preliminary first semiconductor pattern 320A1, the first contact hole HC overlaps the second semiconductor pattern 320B, and the second contact hole HD overlaps the third semiconductor pattern 320C.

[0121] FIG. 10A to FIG. 10K Is to show about Figure 7 FIG. 1 is a cross-sectional view of an embodiment of step ST5 .

[0122] Reference Fig. 10A , step ST5 may include forming a memory layer 381 on a surface of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, forming a channel layer 383 on the memory layer 381, and filling a central region of the channel layer 383 with a core insulating layer 385.

[0123] By sequentially stacking references Figure 5B The described blocking insulating layer BI, the data storage layer DL, and the tunnel insulating layer TI form a memory layer 381. The memory layer 381 may be simultaneously formed on the surfaces of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD.

[0124] According to one embodiment, the channel layer 383 may be conformally formed on the memory layer 381, and the core insulating layer 385 may be formed by filling a central area of ​​each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD, which is not filled with the channel layer 383, with a flowable material layer, and then by hardening the flowable material layer. The flowable material layer may include polysilazane (PSZ).

[0125] Reference Fig. 10B , step ST5 may include removing Fig. 10A The core insulating layer 385 is shown to define a hollow portion HP at the upper end of each of the channel hole HA, the dummy hole HB, the first contact hole HC, and the second contact hole HD. Therefore, a core insulating pattern 385P that opens the upper end of the channel layer 383 may be defined.

[0126] Subsequently, step ST5 may include forming a doped semiconductor layer 391L to fill the hollow portion HP. The doped semiconductor layer 391L may include at least one of an n-type impurity and a p-type impurity.

[0127] Reference Fig. 10C Step ST5 may include Fig. 10B The doped semiconductor layer 391L is shown planarized to expose the first mask layer 371. Thus, a capping pattern 391 surrounded by an upper end of the channel layer 383 may be formed.

[0128] By reference FIG. 10A to FIG. 10C The described processes, respectively, may form a channel structure 380A in the channel hole HA, and may form a support pillar 380B in the dummy hole HB, and may form a first dummy channel structure 380C and a second dummy channel structure 380D in the first contact hole HC and the second contact hole HD. According to one embodiment, each of the channel structure 380A, the support pillar 380B, the first dummy channel structure 380C and the second dummy channel structure 380D may include a channel layer 383, a core insulation pattern 385P and a capping pattern 391.

[0129] Despite Fig. 10C Not shown, but according to one embodiment, the capping pattern 391 may be omitted, and each of the channel structure 380A, the support pillar 380B, the first dummy channel structure 380C, and the second dummy channel structure 380D may include a channel layer 383 filling a central region of the memory layer 381.

[0130] Reference Fig. 10D Step ST5 may include forming a second mask layer 393 extending to cover the channel structure 380A and the support pillar 380B on the first mask layer 371. The second mask layer 393 may be etched to expose Fig. 10C A first dummy channel structure 380C and a second dummy channel structure 380D are shown.

[0131] Subsequently, step ST5 may include removing the second mask layer 393 from each of the first contact hole HC and the second contact hole HD through an etching process using the second mask layer 393 as an etching barrier. Fig. 10C The capping pattern 391 is shown. Therefore, the core insulation pattern 385P may be exposed. When the capping pattern 391 is etched, the first contact hole HC and the second contact hole HD may be removed. Fig. 10C The upper end of the channel layer 383 is shown, and a portion of the channel layer 383 may remain.

[0132] Reference Fig.10E The step ST5 may include removing the second mask layer 393 from each of the first contact hole HC and the second contact hole HD through an etching process using the second mask layer 393 as an etching barrier. Fig. 10D A core insulation pattern 385P is shown.

[0133] Reference Fig.10FThe step ST5 may include removing the second mask layer 393 from each of the first contact hole HC and the second contact hole HD through an etching process using the second mask layer 393 as an etching barrier. Fig.10E The channel layer 383P is shown. Therefore, the memory layer 381 formed along the surface of each of the first contact hole HC and the second contact hole HD may be exposed.

[0134] Reference Figure 10G , step ST5 may include forming an oxide layer 395 on the memory layer 381 exposed on the surface of each of the first contact hole HC and the second contact hole HD. The oxide layer 395 may be formed to compensate for the insulating characteristics of the memory layer 381. According to one embodiment, the formation of the oxide layer 395 may be omitted.

[0135] Reference Fig. 10H , step ST5 may include forming a first contact hole extension EA coupled to the first contact hole HC and a second contact hole extension EB coupled to the second contact hole HD.

[0136] The first contact hole extension EA may pass through the memory layer 381 and the oxide layer 395 of the bottom surface of the first contact hole HC and through the first semiconductor layer 321 of the second semiconductor pattern 320B to expose the second lower contact plug 311B. The second contact hole extension EB may pass through the memory layer 381 and the oxide layer 395 of the bottom surface of the second contact hole HD and through the first semiconductor layer 321 of the third semiconductor pattern 320 to expose the third lower contact plug 311C. Hereinafter, the memory layer and the oxide layer remaining in each of the first contact hole HC and the second contact hole HD may be referred to as a dummy memory layer 381P and an oxide layer pattern 395P.

[0137] Reference Fig.10I , step ST5 may include forming a first contact plug 397A filling the first contact hole HC and the first contact hole extension EA and a second contact plug 397B filling the second contact hole HD and the second contact hole extension EB.

[0138] The first contact plug 397A and the second contact plug 397B may include various conductive materials capable of transmitting electrical signals. The first contact plug 397A may contact the second lower contact plug 311B, and the second contact plug 397B may contact the third lower contact plug 311C. When the first contact plug 397A and the second contact plug 397B are formed, the Fig. 10H A second mask layer 393 is shown.

[0139] Reference Fig.10J After forming the first contact plug 397A and the second contact plug 397B, the Fig.10IA first mask layer 371 is shown.

[0140] Reference Figure 10K , the region where the first mask layer is removed may be filled with a first upper insulating layer 399. The first upper insulating layer 399 may surround upper ends of the channel structure 380A, the support pillar 380B, the first contact plug 397A, and the second contact plug 397B.

[0141] As mentioned above FIG. 10A to FIG. 10I As described above, the dummy memory layer 381P surrounding each of the first and second contact plugs 397A and 397B may be formed by the process of forming the memory layer 381 surrounding the channel structure 380A. The dummy memory layer 381P may serve as an insulating structure to insulate the first and second contact plugs 397A and 397B.

[0142] FIG. 11A to FIG. 11C Is to show about Figure 7 FIG. 1 is a cross-sectional view of an embodiment of step ST7 shown.

[0143] Reference Fig.11A Before performing step ST7, an upper slit may be formed, an isolation insulating layer 401 filling the upper slit may be formed, and a second upper insulating layer 411 may be formed on the first upper insulating layer 399. The second upper insulating layer 411 may extend to cover Figure 10K The channel structure 380A, the support pillar 380B, the first contact plug 397A and the second contact plug 397B are shown. The upper slit may correspond to Figure 2 and Figure 3C The upper slit USI is shown.

[0144] Step ST7 may include forming a slit 413 through the second upper insulating layer 411, the first upper insulating layer 399, and the stepped stack structure 379. The slit 413 may extend into the preliminary first semiconductor pattern 320A1. The slit 413 may pass through the second semiconductor layer 329 of the preliminary first semiconductor pattern 320A1. The slit 413 may extend into the sacrificial layer 325 of the preliminary first semiconductor pattern 320A1. The sacrificial layer 325 may be exposed through the bottom surface of the slit 413.

[0145] Reference Fig. 11B , step ST7 may include removing Fig.11A The sacrificial layer 325 of the preliminary first semiconductor pattern 320A1 is removed to expose the memory layer through the slit 413, and the memory layer is divided into the first memory pattern 381P1 and the second memory pattern 381P2 by removing the exposed memory layer. When the etching process for removing the memory layer is performed, the memory layer can be removed. Fig.11AThe first protection layer 323 and the second protection layer 327 of the preliminary first semiconductor pattern 320A1 are shown to expose the first semiconductor layer 321 and the second semiconductor layer 329 of the preliminary first semiconductor pattern 320A1.

[0146] Hereinafter, a space disposed between the first semiconductor layer 321 and the second semiconductor layer 329 and extending between the first memory pattern 381P1 and the second memory pattern 381P2 may be defined as a horizontal space 415. The horizontal space 415 may expose the channel layer 383 of the channel structure 380A.

[0147] Reference Fig. 11C Step ST7 may include filling the trench connection pattern 421 with Fig. 11B A horizontal space 415 is shown. The channel coupling pattern 421 may contact the first and second semiconductor layers 321 and 329 and the channel layer 383. The channel coupling pattern 421 may include n-type impurities or p-type impurities.

[0148] The channel coupling pattern 421 may be formed by a selective growth method such as a selective epitaxial growth (SEG) method using at least one of the first and second semiconductor layers 321 and 329 and the channel layer 383 as a seed layer. According to one embodiment, the channel coupling pattern 421 may be formed by a non-selective method such as a chemical vapor deposition (CVD) method.

[0149] The above reference FIG. 11A to FIG. 11C The described process forms the first semiconductor pattern 320A2 including the first semiconductor layer 321 , the second semiconductor layer 329 , and the channel coupling pattern 421 .

[0150] Fig. 12A , Fig. 12B , Fig.13 , Fig.14A and Fig. 14B Is to show about Figure 7 FIG. 1 is a cross-sectional view of one embodiment of a process performed after step ST7 .

[0151] Fig. 12A and Fig. 12B is shown using a conductive pattern instead of a reference Fig. 9A The first sacrificial layer 343 described in reference Fig.9F A cross-sectional view of the second sacrificial layer 363 is depicted.

[0152] Reference Fig. 12A , an oxide layer 425 may be formed on the surface of the first semiconductor pattern 320A2 through the slits 413. The oxide layer 425 may be formed by oxidizing a portion of the first semiconductor pattern 320A2.

[0153] Subsequently, the first and second sacrificial layers adjacent to the slit 413 may be selectively removed. Hereinafter, the region where the first and second sacrificial layers are removed may be referred to as a gate region 431. The gate region 431 may be defined between the first and second interlayer insulating layers 341 and 361, respectively.

[0154] Reference Fig. 12B ,exist Fig. 12A After the gate regions 431 are opened, the gate regions 431 may be filled with conductive patterns 433 .

[0155] The step of forming the conductive pattern 433 may include: forming a barrier metal layer extending along the surface of the gate region 431; forming a conductive layer thick enough to fill the gate region 431 on the barrier metal layer; and etching the barrier metal layer and the conductive layer to be separated into the conductive pattern 433. Thus, a gate stack structure 430 including the first and second interlayer insulating layers 341 and 361 and the conductive pattern 433 disposed between respective layers of the first and second interlayer insulating layers 341 and 361 adjacent to each other may be formed.

[0156] Fig.13 Through the above reference FIG. 11A to FIG. 11C The end of the first semiconductor pattern 320A2 formed by the process described above is Fig. 12A and Fig. 12B The described process forms a step structure of the gate stack structure 430 , and a cross-sectional view of the first sacrificial layer 343 and the second sacrificial layer 363 that remain and form the dummy stack structure 440 .

[0157] Reference Fig.13 , the first vertical doped pattern 331A may remain on the sidewall of the first semiconductor pattern 320A2.

[0158] The gate stack structure 430 may surround the channel structure 380A, the support pillar 380B, and the first contact plug 397A. The support pillar 380B and the first contact plug 397A may pass through the stepped structure of the gate stack structure 430 covered by the first gap-filling insulating layer 350 and the second gap-filling insulating layer 368. The conductive pattern 433 of the gate stack structure 430 may surround the channel structure 380A, and a portion of the conductive pattern 433 forming the stepped structure of the gate stack structure 430 may surround the support pillar 380B and the first contact plug 397A.

[0159] The channel coupling pattern 421 of the first semiconductor pattern 320A2 may not only extend between the first memory pattern 381P1 and the second memory pattern 381P2, but may also extend to contact the channel layer 383 of the support pillar 380B. Therefore, the memory layer around the support pillar 380B may be divided into the first dummy pattern 381P1d and the second dummy pattern 381P2d. The support pillar 380B may be insulated from the conductive pattern 433 by the second dummy pattern 381P2d.

[0160] The first contact plug 397A may be insulated from the conductive pattern 433 by the dummy memory layer 381P. Therefore, according to one embodiment, even when a barrier structure for preventing the conductive pattern 433 from being formed around the first contact plug 397A is not additionally formed, the operation characteristics of the semiconductor memory device may be ensured. Therefore, the semiconductor memory device according to one embodiment may prevent process difficulties and defects caused by a manufacturing process for forming a barrier structure.

[0161] When the gate stack structure 430 is formed, some of the first sacrificial layer 343 and the second sacrificial layer 363 disposed in the second area A2 may not be replaced by the conductive pattern 433 but may be retained. Figure 2 The first area A1 shown is FIG. 12A to FIG. 12B The first and second sacrificial layers 343 and 363 and the first and second interlayer insulating layers 341 and 361 remaining in the second region A2 may form a dummy stack structure 440. The dummy stack structure 440 may overlap the third semiconductor pattern 320C and may surround the second contact plug 397B.

[0162] Fig.14A and Fig. 14B 4 is a cross-sectional view showing the formation of a bit line contact plug 451 , a gate contact plug 453 , a first upper contact plug 455 , and a second upper contact plug 457 .

[0163] Reference Fig.14A , upper contact holes 441, 443, 445, and 447 may be formed through at least one of the second upper insulating layer 411, the first upper insulating layer 399, the second gap-filling insulating layer 368, and the first gap-filling insulating layer 350. The support pillar 380B may be covered by the second upper insulating layer 411 without being exposed to the outside.

[0164] The upper contact holes 441, 443, 445, and 447 may include: a first upper contact hole 441 exposing the capping pattern 391 of the channel structure 380A; a second upper contact hole 443 exposing a corresponding one of the conductive patterns 433; a third upper contact hole 445 exposing the first contact plug 397A; and a fourth upper contact hole 447 exposing the second contact plug 397B. The second upper contact hole 443 may overlap the stepped structure and may expose the conductive pattern 433 corresponding to the second upper contact hole 443.

[0165] Reference Fig. 14B After each of the first upper contact hole 441, the second upper contact hole 443, the third upper contact hole 445, and the fourth upper contact hole 447 is filled with a conductive material, the surface of the conductive material may be planarized. Thus, a bit line contact plug 451, a gate contact plug 453, a first upper contact plug 455, and a second upper contact plug 457 may be formed.

[0166] The bit line contact plug 451 may be coupled to the channel structure 380A, the gate contact plug 453 may be coupled to the conductive pattern 433 corresponding to the gate contact plug 453 , the first upper contact plug 455 may be coupled to the first contact plug 397A, and the second upper contact plug 457 may be coupled to the second contact plug 397B.

[0167] Subsequently, a process subsequent to the process of forming the bit line contact plug 451, the gate contact plug 453, the first upper contact plug 455, and the second upper contact plug 457 may be performed, such as forming Figure 1 The bit line BL is shown. The bit line BL may be coupled to a bit line contact plug 451 .

[0168] Fig.15 is a block diagram illustrating a memory system 1100 according to one embodiment.

[0169] Reference Fig.15 , the memory system 1100 may include a memory device 1120 and a memory controller 1110 .

[0170] The memory device 1120 may be a multi-chip package including a plurality of flash memory chips. The memory device 1120 may include: a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a step structure; a contact plug passing through the step structure of the gate stack structure; and an insulating structure surrounding the contact plug.

[0171] The memory controller 1110 may be configured to control the memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 may be used as an operation memory of the CPU 1112, the CPU 1112 may perform a general control operation for data exchange of the memory controller 1110, and the host interface 1113 may include a data exchange protocol of a host accessing the memory system 1100. In addition, the error correction block 1114 may detect and correct errors included in data read from the memory device 1120, and the memory interface 1115 may perform an interface connection with the memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) for storing code data for interfacing with the host.

[0172] The memory system 1100 having the above configuration may be a solid state drive (SSD) or a memory card in which the memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with an external device (e.g., a host) through one of various interface protocols including, but not limited to, a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer mini interface (SCSI), an enhanced small disk interface (ESDI), and an integrated drive electronics (IDE).

[0173] Fig.16 is a block diagram showing a configuration of a computing system 1200 according to one embodiment.

[0174] Reference Fig.16 The computing system 1200 may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. In addition, when the computing system 1200 is a mobile device, it may further include a battery for providing an operating voltage to the computing system 1200, and may also include an application chipset, an image processor, a mobile DRAM, and the like.

[0175] The memory system 1210 may include a memory device 1212 and a memory controller 1211. The memory device 1212 may include: a gate stack structure including interlayer insulating layers and conductive patterns alternately stacked on each other and having a step structure; a contact plug passing through the step structure of the gate stack structure; and an insulating structure surrounding the contact plug.

[0176] According to the present disclosure, the manufacturing process can be simplified by forming the contact hole using the channel hole forming process.

[0177] According to the present disclosure, an insulating structure capable of insulating a contact plug disposed in a contact hole from a conductive pattern of a gate stack structure can be formed through a memory layer formation process, thereby simplifying a manufacturing process.

[0178] CROSS-REFERENCE TO RELATED APPLICATIONS

[0179] This application claims the priority of Korean Patent Application No. 10-2019-0138568 filed in the Korean Intellectual Property Office on November 1, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: lower contact plug; a semiconductor pattern overlapping the lower contact plug, the semiconductor pattern comprising a first semiconductor layer, a first protection layer, a sacrificial layer, a second protection layer, and a second semiconductor layer; a gate stack structure overlapping the semiconductor pattern and including a cell array region and a step region extending from the cell array region; A channel structure, wherein the channel structure passes through the cell array region of the gate stack structure; a memory layer surrounding a sidewall of the channel structure; a first contact plug disposed in the stepped region of the gate stack structure; as well as an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure, The first contact plug passes through the insulating structure and the semiconductor pattern to contact the lower contact plug.

2. The semiconductor memory device according to claim 1, wherein The first semiconductor layer, the first protection layer, the sacrificial layer, the second protection layer, and the second semiconductor layer of the semiconductor pattern are sequentially stacked over the lower contact plug.

3. The semiconductor memory device according to claim 1, wherein: The first semiconductor layer and the second semiconductor layer of the semiconductor pattern include doped silicon layers.

4. The semiconductor memory device according to claim 1, wherein: The first and second protective layers of the semiconductor pattern include a material having an etch rate different from an etch rate of the sacrificial layer.

5. The semiconductor memory device according to claim 1, wherein: The sacrificial layer of the semiconductor pattern includes a silicon layer.

6. The semiconductor memory device according to claim 1, wherein: The first semiconductor layer, the first protection layer, the sacrificial layer, the second protection layer, and the second semiconductor layer of the semiconductor pattern surround the first contact plug.

7. The semiconductor memory device according to claim 1, wherein: The lower contact plug is connected to a transistor included in a peripheral circuit via an interconnection structure.

8. The semiconductor memory device according to claim 1, wherein: A width of the semiconductor pattern is greater than a width of the first contact plug.

9. The semiconductor memory device according to claim 1, further comprising: a channel connection pattern, the channel connection pattern overlapping the cell array region of the gate stack structure; as well as two semiconductor layers, the channel coupling pattern being interposed between the two semiconductor layers, One of the two semiconductor layers is disposed at a level at which the first semiconductor layer is disposed, and the other of the two semiconductor layers is disposed at a level at which the second semiconductor layer is disposed.

10. The semiconductor memory device according to claim 9, wherein: The channel structure extends into the channel coupling pattern and the two semiconductor layers.

11. The semiconductor memory device according to claim 10, wherein: The memory layer is divided into a first memory pattern and a second memory pattern, Wherein, the first memory pattern covers the bottom of the channel structure, Wherein, the second memory pattern is arranged between the channel structure and the gate stack structure, and The channel coupling pattern extends between the first memory pattern and the second memory pattern to contact the channel structure.

12. The semiconductor memory device according to claim 1, wherein: The insulating structure includes an oxide layer.

13. The semiconductor memory device according to claim 1, wherein: The gate stack structure includes a first stack structure and a second stack structure on the first stack structure, The gate stack structure further includes a hole having an undercut region at a boundary between the first stack structure and the second stack structure, and Wherein, the memory layer and the channel structure are arranged in the hole.

14. The semiconductor memory device according to claim 1, further comprising a dummy stacked structure, the dummy stacked structure being disposed at a level at which the gate stacked structure is disposed, the dummy stacked structure comprising dummy interlayer insulating layers and sacrificial layers alternately stacked on each other. 15 . The semiconductor memory device according to claim 14 , further comprising a second contact plug passing through the dummy stack structure.

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