Electronic device

Abstract

The invention relates to an electronic device. Performance of an electronic device may be improved. An electronic device includes a wiring substrate, a semiconductor memory device disposed on the wiring substrate, and a semiconductor controller device disposed on the wiring substrate. The wiring substrate includes a first fixed potential wiring and a second fixed potential wiring, and a plurality of signal wirings provided between the first fixed potential wiring and the second fixed potential wiring. The plurality of signal wires includes a first signal wire adjacent to the first fixed potential wire, a second signal wire adjacent to the first signal wire, and a third signal wire adjacent to the second signal wire. A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-116556 filed on Jul. 18, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to an electronic device, and for example, the present invention can be suitably used for an electronic device including a plurality of semiconductor devices and a wiring substrate. Background Art

[0004] The disclosed techniques are listed below.

[0005] [Patent Document 1] Japanese Laid-Open Patent Application Publication No. 2006-237385;

[0006] Patent Document 1 discloses a technique related to a semiconductor device in which a plurality of semiconductor memory devices and a semiconductor data processing device that controls the plurality of semiconductor memory devices are on a mounting substrate. Summary of the invention

[0007] The inventor has considered arranging multiple signal wirings evenly so that crosstalk becomes uniform. On the other hand, in recent years, there is also a demand to reduce the cost of electronic devices. Therefore, the inventor considers reducing the number of wiring layers of the wiring substrate to be used. Therefore, it is necessary to ensure that the area (space) for arranging other wirings provided on other wiring layers is provided on the wiring layer providing these signal wirings. As a countermeasure, the inventor considers further reducing the distance (spacing) between adjacent wirings. However, according to the research of the inventor, when multiple (3 or more) signal wirings are evenly arranged, it is found that the signal propagating a certain signal wiring is easily affected by the propagation of the signal that is not located next to the signal wiring, but two or more signal wirings located next to it. That is, the risk of timing fluctuations due to signal interference may increase. This is because it causes the performance of electronic devices to decline, and therefore measures need to be taken.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0009] According to one embodiment, an electronic device includes a wiring substrate, a first semiconductor device disposed on the wiring substrate, and a second semiconductor device, the second semiconductor device being disposed on the wiring substrate and controlling the first semiconductor device. The wiring substrate includes a first fixed potential wiring, a second fixed potential wiring, and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring. The plurality of signal wirings include a first signal wiring adjacent to the first fixed potential wiring, a second signal wiring adjacent to the first signal wiring, and a third signal wiring adjacent to the second signal wiring. A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring.

[0010] According to one embodiment, the performance of an electronic device may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a plan view schematically showing the electronic device according to the first embodiment.

[0012] Figure 2 is a sectional view of a main portion of the electronic device according to the first embodiment.

[0013] Figure 3 is a partially enlarged plan view of a wiring region of a wiring substrate used in the electronic device according to the first embodiment.

[0014] Figure 4 is a partially enlarged plan view of a wiring region of a wiring substrate used in the electronic device according to the first embodiment.

[0015] Figure 5 is a partially enlarged plan view of a wiring region of a wiring substrate used in the electronic device according to the first embodiment.

[0016] Figure 6 is a partially enlarged plan view of a wiring region of a wiring substrate used in the electronic device according to the first embodiment.

[0017] Figure 7 is a plan view of a main portion of a wiring substrate according to a first inspection example.

[0018] Figure 8 is a plan view of a main portion of a wiring substrate according to a second inspection example.

[0019] Fig. 9 is an explanatory diagram used to explain the timing changes caused by crosstalk.

[0020] Fig.10 is a diagram showing an example of a timing margin when a semiconductor control device performs a write operation on a semiconductor memory device.

[0021] Fig.11 is a diagram showing an example of a timing margin when a semiconductor control device performs a read operation on a semiconductor memory device.

[0022] Fig.12 is a partially enlarged plan view of a wiring region of a wiring substrate used in an electronic device according to a second embodiment.

[0023] Fig.13 is a partially enlarged plan view of a wiring region of a wiring substrate used in an electronic device according to a second embodiment. DETAILED DESCRIPTION

[0024] In the following embodiments, when necessary for convenience, the description is divided into multiple parts or embodiments, but unless otherwise specified, they are not independent of each other, and one is related to a part or all of the modified examples, details, supplementary descriptions, etc. of another. In the following embodiments, except for the case where the quantity is specifically indicated and is clearly limited to a specific number in principle, the number of elements, etc. (including the number of elements, numerical values, amounts, ranges, etc.) is not limited to a specific number, but may not be less than or equal to a specific number. In addition, in the following embodiments, it is obvious that except for the case where the constituent elements are specifically specified and they are considered to be obviously necessary in principle, the constituent elements (including element steps, etc.) are not necessarily necessary. Similarly, in the following embodiments, except for the case where the shape is specifically specified and they are considered to be obvious in principle, etc., when referring to the shape, positional relationship, etc. of the component, etc., it is assumed that the shape, etc. is substantially similar to or similar to the shape, etc. This also applies to the above-mentioned numerical values ​​and ranges.

[0025] The embodiments are described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components with the same function are represented by the same reference numerals, and their repeated description is omitted. In the following embodiments, unless particularly necessary, the description of the same or similar parts will not be repeated in principle.

[0026] In the drawings used in the embodiments, hatching may be omitted even in the case of a cross-sectional view to make the drawings easier to see. In addition, hatching may be used even in the case of a plan view to make the drawings easier to see.

[0027] (First embodiment)

[0028] <Overall Configuration of Electronic Devices>

[0029] Figure 1 : is a plan view schematically showing the electronic device DS of this embodiment.

[0030] like Figure 1As shown, the electronic device DS of this embodiment includes a wiring substrate (mounting substrate) PB, a memory (storage) semiconductor device (semiconductor memory device) MD mounted on the wiring substrate PB, and a control semiconductor device (semiconductor control device) CD mounted on the wiring substrate PB. Other electronic components (not shown) may also be mounted on the wiring substrate PB.

[0031] The semiconductor device MD is a semiconductor device including a memory chip (semiconductor chip for memory). In this embodiment, a semiconductor package that packages the memory chip is applied as the semiconductor device MD. In another embodiment, the memory chip may be applied as the semiconductor device MD.

[0032] In this embodiment, it is described that two semiconductor devices MD are mounted on the wiring substrate PB. One semiconductor device MD mounted on the wiring substrate PB of the two semiconductor devices MD is hereinafter referred to as semiconductor device MD1, and the other is hereinafter referred to as semiconductor device MD2. The semiconductor devices MD1 and MD2 can use semiconductor devices of the same type (configuration) as each other.

[0033] The semiconductor device CD is a semiconductor device that controls the semiconductor devices MD1 and MD2. In the present embodiment, the semiconductor device CD is a control chip (a semiconductor chip for controlling) that controls the semiconductor devices MD1 and MD2. That is, in the present embodiment, an unpackaged control chip (i.e., the control chip itself) is used as the semiconductor device CD. The control chip may be, for example, a system on chip (SoC). In another embodiment, a semiconductor package that packages the control chip may also be applied as the semiconductor device CD.

[0034] The wiring substrate PB has a plurality of wirings electrically connecting the semiconductor control device CD and the semiconductor memory device MD1 , a plurality of wirings electrically connecting the semiconductor control device CD and the semiconductor memory device MD2 , and a plurality of power supply wirings PW1 , PW2 , PW3 , and PW4 .

[0035] Figure 1 The wiring region RG1 shown is an area where a plurality of wirings electrically connecting the semiconductor control device CD and the semiconductor memory device MD1 are arranged. A plurality of (many) signal wirings and a plurality of ground wirings are arranged in the wiring region RG1. Figure 1 The wiring area RG2 shown is an area where a plurality of wirings electrically connecting the semiconductor control device CD and the semiconductor memory device MD2 are arranged. A plurality of (many) signal wirings and a plurality of ground wirings are arranged in the wiring area RG2. In the wiring substrate PB, the wiring area RG1 is arranged between the semiconductor device CD and the semiconductor device MD1, and the wiring area RG2 is arranged between the semiconductor device CD and the semiconductor device MD2.

[0036] The power wirings PW1, PW2, PW3, and PW4 are electric wires for providing power supply potential. In the wiring substrate PB, the power wirings PW1 and PW2 extend between the semiconductor device CD and the semiconductor device MD1, thereby sandwiching the wiring region RG1. That is, in the wiring substrate PB, the wiring region RG1 is arranged between the power wirings PW1 and PW2.

[0037] In the wiring substrate PB, the power supply wirings PW3 and PW4 extend between the semiconductor device CD and the semiconductor device MD2 so as to sandwich the wiring region RG2. That is, in the wiring substrate PB, the wiring region RG2 is arranged between the power supply wirings PW3 and PW4.

[0038] The semiconductor control device CD is electrically connected to each of the power wirings PW1, PW2, PW3, and PW4. The semiconductor memory device MD1 is electrically connected to each of the power wirings PW1 and PW2. The semiconductor memory device MD2 is electrically connected to each of the power wirings PW3 and PW4. This allows the semiconductor device CD to be supplied with a power supply potential from each of the power wirings PW1, PW2, PW3, and PW4. The power supply potential can be supplied to the semiconductor device MD1 from each of the power wirings PW1 and PW2. The power supply potential can be supplied to the semiconductor device MD2 from each of the power wirings PW3 and PW4.

[0039] In the electronic device DS, since the semiconductor device CD as a semiconductor chip and a plurality of semiconductor devices MD1, MD2 including semiconductor chips not shown are mounted on the wiring substrate PB, the electronic device DS is considered to include a semiconductor chip. Therefore, the electronic device DS can also be considered to be a semiconductor device.

[0040] Figure 2 is a cross-sectional view of a main portion of the electronic device DS. Figure 2 Shown through Figure 1 The cross section of the wiring area RG1 or RG2 is shown. Figure 2 The cross section in passes through the wiring area RG1, then Figure 2 The signal wiring SG shown is the signal wiring SG arranged in the wiring region RG1. Figure 2 The cross section in passes through the wiring area RG2, then Figure 2 The illustrated signal wiring SG is the signal wiring SG arranged in the wiring region RG2 .

[0041] Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the Figure 1 A partially enlarged view of a portion of the wiring region RG1 or the wiring region RG2 is shown.

[0042] Although the details will be described later, the technical idea of ​​the present embodiment is to arrange three or more signal wirings SG between the ground wiring G1 and the ground wiring G2 and to arrange the three or more signal wirings SG alternately at smaller wiring intervals and larger wiring intervals. Figure 3 , Figure 4 , Figure 5 and Figure 6 The technical concept was followed, but Figure 3 , Figure 4 , Figure 5 and Figure 6 In the embodiment, the numbers of the signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are different from each other.

[0043] Figure 3 Two ground wirings GR and three signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Figure 4 Two ground wirings GR and four signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Figure 5 Two ground wirings GR and five signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Figure 6 Two ground wirings GR and six signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Figure 1 In each wiring region RG1, RG2, many signal wirings SG and ground wirings GR are arranged, and Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the figures shows a part of many signal wirings SG and ground wirings GR arranged in the wiring region RG1 or the wiring region RG2 .

[0044] The semiconductor device CD has a plurality of terminals (electrodes) TE1 (see Figure 2 ). The semiconductor device MD has a plurality of terminals (electrodes) TE2 (see Figure 2 ).

[0045] if Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the figures is an enlarged view of a portion of the wiring region RG1. Figure 3 , Figure 4 , Figure 5 and Figure 6One end portion of each of the signal wirings SG shown is electrically connected to any one of a plurality of terminals TE1 of the semiconductor device CD, and Figure 3 , Figure 4 , Figure 5 and Figure 6 The other end of each signal wiring SG shown is electrically connected to any one of the plurality of terminals TE2 of the semiconductor device MD1. Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the signal wirings SG shown functions as a signal wiring that electrically connects the semiconductor device CD and the semiconductor device MD1 and transmits a signal between the semiconductor device CD and the semiconductor device MD1 .

[0046] if Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the figures is an enlarged view of a portion of the wiring region RG2. Figure 3 , Figure 4 , Figure 5 and Figure 6 One end portion of each of the signal wirings SG shown is electrically connected to any one of a plurality of terminals TE1 of the semiconductor device CD, and Figure 3 , Figure 4 , Figure 5 and Figure 6 The other end of each signal wiring SG shown is electrically connected to any one of the plurality of terminals TE2 of the semiconductor device MD2. Figure 3 , Figure 4 , Figure 5 and Figure 6 Each of the signal wirings SG shown functions as a signal wiring that electrically connects the semiconductor device CD and the semiconductor device MD2 and transmits a signal between the semiconductor device CD and the semiconductor device MD2 .

[0047] A signal can be transmitted from the semiconductor device CD to the semiconductor device MD1 or from the semiconductor device MD1 to the semiconductor device CD by means of a plurality of signal wirings SG provided in the wiring region RG1. A signal can be transmitted from the semiconductor device CD to the semiconductor device MD2 or from the semiconductor device MD2 to the semiconductor device CD by means of a plurality of signal wirings SG provided in the wiring region RG2. Note that Figure 3 , Figure 4 , Figure 5 , Figure 6 Each of the signal wirings SG shown is a single-ended type signal wiring.

[0048] In the case where the wiring substrate PB has a plurality of wiring layers, Figure 3, Figure 4 , Figure 5 and Figure 6 The ground wiring GR and the signal wiring SG shown in each figure are formed in any one of a plurality of wiring layers of the wiring substrate PB.

[0049] Here, in Figure 3 , Figure 4 , Figure 5 and Figure 6 In each of the figures, one of the two ground wirings GR is referred to as a ground wiring G1 and the other of the two ground wirings GR is referred to as a ground wiring G2. The ground wiring G1 and the ground wiring G2 are separated from each other in a plan view. Figure 3 In the embodiment, in the direction from the ground wiring G1 to the ground wiring G2, three signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are respectively referred to as a signal wiring S1, a signal wiring S2, and a signal wiring S3. Figure 4 In the embodiment, in the direction from the ground wiring G1 to the ground wiring G2, four signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are respectively referred to as a signal wiring S1, a signal wiring S2, a signal wiring S3, and a signal wiring S4. Figure 5 In the direction from the ground wiring G1 to the ground wiring G2, the five signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are respectively referred to as the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4 and the signal wiring S5. Figure 6 In the figure, in the direction from the ground wiring G1 to the ground wiring G2, the six signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are respectively called signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5 and signal wiring S6.

[0050] exist Figure 3 In the case of , the ground wiring G1, the signal wiring S1, the signal wiring S2, the signal wiring S3, and the ground wiring G2 are formed in the same layer (same wiring layer) on the wiring substrate PB, and are arranged in this order in a plan view and run in parallel. The same applies to Figure 4 , Figure 5 and Figure 6 A case in which the ground wiring G1, signal wirings S1 to S4, S1 to S5, S1 to S6, and the ground wiring G2 are formed in the same layer on the wiring substrate PB and are arranged in this order in a plan view and run in parallel.

[0051] exist Figure 3 , Figure 4 , Figure 5 and Figure 6In the example, the ground wiring G1 and the signal wiring S1 are adjacent to each other, the signal wiring S1 and the signal wiring S2 are adjacent to each other, and the signal wiring S2 and the signal wiring S3 are adjacent to each other. Figure 3 , Figure 4 , Figure 5 and Figure 6 In the embodiment, the signal wiring S1 is arranged between the ground wiring G1 and the signal wiring S2, and the signal wiring S2 is arranged between the signal wiring S1 and the signal wiring S3.

[0052] exist Figure 4 , Figure 5 and Figure 6 In each of the figures, the signal wiring S3 and the signal wiring S4 are adjacent to each other, and the signal wiring S3 is arranged between the signal wiring S2 and the signal wiring S4. Figure 5 and Figure 6 In each of the figures, the signal wiring S4 and the signal wiring S5 are adjacent to each other, and the signal wiring S4 is arranged between the signal wiring S3 and the signal wiring S5. Figure 6 In the embodiment, the signal wiring S5 and the signal wiring S6 are adjacent to each other, and the signal wiring S5 is arranged between the signal wiring S4 and the signal wiring S6.

[0053] exist Figure 3 In FIG. 1 , the signal wiring S3 and the ground wiring G2 are adjacent to each other, and the signal wiring S3 is arranged between the signal wiring S2 and the ground wiring G2. Figure 4 In FIG. 1 , the signal wiring S4 and the ground wiring G2 are adjacent to each other, and the signal wiring S4 is arranged between the signal wiring S3 and the ground wiring G2. Figure 5 In FIG. 1 , the signal wiring S5 and the ground wiring G2 are adjacent to each other, and the signal wiring S5 is arranged between the signal wiring S4 and the ground wiring G2. Figure 6 In the example, the signal wiring S6 and the ground wiring G2 are adjacent to each other, and the signal wiring S6 is arranged between the signal wiring S5 and the ground wiring G2.

[0054] Note that two lines being adjacent to each other means that no other lines are arranged between the two lines.

[0055] The ground wiring GR is a line that provides a ground potential (reference potential). The ground wiring G1 and the ground wiring G2 have a function of electromagnetically shielding a plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 from lines outside the ground wiring G1 and G2. Figure 3 , Figure 4 , Figure 5 and Figure 6 In the embodiment, no ground wiring is arranged between the plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2.

[0056] Next, we will describe Figure 3 , Figure 4 , Figure 5 and Figure 6 The spacing between the signal wirings SG in each figure.

[0057] Here, the distance (pitch) between the signal wiring S1 and the signal wiring S2 is referred to as the distance D1. The distance (pitch) between the signal wiring S2 and the signal wiring S3 is referred to as the distance D2. The distance (pitch) between the signal wiring S3 and the signal wiring S4 is referred to as the distance D3. The distance (pitch) between the signal wiring S4 and the signal wiring S5 is referred to as the distance D4. The distance (pitch) between the signal wiring S5 and the signal wiring S6 is referred to as the distance D5.

[0058] exist Figure 3 , Figure 4 , Figure 5 and Figure 6 In each of the figures in FIG. 1 , the plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are not arranged at equal intervals.

[0059] Specifically, in Figure 3 In this case, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (ie, “D2>D1”).

[0060] exist Figure 4 In the case of , the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and the distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (i.e., "D2>D1" and "D2>D3"). Preferably, the distance D1 between the signal wiring S1 and the signal wiring S2 and the distance D3 between the signal wiring S3 and the signal wiring S4 are the same as each other (i.e., "D1=D3").

[0061] exist Figure 5In the case of, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., "D2>D1" and "D4>D1"). Furthermore, the distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., "D2>D3" and "D4>D3"). Preferably, the distance D1 between the signal wiring S1 and the signal wiring S2 and the distance D3 between the signal wiring S3 and the signal wiring S4 are the same as each other (i.e., "D1=D3"). Preferably, the distance D2 between the signal wiring S2 and the signal wiring S3 and the distance D4 between the signal wiring S4 and the signal wiring S5 are the same as each other (i.e., "D2=D4").

[0062] exist Figure 6 In the case of , the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., "D2>D1" and "D4>D1"). Furthermore, the distance D3 between the signal wiring S3 and the signal wiring S4 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., "D2>D3" and "D4>D3"). Furthermore, the distance D5 between the signal wiring S5 and the signal wiring S6 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3, and is also smaller than the distance D4 between the signal wiring S4 and the signal wiring S5 (i.e., "D2>D5" and "D4>D5"). Preferably, the distance D1 between the signal wiring S1 and the signal wiring S2, the distance D3 between the signal wiring S3 and the signal wiring S4, and the distance D5 between the signal wiring S5 and the signal wiring S6 are the same as each other (i.e., "D1 = D3 = D5"). Preferably, the distance D2 between the signal wiring S2 and the signal wiring S3, and the distance D4 between the signal wiring S4 and the signal wiring S5 are the same as each other (i.e., "D2 = D4").

[0063] By providing such a wiring interval for the plurality of signal wirings SG arranged between the ground wiring G1 and the ground wiring G2, it is possible to suppress the area required for arranging these lines and suppress timing variations (signal timing variations) caused by signal interference in each of the plurality of signal wirings SG. The reason for this will be explained in detail later.

[0064] According to the technical concept of this embodiment, a plurality of signal wirings SG (3 or more) arranged between the ground wirings G1 and G2 are connected as follows: Figure 1The wiring regions RG1 and RG2 shown may exist in one or both of the wiring regions. Figure 3 The number of signal wirings SG between the ground wirings G1 and G2 is 3. Figure 4 There are 4 in the middle. Figure 5 There are 5 in the middle. Figure 6 There are 6 in total, but there can be 7 or more.

[0065] In the present embodiment, it has been described that when two semiconductor devices MD (MD1, MD2) for memory and a semiconductor device CD for controlling the two semiconductor devices MD for memory are arranged on a wiring substrate PB, the number of semiconductor devices MD for memory arranged on the wiring substrate PB is not limited to two. For example, instead of mounting the semiconductor device MD2 on the wiring substrate PB, one semiconductor memory device MD (MD1) and a semiconductor device CD for controlling the semiconductor memory device MD may be mounted on the wiring substrate PB. Alternatively, three or more semiconductor memory devices MD and a semiconductor device CD for controlling the three or more semiconductor memory devices MD may be mounted on the wiring substrate PB.

[0066] <Research Background>

[0067] Figure 7 is a plan view of the main part of the wiring substrate of the first inspection example studied by the inventors, the first inspection example corresponding to the present embodiment Figure 3 , Figure 4 , Figure 5 and Figure 6 .

[0068] exist Figure 7 In the case of the first inspection example in , the signal wirings SG and the ground wirings GR are arranged alternately. Therefore, each signal wiring SG is less likely to receive crosstalk from other signal wirings SG.

[0069] However, in Figure 7 In the case of the first inspection example in FIG. 1 , due to the alternating arrangement of the signal wiring SG and the ground wiring GR, the number of required signal wirings SG increases, and the number of required ground wirings GR also increases accordingly. Therefore, the area required for arranging the signal wiring in the wiring substrate (corresponding to the above-mentioned wiring areas RG1, RG2) increases. This leads to an increase in the plane dimension (plane area) of the semiconductor device to which the signal wiring is connected, and further increases the plane dimension of the wiring substrate.

[0070] Figure 8 is a plan view of the main part of the wiring substrate of the second inspection example studied by the inventors, the second inspection example corresponding to the present embodiment Figure 3 , Figure 4 , Figure 5 and Figure 6 .

[0071] exist Figure 8 In the case of the second inspection example in FIG. 1 , a plurality of (six in this case) signal wirings S11, S12, S13, S14, S15, and S16 are arranged between two ground wirings G11 and G12 at equal intervals. Figure 8 In the case of the second inspection example in , the distance D11 between the signal wiring S11 and the signal wiring S12, the distance D12 between the signal wiring S12 and the signal wiring S13, the distance D13 between the signal wiring S13 and the signal wiring S14, the distance D14 between the signal wiring S14 and the signal wiring S15, and the distance D15 between the signal wiring S15 and the signal wiring S16 are the same. In other words, "D11 = D12 = D13 = D14 = D15" holds. No ground wiring is arranged between the signal wirings S11, S12, S13, S14, S15, and S16.

[0072] exist Figure 8 In the case of the second inspection example in FIG. 1 , by arranging the signal wirings S11, S12, S13, S14, S15, S16 between the two ground wirings G11, G12, and not arranging the ground wirings between the signal wirings S11, S12, S13, S14, S15, S16, even if the number of required signal wirings SG increases, the number of required ground wirings GR can be suppressed. Therefore, the area required for arranging the signal wirings in the wiring substrate (corresponding to the above-mentioned wiring areas RG1, RG2) can be suppressed.

[0073] In addition, Figure 8 In the case of the second inspection example in , by arranging the signal wirings S11, S12, S13, S14, S15, S16 at equal intervals, the crosstalk occurring between adjacent signal wirings in the signal wirings S11, S12, S13, S14, S15, S16 can be more easily suppressed. This is because the amplitude of the crosstalk occurring between adjacent signal wirings is related to the distance between adjacent signal wirings, and the smaller the distance between adjacent signal wirings, the greater the crosstalk between adjacent signal wirings. If the distance between the ground wiring G11 and the ground wiring G12 does not change, making the distances D11, D12, D13, D14, D15 the same as each other can maximize the minimum distance among the adjacent signal wirings S11, S12, S13, S14, S15, S16. Therefore, the amplitude of the crosstalk occurring between adjacent signal wirings in the signal wirings S11, S12, S13, S14, S15, S16 can be equalized and the crosstalk can be prevented from becoming larger in a specific signal wiring.

[0074] However, according to the research of the present inventors, Figure 8 In the case of the second inspection example, each of the signal wirings S11, S12, S13, S14, S15, S16 arranged at equal intervals easily suppresses the influence of crosstalk from one adjacent signal wiring, but there is a high risk of timing variation (signal timing variation) due to the influence of crosstalk from two or more adjacent signal wirings. This will be explained below.

[0075] When all signal wirings S11, S12, S13, S14, S15, S16 are asynchronously and randomly moved, the above Figure 8 The wiring arrangement of the second inspection example in is considered to be a preferred wiring arrangement. However, in reality, the signal propagated by means of the signal wiring is a synchronous signal synchronized with the clock. In signal wiring, it is more important to suppress the timing variation caused by crosstalk than to suppress the amplitude of the crosstalk itself. In other words, if the timing variation caused by crosstalk can be suppressed, there is no need to suppress the amplitude of the crosstalk itself.

[0076] Therefore, for the synchronization signal, the present inventors considered minimizing the timing variation caused by the crosstalk, rather than minimizing the crosstalk itself.

[0077] Fig. 9 is an explanatory diagram used to explain the timing changes caused by crosstalk. Fig. 9 In , the victim signal is indicated by a solid line and the aggressor signal is indicated by a dashed line. Fig. 9 , reference symbol CC is an input / output circuit of a semiconductor control device, and reference symbol MC is an input / output circuit of a DRAM (semiconductor memory device).

[0078] When the aggressor signal (dashed line) performs a 0 / 1 conversion to the victim signal (solid line), a certain proportion of the aggressor signal is added to the victim signal as crosstalk at the time of the 0 / 1 conversion, causing the victim signal voltage to fluctuate. At this time, if the voltage is fixed, the victim signal fluctuates by the amount of B1 / B2 in the time direction, which is inversely proportional to the slope B2 of the victim signal. This is a timing change caused by crosstalk. Here, the above B1 is the victim signal voltage change caused by crosstalk.

[0079] When the victim signal undergoes a 0 / 1 transition, the slope of the victim signal inevitably becomes maximum at the 0 / 1 transition point of the victim signal and decreases as it moves away from the 0 / 1 transition point of the victim signal. Therefore, when the 0 / 1 transition timing of the victim signal coincides with the 0 / 1 transition timing of the aggressor signal, the timing variation of each crosstalk voltage is minimized. In other words, the smaller the skew between the victim signal and the aggressor signal, the smaller the timing variation of each crosstalk voltage.

[0080] In other words, if the crosstalk timing generated by the attacker signal coincides with the 0 / 1 conversion timing of the victim signal, the timing change (time direction change) of the victim signal caused by the crosstalk is small. And, the greater the deviation between the crosstalk timing generated by the attacker signal and the 0 / 1 conversion timing of the victim signal, the greater the timing change (time direction change) of the victim signal caused by the crosstalk. The crosstalk timing generated from the attacker signal coincides with the 0 / 1 conversion timing of the attacker signal. Therefore, if the skew between the victim signal and the attacker signal is zero, the timing change (time direction change) of the victim signal caused by the crosstalk is small, but the greater the skew between the victim signal and the attacker signal, the greater the timing change (time direction change) of the victim signal caused by the crosstalk. Therefore, it can be understood that among signals with small skew, the timing change of each crosstalk voltage is small.

[0081] Therefore, it is important that the signal wiring on the wiring substrate transmits the signal with a small skew. In the wiring substrate, there is a high probability that the skew of the signal transmitted between adjacent signal wirings is small. The reason is as follows.

[0082] Multiple terminals of a semiconductor control device and multiple terminals of a semiconductor memory device are electrically connected via multiple signal wirings, and signals are transmitted between the semiconductor control device and the semiconductor memory device with the aid of these signal wirings. When considering the arrangement of multiple bus-type signal wirings, the order of the signal wirings is not randomly determined. Adjacent signal wirings are likely to be connected to adjacent terminals in the semiconductor control device and adjacent terminals in the semiconductor memory device. Additionally, adjacent signal wirings may have similar characteristic impedances. Therefore, the skew of the signal transmitted between adjacent signal wirings may be small. On the other hand, between signal wirings having one or more other signal wirings in between, the skew of the transmitted signal may be large.

[0083] For example, in Figure 8 In the second inspection example in , attention is paid to the signal wiring S11. The skew of the signal transmitted on the signal wiring S11 and the signal transmitted on the signal wiring S12 may be small. On the contrary, the skew of the signal transmitted on the signal wiring S11 and the signal transmitted on the signal wiring S13 is large, the skew of the signal transmitted on the signal wiring S11 and the signal transmitted on the signal wiring S14 is even larger, and the skew of the signal transmitted on the signal wiring S11 and the signal transmitted on the signal wiring S15 is even larger.

[0084] exist Figure 8In the second inspection example in [reference document], due to crosstalk from signal wirings S12, S13, S14, S15, and S16, the signal transmitted on signal wiring S11 may undergo a timing change. As described above, since the skew of the signals transmitted between adjacent signal wirings may be small, it is unlikely that a timing change will occur in the signal transmitted on signal wiring S11 due to crosstalk from signal wiring S12. However, in Figure 8 in the case of the second inspection example in [reference document], due to crosstalk from signal wirings S13, S14, S15, and S16, a timing change may occur in the signal transmitted on signal wiring S11, which is a problem. On the other hand, in Figure 8 in the second inspection example in [reference document], if we focus on signal wiring S12, due to crosstalk from signal wirings S11 and S13, it is unlikely that a timing change will occur in the signal transmitted on signal wiring S12. However, due to crosstalk from signal wirings S14, S15, and S16, a timing change may occur in the signal transmitted on signal wiring S12, which is a problem. The same situation can be considered for the timing changes of the signals transmitted on other signal wirings S13, S14, S15, and S16.

[0085] Due to crosstalk, the timing change in the signal transmitted on the signal wiring may cause a degradation in the performance of the electronic device, so it is necessary to suppress it.

[0086] <Main Features and Effects>

[0087] The electronic device DS of this embodiment is equipped with a wiring substrate PB, a semiconductor memory device MD arranged on the wiring substrate PB, and a semiconductor control device CD arranged on the wiring substrate PB and controlling the semiconductor device MD. The wiring substrate PB has ground wirings G1 and G2, and the ground wirings G1 and G2 are fixed potential lines; and a plurality of signal wirings SG, and the plurality of signal wirings SG are arranged between the ground wirings G1 and G2 in a plan view and transmit signals between the semiconductor device CD and the semiconductor device MD. The plurality of signal wirings SG arranged between the ground wirings G1 and G2 include a signal wiring S1 adjacent to the ground wiring G1, a signal wiring S2 adjacent to the signal wiring S1, and a signal wiring S3 adjacent to the signal wiring S2. In the plan view, the signal wiring S1 is arranged between the signal wiring S2 and the ground wiring G1, and the signal wiring S2 is arranged between the signal wiring S3 and the signal wiring S1.

[0088] One of the main features of this embodiment is that the distance D1 between the signal wiring S1 and the signal wiring S2 is less than the distance D2 between the signal wiring S2 and the signal wiring S3 ("D1 < D2") (refer to Figure 3 , Figure 4 , Figure 5 and Figure 6 )。

[0089] Suppose that the signal wirings S1, S2, and S3 are arranged at equal intervals, which is different from this embodiment. In this case, as explained in the second inspection example in Figure 8 , it is easy to suppress crosstalk between the signal wiring S1 and the signal wiring S2, and crosstalk between the signal wiring S2 and the signal wiring S3. However, due to the crosstalk between them, timing fluctuations may occur in the signals transmitted through the signal wirings S1 and S3, which is a problem.

[0090] On the contrary, in this embodiment, the distance D1 between the signal wiring S1 and the signal wiring S2 is smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 (i.e., "D1 < D2"). By reducing the distance D1 between the signal wiring S1 and the signal wiring S2, the electromagnetic coupling between the signal wiring S1 and the signal wiring S2 becomes stronger, and the signal pair of the signal wiring S1 and the signal wiring S2 becomes less susceptible to crosstalk from other signal wirings SG (S3). Therefore, due to the crosstalk between the signal wiring S1 and the signal wiring S3 and the crosstalk between the signal wiring S2 and the signal wiring S3, timing fluctuations in the signals transmitted through the signal wirings S1, S2, and S3 can be suppressed. Preferably, the signal wirings S1 and S2 have the same length and the same characteristic impedance.

[0091] On the other hand, in this embodiment, by reducing the distance D1 between the signal wiring S1 and the signal wiring S2, the crosstalk itself between the signal wiring S1 and the signal wiring S2 may increase. However, since the signal wirings S1 and S2 are adjacent to each other, the skew of the signals transmitted through the signal wirings S1 and S2 may be small. Therefore, due to the crosstalk between the signal wiring S1 and S2, the risk of timing fluctuations in the signals transmitted through them is small.

[0092] Therefore, by making the distance D1 between the signal wiring S1 and the signal wiring S2 smaller than the distance D2 between the signal wiring S2 and the signal wiring S3 ("D1 < D2"), timing fluctuations caused by crosstalk in the signals transmitted through the signal wirings S1, S2, and S3 can be suppressed.

[0093] In Figure 4 、 Figure 5 and Figure 6Among them, a plurality of signal wirings SG arranged between ground wirings G1 and G2 include signal wiring S3 and adjacent signal wiring S4. The distance D3 between signal wiring S3 and signal wiring S4 is less than the distance D2 between signal wiring S2 and signal wiring S3 ("D3 < D2"). Preferably, the distance D1 between signal wiring S1 and signal wiring S2 and the distance D3 between signal wiring S3 and signal wiring S4 are the same (D1 = D3).

[0094] By reducing the distance D3 between signal wiring S3 and signal wiring S4, the electromagnetic coupling between signal wiring S3 and signal wiring S4 becomes stronger, and the signal pair of signal wiring S3 and signal wiring S4 becomes less susceptible to crosstalk from other signal wirings SG (S1, S2). Therefore, due to the crosstalk between signal wiring S1 and signal wiring S3, the crosstalk between signal wiring S1 and signal wiring S4, the crosstalk between signal wiring S2 and signal wiring S3, and the crosstalk between signal wiring S2 and signal wiring S4, the timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, and S4 can be suppressed. Preferably, signal wirings S3 and S4 have the same length and the same characteristic impedance.

[0095] On the other hand, by reducing the distance D3 between signal wiring S3 and signal wiring S4, the crosstalk between signal wiring S3 and signal wiring S4 itself may increase. However, since signal wirings S3 and S4 are adjacent to each other, the skew of the signals transmitted through signal wirings S3 and S4 may be small. Therefore, due to the crosstalk between signal wiring S3 and S4, the risk of timing fluctuations in the signals transmitted through signal wirings S3 and S4 is small.

[0096] Therefore, due to crosstalk, the timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, and S4 can be suppressed.

[0097] In Figure 5 and Figure 6 Among them, a plurality of signal wirings SG arranged between ground wirings G1 and G2 further include signal wiring S4 and adjacent signal wiring S5. The distance D4 between signal wiring S4 and S5 is greater than the distance D1 between signal wiring S1 and S2 ("D4 > D1"), and is also greater than the distance D3 between signal wiring S3 and signal wiring S4 ("D4 > D3"). Preferably, the distances D1 and D3 are the same ("D1 = D3"). Preferably, the distances D2 and D4 are the same ("D2 = D4").

[0098] By increasing the distance D4 between signal wirings S4 and S5, the signal pairs of signal wirings S1 and S2 and signal wirings S3 and S4 become less susceptible to crosstalk from signal wiring S5. Therefore, due to the crosstalk between signal wiring S1 and S5, signal wiring S2 and S5, signal wiring S3 and S5, and signal wiring S4 and S5, timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, S4, and S5 can be suppressed.

[0099] Therefore, due to crosstalk, timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, S4, and S5 can be suppressed.

[0100] In Figure 6 In this embodiment, among the multiple signal wirings SG arranged between ground wirings G1 and G2, there are also signal wiring S5 and adjacent signal wiring S6. The distance D5 between signal wirings S5 and S6 is less than the distance D2 between signal wirings S2 and S3 (“D5 < D2”), and is also less than the distance D4 between signal wirings S4 and S5 (“D5 < D4”). Preferably, the distances D1, D3, and D5 are the same (“D1 = D3 = D5”). Preferably, the distances D2 and D4 are the same (“D2 = D4”).

[0101] Therefore, the electromagnetic coupling between signal wirings S5 and S6 becomes stronger and the signal pair of signal wirings S5 and S6 becomes less susceptible to crosstalk from other signal wirings SG (S1, S2, S3, S4). Therefore, due to the crosstalk between signal wiring S1 and S3, signal wiring S1 and S4, signal wiring S1 and S5, signal wiring S1 and S6, signal wiring S2 and S3, signal wiring S2 and S3, signal wiring S2 and S4, signal wiring S2 and S4, signal wiring S2 and S5, and signal wiring S2 and S6, timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, S4, S5, and S6 can be suppressed. In addition, due to the crosstalk between signal wiring S3 and S5, signal wiring S3 and S6, signal wiring S4 and S5, and signal wiring S4 and S6, timing fluctuations in the signals transmitted through signal wirings S1, S2, S3, S4, S5, and S6 can be suppressed. It should be noted that signal wirings S5 and S6 preferably have the same length and the same characteristic impedance.

[0102] On the other hand, by reducing the distance D5 between signal wirings S5 and S6, the crosstalk between signal wirings S5 and S6 itself may increase. However, since signal wirings S5 and S6 are adjacent to each other, the skew of the signals transmitted through signal wirings S5 and S6 may be very small. Therefore, due to the crosstalk between signal wirings S5 and S6, the risk of timing fluctuations in the signals transmitted through signal wirings S5 and S6 is very small.

[0103] Therefore, it is possible to suppress the occurrence of timing fluctuation in the signals transmitted via the signal wirings S1 , S2 , S3 , S4 , S5 , and S6 due to crosstalk.

[0104] Thus, in the present embodiment, timing fluctuation due to crosstalk in a signal transmitted via the signal wiring can be suppressed, thereby improving the performance of the electronic device.

[0105] In the present embodiment, a plurality of signal wirings SG are arranged between the ground wiring G1 and the ground wiring G2 and no ground wiring is arranged between these signal wirings SG. Therefore, even if the number of necessary signal wirings SG increases, the number of necessary ground wirings GR can be suppressed. Therefore, the area required for arranging the signal wiring on the wiring substrate (corresponding to the wiring regions RG1, RG2) can be suppressed. Therefore, both the improvement of the performance of the electronic device and the miniaturization of the electronic device can be achieved.

[0106] Each of the intervals D1, D3, D5 is smaller than each of the intervals D2, D4. Therefore, the intervals D1, D3, D5 can be considered as small wiring intervals, and the intervals D2, D4 can be considered as large wiring intervals. In the present embodiment, a plurality of signal wirings SG are arranged between the ground wiring G1 and the ground wiring G2, alternating between small wiring intervals and large wiring intervals. Therefore, as Figure 6 In the modification example, when an additional signal wiring S7 (not shown) is arranged between the signal wiring S6 and the ground wiring G2, the interval between the signal wiring S7 and the signal wiring S6 should be set to a large wiring interval that is the same as the intervals D2 and D4. When an additional signal wiring S8 (not shown) is arranged between the signal wiring S7 and the ground wiring G2, the interval between the signal wiring S8 and the signal wiring S7 should be set to a small wiring interval that is the same as the intervals D1, D3, and D5. The same situation can also be considered when adding more signal wirings.

[0107] In this embodiment, the signal wiring SG to which the technical concept of this embodiment is applied is a single-ended signal wiring, and preferably a single-ended data signal wiring. The data signal transmitted via the data signal wiring has a higher frequency than the command address signal and the clock signal.

[0108] In the present embodiment, a plurality of signal wirings SG are arranged between two fixed potential wirings, and these signal wirings SG are shielded and ground wirings G1 and G2 are used as two fixed potential wirings. The ground wirings G1 and G2 are fixed potential wirings that provide a ground potential, and the potential of each of the ground wirings G1 and G2 is fixed at the ground potential. As a modified example, a fixed potential wiring that provides a fixed potential (power supply potential) other than the ground potential may also be used instead of the ground wirings G1 and G2. That is, a plurality of signal wirings SG may be arranged between two fixed potential wirings that provide a fixed potential other than the ground potential, and the distance between these signal wirings SG may be set as described above. In this case, the fixed potential provided to each of the two fixed potential wirings is the same as each other.

[0109] Fig.10 is a diagram showing an example of a timing margin when a semiconductor control device performs a write operation on a semiconductor memory device. Fig.11 1 is a diagram showing an example of a timing margin when a semiconductor control device performs a read operation from a semiconductor memory device. The timing margin is one of the indicators used to evaluate the magnitude of the timing fluctuation occurring in a signal transmitted via a signal wiring. The larger the timing margin, the smaller the timing fluctuation occurring in the signal transmitted via the signal wiring.

[0110] exist Fig.10 and Fig.11 In each figure, apply Figure 3 , Figure 4 , Figure 5 and Figure 6 The wiring arrangement of the present embodiment shown is shown by solid lines, and the following is applied: Figure 8 The situation of the wiring arrangement of the second inspection example shown is shown by a dotted line.

[0111] exist Fig.10 and Fig.11 In the example, the timing margin in the solid line graph (this embodiment) is greater than the timing margin in the dotted line graph (the second inspection example). Figure 8 In the second inspection example shown, compared with the case where a plurality of signal wirings are arranged at equal intervals between the ground wirings G11 and G12, as in the present embodiment, by utilizing small wiring intervals and large wiring intervals, a plurality of signal wirings SG are alternately arranged between the ground wirings G1 and G2, so that timing fluctuations occurring in signals transmitted by means of the signal wirings can be suppressed.

[0112] (Second embodiment)

[0113] In the first embodiment, the method of setting the wiring intervals of the plurality of single-ended signal wirings SG arranged between the ground wirings G1 and G2 is explained.

[0114] In the second embodiment, it will be explained that the plurality of signal wirings SG arranged between the ground wirings G1 and G2 are not single-ended but differential signal wirings. In the case of differential signal wirings, a differential signal pair is considered as one signal and the signal wirings are arranged according to the rule of the first embodiment.

[0115] Fig.12 and Fig.13 Each figure shows Figure 1 An enlarged partial view of an enlarged portion of the wiring region RG1 or the wiring region RG2 is shown.

[0116] The technical concept of the first embodiment is to arrange three or more single-ended signal wirings between the ground wiring G1 and the ground wiring G2 and to arrange the three or more single-ended signal wirings alternately at a smaller wiring interval and a larger wiring interval.

[0117] On the other hand, the technical concept of the second embodiment involves arranging three or more differential pairs between the ground wiring G1 and the ground wiring G2, and arranging these three or more differential pairs in a pattern that alternates between smaller intervals and larger intervals. This is because the signal wiring pair (differential pair) acts as an equivalent signal wiring of the single-ended signal wiring. The aforementioned smaller interval and larger interval are each the intervals between two adjacent differential pairs. Fig.12 and Fig.13 Following the technical concept, but Fig.12 and Fig.13 The difference between them is that the number of differential pairs arranged between the ground wiring G1 and the ground wiring G2 is different. Fig.12 In the case of , the number of differential pairs arranged between the ground wirings G1 and G2 is 3, and Fig.13 In the case of , the number is 4.

[0118] Fig.12 Two ground wirings GR and six signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Fig.13 Two ground wirings GR and eight signal wirings SG arranged between the two ground wirings GR are shown in the plan view. Similar to the first embodiment, in the second embodiment, each signal wiring SG electrically connects the semiconductor device CD and the semiconductor device MD, and serves as a signal wiring for transmitting a signal between the semiconductor device CD and the semiconductor device MD.

[0119] However, in the second embodiment, Fig.12 and Fig.13 Each of the signal wirings SG shown in is not a single-ended signal wiring but a differential signal wiring, and a differential pair is formed by two adjacent signal wirings SG.

[0120] Likewise in the second embodiment, Fig.12 and Fig.13 In each of the figures in FIG. 1 , one of the two ground wirings GR is referred to as a ground wiring G1 and the other ground wiring is referred to as a ground wiring G2. Fig.12 In the figure, the six signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are sequentially referred to as the signal wiring S1, the signal wiring S2, the signal wiring S3, the signal wiring S4, the signal wiring S5 and the signal wiring S6 in the direction from the ground wiring G1 to the ground wiring G2. Fig.13 In the figure, the eight signal wirings SG arranged between the ground wiring G1 and the ground wiring G2 are respectively called signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5, signal wiring S6, signal wiring S7 and signal wiring S8 in the direction from the ground wiring G1 to the ground wiring G2.

[0121] exist Fig.12 In the case of , the ground wiring G1, signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5, signal wiring S6 and ground wiring G2 are formed in the same layer (same wiring layer) on the wiring substrate PB and in a plan view, they are arranged in this order and run in parallel. Fig.13 In this case, the ground wiring G1, signal wiring S1, signal wiring S2, signal wiring S3, signal wiring S4, signal wiring S5, signal wiring S6, signal wiring S7, signal wiring S8 and ground wiring G2 are formed in the same layer (same wiring layer) on the wiring substrate PB and in a plan view, they are arranged in this order and run in parallel.

[0122] exist Fig.12 and Fig.13 In the example, the ground wiring G1 and the signal wiring S1 are adjacent to each other, the signal wiring S1 and the signal wiring S2 are adjacent to each other, the signal wiring S2 and the signal wiring S3 are adjacent to each other, the signal wiring S3 and the signal wiring S4 are adjacent to each other, the signal wiring S4 and the signal wiring S5 are adjacent to each other, and the signal wiring S5 and the signal wiring S6 are adjacent to each other. Fig.12 and Fig.13 In each of the figures, the signal wiring S1 is arranged between the ground wiring G1 and the signal wiring S2, the signal wiring S2 is arranged between the signal wirings S1 and S3, the signal wiring S3 is arranged between the signal wirings S2 and S4, the signal wiring S4 is arranged between the signal wirings S3 and S5, and the signal wiring S5 is arranged between the signal wirings S4 and S6.

[0123] exist Fig.12In the example, the signal wiring S6 and the ground wiring G2 are adjacent to each other, and the signal wiring S6 is arranged between the signal wiring S5 and the ground wiring G2.

[0124] exist Fig.13 In FIG, the signal wirings S6 and S7 are adjacent to each other, the signal wirings S7 and S8 are adjacent to each other, and the signal wiring S8 and the ground wiring G2 are adjacent to each other. Fig.13 In FIG. 5 , the signal wiring S6 is arranged between the signal wirings S5 and S7 , the signal wiring S7 is arranged between the signal wirings S6 and S8 , and the signal wiring S8 is arranged between the signal wiring S7 and the ground wiring G2 .

[0125] exist Fig.12 and Fig.13 In each of the figures in FIG. 1 , no ground wiring is arranged between the plurality of signal wirings SG arranged between the ground wirings G1 and G2 .

[0126] exist Fig.12 In the case of , the differential pair P1 is formed by the signal wiring S1 and the signal wiring S2, the differential pair P2 is formed by the signal wiring S3 and the signal wiring S4, and the differential pair P3 is formed by the signal wiring S5 and the signal wiring S6. Fig.13 In this case, the differential pair P1 is formed by the signal wiring S1 and the signal wiring S2, the differential pair P2 is formed by the signal wiring S3 and the signal wiring S4, the differential pair P3 is formed by the signal wiring S5 and the signal wiring S6, and the differential pair P4 is formed by the signal wiring S7 and the signal wiring S8.

[0127] exist Fig.12 and Fig.13 In each of the figures, the differential pair P1 is adjacent to the ground wiring G1, the differential pair P2 is adjacent to the differential pair P1, and the differential pair P3 is adjacent to the differential pair P2. Fig.12 and Fig.13 In each of the figures, the differential pair P1 is arranged between the differential pair P2 and the ground wiring G1, and the differential pair P2 is arranged between the differential pair P3 and the differential pair P1. Fig.12 In the embodiment, the ground wiring G2 is adjacent to the differential pair P3, and the differential pair P3 is arranged between the ground wiring G2 and the differential pair P2.

[0128] exist Fig.13 In , the differential pair P4 is adjacent to the differential pair P3, and the ground wiring G2 is adjacent to the differential pair P4. Fig.13 In the example, the differential pair P3 is arranged between the differential pair P4 and the differential pair P2 and the differential pair P4 is arranged between the ground wiring G2 and the differential pair P3.

[0129] exist Fig.12 and Fig.13In each of the figures, the distance D6 between differential pairs P1 and P2 is less than the distance D7 between differential pairs P2 and P3 (i.e., "D6 < D7"). In Fig.13 the distance D8 between differential pairs P3 and P4 is less than the distance D7 between differential pairs P2 and P3 (i.e., "D8 < D7"). Preferably, the distance D8 between differential pairs P3 and P4 is the same as the distance D6 between differential pairs P1 and P2 (i.e., "D6 = D8").

[0130] The distance D6 between differential pairs P1 and P2 is the distance between signal routing S2 forming differential pair P1 and signal routing S3 forming differential pair P2. The distance D7 between differential pairs P2 and P3 is the distance between signal routing S4 forming differential pair P2 and signal routing S5 forming differential pair P3. The distance D8 between differential pairs P3 and P4 is the distance between signal routing S6 forming differential pair P3 and signal routing S7 forming differential pair P4.

[0131] When applying the technical concept of the first embodiment to this second embodiment 2, differential pair P1 in this second embodiment 2 corresponds to single - ended signal routing S1 in the first embodiment. Differential pair P2 in this second embodiment 2 corresponds to single - ended signal routing S2 in the first embodiment. Differential pair P3 in this second embodiment 2 corresponds to single - ended signal routing S3 in the first embodiment. In the second embodiment, differential pair P4 corresponds to single - ended signal routing S4 in the first embodiment.

[0132] Therefore, in the first embodiment, making the distance D1 between signal routings S1 and S2 less than the distance D2 between signal routings S2 and S3 ("D1 < D2") corresponds to, in the second embodiment, making the distance D6 between differential pairs P1 and P2 less than the distance D7 between differential pairs P2 and P3 ("D6 < D7"). Making the distance D3 between signal routings S3 and S4 less than the distance D2 between signal routings S2 and S3 ("D3 < D2") corresponds to, in the second embodiment, making the distance D8 between differential pairs P3 and P4 less than the distance D7 between differential pairs P2 and P3 ("D8 < D7").

[0133] Suppose the case where differential pairs P1, P2, and P3 are arranged at equal intervals, which is different from the second embodiment. In this case, it is easy to suppress crosstalk between differential pairs P1 and P2, and crosstalk between differential pairs P2 and P3, but there is a problem that the signals transmitted by differential pairs P1 and P3 may have timing variations due to crosstalk between them.

[0134] In contrast, in the second embodiment, the distance D6 between differential pair P1 and differential pair P2 is less than the distance D7 between differential pair P2 and differential pair P3 (“D6 < D7”) (see Fig.12 and Fig.13 ). By reducing the distance D6 between differential pair P1 and differential pair P2, the electromagnetic coupling between differential pair P1 and differential pair P2 becomes stronger and the signal pairs of differential pair P1 and differential pair P2 become less susceptible to crosstalk from other differential pairs (P3). Therefore, due to the crosstalk between differential pair P1 and differential pair P3, and the crosstalk between differential pair P2 and differential pair P3, timing variations occurring in the signals transmitted by differential pairs P1, P2, and P3 can be suppressed.

[0135] On the other hand, in the second embodiment, by reducing the distance D6 between differential pair P1 and differential pair P2, the crosstalk between differential pair P1 and differential pair P2 itself can increase. However, since differential pair P1 and differential pair P2 are adjacent to each other, the skew of the signal transmitted by differential pair P1 and the signal transmitted by differential pair P2 may be small. Therefore, due to the crosstalk between differential pair P1 and P2, the risk of timing variations occurring in the signals they transmit is small.

[0136] Therefore, by making the distance D6 between differential pair P1 and differential pair P2 less than the distance D7 between differential pair P2 and differential pair P3 (“D6 < D7”), the timing variations occurring in the signals transmitted by differential pairs P1, P2, and P3 due to crosstalk can be suppressed.

[0137] In Fig.13 , differential pair P4 is arranged between ground wirings G1 and G2, adjacent to differential pair P3. The distance D8 between differential pair P3 and differential pair P4 is less than the distance D7 between differential pair P2 and differential pair P3 (“D8 < D7”). Preferably, the distance D8 between differential pair P3 and differential pair P4 is the same as the distance D6 between differential pair P1 and differential pair P2 (“D6 = D8”).

[0138] By reducing the distance D8 between differential pair P3 and differential pair P4, the electromagnetic coupling between differential pair P3 and differential pair P4 becomes stronger, and the signal pairs of differential pair P3 and differential pair P4 become less susceptible to crosstalk from other differential pairs (P1, P2). Therefore, due to the crosstalk between differential pair P1 and differential pair P3, the crosstalk between differential pair P1 and differential pair P4, the crosstalk between differential pair P2 and differential pair P3, and the crosstalk between differential pair P2 and differential pair P4, timing variations occurring in the signals transmitted by differential pairs P1, P2, P3, and P4 can be suppressed.

[0139] On the other hand, by reducing the distance D8 between the differential pair P3 and the differential pair P4, the crosstalk itself between the differential pair P3 and the differential pair P4 may increase. However, since the differential pairs P3 and P4 are adjacent to each other, the skew of the signal transmitted to the differential pair P3 and P4 may be small. Therefore, there is little risk of timing variation in the signal transmitted to the differential pair P3 and P4 due to the crosstalk between the differential pair P3 and P4.

[0140] Therefore, it is possible to suppress the occurrence of timing variations in signals transmitted to the differential pairs P1 , P2 , P3 , and P4 due to crosstalk.

[0141] Thus, in the second embodiment, it is possible to suppress the occurrence of timing variations in signals transmitted to the signal wiring due to crosstalk, thereby improving the performance of the electronic device.

[0142] As in the first embodiment, in the second embodiment, a plurality of signal wirings SG are arranged between the ground wirings G1 and G2, and no ground wiring is arranged between the plurality of signal wirings SG. This allows the number of necessary ground wirings GR to be suppressed even if the number of necessary signal wirings SG increases. Therefore, the area of ​​the region required for arranging the signal wirings in the wiring substrate (corresponding to the wiring regions RG1 and RG2) can be suppressed. Therefore, both the improvement of the performance of the electronic device and the miniaturization of the electronic device can be achieved.

[0143] Each of the distances D6 and D8 is smaller than the distance D7. Therefore, the distances D6 and D8 can be considered as small distances and the distance D7 can be considered as a large distance. In the second embodiment, a plurality of differential pairs are arranged by alternately repeating small distances and large distances between the ground wirings G1 and G2. Note that each of the small distance and the large distance is a distance between two adjacent differential pairs.

[0144] Therefore, as Fig.13 In the modification example of FIG. 1 , when an additional differential pair P5 (not shown) is arranged between the differential pair P4 and the ground wiring G2, the distance between the differential pair P5 and the differential pair P4 can be set to a large interval that is the same as the distance D7. When an additional differential pair P6 (not shown) is arranged between the differential pair P5 and the ground wiring G2, the distance between the differential pair P6 and the differential pair P5 can be set to a small distance that is the same as the distances D6 and D8. The same situation can be considered even if more differential pairs are added.

[0145] The signal wiring SG to which the technical idea of ​​the second embodiment is applied is a differential signal wiring, but is preferably a differential data signal wiring.

[0146] As in the first embodiment, in the second embodiment, fixed potential lines that provide a fixed potential (power supply potential) other than the ground potential may be used instead of the ground wirings G1 and G2.

[0147] Although the invention made by the present inventors has been specifically described based on the embodiments, it goes without saying that the invention is not limited to the embodiments and can be variously modified without departing from the spirit thereof.

Claims

1. An electronic device comprising: Wiring substrate; A first semiconductor device is provided on the wiring substrate; as well as a second semiconductor device which is provided on the wiring substrate and controls the first semiconductor device, The wiring substrate comprises: a first fixed potential wiring; second fixed potential wiring; and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring in a plan view, the plurality of signal wirings being wirings for transmitting signals between the first semiconductor device and the second semiconductor device, The plurality of signal routings include: a first signal wiring adjacent to the first fixed potential wiring; a second signal wiring adjacent to the first signal wiring; and a third signal wiring adjacent to the second signal wiring, wherein the first signal wiring is arranged between the second signal wiring and the first fixed potential wiring, wherein the second signal wiring is arranged between the third signal wiring and the first signal wiring, and A first distance between the first signal wiring and the second signal wiring is smaller than a second distance between the second signal wiring and the third signal wiring. 2 . The electronic device according to claim 1 , wherein the third signal wiring and the second fixed potential wiring are adjacent to each other.

3. The electronic device according to claim 1, wherein the plurality of signal wirings further includes a fourth signal wiring adjacent to the third signal wiring, wherein the third signal wiring is arranged between the fourth signal wiring and the second signal wiring, and A third distance between the third signal wiring and the fourth signal wiring is smaller than the second distance. The electronic device according to claim 3 , wherein the first distance and the third distance are identical to each other. 5 . The electronic device according to claim 4 , wherein the fourth signal wiring and the second fixed potential wiring are adjacent to each other.

6. The electronic device according to claim 3, wherein the plurality of signal wirings further includes a fifth signal wiring adjacent to the fourth signal wiring, wherein the fourth signal wiring is arranged between the fifth signal wiring and the third signal wiring, and wherein a fourth distance between the fourth signal wiring and the fifth signal wiring is greater than each of the first distance and the third distance.

7. The electronic device according to claim 6, wherein the first distance and the third distance are the same as each other, and The second distance and the fourth distance are the same. 8 . The electronic device according to claim 7 , wherein the fifth signal wiring and the second fixed potential wiring are adjacent to each other.

9. The electronic device according to claim 6, wherein the plurality of signal wirings further includes a sixth signal wiring adjacent to the fifth signal wiring, wherein the fifth signal wiring is arranged between the sixth signal wiring and the fourth signal wiring, and wherein the fifth distance between the fifth signal wiring and the sixth signal wiring is smaller than each of the second distance and the fourth distance.

10. The electronic device according to claim 9, wherein the first distance, the third distance and the fifth distance are the same as each other, and The second distance and the fourth distance are the same. 11 . The electronic device according to claim 10 , wherein the sixth signal wiring and the second fixed potential wiring are adjacent to each other. 12 . The electronic device according to claim 1 , wherein each of the plurality of signal wirings is a single-ended type wiring.

13. An electronic device comprising: Wiring substrate; A first semiconductor device is provided on the wiring substrate; as well as a second semiconductor device which is provided on the wiring substrate and controls the first semiconductor device, The wiring substrate comprises: a first fixed potential wiring; second fixed potential wiring; and a plurality of signal wirings arranged between the first fixed potential wiring and the second fixed potential wiring in a plan view, the plurality of signal wirings being wirings for transmitting signals between the first semiconductor device and the second semiconductor device, The plurality of signal routings include: a first differential pair, the first differential pair consisting of a first signal wiring and a second signal wiring, the first differential pair being adjacent to the first fixed potential wiring; a second differential pair, the second differential pair consisting of a third signal wiring and a fourth signal wiring, the second differential pair being adjacent to the first differential pair; and a third differential pair, the third differential pair consisting of a fifth signal wiring and a sixth signal wiring, the third differential pair being adjacent to the second differential pair, wherein the first differential pair is arranged between the second differential pair and the first fixed potential wiring, wherein the second differential pair is arranged between the third differential pair and the first differential pair, and A first distance between the first differential pair and the second differential pair is smaller than a second distance between the second differential pair and the third differential pair. 14 . The electronic device according to claim 13 , wherein the third differential pair and the second fixed potential wiring are adjacent to each other.

15. The electronic device according to claim 13, wherein the plurality of signal wirings further include a fourth differential pair consisting of a seventh signal wiring and an eighth signal wiring, the fourth differential pair being adjacent to the third differential pair, wherein the third differential pair is arranged between the fourth differential pair and the second differential pair, and Wherein a third distance between the third differential pair and the fourth differential pair is smaller than the second distance. The electronic device according to claim 15 , wherein the first distance and the third distance are identical to each other. 17 . The electronic device according to claim 16 , wherein the fourth differential pair and the second fixed potential wiring are adjacent to each other.

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