Shield grid type image sensing device with piezoresistive sensing function and preparation method thereof

Abstract

The invention relates to the technical field of image sensing devices, in particular to a shield grid type image sensing device with a piezoresistive sensing function and a preparation method of the shield grid type image sensing device. The shield grid type image sensing device with the piezoresistive sensing function comprises a plurality of pixels, and each pixel comprises a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S; and the driving backboard is provided with a plurality of via holes which are regularly arranged, the driving backboard bears a plurality of pixels, and the driving backboard drives the red image sensing sub-pixel R, the green image sensing sub-pixel G and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information. The shielding grid type sensing module prepared by using a semiconductor process can efficiently receive external pressure and image information, and a feasible scheme is provided for interactive single-chip integration.

Description

Technical Field

[0001] The present invention relates to the technical field of image sensor devices, and in particular to a shielded grid type image sensor device equipped with a piezoresistive sensing function and a preparation method thereof. Background Art

[0002] The performance of an image sensor depends not only on the number of pixels, but also on a variety of factors such as pixel size, size of the photosensitive element, signal-to-noise ratio, etc. With the advancement of technology, image sensors are developing in the direction of high resolution, miniaturization, low power consumption, and low cost to meet the growing market demand. However, if the image sensor of the prior art wants to receive external pressure information in real time, it needs to be equipped with a pressure sensing device, and the pixel arrangement of the existing image sensor needs to be optimized.

[0003] If the piezoresistive sensor is formed in the manufacturing process of the image sensor, it can provide a practical solution for the single-chip integration of interactive display. Summary of the invention

[0004] The technical problem to be solved by the present invention is: in order to solve the problems existing in the prior art in the above-mentioned background technology, a shielded gate type image sensor device equipped with a piezoresistive sensing function is provided.

[0005] The technical solution adopted by the present invention to solve the technical problem is: a shielded gate type image sensor device equipped with a piezoresistive sensing function, comprising: A plurality of pixels, each of the pixels comprising a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S; A driving backplane, wherein a plurality of regularly arranged vias are provided on the driving backplane, wherein the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B or the pressure sensing sub-pixel S covers at least one via, and the driving backplane carries a plurality of pixels and respectively drives the red image sensing sub-pixel R, the green image sensing sub-pixel G and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information; The red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S each include an anode, a semiconductor device and an ITO thin film layer, wherein the anode is disposed on the driving backplane and covers at least one via hole, the semiconductor device is located on a side of the anode away from the driving backplane, and the ITO thin film layer is located on a side of the semiconductor device away from the driving backplane; The semiconductor device comprises a P-type collector region, an N-type buffer layer, an N-type drift layer, a P-type base region, a gate, a metal shielding layer, an N+ region and an emitter region.

[0006] Furthermore, the P-type collector region is located on the side of the anode away from the driving backplane, an N-type buffer layer and an N-type drift layer are sequentially formed on the P-type collector region, a P-type base region is formed on the N-type drift layer, a gate is provided from the upper surface of the P-type base region to the upper part of the N-type drift layer, a metal shielding layer is provided on the outside of the gate, an N+ region is provided in the N-type drift layer, and an emitter region is provided on the metal shielding layer.

[0007] Furthermore, the ITO thin film layer in the pressure sensing sub-pixel S is provided with a Si layer with a hollow structure, a SiO2 layer is provided on the Si layer, a P-type silicon is provided on the SiO2 layer, a P-type silicon is connected to a P-type single crystal silicon sensing film with a piezoresistive electrode on the P-type silicon, a through hole is provided from the upper surface of the P-type silicon to the lower bottom surface of the Si layer, and tungsten connecting the P-type single crystal silicon sensing film and the ITO thin film layer is provided in the through hole.

[0008] Furthermore, it also includes an interlayer dielectric layer and a common cathode, the interlayer dielectric layer is produced and filled between the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S, and the interlayer dielectric layers corresponding to the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B are all provided with electrode grooves, the common cathode is arranged on the side of the interlayer dielectric layer away from the driving backplane and covers the electrode grooves, and the common cathode contacts the upper surfaces of the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B through the electrode grooves, and in the pressure sensing sub-pixel S, the P-type silicon is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film.

[0009] Furthermore, it also includes a packaging layer, which is located on a side of the common cathode away from the driving backplane and covers the common cathode.

[0010] Furthermore, it also includes an RGB filter layer, a microlens and a thin film encapsulation layer, wherein the RGB filter layer is arranged on a side of the encapsulation layer away from the driving backplane, and the RGB filter layer includes a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix, and the red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the encapsulation layer; the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the red filter unit R, the green filter unit G and the blue filter unit B are all provided with a microlens on the side away from the driving backplane, and the thin film encapsulation layer is arranged above the microlens and covers the microlens and the RGB filter layer.

[0011] A method for preparing a shielded gate type image sensor device equipped with a piezoresistive sensing function is also mentioned, comprising the following steps: S1, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; S2, sequentially growing a P-type collector region, an N-type buffer layer and an N-type drift layer on the driving back plate and the anode to form a semiconductor layer; S3, patterning the semiconductor layer, filling the removed portion with the interlayer dielectric layer, and smoothing the interlayer dielectric layer using a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type drift layer; S4, ion implantation on the upper surface of the N-type drift layer to form a P-type base region; S5, etching a groove with an arc-shaped cross-section from the upper surface of the P-type base region to the upper part of the N-type drift layer and growing a gate oxide layer on the surface of the groove; S6, growing a polysilicon gate in a trench with a gate oxide layer on the surface, digging a deep trench outside the polysilicon gate and depositing a metal shielding layer, and growing a SiO2 passivation protection layer on the outer surface of the metal shielding layer, the polysilicon gate and the P-type base region; S7, patterning the SiO2 passivation protection layer, forming a through hole in the middle of the SiO2 passivation protection layer, implanting ions into the P-type base region through the through hole to form an N+ region, and growing an emitter region on the SiO2 passivation protection layer; S8, coating an ITO thin film layer on the emitter region, growing a filling interlayer dielectric layer, and smoothing the interlayer dielectric layer using a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer; S9, depositing a Si layer on the ITO thin film layer of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer and a P-type silicon layer on the top of the Si layer of the hollow structure, and then performing deep silicon etching and drilling, depositing tungsten in the hole by a CVD process, and then bonding a P-type single crystal silicon sensing film with a piezoresistive electrode by a bonding process; S10, setting a common cathode, growing and patterning a packaging layer; S11, prepare an RGB filter layer on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B using a yellow light process, and make microlenses on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer, and finally make a thin film encapsulation layer on the RGB filter layer and the microlens.

[0012] Another method for preparing a shielded gate type image sensor device with a piezoresistive sensing function is also mentioned, comprising the following steps: Sa, forming a number of regularly arranged via holes on the driving backplane, and filling the via holes with a conductive material, and then forming a number of anodes on the upper surface of the driving backplane, and each anode covers at least one via hole; Sb, sequentially growing a P-type collector region, an N-type buffer layer and an N-type drift layer on the driving back plate and the anode to form a semiconductor layer; Sc, patterning the semiconductor layer, filling the removed portion with an interlayer dielectric layer, and smoothing the interlayer dielectric layer using a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the N-type drift layer; Sd and N-type drift layer are ion-implanted to form a P-type base region; Se, etching a rectangular groove with a step at the bottom from the upper surface of the P-type base region to the lower part of the N-type drift layer and growing a gate oxide layer on the surface of the groove; Sf, growing a polysilicon gate and a metal shielding layer on the two step surfaces respectively, and at the same time growing a SiO2 passivation protection layer on the outer surfaces of the metal shielding layer, the polysilicon gate and the P-type base region; Sg, a patterned SiO2 passivation protection layer, a through hole is formed in the middle of the SiO2 passivation protection layer, ions are implanted into the P-type base region through the through hole to form an N+ region, and an emitter region is grown on the SiO2 passivation protection layer; Sh, coating an ITO thin film layer on the emitter region, growing a filling interlayer dielectric layer, and grinding the interlayer dielectric layer by a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer is flush with the upper surface of the ITO thin film layer; Si, depositing a Si layer on the ITO thin film layer of the pressure sensing sub-pixel S and patterning it to form a hollow structure, growing a thin SiO2 layer and a P-type silicon layer on the top of the Si layer of the hollow structure in sequence, and then performing deep silicon etching and drilling, depositing tungsten in the hole using a CVD process, and then bonding a P-type single crystal silicon sensing film with a piezoresistive electrode through a bonding process; Sj, setting a common cathode, growing and patterning a packaging layer; Sk, prepare an RGB filter layer on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B using a yellow light process, and make microlenses on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer, and finally make a thin film encapsulation layer on the RGB filter layer and the microlens.

[0013] Beneficial effects of the present invention: The present invention uses a shielded grid type sensor module prepared by semiconductor technology, which can efficiently receive external pressure and image information, and provides a practical solution for interactive single-chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0015] Figure 1 It is a structural diagram of embodiment 1 of the present invention.

[0016] Figure 2It is a schematic diagram of step 1 of embodiment 1 of the present invention.

[0017] Figure 3 It is a schematic diagram of step 2 of embodiment 1 of the present invention.

[0018] Figure 4 It is a schematic diagram of step 3 of embodiment 1 of the present invention.

[0019] Figure 5 It is a schematic diagram of step 4 of embodiment 1 of the present invention.

[0020] Figure 6 It is a schematic diagram of step 5 of embodiment 1 of the present invention.

[0021] Figure 7 It is a schematic diagram of step 6 of embodiment 1 of the present invention.

[0022] Figure 8 It is a schematic diagram of step 7 of embodiment 1 of the present invention.

[0023] Fig. 9 It is a schematic diagram of step 8 of embodiment 1 of the present invention.

[0024] Fig.10 It is a schematic diagram of step 9 of embodiment 1 of the present invention.

[0025] Fig.11 It is a schematic diagram of step 10 of the first embodiment of the present invention.

[0026] Fig.12 It is a structural diagram of step 11 of the first embodiment of the present invention.

[0027] Fig.13 It is a structural diagram of embodiment 2 of the present invention.

[0028] Fig.14 It is a schematic diagram of step a of embodiment 2 of the present invention.

[0029] Fig.15 It is a schematic diagram of step b of embodiment 2 of the present invention.

[0030] Fig.16 It is a schematic diagram of step c of embodiment 2 of the present invention.

[0031] Fig.17 It is a schematic diagram of step d of embodiment 2 of the present invention.

[0032] Fig.18 It is a schematic diagram of step e of embodiment 2 of the present invention.

[0033] Fig.19 It is a schematic diagram of step f of embodiment 2 of the present invention.

[0034] Fig. 20It is a schematic diagram of step g of embodiment 2 of the present invention.

[0035] Fig.21 It is a schematic diagram of step h of embodiment 2 of the present invention.

[0036] Fig. 22 It is a schematic diagram of step i of embodiment 2 of the present invention.

[0037] Fig.23 It is a schematic diagram of step j of embodiment 2 of the present invention.

[0038] Fig.24 It is a schematic diagram of step k of embodiment 2 of the present invention.

[0039] Fig.25 It is a diagram of the optimized pixel arrangement scheme of Embodiment 1 and Embodiment 2 of the present invention.

[0040] Fig.26 1 is a driving circuit diagram of Embodiment 1 and Embodiment 2 of the present invention.

[0041] In the figure: 1. driving backplane; 2. via; 3. anode; 4. semiconductor device; 41. P-type collector region; 42. N-type buffer layer; 43. N-type drift layer; 44. P-type base region; 45. gate; 46. metal shielding layer; 47. N+ region; 48. emitter region; 49. SiO2 passivation protection layer; 410. gate oxide layer; 5. ITO thin film layer; 6. Si layer; 7. SiO2 layer; 8. P-type silicon; 9. P-type single crystal silicon sensing film; 10. tungsten; 11. interlayer dielectric layer; 12. common cathode; 13. packaging layer; 14. RGB filter layer; 15. microlens; 16. thin film packaging layer. DETAILED DESCRIPTION

[0042] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0043] Embodiment 1 like Figure 1As shown, a shielded gate type image sensor device with a piezoresistive sensing function includes: a plurality of pixels, each of which includes a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S; a driving backplane 1, on which a plurality of regularly arranged via holes 2 are provided, and the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B or the pressure sensing sub-pixel S covers at least one via hole 2, and the driving backplane 1 carries a plurality of pixels and drives the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B or the pressure sensing sub-pixel S respectively. Sub-pixel R, green image sensing sub-pixel G and light-emitting sub-pixel B receive image information and drive pressure sensing sub-pixel S to receive pressure information; red image sensing sub-pixel R, green image sensing sub-pixel G, blue image sensing sub-pixel B and pressure sensing sub-pixel S all include an anode 3, a semiconductor device 4 and an ITO thin film layer 5, the anode 3 is arranged on the driving backplane 1 and covers at least one via 2, the semiconductor device 4 is located on the side of the anode 3 away from the driving backplane 1, and the ITO thin film layer 5 is located on the side of the semiconductor device 4 away from the driving backplane 1.

[0044] It also includes an interlayer dielectric layer 11 and a common cathode 12. The interlayer dielectric layer 11 is filled between the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S. The interlayer dielectric layer 11 corresponding to the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B is provided with an electrode groove. The common cathode 12 is arranged on the side of the interlayer dielectric layer 11 away from the driving backplane 1 and covers the electrode groove. The common cathode 12 contacts the upper surface of the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B through the electrode groove. In the pressure sensing sub-pixel S, the common cathode 8 is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film 9. It also includes an encapsulation layer 13. The encapsulation layer 13 is located on the side of the common cathode 12 away from the driving backplane 1 and covers the common cathode 12.

[0045] It also includes an RGB filter layer 14, a microlens 15 and a thin film encapsulation layer 16. The RGB filter layer 14 is arranged on a side of the encapsulation layer 13 away from the driving backplane 1. The RGB filter layer 14 includes a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix. The red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the encapsulation layer 13; the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B, and the red filter unit R, the green filter unit G and the blue filter unit B are all provided with a microlens 15 on one side away from the driving backplane 1. The thin film encapsulation layer 16 is arranged above the microlens 15 and covers the microlens 15 and the RGB filter layer 14.

[0046] Among them, the semiconductor device 4 includes a P-type collector region 41, an N-type buffer layer 42, an N-type drift layer 43, a P-type base region 44, a gate 45, a metal shielding layer 46, an N+ region 47 and an emitter region 48. The P-type collector region 41 is located on the side of the anode 3 away from the driving backplane 1. An N-type buffer layer 42 and an N-type drift layer 43 are sequentially formed on the P-type collector region 41. A P-type base region 44 is formed on the N-type drift layer 43. A gate 45 is provided from the upper surface of the P-type base region 44 to the upper part of the N-type drift layer 43. A metal shielding layer 46 is provided on the outer side of the gate 45. An N+ region 47 is provided in the N-type drift layer 43, and an emitter region 48 is provided on the metal shielding layer 46.

[0047] A Si layer 6 with a hollow structure is provided on the ITO thin film layer 5 in the pressure sensing sub-pixel S, a Si layer 6 is provided on the Si layer 6, a SiO2 layer 7 is provided on the SiO2 layer 7, a P-type silicon 8 is provided on the P-type silicon 8, a P-type single crystal silicon sensing film 9 with a piezoresistive electrode is connected to the P-type silicon 8, a through hole is provided from the upper surface of the P-type silicon 8 to the lower bottom surface of the Si layer 6, and tungsten 10 connecting the P-type single crystal silicon sensing film 9 and the ITO thin film layer 5 is provided in the through hole.

[0048] The method for preparing the shielded gate type image sensor device with piezoresistive sensing function of the first embodiment comprises the following specific steps: Step 1: If Figure 2 As shown, a plurality of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes 2, and then a plurality of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step 2: If Figure 3 As shown, a P-type collector region 41, an N-type buffer layer 42 and an N-type drift layer 43 are sequentially grown on the driving back plate 1 and the anode 3 to form a semiconductor layer; Step 3: If Figure 4 As shown, the patterned semiconductor layer is filled with the removed portion through the interlayer dielectric layer 11, and the interlayer dielectric layer 11 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the N-type drift layer 43; Step 4: Figure 5 As shown, ions are implanted on the upper surface of the N-type drift layer 43 to form a P-type base region 44; Step 5: Figure 6 As shown, a groove with an arc-shaped cross section is etched from the upper surface of the P-type base region 44 to the upper part of the N-type drift layer 43, and a gate oxide layer 410 is grown on the surface of the groove; Step 6: Figure 7 As shown, a polysilicon gate 45 is grown in a groove with a gate oxide layer 410 on the surface, and a deep groove is dug outside the polysilicon gate 45 and a metal shielding layer 46 is deposited, and a SiO2 passivation protection layer 49 is grown on the outer surface of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44; Step 7: Figure 8 As shown, a SiO2 passivation protection layer 49 is patterned, a through hole is formed in the middle of the SiO2 passivation protection layer 49, ions are implanted into the P-type base region 44 through the through hole to form an N+ region 47, and an emitter region 48 is grown on the SiO2 passivation protection layer 49; Step 8: Fig. 9 As shown, an ITO thin film layer 5 is plated on the emitter region 48, an interlayer dielectric layer 11 is grown and filled, and the interlayer dielectric layer 11 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the ITO thin film layer 5; Step 9: Fig.10 As shown, a Si layer 6 is deposited on the ITO thin film layer 5 of the pressure sensing sub-pixel S and patterned to form a hollow structure, a thin SiO2 layer 7 and a P-type silicon 8 are sequentially grown on the top of the Si layer 6 of the hollow structure, and then deep silicon etching is performed to drill holes and tungsten 10 is deposited in the holes by a CVD process, and then a P-type single crystal silicon sensing film 9 with a piezoresistive electrode is bonded by a bonding process; Step 10: Fig.11 As shown, a common cathode 12 is provided, and an encapsulation layer 13 is grown and patterned; Step 11: Fig.12 As shown, an RGB filter layer 14 is prepared on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B by using a yellow light process, and a microlens 15 is made on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer 14. Finally, a thin film encapsulation layer 16 is made on the RGB filter layer 14 and the microlens 15. The current flow is shown by the red arrow in the semiconductor device 4.

[0049] Embodiment 2 The difference from the first embodiment is that: Fig.13 As shown, a rectangular groove with a step at the bottom is etched from the upper surface of the P-type base region 44 to the lower part of the N-type drift layer 43, and a gate oxide layer is grown on the surface of the groove; a polysilicon gate 45 and a metal shielding layer 46 are grown on the two step surfaces respectively, and at the same time, a SiO2 passivation protection layer 49 is grown on the outer surfaces of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44.

[0050] The method for preparing the shielded gate type image sensor device with piezoresistive sensing function of the second embodiment comprises the following specific steps: Step a: Fig.14 As shown, a plurality of regularly arranged via holes 2 are formed on the driving back plate 1, and a conductive material is filled in the via holes 2, and then a plurality of anodes 3 are formed on the upper surface of the driving back plate 1, and each anode 3 covers at least one via hole 2; Step b: Fig.15As shown, a P-type collector region 41, an N-type buffer layer 42 and an N-type drift layer 43 are sequentially grown on the driving back plate 1 and the anode 3 to form a semiconductor layer; Step c: Fig.16 As shown, the patterned semiconductor layer is filled with the removed portion through the interlayer dielectric layer 11, and the interlayer dielectric layer 11 is polished by a chemical mechanical polishing process so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the N-type drift layer 43; Step d: Fig.17 As shown, ions are implanted on the upper surface of the N-type drift layer 43 to form a P-type base region 44; Step e: Fig.18 As shown, a rectangular trench with a step at the bottom is etched from the upper surface of the P-type base region 44 to the lower part of the N-type drift layer 43, and a gate oxide layer 410 is grown on the surface of the trench; Step f: Fig.19 As shown, a polysilicon gate 45 and a metal shielding layer 46 are grown on the two step surfaces respectively, and at the same time, a SiO2 passivation protection layer 49 is grown on the outer surfaces of the metal shielding layer 46, the polysilicon gate 45 and the P-type base region 44; Step g: Fig. 20 As shown, a SiO2 passivation protection layer 49 is patterned, a through hole is formed in the middle of the SiO2 passivation protection layer 49, ions are implanted into the P-type base region 44 through the through hole to form an N+ region 47, and an emitter region 48 is grown on the SiO2 passivation protection layer 49; Step h: Fig.21 As shown, an ITO thin film layer 5 is plated on the emitter region 48, an interlayer dielectric layer 11 is grown and filled, and the interlayer dielectric layer 11 is smoothed by a chemical mechanical polishing process, so that the upper surface of the interlayer dielectric layer 11 is flush with the upper surface of the ITO thin film layer 5; Step i: Fig. 22 As shown, a Si layer 6 is deposited on the ITO thin film layer 5 of the pressure sensing sub-pixel S and patterned to form a hollow structure, a thin SiO2 layer 7 and a P-type silicon 8 are sequentially grown on the top of the Si layer 6 of the hollow structure, and then deep silicon etching is performed to drill holes and tungsten 10 is deposited in the holes by a CVD process, and then a P-type single crystal silicon sensing film 9 with a piezoresistive electrode is bonded by a bonding process; Step j: Fig.23 As shown, a common cathode 12 is provided, and an encapsulation layer 13 is grown and patterned; Step k: Fig.24As shown, an RGB filter layer 14 is prepared on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B by using a yellow light process, and a microlens 15 is made on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer 14. Finally, a thin film encapsulation layer 16 is made on the RGB filter layer 14 and the microlens 15. The current flow is shown by the red arrow in the semiconductor device 4.

[0051] The optimized pixel arrangement schemes of the first and second embodiments are as follows: Fig.25 As shown, a pixel includes a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S. In terms of spatial distribution, the four vertices of a square include the green image sensing sub-pixel G and the blue image sensing sub-pixel B at the two diagonal vertices and the red image sensing sub-pixel R and the pressure sensing sub-pixel S at the remaining two vertices, and the side length of the square is equal to the pixel width. Four concentrated red image sensing sub-pixels R, green image sensing sub-pixels G, blue image sensing sub-pixels B or pressure sensing sub-pixels S are grouped together and share a mask opening.

[0052] Embodiment 1 and embodiment 2 adopt Fig.25 The pixel optimization arrangement scheme shown in combination with the high-resolution driving backplane 1 can break through the physical limit of the existing high-resolution metal mask FMM, achieving high-resolution, high-brightness, high-contrast display with low response time.

[0053] Embodiment 1 and embodiment 2 are matched as follows Fig.26 The driving circuit shown can improve the performance and reliability of the display, and has the beneficial effects of high integration, low power consumption, high speed and good stability, so that it has a wide range of applications.

[0054] Based on the above ideal embodiments of the present invention, the relevant staff can make various changes and modifications without departing from the technical concept of the present invention through the above description. The technical scope of the present invention is not limited to the contents of the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A shielded gate type image sensor device equipped with a piezoresistive sensing function, characterized in that: include: A plurality of pixels, each of the pixels comprising a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S; A driving backplane (1), wherein a plurality of regularly arranged via holes (2) are provided on the driving backplane (1), wherein the red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B or the pressure sensing sub-pixel S covers at least one via hole (2), and the driving backplane (1) carries a plurality of pixels and respectively drives the red image sensing sub-pixel R, the green image sensing sub-pixel G and the light-emitting sub-pixel B to receive image information and drives the pressure sensing sub-pixel S to receive pressure information; The red image sensing sub-pixel R, the green image sensing sub-pixel G, the blue image sensing sub-pixel B and the pressure sensing sub-pixel S all comprise an anode (3), a semiconductor device (4) and an ITO thin film layer (5); the anode (3) is arranged on the driving backplane (1) and covers at least one via hole (2); the semiconductor device (4) is located on a side of the anode (3) away from the driving backplane (1); and the ITO thin film layer (5) is located on a side of the semiconductor device (4) away from the driving backplane (1); The semiconductor device (4) comprises a P-type collector region (41), an N-type buffer layer (42), an N-type drift layer (43), a P-type base region (44), a gate (45), a metal shielding layer (46), an N+ region (47) and an emitter region (48).

2. The shielded gate type image sensor device with piezoresistive sensing function according to claim 1, characterized in that: The P-type collector region (41) is located on a side of the anode (3) away from the driving back plate (1); an N-type buffer layer (42) and an N-type drift layer (43) are sequentially formed on the P-type collector region (41); a P-type base region (44) is formed on the N-type drift layer (43); a gate (45) is provided from the upper surface of the P-type base region (44) to the upper part of the N-type drift layer (43); a metal shielding layer (46) is provided on the outer side of the gate (45); an N+ region (47) is provided in the N-type drift layer (43); and an emitter region (48) is provided on the metal shielding layer (46).

3. The shielded gate type image sensor device with piezoresistive sensing function according to claim 1, characterized in that: A Si layer (6) with a hollow structure is provided on the ITO thin film layer (5) in the pressure sensing sub-pixel S, a SiO2 layer (7) is provided on the Si layer (6), a P-type silicon (8) is provided on the SiO2 layer (7), a P-type single crystal silicon sensing film (9) with a piezoresistive electrode is connected to the P-type silicon (8), a through hole is provided from the upper surface of the P-type silicon (8) to the lower bottom surface of the Si layer (6), and tungsten (10) connecting the P-type single crystal silicon sensing film (9) and the ITO thin film layer (5) is provided in the through hole.

4. The shielded gate type image sensor device with piezoresistive sensing function according to claim 3, characterized in that: It also includes an interlayer dielectric layer (11) and a common cathode (12), wherein the interlayer dielectric layer (11) is filled between a red image sensing sub-pixel R, a green image sensing sub-pixel G, a blue image sensing sub-pixel B and a pressure sensing sub-pixel S, and the interlayer dielectric layer (11) corresponding to the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B is provided with an electrode groove, and the common cathode (12) is arranged on a side of the interlayer dielectric layer (11) away from the driving backplane (1) and covers the electrode groove, and the common cathode (12) contacts the upper surfaces of the red image sensing sub-pixel R, the green image sensing sub-pixel G and the blue image sensing sub-pixel B through the electrode groove, and in the pressure sensing sub-pixel S, the P-type silicon (8) is connected to the piezoresistive electrode of the P-type single crystal silicon sensing film (9).

5. The shielded gate type image sensor device with piezoresistive sensing function according to claim 4, characterized in that: It also includes a packaging layer (13), wherein the packaging layer (13) is located on a side of the common cathode (12) away from the driving backplane (1) and covers the common cathode (12).

6. The shielded gate type image sensor device with piezoresistive sensing function according to claim 5, characterized in that: The invention also comprises an RGB filter layer (14), a microlens (15) and a thin film encapsulation layer (16); the RGB filter layer (14) is arranged on a side of the encapsulation layer (13) away from the driving backplane (1); the RGB filter layer (14) comprises a red filter unit R, a green filter unit G, a blue filter unit B and a black matrix; the red filter unit R, the green filter unit G and the blue filter unit B are arranged in sequence and spaced apart on the upper surface of the encapsulation layer (13); the black matrix is ​​arranged around the periphery of the red filter unit R, the green filter unit G and the blue filter unit B; the red filter unit R, the green filter unit G and the blue filter unit B are all provided with a microlens (15) on a side of the red filter unit R, the green filter unit G and the blue filter unit B away from the driving backplane (1); and the thin film encapsulation layer (16) is arranged above the microlens (15) and covers the microlens (15) and the RGB filter layer (14).

7. A method for preparing a shielded gate type image sensor device with a piezoresistive sensing function according to any one of claims 1 to 6, characterized in that: The steps include: S1, forming a plurality of regularly arranged via holes (2) on a driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); S2, sequentially growing a P-type collector region (41), an N-type buffer layer (42) and an N-type drift layer (43) on the driving back plate (1) and the anode (3) to form a semiconductor layer; S3, patterning the semiconductor layer, filling the removed portion with an interlayer dielectric layer (11), and smoothing the interlayer dielectric layer (11) using a chemical mechanical smoothing process, so that the upper surface of the interlayer dielectric layer (11) is flush with the upper surface of the N-type drift layer (43); S4, ion implantation on the upper surface of the N-type drift layer (43) to form a P-type base region (44); S5, etching a groove with an arc-shaped cross-section from the upper surface of the P-type base region (44) to the upper part of the N-type drift layer (43) and growing a gate oxide layer on the surface of the groove; S7, growing a polysilicon gate (45) in a trench with a gate oxide layer on the surface, digging a deep trench outside the polysilicon gate (45) and depositing a metal shielding layer (46), and growing a SiO2 passivation protection layer (49) on the outer surfaces of the metal shielding layer (46), the polysilicon gate (45) and the P-type base region (44); S8, patterning the SiO2 passivation protection layer (49), forming a through hole in the middle of the SiO2 passivation protection layer (49), implanting ions into the P-type base region (44) through the through hole to form an N+ region (47), and growing an emitter region (48) on the SiO2 passivation protection layer (49); S9, coating an ITO thin film layer (5) on the emitter region (48), growing a filling interlayer dielectric layer (11), and grinding the interlayer dielectric layer (11) using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (11) is flush with the upper surface of the ITO thin film layer (5); S10, depositing a Si layer (6) on the ITO thin film layer (5) of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer (7) and a P-type silicon (8) on the top of the Si layer (6) of the hollow structure, then performing deep silicon etching to drill holes and depositing tungsten (10) in the holes using a CVD process, and then bonding a P-type single crystal silicon sensing film (9) with a piezoresistive electrode using a bonding process; S11, setting a common cathode (12), growing and patterning a packaging layer (13); S12, using a yellow light process to prepare an RGB filter layer (14) on the red image sensing sub-pixel R, the green image sensing sub-pixel G, and the blue image sensing sub-pixel B, and fabricating a microlens (15) on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer (14), and finally fabricating a thin film encapsulation layer (16) on the RGB filter layer (14) and the microlens (15).

8. A method for preparing a shielded gate type image sensor device with a piezoresistive sensing function according to any one of claims 1 to 6, characterized in that: The steps include: Sa, forming a plurality of regularly arranged via holes (2) on the driving back plate (1), and filling the via holes (2) with a conductive material, and then forming a plurality of anodes (3) on the upper surface of the driving back plate (1), with each anode (3) covering at least one via hole (2); Sb, sequentially growing a P-type collector region (41), an N-type buffer layer (42) and an N-type drift layer (43) on the driving back plate (1) and the anode (3) to form a semiconductor layer; Sc, a patterned semiconductor layer, the removed portion is filled with an interlayer dielectric layer (11), and the interlayer dielectric layer (11) is smoothed by a chemical mechanical smoothing process, so that the upper surface of the interlayer dielectric layer (11) is flush with the upper surface of the N-type drift layer (43); Sd and N-type drift layer (43) are ion-implanted onto the upper surface to form a P-type base region (44); Se, etching a rectangular groove with a step bottom from the upper surface of the P-type base region (44) to the lower part of the N-type drift layer (43) and growing a gate oxide layer on the surface of the groove; Sf, respectively growing a polysilicon gate (45) and a metal shielding layer (46) on the two step surfaces, and at the same time growing a SiO2 passivation protection layer (49) on the outer surfaces of the metal shielding layer (46), the polysilicon gate (45) and the P-type base region (44); Sg, a patterned SiO2 passivation protection layer (49), forming a through hole in the middle of the SiO2 passivation protection layer (49), implanting ions into the P-type base region (44) through the through hole to form an N+ region (47), and growing an emitter region (48) on the SiO2 passivation protection layer (49); Sh, coating an ITO thin film layer (5) on the emitter region (48), growing a filling interlayer dielectric layer (11), and grinding the interlayer dielectric layer (11) using a chemical mechanical grinding process so that the upper surface of the interlayer dielectric layer (11) is flush with the upper surface of the ITO thin film layer (5); Si, depositing a Si layer (6) on the ITO thin film layer (5) of the pressure sensing sub-pixel S and patterning it to form a hollow structure, sequentially growing a thin SiO2 layer (7) and a P-type silicon (8) on the top of the Si layer (6) of the hollow structure, and then performing deep silicon etching to drill holes and depositing tungsten (10) in the holes by a CVD process, and then bonding a P-type single crystal silicon sensing film (9) with a piezoresistive electrode by a bonding process; Sj, setting a common cathode (12), growing and patterning an encapsulation layer (13); Sk, using a yellow light process to prepare an RGB filter layer (14) on a red image sensing sub-pixel R, a green image sensing sub-pixel G, and a blue image sensing sub-pixel B, and manufacturing microlenses (15) on the red filter unit R, the green filter unit G, and the blue filter unit B of the RGB filter layer (14); and finally manufacturing a thin film encapsulation layer (16) on the RGB filter layer (14) and the microlens (15).

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