Light detection element and method for manufacturing light detection element

Abstract

The purpose of the present invention is to alleviate the restriction of the arrangement position of a through electrode connected to an external terminal of a packaged light detection element. The light detection element includes: a first chip on which a first wiring layer is formed; a second chip on which a second wiring layer is formed, the second chip being laminated on the first chip; a third chip on which a third wiring layer is formed, the third chip being stacked on the first chip, the third chip being aligned with a gap of an opening between the third chip and the second chip; a buried layer stacked on the first chip such that the second chip and the third chip are buried; and a through electrode positioned between the second chip and the third chip, penetrating the buried layer, and connected to the first wiring layer. The first wiring layer may also be directly bonded to the second wiring layer and the third wiring layer.

Description

Technical Field

[0001] The present technology relates to a light detection element and a method for manufacturing the light detection element. Specifically, the present technology relates to a wiring structure of the light detection element. Background Art

[0002] In the packaging of semiconductor chips, a three-dimensional integrated structure in which a single semiconductor chip is laminated can be used to suppress the increase in the mounting area. As such a three-dimensional integrated structure, for example, there is a structure in which a single memory circuit and a logic circuit are arranged in a horizontal direction, embedded with an oxide film, and flattened, and then laminated so as to be included in the plane direction under the solid-state imaging device (see patent documents 1 and 3). In addition, there is a structure in which a first connection via connects a first substrate structure and a second substrate structure, penetrates the first substrate and the first interlayer insulating layer, extends to the second interlayer insulating layer of the second substrate structure, and is connected to the second wiring layer of the second interlayer insulating layer and the first wiring layer of the first interlayer insulating layer (for example, see patent document 2).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: WO 2019 / 087764 A

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 2019-68049

[0007] Patent Document 3: WO 2020129686A Summary of the invention

[0008] Problems to be solved by the present invention

[0009] However, in the above conventional technology, since the arrangement position of the through-electrodes connected to the external terminals of the package is greatly restricted, there is a possibility that the path length from the laminated chip to the external terminals increases or the number of external terminals to be arranged is restricted.

[0010] The present invention has been made in view of the above circumstances, and an object of the present invention is to relax restrictions on the layout position of a through electrode connected to an external terminal of a packaged light detecting element.

[0011] Solution to the problem

[0012] The present technology is made to solve the above-mentioned problems. The first mode of the present invention provides a light detecting element, which includes: a first chip, on which a first wiring layer is formed; a second chip, which is laminated on the first chip, and a second wiring layer is formed on the second chip; a third chip, which is arranged side by side with the second chip and laminated on the first chip, and a third wiring layer is formed on the third chip; an embedded layer, which is laminated on the first chip so that the second chip and the third chip are embedded in the embedded layer; and a through electrode, which is located between the second chip and the third chip, penetrates the embedded layer and is connected to the first wiring layer. This has the effect of alleviating the limitation of the layout position of the through electrode connected to the external terminal of the packaged light detecting element.

[0013] In addition, according to the first aspect, the first wiring layer can be directly bonded to the second wiring layer and the third wiring layer. This has the effect of enabling miniaturization of connection portions of wiring layers formed on different chips.

[0014] In addition, according to the first aspect, a support substrate disposed on the embedded layer may be further included, and the through electrode may penetrate the support substrate and the embedded layer and be connected to the first wiring layer. This has the effect of being able to cope with the thinning of the chip and ensuring the strength of the packaged light detection element.

[0015] In addition, according to the first aspect, a sensor chip may be further included, on which the first chip is laminated, and the sensor chip has a fourth wiring layer formed on the front surface side and pixels formed on the rear surface side. This has the effect of suppressing the increase in the mounting area of ​​the packaged light detection element and adding a data processing function, a storage function, etc. to the imaging function.

[0016] In addition, according to the first aspect, the first wiring layer may include: a front surface wiring layer formed on the front surface side of the first chip; a rear surface wiring layer formed on the rear surface side of the first chip; the front surface wiring layer may be directly bonded to the fourth wiring layer; the rear surface wiring layer may be directly bonded to the second wiring layer and the third wiring layer; and the through electrode may penetrate the embedded layer and be connected to the rear surface wiring layer. This has the effect of easing the limitation of the arrangement position of the through electrode connected to the external terminal of the packaged light detection element.

[0017] Furthermore, according to the first aspect, a transparent substrate provided on the sensor chip may be further included. This has the effect of being able to cope with the thinning of the sensor chip and ensuring the strength of the packaged light detection element.

[0018] In addition, according to the first aspect, a cavity may be further included to separate the imaging region of the sensor chip from the transparent substrate. This has the effect of ensuring the strength of the packaged light detection element without affecting the optical function of the sensor chip.

[0019] In addition, the second aspect provides a light detection element, comprising: a first chip on which a first wiring layer is formed; a second chip laminated on the first chip and a second wiring layer formed on the second chip; an embedded layer laminated on the first chip so that the second chip is embedded in the embedded layer; a redistribution layer formed on the embedded layer; and a through electrode penetrating the embedded layer and connecting the redistribution layer and the first wiring layer. This has the effect of alleviating the limitation of the arrangement position of the through electrode connected to the external terminal of the packaged light detection element.

[0020] In addition, a third mode provides a light detection element, comprising: a first chip on which a first wiring layer is formed; a second chip mounted face-down on the first wiring layer and on which a second wiring layer is formed; an embedding layer laminated on the first chip so that the second chip is embedded in the embedding layer; and a first through-electrode penetrating the embedding layer and connected to the second wiring layer via the first wiring layer. This has the effect that the first through-electrode connected to the second wiring layer on the semiconductor layer of the second chip extends to the outside without penetrating the semiconductor layer of the second chip.

[0021] In addition, according to the third aspect, a second through electrode penetrating the embedded layer and connected to the first wiring layer without the second wiring layer being interposed therebetween may be further included. This has the effect that the second through electrode connected to the first wiring layer of the first chip extends to the outside without penetrating the semiconductor layer of the second chip.

[0022] In the third aspect, the first wiring layer may be directly bonded to the second wiring layer. This has the effect of enabling miniaturization of a connection portion of wiring layers formed on different chips.

[0023] In addition, according to the third aspect, a sensor chip may be further included, on which the first chip is laminated, and the sensor chip has a third wiring layer formed on the front surface side and pixels formed on the rear surface side. This has the effect of suppressing the increase in the mounting area of ​​the packaged light detection element and adding a data processing function, a storage function, etc. to the imaging function.

[0024] In addition, according to the third aspect, the first wiring layer may include: a front surface wiring layer formed on the front surface side of the first chip; and a rear surface wiring layer formed on the rear surface side of the first chip; the front surface wiring layer may be directly bonded to the third wiring layer; the rear surface wiring layer may be directly bonded to the second wiring layer; and the first through-electrode may penetrate the embedded layer and be connected to the second wiring layer via the rear surface wiring layer. This has the effect of easing the limitation of the arrangement position of the through-electrode connected to the external terminal of the packaged light detection element.

[0025] In addition, according to the third aspect, a fourth chip may be further included, which is laminated between the sensor chip and the first chip, and the fourth chip is formed on the fourth chip. This has the effect of suppressing the increase in the mounting area of ​​the packaged light detection element and expanding the data processing function, storage function, etc. related to the imaging function.

[0026] In addition, the fourth method provides a light detecting element, which includes: a first chip, on which a first wiring layer is formed; a second chip, which forms a laminated structure with the first chip, and a second wiring layer is formed on the second chip; a third chip, which forms a laminated structure with the first chip and the second chip, and a third wiring layer is formed on the third chip; an embedded layer, which forms a laminated structure with the first chip and the second chip, so that the third chip is embedded in the embedded layer; and a first through electrode, which penetrates the embedded layer and is connected to the second wiring layer. This has the effect of being able to support a laminated structure of chips with more than 3 layers, and being able to ease the limitation of the arrangement position of the through electrode connected to the external terminal of the packaged light detecting element.

[0027] In addition, according to the fourth aspect, the first chip may be located in the first layer, the second chip may be located in the second layer, and the third chip may be located in the third layer; the light detection element may further include a second through-electrode that penetrates the embedded layer, is connected to the third wiring layer, and is shorter than the length of the first through-electrode. This has the effect of extending the through-electrode connected to the chips of different layers to the outside.

[0028] In addition, according to the fourth aspect, the first chip can be located in the first layer, the second chip can be located in the third layer, and the third chip can be located in the second layer; the light detection element can also include a second through electrode, which penetrates the semiconductor layer of the second chip, is connected to the second wiring layer, and is shorter than the length of the first through electrode; and the first through electrode can penetrate the semiconductor layer and the embedded layer of the second chip, and is connected to the second wiring layer. This has the effect of improving the strength of the packaged light detection element without supporting the substrate, and obtaining the effect of extending the through electrode connected to the chips of different layers to the outside.

[0029] Furthermore, according to the fourth aspect, at least a portion of the first through electrode may include a columnar electrode. This has the effect of forming the first through electrode penetrating the embedded layer while reducing the depth of the through hole in which the first through electrode is embedded.

[0030] In addition, in the fourth aspect, the second chip may include: a semiconductor layer on which a second wiring layer is formed; and a through hole that penetrates the semiconductor layer and is connected to the second wiring layer; and the first through electrode may penetrate the embedded layer and be connected to the second wiring layer via the through hole. This has the effect of electrically connecting to the second wiring layer formed on the second chip while reducing the depth of the through hole in which the first through electrode is embedded.

[0031] In addition, according to the fourth aspect, a dummy chip embedded in the embedding layer may be further included, and the first through-electrode may penetrate the embedding layer and the dummy chip and be connected to the second wiring layer. This has the effect of reducing the depth of the through hole formed in the embedding layer while connecting the through-electrode to the second wiring layer of the second chip laminated on the embedding layer.

[0032] In addition, according to the fourth aspect, the second chip may include a semiconductor layer formed with a second wiring layer, and the first through-electrode may penetrate the embedded layer, the dummy chip and the semiconductor layer, and be connected to the second wiring layer. This has the effect of reducing the depth of the through hole formed in the embedded layer while connecting the through-electrode to the second wiring layer of the second chip laminated on the embedded layer.

[0033] In addition, in the fourth aspect, the second chip may include: a semiconductor layer on which the second wiring layer is formed; and the first through-electrode may penetrate the embedded layer and the dummy chip and be connected to the second wiring layer via a through hole. This has the following effect: while reducing the depth of the through hole in which the through-electrode is embedded, the through-electrode is electrically connected to the second wiring layer of the second chip laminated on the embedded layer, and there is no need to form a through hole in the embedded layer.

[0034] In addition, according to the fourth aspect, a dummy chip may be included, which is embedded in the embedding layer and has a dummy wiring layer formed on the dummy substrate, and the first through-electrode may penetrate the embedding layer and the dummy substrate and be connected to the second wiring layer via the dummy wiring layer. This has the effect of electrically connecting to the second wiring layer formed on the second chip while reducing the depth of the through hole in which the through-electrode is embedded.

[0035] In addition, in the fourth aspect, it is also possible to further include a supporting substrate that supports the embedding layer in which the third chip is embedded, and the through electrode penetrates the supporting substrate. This can cope with the thinning of the chip embedded in the embedding layer and ensure the strength of the packaged light detection element.

[0036] In addition, a fifth embodiment provides a light detecting element, which includes: a first chip in which a first wiring layer is formed on a first semiconductor substrate; an embedding layer in which the first chip is embedded; a through electrode penetrating the embedding layer; and an embedding member embedded in the first semiconductor substrate at a position insulated from the first wiring layer. This has the effect of alleviating the unevenness of stress applied to the first chip due to the through electrode, while easing the restriction on the arrangement position of the through electrode connected to the external terminal of the light detecting element.

[0037] In addition, according to the fifth aspect, a second chip may be included, which forms a laminated structure with the first chip, and a second wiring layer extending to the embedded layer is formed on the second chip, and the embedded layer may form a laminated structure with the second chip, so that the first chip is embedded in the embedded layer. This has the effect of being able to support a laminated structure of chips with more than 3 layers, and being able to ease the limitation of the arrangement position of the through electrode connected to the external terminal of the packaged light detection element.

[0038] According to the fifth aspect, a support substrate supporting the embedding layer in which the first chip is embedded may be further included, and the through electrode may penetrate the support substrate. This achieves an effect that the through electrode extends to the outside while processing the thinning of the first chip.

[0039] In the fifth aspect, in the first semiconductor substrate, the area density of the embedded components in the region close to the through-electrode may be smaller than the area density in the region far from the through-electrode. This eliminates the need to provide an isolation region between the first chip and the through-electrode and can alleviate stress applied to the first chip.

[0040] Furthermore, according to the fifth aspect, the area density of the embedded components in the region up to 200 μm from the end on the through-electrode side of the first semiconductor substrate can be smaller than the area density of the embedded components in the region exceeding 200 μm from the end of the first semiconductor substrate. This has the effect of eliminating the need to provide an isolation region between the first chip and the through-electrode and relieving the stress applied to the first chip.

[0041] In addition, according to the fifth aspect, any one of the heat dissipation film, the protective film, the warpage correction film, and the laminated film obtained by combining these films can be formed on the rear surface side of the first chip. This has the effect of improving the characteristics and reliability of the first chip while suppressing the complexity of the manufacturing process.

[0042] In addition, the sixth mode provides a method for manufacturing a light detecting element, the method comprising: forming a laminated wafer in which a second wafer to be singulated into a second chip is laminated on a first wafer to be singulated into a first chip; a third chip is laminated on the laminated wafer; an embedding layer laminated on the laminated wafer is formed so that the third chip is embedded in the embedding layer; a through electrode is formed, the through electrode is electrically connected to the second chip via the embedding layer; and a light detecting element is formed in which the laminated wafer is singulated together with the embedding layer in which the third chip is embedded. This has the effect of reducing the restrictions on the arrangement position of the through electrode connected to the external terminal of the light detecting element of the laminated structure of the chip with more than three layers, while being able to form a plurality of light detecting elements in one piece.

[0043] In addition, according to the sixth aspect, a step of laminating a support substrate wafer on the embedding layer may be further included, the through-electrode may penetrate the support substrate wafer, and the laminated wafer and the support substrate wafer may be singulated along the same cut surface together with the embedding layer in which the third chip is embedded. This has the effect of producing a support substrate attached to a plurality of light detection elements at the same time.

[0044] Furthermore, according to the sixth aspect, the first chip may include: a sensor chip having a wiring layer formed on the front surface side and pixels formed on the rear surface side; the method may also include the step of laminating a transparent substrate wafer on the pixel forming surface side; and the laminated wafer and the transparent substrate wafer may be singulated along the same cut surface together with the embedding layer in which the third chip is embedded. This has the effect of mounting the transparent substrate on a plurality of light detecting elements at once. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a cross-sectional view showing a first example of the arrangement of the light detecting element according to the first embodiment.

[0046] Figure 2 It is a cross-sectional view showing a second example of the arrangement of the light detection element according to the first embodiment.

[0047] Figure 3 This is a first cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0048] Figure 4 This is a second cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0049] Figure 5 This is a third cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0050] Figure 6 It is a fourth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0051] Figure 7 It is a fifth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0052] Figure 8 It is a sixth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0053] Fig. 9 It is a seventh cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0054] Fig.10It is an eighth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0055] Fig.11 This is a ninth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0056] Fig.12 It is a tenth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0057] Fig.13 It is a cross-sectional view showing a first example of the arrangement of the light detecting element according to the second embodiment.

[0058] Fig.14 is a cross-sectional view showing a second example of the configuration of the light detecting element according to the second embodiment.

[0059] Fig.15 It is a plan view showing an example of arrangement of external terminals of the photodetection element according to the second embodiment.

[0060] Fig.16 It is a cross-sectional view showing a first example of the arrangement of the photodetection element according to the third embodiment.

[0061] Fig.17 It is a cross-sectional view showing a second example of the arrangement of the photodetection element according to the third embodiment.

[0062] Fig.18 It is a cross-sectional view showing a third example of the arrangement of the light detecting element according to the third embodiment.

[0063] Fig.19 It is a plan view showing an example of the arrangement of external terminals and redistribution lines of the photodetection element according to the third embodiment.

[0064] Fig. 20 It is a cross-sectional view showing a first example of the arrangement of the photodetection element according to the fourth embodiment.

[0065] Fig.21 It is a cross-sectional view showing a second example of the arrangement of the photodetection element according to the fourth embodiment.

[0066] Fig. 22 It is a cross-sectional view showing a third example of the arrangement of the photodetection element according to the fourth embodiment.

[0067] Fig.23 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the fifth embodiment.

[0068] Fig.24 It is a first cross-sectional view and a plan view showing an example of a method for manufacturing a light detecting element according to the fifth embodiment.

[0069] Fig.25 This is a second cross-sectional view showing an example of the method for manufacturing the light detecting element according to the fifth embodiment.

[0070] Fig.26 It is a third cross-sectional view showing an example of the method for manufacturing the light detecting element according to the fifth embodiment.

[0071] Fig. 27 It is a fourth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the fifth embodiment.

[0072] Fig.28 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the sixth embodiment.

[0073] Fig.29 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the seventh embodiment.

[0074] Fig.30 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the eighth embodiment.

[0075] Fig.31 is a cross-sectional view showing a configuration example of a light detecting element according to a ninth embodiment.

[0076] Fig.32 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the tenth embodiment.

[0077] Fig.33 is a cross-sectional view showing a configuration example of a light detecting element according to an eleventh embodiment.

[0078] Fig.34 It is a diagram showing an example of arrangement of light detection elements according to the twelfth embodiment.

[0079] Fig.35 It is a diagram showing the relationship between the horizontal position and stress of the photodetection element according to the twelfth embodiment.

[0080] Fig.36 It is a diagram showing another arrangement example of the photodetection element according to the twelfth embodiment.

[0081] Fig.37 It is a diagram showing another arrangement example of the photodetection element according to the twelfth embodiment.

[0082] Fig.38 It is a diagram showing an example of arrangement of a photodetection element according to the thirteenth embodiment.

[0083] Fig.39 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the fourteenth embodiment.

[0084] Fig.40 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the fifteenth embodiment.

[0085] Fig.41 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the sixteenth embodiment.

[0086] Fig.42 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the seventeenth embodiment.

[0087] Fig.43 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the eighteenth embodiment.

[0088] Fig.44 It is a first cross-sectional view showing an example of a method for manufacturing a light detecting element according to the nineteenth embodiment.

[0089] Fig.45 It is a second cross-sectional view showing an example of the method for manufacturing the photodetection element according to the nineteenth embodiment.

[0090] Fig.46 It is a third cross-sectional view showing an example of the method for manufacturing the photodetection element according to the nineteenth embodiment.

[0091] Fig.47 It is a fourth cross-sectional view showing an example of the method for manufacturing the photodetection element according to the nineteenth embodiment.

[0092] Fig.48 It is a fifth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the nineteenth embodiment.

[0093] Fig.49 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the twentieth embodiment.

[0094] Fig.50 It is a first cross-sectional view showing an example of a method for manufacturing a light detecting element according to a twentieth embodiment.

[0095] Fig.51 This is a second cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0096] Fig.52 It is a third cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0097] Fig.53 It is a fourth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0098] Fig.54 It is a fifth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0099] Fig.55 It is a sixth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0100] Fig.56 It is a seventh cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0101] Fig.57 It is an eighth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0102] Fig.58 It is a ninth cross-sectional view showing an example of the method for manufacturing the light detecting element according to the twentieth embodiment.

[0103] Fig.59 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twentieth embodiment.

[0104] Fig.60 It is a cross-sectional view showing an example of arrangement of a light detection element according to the twenty-first embodiment.

[0105] Fig.61 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-first embodiment.

[0106] Fig.62 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the twenty-second embodiment.

[0107] Fig.63 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-second embodiment.

[0108] Fig.64 It is a cross-sectional view showing an example of the arrangement of a light detecting element according to the twenty-third embodiment.

[0109] Fig.65 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-third embodiment.

[0110] Fig.66 is a cross-sectional view showing a configuration example of a light detecting element according to a twenty-fourth embodiment.

[0111] Fig.67 is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-fourth embodiment.

[0112] Fig.68It is a cross-sectional view showing an example of the arrangement of a light detection element according to the twenty-fifth embodiment.

[0113] Fig.69 is a block diagram showing a schematic configuration embodiment of a vehicle control system.

[0114] Fig.70 It is an explanatory diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0115] A mode for carrying out the present technology (hereinafter referred to as an embodiment) will be described below. The description will be given in the following order.

[0116] 1. First Embodiment (Example in which through-electrodes connected to external terminals are provided between lower-layer chips embedded in an embedding layer laminated on an upper-layer chip)

[0117] 2. Second Embodiment (Example of connecting to an upper chip or a lower chip via a through electrode electrically connected to an external terminal via an embedded layer embedded in a lower chip)

[0118] 3. Third Embodiment (Example in which the through-electrode is connected to the external terminal via the rewiring line formed on the embedding layer in which the lower chip is embedded)

[0119] 4. Fourth Embodiment (Example in which a through electrode is connected to an external terminal via a support substrate arranged on an embedding layer in which a lower chip is embedded)

[0120] 5. Fifth Embodiment (Example of Face-Down Mounting of an Upper Chip Connected to a Through Electrode Electrically Connected to an External Terminal via an Embedding Layer Embedding a Lower Chip)

[0121] 6. Sixth Embodiment (Example in which a through-hole embedded layer in which a lower chip is mounted face-down on an upper chip is embedded, through-electrodes electrically connected to external terminals are connected to the lower chip via rear surface wiring of the upper chip, and a sensor chip is laminated on the uppermost layer)

[0122] 7. Seventh Embodiment (Example in which a through-hole embedding layer in which a lower chip is mounted face-down on an upper chip is embedded, through electrodes electrically connected to external terminals are connected to the lower chip through wiring of the upper chip, and a sensor chip is laminated on the uppermost layer)

[0123] 8. Eighth Embodiment (Example in which the lower chip is mounted face down on the three-layer laminated chip and the through-electrodes electrically connected to the external terminals via the embedding layer in which the lower chip is embedded are connected to the lower chip via the wiring of the upper chip)

[0124] 9. Ninth Embodiment (An embodiment in which a lower chip is mounted face down on a three-layer laminated chip and a through electrode electrically connected to an external terminal through an embedding layer in which the lower chip is embedded is connected to the lower chip through rear surface wiring of an upper chip)

[0125] 10. Tenth Embodiment (Example in which the lengths of through electrodes penetrating the lower chip and electrically connected to the external terminal are varied)

[0126] 11. Eleventh Embodiment (Example in which a through-electrode in which a through-hole embedding layer is electrically connected to an external terminal is connected to a lower chip via wiring of an upper chip, wherein the lower chip is mounted face-down on the upper chip)

[0127] 12. Twelfth Embodiment (Example of Embedding an Embedding Member into a Semiconductor Substrate of a Chip Embedding Layer of Through Electrodes)

[0128] 13. Thirteenth Embodiment (Example in which the position of the embedding member embedded in the semiconductor substrate of the chip is made different according to the arrangement position of the through-electrode)

[0129] 14. Fourteenth Embodiment (Example of Forming Stress Relaxing Films on Bottom and Side Surfaces of Embedding Member Embedded in Semiconductor Substrate of Chip)

[0130] 15. Fifteenth Embodiment (Example of Forming an Embedding Member in a Semiconductor Substrate Embedded with a Chip Using an Embedding Layer Embedding a Chip)

[0131] 16. Sixteenth Embodiment (Example of Forming Functional Film on Bottom Surface and Side Surface of Embedding Member of Semiconductor Substrate in Which Chip is Embedded)

[0132] 17. Seventeenth Embodiment (Example of Forming a Functional Film on the Rear Surface Side of a Chip Embedded with an Embedding Member)

[0133] 18. Eighteenth Embodiment (Example in which a portion of an embedding member of a chip embedded in an embedding layer penetrates a semiconductor substrate)

[0134] 19. Nineteenth Embodiment (Example of Forming Different Functional Films on the Lower Surface, Side Surface, and Front Surface of the Embedding Member of the Chip Embedded in the Embedding Layer)

[0135] 20. Twentieth Embodiment (Example in which a part of the through-electrodes in the embedding layer in which the chip is embedded is configured by columnar electrodes)

[0136] 21. Twenty-first Embodiment (Example of Providing a Through Electrode Having a Wiring Layer Embedded in an Embedding Layer in Which a Chip is Embedded, Penetrating a Dummy Chip)

[0137] 22. Twenty-second Embodiment (Example of Providing a Through Electrode Not Embedded in a Wiring Layer in an Embedding Layer in Which a Chip is Embedded, Penetrating a Dummy Chip)

[0138] 23. Twenty-third Embodiment (Example in which a through electrode in an embedding layer in which a chip is embedded penetrates the dummy chip and also penetrates the semiconductor layer of a chip laminated on the embedding layer and is connected to a wiring layer)

[0139] 24. Twenty-fourth Embodiment (Example in which a through-electrode penetrating a dummy chip embedded in an embedding layer in which a chip is embedded is connected to a wiring layer via a through hole in the chip embedded laminated on the embedding layer)

[0140] 25. Twenty-fifth Embodiment (Example in which a through electrode penetrating an embedded layer having an embedded chip is connected to a wiring layer through a through hole in an embedded chip laminated on the embedded layer)

[0141] 26. Application Example for Moving Objects

[0142] <1. First Embodiment>

[0143] Figure 1 is a cross-sectional view showing a first example of a configuration of a light detecting element according to a first embodiment;

[0144] exist Figure 1 In the embodiment, the light detecting element 100 includes chips 101 to 104. The chips 101 to 104 may be semiconductor chips or may include optical chips. At this time, the optical chip can be used as the uppermost chip disposed on the light detecting element 100.

[0145] The optical element is formed on the optical chip. The optical element can be a solid-state imaging element, such as a charge coupled device (CCD) or a complementary metal oxide semiconductor (CMOS). The light received by the solid-state imaging element can be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, etc. The optical element can be a light receiving element such as a photodiode (PD), or can be a light emitting element such as a laser diode (LD), a light emitting diode (LED) or a vertical cavity surface emitting laser (VCSEL). The optical element can be a microelectromechanical system (MEMS) element such as an optical switch or a reflector device. As the substrate of the optical chip, semiconductors such as Si, GaAs, InGaAsP can be used, and dielectrics such as LiNbO3, glass, and transparent resin can also be used.

[0146] Semiconductor elements are formed on semiconductor chips. Semiconductor elements may include transistors, resistors, capacitors, etc. In a semiconductor chip, a memory may be formed, a processor may be formed, a signal processing circuit may be formed, a data processing circuit may be formed, an interface circuit may be formed, or an optical element may be formed. For example, in a semiconductor chip, a hardware circuit such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC) may be formed. The material of the matrix material for the semiconductor chip may be Si, GaAs, SiC, GaN, InGaAsP, etc.

[0147] In the following description, a case where a back-illuminated solid-state imaging element is formed on the chip 101 and a semiconductor element is formed on each of the chips 102 to 104 is taken as an example. In this case, a logic circuit or a semiconductor memory device may also be formed in the chips 102 to 104. The semiconductor memory device may include a read-only memory (ROM), a dynamic random access memory (DRAM), or a NAND flash memory.

[0148] The chip 101 includes a semiconductor layer 111 and a wiring layer 141. The chip 101 is provided with an imaging region RA and a non-imaging region RB. The imaging region RA is provided with a pixel array unit in which pixels 121 are arranged in a matrix along row and column directions. The pixels 121 are provided with photodiodes and pixel transistors 131. In the non-imaging region RB, a peripheral circuit that drives the pixel transistor 131 and outputs a signal read from the pixel 121 is provided.

[0149] The wiring layer 141 is formed on the front surface side of the semiconductor layer 111. At this time, a photodiode may be configured on the rear surface side of the semiconductor layer 111. The wiring layer 141 is provided with a wiring 151 embedded in an insulating layer, a pad electrode 171, and a via 181. The via 181 may be used for interlayer connection of the wiring 151. The pad electrode 171 may be used for direct bonding of the chip 101. A barrier metal film 161 may be formed around the wiring 151, the pad electrode 171, and the via 181.

[0150] On the rear surface side of the semiconductor layer 111, a color filter 115 is formed for each pixel 121. The color filter 115 may form, for example, a Bayer array. An on-chip lens 125 is formed on the color filter 115 for each pixel 121. The material of the color filter 115 may be configured by, for example, adding a pigment or the like to a transparent resin such as acrylic resin or polycarbonate. As the material of the on-chip lens 125, for example, a transparent resin such as acrylic resin or polycarbonate may be used.

[0151] In addition, on the rear surface side of the semiconductor layer 111, a transparent resin 135 is formed to cover the on-chip lens 125. A transparent substrate 145 is arranged on the transparent resin 135. The material of the transparent resin 135 is, for example, silicone resin, acrylic resin, or polycarbonate. At this time, the refractive index of the transparent resin 135 can be made smaller than the refractive index of the on-chip lens 125. Depending on the wavelength of the optical element, the material of the transparent substrate 145 can be, for example, quartz, glass, or Al2O3, CaF2, MgF2, LiF, etc. The transparent resin 135 can be used as an adhesive layer for bonding the transparent substrate 145. In addition, the transparent substrate 145 can be used as a reinforcing material for reinforcing the light detecting element 100. Note that the chip 101 is an embodiment of the sensor chip described in the claims.

[0152] The chip 102 is laminated on the chip 101. The planar size and shape of the chip 102 may be equal to the planar size and shape of the chip 101. The chip 102 includes a semiconductor layer 112, a wiring layer 142, and a rear surface wiring layer 146. The MOS transistor 132 may be formed on the semiconductor layer 112. Note that the wiring layer 142 is an example of a front surface wiring layer described in the claims.

[0153] The wiring layer 142 is formed on the front surface side of the semiconductor layer 112. The wiring layer 142 is provided with the wiring 152 embedded in the insulating layer, the pad electrode 172 and the via 182. The via 182 can be used for interlayer connection of the wiring 152. The pad electrode 172 can be used for direct bonding of the front surface side of the chip 102. For example, hybrid bonding can be used to directly bond the chip 101 to the chip 102.

[0154] In the hybrid bonding, the pad electrode 171 is exposed on the surface of the wiring layer 141, the pad electrode 172 is exposed on the surface of the wiring layer 142, and the pad electrodes 171 and 172 are formed at positions facing each other. At this time, Cu can be used as the material of each of the pad electrodes 171 and 172. As the material of the insulating layer of the wiring layers 141 and 142, for example, SiO2, SiN, SiCN, etc. can be used. In addition, the pad electrodes 171 and 172 are recessed from the surfaces of the wiring layers 141 and 142 by about tens of nm. At this time, the plane size of each of the pad electrodes 171 and 172 can be set in the range of 0.1μm to 10μm. Then, after performing surface treatment of the insulating layers of the wiring layers 141 and 142, these insulating layers are brought into contact facing each other so that these insulating layers are connected to each other. At this time, a small gap is formed between the pad electrode 171 and the pad electrode 172. Then, the insulating layers of the wiring layers 141 and 142 are subjected to heat treatment in a state of being pressed against each other, whereby the pad electrodes 171 and 172 expand, the pad electrodes 171 and 172 come into contact with each other, and mutual diffusion of Cu results in formation of a connection between the pad electrodes 171 and 172 .

[0155] In this hybrid bonding, the planar size of each of the pad electrodes 171 and 172 can be set within a range of 0.1 μm to 10 μm. Therefore, compared with the method of bonding the chips 101 and 102 by solder, the pitch of the bonding electrodes can be narrowed, and the input and output of the chips 101 and 102 can be increased.

[0156] On the rear surface side of the semiconductor layer 112, a rear surface wiring layer 146 is formed via a protective film 116. On the rear surface wiring layer 146, rear surface wiring 156 embedded in an insulating layer, a pad electrode 176, and a through hole 186 are provided. The through hole 186 can be used for interlayer connection of the rear surface wiring 156. The pad electrode 176 can be used for direct bonding of the rear surface side of the chip 102.

[0157] The through holes 126 and 136 are embedded in the semiconductor layer 112. The diameter of the through hole 126 can be made larger than the diameter of the through hole 136. For example, the diameter of the through hole 126 can be set in the range of 1 μmΦ to 20 μmΦ, and the diameter of the through hole 136 can be set in the range of 0.1 μmΦ to 1 μmΦ. At this time, the through hole 126 can be used for the connection of the power wiring, and the through hole 136 can be used for the connection of the signal wiring. In addition, each of the through holes 126 and 136 can be arranged in the peripheral portion of the chip 102 or can be arranged in the central portion of the chip 102.

[0158] Each of the vias 126 and 136 penetrates the semiconductor layer 112 of the chip 102 and can establish conduction between the wiring layer 142 and the rear surface wiring layer 146. At this time, the insulating layer of the rear surface wiring layer 146 can also be embedded in the via 197 formed in the semiconductor layer 112, and the via 126 is insulated from the semiconductor layer 112 by the insulating layer of the rear surface wiring layer 146. In addition, in order to insulate the via 136 from the semiconductor layer 112, an insulating layer 196 can be formed around the via 136.

[0159] The chip 103 is laminated on the rear surface wiring layer 146 of the chip 102. The planar size of the chip 103 can be made smaller than that of the chip 101. The chip 103 includes a semiconductor layer 113 and a wiring layer 143. The MOS transistor 133 can be formed in the semiconductor layer 113.

[0160] The wiring layer 143 is formed on the front surface side of the semiconductor layer 113. The wiring layer 143 is provided with the wiring 153 embedded in the insulating layer, the pad electrode 173 and the via 183. The via 183 can be used for interlayer connection of the wiring 153. The pad electrode 173 can be used for direct bonding of the front surface side of the chip 103. For example, the chip 103 can be directly bonded to the chip 102 by hybrid bonding.

[0161] The chip 104 is laminated on the rear surface wiring layer 146 of the chip 102. At this time, the chip 104 is arranged side by side on the rear surface wiring layer 146 with a gap between the chip 103. The plane size of the chip 104 can be made smaller than the plane size of the chip 101. The chip 104 includes a semiconductor layer 114 and a wiring layer 144. The MOS transistor 134 can be formed in the semiconductor layer 114.

[0162] The wiring layer 144 is formed on the front surface side of the semiconductor layer 114. The wiring layer 144 is provided with the wiring 154 embedded in the insulating layer, the pad electrode 174 and the via 184. The via 184 can be used for interlayer connection of the wiring 154. The pad electrode 174 can be used for direct bonding of the front surface side of the chip 104. For example, the chip 104 can be directly bonded to the chip 102 by hybrid bonding.

[0163] In addition, on the rear surface wiring layer 146, the embedded layer 117 is laminated in such a manner as to embed the chips 103 and 104. The front surface of the embedded layer 117 may be flattened. A through electrode 127 is embedded in the embedded layer 117. At this time, the through electrode 127 penetrates the embedded layer 117, is connected to the rear surface wiring layer 146, and extends to the surface of the embedded layer 117. The through electrode 127 may be located between the chip 103 and the chip 104. The through electrode 127 may be arranged around each of the chips 103 and 104.

[0164] The bump electrode 137 is formed on the embedding layer 117 and connected to the through electrode 127. The bump electrode 137 may be used as an external terminal for electrically connecting the light detection element 100 to the outside. Note that the bump electrode 137 may be a solder ball or a columnar electrode.

[0165] Here, the light detecting element 100 can be divided into individual light detecting elements 100 from a state where a plurality of light detecting elements 100 are integrated into a wafer shape. In this singulation, for example, the light detecting element 100 formed into a wafer shape may be cut along a cutting line for dividing the light detecting element 100. At this time, the position of the cut surface of the embedding layer 117, the position of the cut surface of each of the chips 101 and 102, and the position of the cut surface of the transparent substrate 145 may be consistent with each other.

[0166] Each of the semiconductor layers 111 to 114 may be a semiconductor substrate, a thinned semiconductor substrate, or a semiconductor layer for a silicon-on-insulator (SOI) substrate.

[0167] As a material for the insulating layer of each wiring layer 141-144, the protective film 116, and the insulating layer 196, for example, SiO2, SiN, or SiCN can be used. As a material for the wirings 151 to 154, the pad electrodes 171 to 174, the vias 181 to 184, and the through holes 126 and 136, for example, a metal such as Al, Cu, AlCu, AlSiCu, or Co can be used. As a material for the through electrode 127, for example, a metal such as Cu, Ti, Ta, Al, W, Ni, Ru, or Co can be used, and a laminated structure of a plurality of materials can be used. As a material for the barrier metal film 161, for example, a metal such as Ta, TaN, etc. can be used.

[0168] The material of the embedding layer 117 includes an insulating layer of an inorganic or organic material, and a plurality of films may be laminated. For example, in the case of an inorganic film, SiO2, SiON, SiN, SiOC, and SiCN are used, and in the case of an organic film, a resin having a skeleton such as silicone, polyimide, acrylic, epoxy, polymer, or PEEK material, or a material containing a filler such as SiO2, Al2O3, or AlN or BN is used. The material of the embedding layer 117 may be a molding material. In addition, the embedding layer 117 preferably includes a material having heat resistance in the range of 100 to 500 degrees.

[0169] Figure 2 It is a cross-sectional view showing a second example of the arrangement of the light detection element according to the first embodiment.

[0170] exist Figure 2In the light detecting element 110, a cavity 119 is added to the light detecting element 100 of the first example of the first embodiment described above. The other configurations of the light detecting element 110 of the second example of the first embodiment are similar to those of the light detecting element 100 of the first example of the first embodiment described above.

[0171] The cavity 119 separates the imaging region RA of the chip 101 from the transparent resin 135 and the transparent substrate 145. At this time, the transparent resin 135 can be prevented from contacting the on-chip lens 125. The cavity 119 can be provided by forming the transparent resin 135 only on the non-imaging region RB. The cavity 119 can be formed in the transparent substrate 145. Here, by providing the hollow 119 on the imaging region RA, the light detecting element 110 can be enhanced without affecting the optical function of the chip 101. Note that an anti-reflection film or a light shielding film for preventing flare, stray light, etc. can be formed on the transparent substrate 145.

[0172] Figures 3 to 12 It is a cross-sectional view showing an example of the method for manufacturing the light detecting element according to the first embodiment.

[0173] exist Figure 3 In a, for each part into which the chip 101 is cut, a pixel array unit and a peripheral circuit are formed on the semiconductor wafer 111'. Next, a wiring layer 141 provided with wiring 151, a pad electrode 171 and a via 181 is formed on the semiconductor wafer 111'. The insulating layer of the wiring layer 141 can be formed by, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). In addition, the front surface of the wiring layer 141 can be flattened by a method such as chemical mechanical polishing (CMP) to expose the pad electrode 171. The planar size of the pad electrode 171 can be set in the range of 0.1×0.1μm to 10×10μm. It is possible to cut out a plurality of chips 101 used by a plurality of light detection elements 100 from the semiconductor wafer 111'. For example, the semiconductor wafer 111' can be divided along a singularized cutting line for the light detection element 100.

[0174] In addition, semiconductor elements such as transistors 132 are formed on the semiconductor wafer 112' for each portion into which the chip 102 is cut. Next, a wiring layer 142 provided with wiring 152, pad electrodes 172, and vias 182 is formed on the semiconductor wafer 112'. The insulating layer of the wiring layer 142 can be formed by, for example, CVD or PVD. In addition, the front surface of the wiring layer 142 can be flattened by a method such as CMP so that the pad electrode 172 is exposed. The planar size of the pad electrode 172 can be set in the range of 0.1×0.1μm to 10×10μm. It is possible to cut out a plurality of chips 102 used by a plurality of light detecting elements 100 from the semiconductor wafer 112'. For example, the semiconductor wafer 112' can be divided along the cutting line used to divide the light detecting element 100.

[0175] Next, if Figure 3 As shown in b, the wiring layer 141 and the wiring layer 142 are directly bonded so that the wiring layers 141 and 142 face each other. At this time, the pad electrode 171 of the wiring layer 141 and the pad electrode 172 of the wiring layer 142 can be Cu-Cu bonded. In order to improve the bonding strength, the surfaces of the wiring layers 141 and 142 can be plasma treated or wet treated. In order to obtain sufficient bonding strength and good contact of the Cu bonding portion, the laminated wafer laminated with the semiconductor wafers 111' and 112' can be heat treated at 200 to 400 degrees.

[0176] Next, if Figure 4 As shown in a, the semiconductor wafer 112' is thinned from the rear surface side. When the semiconductor wafer 112' is thinned, a grinder, CMP or etch-back may be used. At this time, the thickness of the semiconductor wafer 112' may be set within a range of 1 μm to 20 μm.

[0177] Then, if Figure 4As shown in b, a protective film 116 is formed on the rear surface side of the semiconductor wafer 112' by a method such as CVD. Next, a through hole 197 is formed in the semiconductor layer 112 by using a photolithography technique and a dry etching technique. Next, an insulating layer 198 is formed on the protective film 116 so that the through hole 197 is embedded by a method such as CVD. Next, the insulating film at the connection position of each through hole 126 and 136 is removed, and each through hole 126 and 136 is embedded to be electrically connected to the wiring 152. For example, electroplating can be used to embed the through holes 126 and 136. The top surface of each of the through holes 126 and 136 can be exposed from the insulating layer 198. At this time, a damascene method using CMP or the like can be used. The insulating layer 198 can cover the periphery of the through hole 126 to insulate the through hole 126 from the semiconductor wafer 112'. In addition, the insulating layer 196 can be formed around the through hole 136 to insulate the through hole 136 from the semiconductor wafer 112'. Alternatively, a barrier metal film such as Ti or TiN may be formed on the side surfaces and bottom surfaces of each of the through holes 126 and 136 .

[0178] Then, if Figure 5 As shown in a, a rear surface wiring layer 146 provided with a rear surface wiring 156, a pad electrode 176, and a via 186 is formed on the protective film 116. At this time, the through holes 126 and 136 can be electrically connected to the rear surface wiring 156. The insulating layer of the rear surface wiring layer 146 can be formed by, for example, CVD or PVD. In addition, the front surface of the rear surface wiring layer 146 can be flattened by a method such as CMP so that the pad electrode 176 is exposed. The plane size of the pad electrode 176 can be set in the range of 0.1×0.1μm to 10×10μm.

[0179] Next, if Figure 5 As shown in b, singulated chips 103 and 104 are prepared. Then, wiring layers 143, 144 are directly bonded to rear surface wiring layer 146 so that wiring layers 143, 144 are opposite to rear surface wiring layer 146. At this time, pad electrode 173 of wiring layer 143 and pad electrode 174 of wiring layer 144 can be Cu-Cu bonded to pad electrode 176 of rear surface wiring layer 146. In order to improve the bonding strength, the surfaces of wiring layers 143, 144 and rear surface wiring layer 146 can be plasma treated or wet treated. In order to obtain sufficient bonding strength and good contact of the Cu bonding portion, the laminated structure in which chips 103 and 104 are laminated on a laminated wafer in which semiconductor wafers 111' and 112' are laminated can be heat treated at 200 to 400 degrees. The chips 103 and 104 can be arranged side by side on a laminate wafer to which the semiconductor wafers 111 ′ and 112 ′ are bonded, in order to cut out the parts of the light detection element 100 .

[0180] Then, if Figure 6As shown in a, the semiconductor layers 113 and 114 are thinned from the rear surface side. When thinning the semiconductor layers 113 and 114, a grinder or CMP may be used. At this time, the thickness of each of the semiconductor layers 113 and 114 may be set within a range of 0.5 μm to 50 μm.

[0181] Next, if Figure 6 As shown in FIG. 1 b, the embedded layer 117 is laminated on the rear surface wiring layer 146 so that the chips 103 and 104 are embedded therein. For the lamination of the embedded layer 117, in the case of an inorganic material, CVD, atomic layer deposition (ALD), vapor deposition, sputtering, etc. can be used, and in the case of an organic material, coating, dipping, spraying, etc. can be used. The embedded layer 117 can be planarized. In the planarization of the embedded layer 117, a grinder or CMP can be used.

[0182] Next, if Figure 7 As shown, a temporary substrate 118 is bonded to the embedded layer 117. The planar size and shape of the temporary substrate 118 can be equal to the planar size and shape of the semiconductor wafer 111'. The thickness of the temporary substrate 118 can be set in the range of 300μm to 800μm. The temporary substrate 118 can be a Si substrate or a glass substrate. In the bonding of the temporary substrate 118, an adhesive or an oxide film can be used for bonding. Note that the process can proceed to the next step without bonding the temporary substrate 118 to the embedded layer 117.

[0183] Then, if Figure 8 As shown, the semiconductor wafer 111' is thinned from the rear surface side. In this thinning, for example, a grinder, CMP, dry etching or wet etching can be used. In the case of forming a back-illuminated individual imaging element on the semiconductor wafer 111', the rear surface side of the thinned semiconductor wafer 111' becomes the light-receiving surface.

[0184] Next, if Fig. 9 As shown, a color filter 115 is formed for each pixel 121 on the rear surface side of the semiconductor layer 111. In addition, an on-chip lens 125 is formed on the color filter 115 for each pixel 121. A pad electrode 191 for connection test evaluation may be formed on the rear surface side of the semiconductor layer 111.

[0185] Next, if Fig.10 As shown, the transparent substrate 145 is arranged on the rear surface side of the semiconductor wafer 111' via the transparent resin 135 formed to cover the on-chip lens 125. Figure 2In the case of the cavity 119 in the semiconductor wafer 111 ′, the transparent resin 135 may be patterned before the transparent substrate 145 is disposed on the rear surface side of the semiconductor wafer 111 ′. The thickness of the transparent resin 135 may be set within a range of 100 μm to 775 μm.

[0186] Next, if Fig.11 As shown, the temporary substrate 118 on the embedded layer 117 is peeled off. As a method for peeling off the temporary substrate 118, in the case where the temporary substrate 118 is a resin, a chemical solution for dissolving the temporary substrate 118 may be used, the temporary substrate 118 may be mechanically scratched, or the adhesion of the peeling surface may be reduced based on ultraviolet irradiation. In the case of oxide film peeling, Si may be cut with a grinder, Si may be dissolved by wet processing, or a combination thereof may be used.

[0187] Next, if Fig.12 As shown, a through electrode 127 is formed which penetrates the embedded layer 117 and is connected to the rear surface wiring layer 146. Note that in order to connect the through electrode 127 to the rear surface wiring layer 146, a pad electrode connected to the through electrode 127 may be formed on the rear surface wiring layer 146. The diameter of the through electrode 127 may be set according to the number of IOs drawn out outside the light detection element 100, for example, may be set in the range of 3 μmΦ to 100 μmΦ. An insulating film such as SiO2, SiN, etc. may also be formed on the side wall of the through electrode 127. However, note that in the case where the embedded layer 117 includes an insulator, it is not necessary to form an insulating film separately on the side wall of the through electrode 127. In addition, a barrier metal film such as Ti, TiN, etc. may also be formed on the side wall of the through electrode 127. For example, the through electrode 127 may be formed by electrolytic plating using Cu as a filling material. As a method of forming a through hole in which the through electrode 127 is embedded in the embedded layer 117, dry etching, wet etching, or laser processing may be used.

[0188] Next, if Figure 1As shown, a bump electrode 137 connected to the through electrode 127 is formed on the embedded layer 117. The bump electrode 137 can be used as an external terminal connected to the mounting substrate on which the light detection element 100 is mounted. The bump electrode 137 can be a solder ball. At this time, a solder resist layer can be formed to determine the solder diameter. The solder diameter can be set in the range of 50μmΦ to 400μmΦ, and SnAgCu, SnCu, SnBi, etc. can be used as solder materials. As a metal pad for receiving solder, a Ti / Cu laminated film can be formed under the solder mask. TiN, Ni, Co, Ta or TaN can be used instead of Ti, or a combination thereof can be used. In addition to forming a structure for forming a metal pad for accommodating solder, solder can be formed by erecting a Cu column. At this time, for example, a laminated structure of Cu / Ni / solder can be used. Next, the laminated wafer of the semiconductor wafers 111 ′ and 112 ′ is singulated together with the embedding layer 117 in which the chips 103 and 104 are embedded, thereby forming the light detection element 100 . In this singulation, a blade dicing may be used.

[0189] As described above, in the first embodiment, the through electrode 127 is arranged between the chip 103 and the chip 104 embedded in the embedding layer 117, and the through electrode 127 is connected to the bump electrode 137 as the external terminal of the light detection element 100. As a result, the through electrode 127 connected to the outer terminal of the light detection element 100 can be arranged not only at the periphery of the light detection element 100 but also at the central part thereof, and the restriction on the arrangement position of the through electrode 127 can be alleviated. For example, power can be supplied not only to the periphery of the light detection element 100 but also to the chip 101 through the through electrode 127 at the central part, and the IR voltage drop caused by the wiring resistance of the chip 101 can be made uniform between the periphery and the central part of the chip 101. Therefore, the potential difference of the power supply between the periphery and the central part of the pixel array unit formed in the chip 101 can be reduced, and the degradation of image quality, such as shading, can be suppressed.

[0190] Furthermore, the through-electrode 127 is embedded in the embedded layer 117 in order to connect the through-electrode 127 to the rear surface wiring layer 146. This eliminates the need to form the through-electrode 127 in the chips 103 and 104, and the area occupied by the semiconductor element formed on the chips 103 and 104 can be increased.

[0191] In addition, by providing the rear surface wiring layer 146 on the chip 102, the chip 102 can be directly bonded to the chip 101 via the wiring layer 141 on the front side of the chip 102, and the chip 102 can be directly bonded to the chips 103 and 104 via the rear surface wiring layer 146 on the rear surface side of the chip 102. As a result, a stacked structure of three-layer chips can be formed without using solder bonding, and the number of connection IOs between chips can be increased while accelerating signal transmission between chips.

[0192] Furthermore, by providing the through holes 126 and 136 penetrating the semiconductor layer 112 of the chip 102, the through electrode 127 can be electrically connected to the wiring layer 141 of the chip 101. Therefore, there is no need to use bonding wires to extend the wiring 151 of the chip 101 to the outside of the light detection element 100, and there is no need to provide a bonding area in the chip 101, so that delay in signal transmission via the bonding wires can be prevented.

[0193] In addition, the light detecting element 100 can be strengthened by bonding the transparent substrate 145 to the rear surface side of the chip 101. Therefore, it is possible to reduce the thickness of the chips 101 to 104 while avoiding difficulty in handling the light detecting element 100, improve the efficiency of interlayer connection, and increase the speed of signal transmission by reducing parasitic capacitance.

[0194] Note that in the first embodiment described above, a laminated structure in which the chip 101 on which the solid-state imaging element is formed is arranged in the uppermost layer is adopted as an example, but the chip 101 on which the solid-state imaging element is formed may be omitted. In addition, direct bonding based on Cu-Cu bonding is used as an example of bonding of the chips 101 to 104, but solder bonding may be used, or direct bonding and solder bonding may be combined.

[0195] <2. Second Embodiment>

[0196] In the first embodiment, the through electrode 127 penetrates the embedded layer 117 and is connected to the rear surface wiring layer 146 of the chip 102. In the first example of the second embodiment, the through electrode penetrates the embedded layer 117 and the chip 102 and is connected to the wiring layer 141 of the chip 101.

[0197] Fig.13 It is a cross-sectional view showing a first example of the arrangement of the light detecting element according to the second embodiment.

[0198] exist Fig.13In the embodiment, the light detecting element 200 includes a through electrode 227 instead of the through electrode 127 of the first embodiment. In addition, the light detecting element 200 adds an insulating film 211 to the light detecting element 100 of the first embodiment. The other configurations of the light detecting element 200 of the second embodiment are similar to those of the light detecting element 100 of the first embodiment.

[0199] The through electrode 227 penetrates the embedded layer 117, the rear surface wiring layer 146, the protective film 116, the semiconductor layer 112, and the wiring layer 142, and is connected to the wiring layer 141. At this time, the through electrode 227 can be connected to the Cu wiring formed in the wiring layer 141, or can be connected to the Al pad electrode. The other configurations of the through electrode 227 are similar to those of the through electrode 127 of the first embodiment described above.

[0200] The insulating film 211 is formed to surround the outer periphery of the through electrode 227. The insulating film 211 can insulate the through electrode 227 from the semiconductor layer 112. As a material of the insulating film 211, SiO2, SiN, or the like can be used, for example.

[0201] As described above, in the first example of the second embodiment, the through electrode 227 connected to the bump electrode 137 extends to the position of the wiring layer 141 and is connected to the wiring layer 141. As a result, in order to extend the wiring 151 of the chip 101 to the outside of the light detection element 200, it is not necessary to make the wiring 151 of the chip 101 pass through the wiring 152 of the chip 102 and the back surface wiring 156, and the speed of signal transmission with the chip 101 can be improved.

[0202] In the first example of the second embodiment, the through electrode 227 penetrates the embedded layer 117 and the chip 102 and is connected to the wiring layer 141 of the chip 101. In the second embodiment, the through electrode penetrates the embedded layer 117 and the chips 103 and 104 and is connected to the wiring layers 143 and 144 of the chips 103 and 104, respectively.

[0203] Fig.14 is a cross-sectional view showing a second example of the configuration of the light detecting element according to the second embodiment.

[0204] exist Fig.14 In the embodiment, the light detecting element 210 includes through electrodes 223 and 224 and bump electrodes 233 and 234, which replace the through electrodes 127 and the bump electrodes 137 of the first embodiment. In addition, the light detecting element 210 adds insulating films 213 and 214 to the light detecting element 100 of the first embodiment. The other configurations of the light detecting element 210 of the second embodiment are similar to those of the light detecting element 100 of the first embodiment.

[0205] The through electrodes 223 and 224 penetrate the embedded layer 117 and the semiconductor layers 113 and 114, and are connected to the wiring layers 143 and 144, respectively. At this time, the through electrode 223 can be connected to the Cu wiring formed in the wiring layer 143, or can be connected to the Al pad electrode. In addition, the through electrode 224 can be connected to the Cu wiring formed in the wiring layer 144, or can be connected to the Al pad electrode. The other configurations of the through electrodes 223 and 224 are similar to the configuration of the through electrode 127 of the first embodiment described above.

[0206] The insulating films 213 and 214 are formed to surround the peripheries of the through electrodes 223 and 224. The insulating films 213 and 214 can insulate the through electrodes 223 and 224 from the semiconductor layers 113 and 114. As the material of the insulating films 213 and 214, for example, SiO2, SiN, etc. can be used.

[0207] In addition, through electrodes of different lengths may be formed in the light detection element. Figure 1 The through electrodes 127 and Fig.13 The through electrode 227 in the embodiment may be formed in one light detecting element, or Figure 1 The through electrodes 127 and Fig.14 The through electrodes 223 and 224 in the embodiment may be formed in one light detecting element. Fig.13 The through electrode 227 and Fig.14 The through electrodes 223 and 224 may be formed in one light detecting element, or Figure 1 The through electrode 127, Fig.13 The through electrode 227 and Fig.14 The through electrodes 223 and 224 may be formed in one light detecting element.

[0208] As described above, in the second example of the second embodiment, the through electrodes 223 and 224 are formed to penetrate the semiconductor layers 113 and 114. Thus, in order to extend the wirings 153 and 154 of the chips 103 and 104 to the outside of the light detecting element 210, it is not necessary to make the wirings 153 and 154 of the chips 103 and 104 pass through the rear surface wiring layer 146 of the chip 102, and the speed of signal transmission between the chips 103 and 104 can be increased.

[0209] Fig.15 1 is a plan view showing an example of the arrangement of the external terminals of the light detecting element of the second embodiment. Fig.15 The a in can be applied to Figure 1 The light detection element 100 or Figure 2 Arrangement of the external terminals of the light detecting element 110. Fig.15 In the above example, b can be applied to Fig.13The configuration of the external terminals of the light detecting element 200. Fig.15 In the example, c can be applied to Fig.14 Configuration of external terminals of the light detection element 210.

[0210] exist Fig.15 In a, in the light detecting elements 100, 110, the bump electrode 137 is connected to the rear surface wiring layer 146 via the through electrode 127. At this time, the bump electrode 137 may be arranged at a position other than the mounting area of ​​the chips 103 and 104. The bump electrode 137 may be arranged in a lattice shape at a position other than the mounting area of ​​each of the chips 103 and 104.

[0211] exist Fig.15 In b, in the light detecting element 200, the bump electrode 137 is connected to the wiring layer 141 via the through electrode 227. At this time, the bump electrode 137 may be arranged at a position other than the mounting area of ​​the chips 103 and 104. The bump electrode 137 may be arranged in a lattice shape at a position other than the mounting area of ​​each of the chips 103 and 104.

[0212] exist Fig.15 In c, in the light detection element 210, the bump electrodes 233 and 234 are connected to the wiring layers 143 and 144 via the through electrodes 223 and 224, respectively. At this time, the bump electrodes 233 and 234 may be arranged on the mounting area of ​​the chips 103 and 104. The bump electrodes 233 and 234 may be arranged in a lattice pattern.

[0213] <3. Third Embodiment>

[0214] In the first embodiment described above, the bump electrode 137 is arranged to be connected to the extended position of the through electrode 127. In the third embodiment, a rewiring line connected to the extended position of the through electrode is provided on the embedded layer, and the bump electrode is connected to the through electrode via the rewiring line.

[0215] Fig.16 It is a cross-sectional view showing a first example of the arrangement of the photodetection element according to the third embodiment.

[0216] exist Fig.16 In the light detecting element 240, a redistribution layer 241 is added to the light detecting element 100 of the first embodiment described above. The other configurations of the light detecting element 240 of the first example of the third embodiment are similar to those of the light detecting element 100 of the first embodiment described above.

[0217] The redistribution layer 241 is formed on the embedded layer 117. The redistribution layer 241 includes a redistribution line 242 and an insulating layer 243. The redistribution line 242 is embedded in the insulating layer 243. The bump electrode 137 is formed on the redistribution layer 241. The through electrode 127 is connected to the bump electrode 137 via the redistribution line 242.

[0218] As a material of the rewiring line 242, for example, SiO2, SiN, or SiCN can be used. As a material of the insulating layer 243, for example, a metal such as Al, Cu, AlCu, AlSiCu, or Co can be used.

[0219] Fig.17 It is a cross-sectional view showing a second example of the arrangement of the photodetection element according to the third embodiment.

[0220] exist Fig.17 In the light detecting element 250, a redistribution layer 251 is added to the light detecting element 200 of the first example of the second embodiment. The other configurations of the light detecting element 250 of the second example of the third embodiment are similar to those of the light detecting element 200 of the first example of the second embodiment.

[0221] The redistribution layer 251 is formed on the embedded layer 117. The redistribution layer 251 includes a redistribution line 252 and an insulating layer 253. The redistribution line 252 is embedded in the insulating layer 253. The bump electrode 137 is formed on the redistribution layer 251. The through electrode 227 is connected to the bump electrode 137 via the redistribution line 252. The other configurations of the redistribution layer 251 are similar to those of the redistribution layer 241 of the third embodiment described above.

[0222] Fig.18 It is a cross-sectional view showing a third example of the arrangement of the light detecting element according to the third embodiment.

[0223] exist Fig.18 In the light detecting element 260, a redistribution layer 261 is added to the light detecting element 210 of the second example of the second embodiment. The other configurations of the light detecting element 260 of the third example of the third embodiment are similar to those of the light detecting element 210 of the second example of the second embodiment.

[0224] The redistribution layer 261 is formed on the embedded layer 117. The redistribution layer 261 includes redistribution lines 263 and 264 and an insulating layer 262. Each of the redistribution lines 263 and 264 is embedded in the insulating layer 262. Bump electrodes 273 and 274 are formed on the redistribution layer 261. The through electrodes 223 and 224 are connected to the bump electrodes 273 and 274 via the redistribution lines 263 and 264, respectively. The other configurations of the redistribution layer 261 are similar to those of the redistribution layer 241 of the third embodiment described above.

[0225] Fig.19 1 is a plan view showing an example of the configuration of the external terminals and the rewiring line of the light detection element of the third embodiment. Fig.19 The configuration example of a can also be applied to Fig.16 Configuration of the external terminals and the redistribution lines of the light detection element 240. Fig.19 The configuration embodiment of b can also be applied to Fig.17 The structure of the external terminals of the light detection element 250 and the redistribution circuit. Fig.19 The configuration example of c can also be applied to Fig.18 The structure of the external terminals and the redistribution circuit of the light detection element 260.

[0226] exist Fig.19 In a, in the light detection element 240, the bump electrode 137 is connected to the rear surface wiring layer 146 via the redistribution line 242 and the through electrode 127. In this case, the redistribution line 242 and the bump electrode 137 may be arranged at a position other than the mounting area of ​​the chips 103 and 104.

[0227] exist Fig.19 In b, in the light detection element 250, the bump electrode 137 is connected to the wiring layer 141 via the redistribution line 252 and the through electrode 227. In this case, the redistribution line 252 and the bump electrode 137 may be arranged at a position other than the mounting area of ​​the chips 103 and 104.

[0228] exist Fig.19 In c, in the light detection element 260, the bump electrodes 273 and 274 are connected to the wiring layers 143 and 144 via the redistribution lines 263 and 264 and the through electrodes 223 and 224, respectively. At this time, the redistribution 263 and the bump electrode 273 can be arranged in the mounting area of ​​the chip 103, and the redistribution 264 and the bump electrode 274 can be arranged in the mounting area of ​​the chip 104. Note that the dummy external terminal 235 can be formed on the redistribution layer 261.

[0229] As described above, in the third embodiment, the redistribution line connected to the extended position of the through electrode is provided on the embedded layer, and the bump electrode is connected to the through electrode via the redistribution line. Thus, the arrangement position of the through electrode can be set without being restricted by the arrangement position of the bump electrode, and the restriction on the arrangement position of the through electrode can be alleviated.

[0230] <4. Fourth Embodiment>

[0231] In the first embodiment, in order to strengthen the light detecting element 100, the transparent substrate 145 is bonded to the rear surface side of the chip 101. In the fourth embodiment, in order to strengthen the light detecting element, a supporting substrate is bonded to the embedding layer 117, and the through-electrode penetrates the embedding layer 117 and the supporting substrate and extends to the outside of the light detecting element.

[0232] Fig. 20 It is a cross-sectional view showing a first example of the arrangement of the photodetection element according to the fourth embodiment.

[0233] exist Fig. 20 In the light detecting element 300, a supporting substrate 301 is added to the light detecting element 100 of the first embodiment described above. The other configurations of the light detecting element 300 of the first example of the fourth embodiment are similar to those of the light detecting element 100 of the first embodiment described above.

[0234] The support substrate 301 is formed on the embedded layer 117. The support substrate 301 may be bonded to the embedded layer 117 via an adhesive layer, or may be bonded to the embedded layer 117 based on an oxide film. The support substrate 301 may be a Si substrate, a ceramic substrate, or a resin substrate. The bump electrode 137 is formed on the support substrate 301. The through electrode 127 penetrates the support substrate 301 and the embedded layer 117, and is connected to the rear surface wiring layer 146. The insulating film 211 is formed to surround the periphery of the through electrode 127.

[0235] Fig.21 It is a cross-sectional view showing a second example of the arrangement of the photodetection element according to the fourth embodiment.

[0236] exist Fig.21 In the light detecting element 310, a supporting substrate 301 is added to the light detecting element 200 of the second embodiment described above. The other configurations of the light detecting element 310 of the second example of the fourth embodiment are similar to those of the light detecting element 200 of the second embodiment described above.

[0237] The support substrate 301 is formed on the embedded layer 117. The bump electrode 137 is formed on the support substrate 301. The through electrode 227 penetrates the embedded layer 117, the rear surface wiring layer 146, the protective film 116, the semiconductor layer 112, and the wiring layer 142, and is connected to the wiring layer 141. The insulating film 211 is formed to surround the periphery of the through electrode 227.

[0238] Fig. 22 It is a cross-sectional view showing a third example of the arrangement of the photodetection element according to the fourth embodiment.

[0239] exist Fig. 22 In the light detecting element 320, a supporting substrate 301 is added to the light detecting element 210 of the second embodiment described above. The other configurations of the light detecting element 320 of the third example of the fourth embodiment are similar to those of the light detecting element 210 of the second embodiment described above.

[0240] The support substrate 301 is formed on the embedded layer 117. Bump electrodes 233 and 234 are formed on the support substrate 301. The through electrodes 223 and 224 penetrate the embedded layer 117 and the semiconductor layers 113 and 114 and are respectively connected to the wiring layers 143 and 144. The insulating films 213 and 214 are formed so as to surround the peripheries of the through electrodes 223 and 224.

[0241] As described above, in the fourth embodiment, the support substrate 301 is bonded to the embedding layer 117, and the through-electrode extends to the outside of the light detecting element through the embedding layer 117 and the support substrate 301. Therefore, the light detecting element can be electrically connected to the outside without wire bonding, and the light detecting element can be strengthened.

[0242] Notice, Fig.16 The redistribution layer 241 in the embodiment may be formed on the supporting substrate 301 of the light detecting element 300. Fig.17 The redistribution layer 251 in the embodiment may be formed on the supporting substrate 301 of the light detecting element 310, or Fig.18 The redistribution layer 261 in the embodiment may be formed on the support substrate 301 of the light detection element 320 .

[0243] <5. Fifth embodiment>

[0244] In the above-mentioned first embodiment, the chip 102 is mounted face-up in the light detecting element 100. In the fifth embodiment, the chip 102 is mounted face-down in the light detecting element.

[0245] Fig.23 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the fifth embodiment.

[0246] exist Fig.23In the embodiment, the light detecting element 150 has the same chips 101 to 104 as the light detecting element 100 of the first embodiment. However, in the light detecting element 100 of the first embodiment, the chip 102 is mounted face-up, while in the light detecting element 150 of the fifth embodiment, the chip 102 is mounted face-down.

[0247] Here, the rear surface wiring layer 146 of the chip 102 is directly bonded to the wiring layer 141 of the chip 101. At this time, the pad electrode 176 of the rear surface wiring layer 146 can be bonded to the pad electrode 171 of the wiring layer 141 by Cu-Cu bonding. In addition, the wiring layer 142 of the chip 102 is directly bonded to the wiring layers 143 and 144 of the chips 103 and 104. At this time, the pad electrode 172 of the wiring layer 142 can be Cu-Cu bonded to the pad electrode 173 of the wiring layer 143 and Cu-Cu bonded to the pad electrode 174 of the wiring layer 144.

[0248] Figure 24 to Figure 27 It is a cross-sectional view showing an example of a method for manufacturing the light detecting element according to the fifth embodiment.

[0249] exist Fig.24 In a, for each portion into which the chip 102 is cut, a semiconductor element such as a transistor 132 is formed on the semiconductor wafer 112'. Next, a wiring layer 142 provided with wirings 152, pad electrodes 172, and vias 182 is formed on the semiconductor wafer 112'.

[0250] Then, if Fig.24 As shown in b, the temporary substrate 351 is bonded to the wiring layer 142. The planar size and shape of the temporary substrate 351 can be equal to the planar size and shape of the semiconductor wafer 112'. The thickness of the temporary substrate 351 can be set in the range of 300μm to 800μm. In the bonding of the temporary substrate 351, an adhesive can be used. Considering the formation of the insulating layer and the annealing temperature of the Cu-Cu bonding in the subsequent steps, the heat-resistant temperature of the adhesive is preferably in the range of 200°C to 500°C. In addition, when the semiconductor wafer 112' is thinned from the rear surface side in the next step, its thickness is made uniform, so that the variation in the thickness of the adhesive can be suppressed.

[0251] Then, if Fig.25 As shown in a, the semiconductor wafer 112' is thinned from the rear surface side. When the semiconductor wafer 112' is thinned, a grinder, CMP or etch-back may be used. At this time, the thickness of the semiconductor wafer 112' may be set within a range of 1 μm to 20 μm.

[0252] Then, if Fig.25As shown in b, a protective film 116 is formed on the rear surface side of the semiconductor wafer 112'. Next, a through hole 197 is formed in the semiconductor layer 112, and an insulating layer 198 is formed on the protective film 116 so as to be embedded in the through hole 197. Next, the insulating film at the connection position of each through hole 126 and 136 is removed, and each through hole 126 and 136 is embedded to be electrically connected to the wiring 152. At this time, the periphery of the through hole 126 may be covered by the insulating layer 198 to insulate the through hole 126 from the semiconductor wafer 112'. In addition, the insulating layer 196 may be formed around the through hole 136 to insulate the through hole 136 from the semiconductor wafer 112'.

[0253] Next, if Fig.25 As shown in c, a rear surface wiring layer 146 provided with a rear surface wiring 156, a pad electrode 176, and a via 186 is formed on the protective film 116. At this time, the through holes 126 and 136 can be electrically connected to the rear surface wiring 156. In addition, the front surface of the rear surface wiring layer 146 can be planarized by a method such as CMP so that the pad electrode 176 is exposed. The plane size of the pad electrode 176 can be set in the range of 0.1×0.1μm to 10×10μm.

[0254] Next, if Fig.26 As shown in a, a semiconductor wafer 111' is prepared, in which a pixel array unit and a peripheral circuit are formed for each part into which the chip 101 is cut. A wiring layer 141 is formed on the semiconductor wafer 111', in which wiring 151, pad electrode 171 and via 181 are provided.

[0255] Next, if Fig.26 As shown in b, the wiring layer 141 and the rear surface wiring layer 146 are directly bonded so that the wiring layer 141 and the rear surface wiring layer 146 face each other. At this time, the pad electrode 171 of the wiring layer 141 and the pad electrode 176 of the rear surface wiring layer 146 can be Cu-Cu bonded. In order to improve the bonding strength, the surfaces of the wiring layer 141 and the rear surface wiring layer 146 can be plasma treated or wet treated. In order to obtain sufficient bonding strength and good contact of the Cu bonding portion, the laminated wafer laminated with semiconductor wafers 111' and 112' can be heat treated at 200 to 400 degrees.

[0256] Then, if Fig. 27As shown in a, the temporary substrate 351 on the wiring layer 142 is peeled off. As a method for peeling off the temporary substrate 351, in the case where the temporary substrate 351 is a resin, a chemical solution for dissolving the temporary substrate 351 can be used, the temporary substrate 351 can be mechanically scratched, or the adhesion of the peeling surface can be reduced based on ultraviolet irradiation. In the case of oxide film peeling, Si can be cut with a grinder, Si can be dissolved by wet processing, or a combination thereof can be used.

[0257] Next, if Fig. 27 As shown in b, singulated chips 103 and 104 are prepared. Then, wiring layers 143 and 144 are directly bonded to wiring layer 142 so that wiring layers 143 and 144 are opposite to wiring layer 142. At this time, pad electrode 173 of wiring layer 143 and pad electrode 174 of wiring layer 144 can be Cu-Cu bonded to pad electrode 172 of wiring layer 142. In order to improve the bonding strength, the surfaces of wiring layers 143, 144 and wiring layer 142 can be plasma treated or wet treated. In order to obtain sufficient bonding strength and good contact of the Cu bonding portion, the laminated structure in which chips 103 and 104 are laminated on a laminated wafer in which semiconductor wafers 111' and 112' are laminated can be heat treated at 200 degrees to 400 degrees. For each part into which chip 101 is cut, each chip 103 and 104 can be arranged side by side on a laminated wafer in which semiconductor wafers 111' and 112' are bonded to each other.

[0258] Next, in the execution Figure 6 Step b and Figures 7 to 12 After the steps, the Fig.23 The light detecting element 150 is provided.

[0259] As described above, in the fifth embodiment described above, the chip 102 is mounted face-down in the light detecting element 150. As a result, each of the chips 103 and 104 can transmit signals to and from the chip 102 without being sandwiched by the through holes 126 and 136, and the transmission of signals to and from the chip 102 can be accelerated.

[0260] In addition, the structure in which the chip 102 is mounted face-down in the light detecting element 150 can be applied to the light detecting elements 200 and 210 of the second embodiment described above, and can also be applied to the light detecting elements 240, 250, and 260 of the third embodiment described above. In addition, the configuration in which the chip 102 is mounted face-down in the light detecting element 150 can also be applied to the light detecting elements 300, 310, and 320 of the fourth embodiment described above.

[0261] <6. Sixth Implementation Method>

[0262] In the first embodiment described above, the through-electrode 127 penetrating the embedding layer 117 in which the chips 103 and 104 are embedded and extending to the outside of the light detecting element 100 is connected to the rear surface wiring layer 146 of the chip 102. In the sixth embodiment, the through-electrode extending to the outside through the embedding layer is electrically connected to the lower chip via the rear surface wiring of the upper chip in which the lower chip mounted face-down on the upper chip is embedded.

[0263] Fig.28 is a cross-sectional view showing a configuration example of a light detecting element according to a sixth embodiment;

[0264] exist Fig.28 , the light detecting element 400 includes chips 401 to 404. Each of the chips 401 to 404 may be a semiconductor chip or may include an optical chip. At this time, as the uppermost chip disposed on the light detecting element 400, an optical chip can be used.

[0265] The optical element is formed on the optical chip. The optical element may be a solid-state imaging element such as a CCD or a CMOS. The light received by the solid-state imaging element may be visible light, or may be near-infrared light, short-wave infrared light, ultraviolet light, X-rays, etc. The optical element may be a light receiving element such as a PD, or may be a light emitting element such as an LD, an LED, or a VCSEL. The optical element may be a MEMS element, such as an optical switch or a reflector device. As the substrate of the optical chip, semiconductors such as Si, GaAs, InGaAsP, etc. may be used, and dielectrics such as LiNbO3, glass, and transparent resins may also be used.

[0266] Semiconductor elements are formed on semiconductor chips. Semiconductor elements may include transistors, resistors, capacitors, etc. In a semiconductor chip, a memory may be formed, a processor may be formed, a signal processing circuit may be formed, a data processing circuit may be formed, an interface circuit may be formed, or an optical element may be formed. For example, in a semiconductor chip, a hardware circuit such as an FPGA or an ASIC may be formed. The material of the base material for the semiconductor chip may be Si, GaAs, SiC, GaN, InGaAsP, etc.

[0267] In the following description, a case where a back-illuminated solid-state imaging element is formed on chip 401 and a semiconductor element is formed on each of chips 402 to 404 is taken as an example. At this time, a logic circuit or a semiconductor memory device may be formed in each of chips 402 to 404. The semiconductor memory device may include a ROM, a DRAM, or a NAND flash memory.

[0268] The chip 401 includes a semiconductor layer 411 and a wiring layer 441. The chip 401 is provided with a pixel array unit, wherein pixels are arranged in a matrix along the row direction and the column direction. Each pixel is provided with a photodiode and a pixel transistor.

[0269] The wiring layer 441 is formed on the front surface side of the semiconductor layer 411. At this time, the photodiode may be arranged on the rear surface side of the semiconductor layer 411. The wiring layer 441 is provided with the wiring 451 embedded in the insulating layer and the pad electrode 471. The pad electrode 471 may be used for direct bonding of the chip 401.

[0270] A color filter 415 is formed for each pixel on the rear surface side of the semiconductor layer 411. An on-chip lens 425 is formed on the color filter 415 of each pixel. Note that the chip 401 is an example of a sensor chip described in the claims.

[0271] Chip 402 is laminated on chip 401. The planar size and shape of chip 402 may be equal to those of chip 401. Chip 402 includes semiconductor layer 412, wiring layer 442, and rear surface wiring layer 446. Note that wiring layer 442 is an example of a front surface wiring layer described in the claims.

[0272] The wiring layer 442 is formed on the front surface side of the semiconductor layer 412. The wiring layer 442 is provided with the wiring 452 embedded in the insulating layer and the pad electrode 472. The pad electrode 472 can be used for direct bonding of the front surface side of the chip 402. For example, hybrid bonding can be used to directly bond the chip 401 to the chip 402.

[0273] A rear surface wiring layer 446 is formed on the rear surface side of the semiconductor layer 412. The rear surface wiring layer 446 is provided with rear surface wirings 456 embedded in an insulating layer and pad electrodes 476. The pad electrodes 476 can be used for direct bonding of the rear surface side of the chip 402.

[0274] The via 422 is embedded in the semiconductor layer 412. The via 422 penetrates the semiconductor layer 412 of the chip 402 and can establish conduction between the wiring layer 442 and the rear surface wiring layer 446. In order to insulate the via 422 from the semiconductor layer 412, an insulating layer 423 may be formed around the via 422.

[0275] The chip 403 is laminated on the rear surface wiring layer 446 of the chip 402. Here, the chip 403 may be mounted face down on the rear surface wiring layer 446 of the chip 402. The planar size of the chip 403 may be made smaller than that of the chip 401. The chip 403 includes a semiconductor layer 413 and a wiring layer 443.

[0276] The wiring layer 443 is formed on the front surface side of the semiconductor layer 413. The wiring layer 443 is provided with the wiring 453 embedded in the insulating layer and the pad electrode 473. The pad electrode 473 can be used to directly bond the front surface side of the chip 403. For example, the chip 403 can be directly bonded to the chip 402 by hybrid bonding.

[0277] The chip 404 is laminated on the rear surface wiring layer 446 of the chip 402. Here, the chip 404 can be mounted face down on the rear surface wiring layer 446 of the chip 402. At this time, the chip 404 is arranged side by side on the rear surface wiring layer 446 at an interval from the chip 403. The plane size of the chip 404 can be made smaller than the plane size of the chip 401. The chip 404 includes a semiconductor layer 414 and a wiring layer 444.

[0278] The wiring layer 444 is formed on the surface side of the semiconductor layer 414. The wiring layer 444 is provided with the wiring 454 embedded in the insulating layer and the pad electrode 474. The pad electrode 474 can be used for direct bonding of the front surface side of the chip 404. For example, the chip 404 can be directly bonded to the chip 402 by hybrid bonding.

[0279] In addition, on the rear surface wiring layer 446, an embedding layer 418 is laminated so that the chips 403 and 404 are embedded therein. The front surface of the embedding layer 418 may be flattened. A support substrate 428 is formed on the embedding layer 418. The support substrate 428 may be adhered to the embedding layer 418 via an adhesive layer. Through electrodes 427 and 457 are embedded in the embedding layer 418 and the support substrate 428.

[0280] The through electrode 427 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the wiring layer 443 via the rear surface wiring layer 446, and extends to the front surface of the support substrate 428. At this time, the through electrode 427 may be located on the conduction path K1 that establishes conduction between the external terminal of the light detection element 400 and the wiring layer 443. Here, the through hole 426 may be formed in the rear surface wiring layer 446, and the through electrode 427 may be electrically connected to the wiring layer 443 via the rear surface wiring 416, the through hole 426, and the pad electrode 436.

[0281] The through electrode 457 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the wiring layer 442 via the rear surface wiring layer 446, and extends to the front surface of the support substrate 428. At this time, the through electrode 457 can be located on the conductive path K2 that establishes conduction between the external terminal of the light detection element 400 and the wiring layer 442. Here, it is possible to prevent the wiring layers 443 and 444 from being interposed on the conductive path K2.

[0282] Wiring 417 and 447 are formed on the support substrate 428. Wiring 417 is connected to the through electrode 427, and wiring 447 is connected to the through electrode 457. At this time, wiring 417 can penetrate the embedded layer 418 and the support substrate 428 to contact the periphery of the through electrode 427, and wiring 447 can penetrate the embedded layer 418 and the support substrate 428 to contact the periphery of the through electrode 457. Bump electrode 437 is formed on wiring 417, and bump electrode 467 is formed on wiring 447. Bump electrodes 437, 467 can be used as external terminals for electrically connecting the light detection element 400 to the outside. Note that each of bump electrodes 437 and 467 can be a solder ball or a columnar electrode.

[0283] Here, the light detecting element 400 can be divided into a single light detecting element 400 from a state where a plurality of light detecting elements 400 are integrated into a wafer shape. In this singulation, for example, the light detecting element 400 formed into a wafer shape may be cut along a cutting line for dividing the light detecting element 400. At this time, the position of the cut surface of the embedding layer 418, the position of the cut surface of each of the chips 401 and 402, and the position of the cut surface of the support substrate 428 may be consistent with each other.

[0284] Each of the semiconductor layers 411 to 414 may be a semiconductor substrate, a thinned semiconductor substrate, or a semiconductor layer for an SOI substrate.

[0285] As a material for the insulating layer for each of the wiring layers 441 to 444 and the insulating layer 423 that insulates the through hole 422, for example, SiO2, SiN, or SiCN can be used. As a material for the wirings 451 to 454, the pad electrodes 471 to 474, and the through hole 422, for example, a metal such as Al, Cu, AlCu, AlSiCu, or Co can be used. As a material for the through electrodes 427 and 457, for example, a metal such as Cu, Ti, Ta, Al, W, Ni, Ru, or Co can be used, and a laminated structure of a plurality of materials can be used.

[0286] The material of the embedding layer 418 includes an insulating layer of an inorganic or organic material, and a plurality of films may be laminated. For example, in the case of an inorganic film, SiO2, SiON, SiN, SiOC, and SiCN are used, and in the case of an organic film, a resin having a skeleton such as silicone, polyimide, acrylic, epoxy, polymer, or PEEK material, or a material containing a filler such as SiO2, Al2O3, or AlN or BN is used. The material of the embedding layer 418 may be a molding material. The support substrate 428 may be a Si substrate, a ceramic substrate, or a resin substrate.

[0287] As described above, in the sixth embodiment, the through electrode 427 extends to the outside via the embedded layer 418 of the chips 403 and 404 mounted face down on the rear surface wiring layer 446 in which the chip 402 is embedded. Then, the through electrode 427 is electrically connected to the chip 403 via the rear surface wiring layer 446 of the chip 402. Thus, it is not necessary to insert the wiring layer 441 of the chip 401 and the wiring layer 442 of the chip 402 in order to electrically connect the chip 403 to the outside of the light detection element 400. As a result, it is not necessary to form a through electrode in any of the chips 401 to 403, and to electrically connect the chip 403 to the outside of the light detection element 400, so that the signal transmission delay caused by the parasitic capacitance formed between the through electrode and the chips 401 to 403 can be prevented.

[0288] In addition, the through-electrode 457 extends outward via the embedded layer 418 of the chips 403 and 404 mounted face-down on the rear surface wiring layer 446 in which the chip 402 is embedded. Then, the through-electrode 457 is electrically connected to the chip 401 via the rear surface wiring layer 446 of the chip 402. At this time, the through-electrode 457 can be arranged not only at the periphery of the light detection element 400, but also at the central portion. As a result, not only power can be supplied to the periphery of the light detection element 400, but also power can be supplied to the chip 401 via the through-electrode 457 in the central portion, and the IR voltage drop caused by the wiring resistance of the chip 401 can be made uniform between the periphery and the central portion of the chip 401. Therefore, the potential difference of the power supply between the periphery and the central portion of the pixel array unit formed in the chip 401 can be reduced, and the degradation of image quality such as shadows can be suppressed.

[0289] In addition, the through electrode 427 penetrates the support substrate 428, and the through electrode 427 extends to the outside. As a result, it is not necessary to use wiring bonding to electrically connect the light detection element 400 to the outside. Therefore, it is not necessary to set a bonding area in the light detection element 400, and it is possible to prevent delay in signal transmission via the bonding wire.

[0290] <7. Seventh Implementation Method>

[0291] In the sixth embodiment described above, the chip 402 on which the wiring layer 442 and the rear surface wiring layer 446 are formed is mounted face up, and the through electrodes 427 and 457 extending to the outside via the support substrate 428 are connected to the rear surface wiring layer 446. In the seventh embodiment, the chip on which the wiring layer and the rear surface wiring layer are formed is mounted face down, and the through electrodes 427 and 457 extending to the outside via the support substrate 428 are connected to the wiring layer of the chip mounted face down.

[0292] Fig.29 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the seventh embodiment.

[0293] exist Fig.29 In the embodiment, the light detecting element 500 includes a chip 502 instead of the chip 402 of the sixth embodiment described above. The other configurations of the light detecting element 500 of the sixth embodiment are similar to the configurations of the light detecting element 400 of the sixth embodiment described above.

[0294] Chip 502 is laminated on chip 401. The planar size and shape of chip 502 may be equal to those of chip 401. Chip 502 includes semiconductor layer 512, wiring layer 542, and rear surface wiring layer 546. Note that wiring layer 542 is an example of a front surface wiring layer described in the claims.

[0295] The wiring layer 542 is formed on the front surface side of the semiconductor layer 512. The wiring layer 542 is provided with the wiring 552 embedded in the insulating layer and the pad electrode 572. The pad electrode 572 can be used for direct bonding on the front surface side of the chip 502. At this time, the pad electrode 572 of the chip 502 and the pad electrodes 473 and 474 of the chips 403 and 404 can be Cu-Cu bonded.

[0296] The rear surface wiring layer 546 is formed on the rear surface side of the semiconductor layer 512. The rear surface wiring layer 546 has the rear surface wiring 556 embedded in the insulating layer and the pad electrode 576. The pad electrode 576 can be used for direct bonding of the rear surface side of the chip 502. At this time, the pad electrode 576 of the chip 502 and the pad electrode 471 of the chip 401 can be Cu-Cu bonded.

[0297] The via 522 is embedded in the semiconductor layer 512. The via 522 penetrates the semiconductor layer 512 of the chip 502 and can establish conduction between the wiring layer 542 and the rear surface wiring layer 546. In order to insulate the via 522 from the semiconductor layer 512, an insulating layer 532 may be formed around the via 522.

[0298] The chips 403 and 404 are laminated on the wiring layer 542 of the chip 502. Here, the chips 403 and 404 can be mounted on the rear surface wiring layer 542 of the chip 502 face down, respectively.

[0299] Furthermore, on the wiring layer 542, an embedding layer 418 is laminated so as to embed the chips 403 and 404. On the embedding layer 418, a supporting substrate 428 is formed.

[0300] The through electrode 427 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the wiring layer 443 via the wiring layer 542, and extends to the front surface of the support substrate 428. Here, the through hole 563 may be formed in the wiring layer 542, and the through electrode 427 may be electrically connected to the wiring layer 443 via the wiring 562, the through hole 563, and the pad electrode 532. In addition, the through electrode 457 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the rear surface wiring layer 546 via the wiring layer 542, and extends to the front surface of the support substrate 428.

[0301] As described above, in the seventh embodiment described above, the chip 502 on which the wiring layer 542 and the rear surface wiring layer 546 are formed is mounted face down, and is connected to the wiring layer 542 via the through electrodes 427 and 457 extending to the outside via the support substrate 428. As a result, each of the chips 403 and 404 can transmit signals to and from the chip 502 without inserting the through hole 522, and the transmission of signals to and from the chip 502 can be accelerated.

[0302] <8. Eighth Implementation Method>

[0303] In the seventh embodiment described above, the chip 502 on which the wiring layer 542 and the rear surface wiring layer 546 are formed is mounted face down, and is connected to the wiring layer 542 via the through electrodes 427 and 457 extending to the outside via the support substrate 428. In the eighth embodiment, the chip on which the wiring layer and the rear surface wiring layer are formed is mounted face down between the chip 401 and the chip 502.

[0304] Fig.30 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the eighth embodiment.

[0305] exist Fig.30 In the light detecting element 600, a chip 601 is added to the light detecting element 500 of the seventh embodiment. The other configurations of the light detecting element 600 of the eighth embodiment are similar to those of the light detecting element 500 of the seventh embodiment.

[0306] The chip 601 is laminated between the chip 401 and the chip 502. The planar size and shape of the chip 601 may be equal to the planar size and shape of the chip 401. The chip 601 includes a semiconductor layer 611, a wiring layer 641, and a rear surface wiring layer 646.

[0307] The wiring layer 641 is formed on the front surface side of the semiconductor layer 611. The wiring layer 641 is provided with a wiring 651 embedded in an insulating layer and a pad electrode 671. The pad electrode 671 can be used for direct bonding on the front surface side of the chip 601. At this time, the pad electrode 671 of the chip 601 and the pad electrode 576 of the chip 502 can be Cu-Cu bonded.

[0308] A rear surface wiring layer 646 is formed on the rear surface side of the semiconductor layer 611. The rear surface wiring layer 646 is provided with a rear surface wiring 656 and a pad electrode 676 embedded in an insulating layer. The pad electrode 676 can be used to directly bond the rear surface side of the chip 601. At this time, the pad electrode 676 of the chip 601 and the pad electrode 471 of the chip 401 can be Cu-Cu bonded.

[0309] The via 621 is embedded in the semiconductor layer 611. The via 621 penetrates the semiconductor layer 611 of the chip 601 and can establish conduction between the wiring layer 641 and the rear surface wiring layer 646. In order to insulate the via 621 from the semiconductor layer 611, an insulating layer 631 may be formed around the via 621.

[0310] As described above, in the eighth embodiment described above, the chip 601 on which the wiring layer 641 and the rear surface wiring layer 646 are formed is mounted face-down between the chip 401 and the chip 502. As a result, a decrease in the signal transmission speed between the chips 401, 601, 502, 403, and 404 can be suppressed, and the data processing function or storage function related to the imaging function can be expanded, and an increase in the mounting area of ​​the light detection element 600 can be suppressed.

[0311] <9. Ninth Implementation Method>

[0312] In the sixth embodiment described above, the chip 402 on which the wiring layer 442 and the rear surface wiring layer 446 are formed is mounted face up, and is connected to the rear surface wiring layer 446 via the through electrodes 427 and 457 extending to the outside via the support substrate 428. In the ninth embodiment, the chip on which the wiring layer and the rear surface wiring layer are formed is mounted face up between the chip 401 and the chip 402.

[0313] Fig.31 is a cross-sectional view showing a configuration example of a light detecting element according to a ninth embodiment.

[0314] exist Fig.31 In the light detecting element 700, a chip 701 is added to the light detecting element 400 of the sixth embodiment described above. The other configurations of the light detecting element 700 of the ninth embodiment are similar to those of the light detecting element 400 of the sixth embodiment described above.

[0315] The chip 701 is mounted face-up between the chip 401 and the chip 402. The planar size and shape of the chip 701 may be equal to the planar size and shape of the chip 401. The chip 701 includes a semiconductor layer 711, a wiring layer 741, and a rear surface wiring layer 746.

[0316] The wiring layer 741 is formed on the front surface side of the semiconductor layer 711. The wiring layer 741 is provided with a wiring 751 embedded in an insulating layer and a pad electrode 771. The pad electrode 771 can be used for direct bonding of the front surface side of the chip 701. At this time, the pad electrode 771 of the chip 701 and the pad electrode 471 of the chip 401 can be Cu-Cu bonded.

[0317] The rear surface wiring layer 746 is formed on the rear surface side of the semiconductor layer 711. The rear surface wiring layer 746 has the rear surface wiring 756 and the pad electrode 776 embedded in the insulating layer. The pad electrode 776 can be used for direct bonding of the rear surface side of the chip 701. At this time, the pad electrode 776 of the chip 701 and the pad electrode 472 of the chip 402 can be Cu-Cu bonded.

[0318] The via 721 is embedded in the semiconductor layer 711. The via 721 penetrates the semiconductor layer 711 of the chip 701 and can conduct the wiring layer 741 and the rear surface wiring layer 746. In order to insulate the via 721 from the semiconductor layer 711, an insulating layer 731 may be formed around the via 721.

[0319] As described above, in the ninth embodiment, the chip 701 formed with the wiring layer 741 and the rear surface wiring layer 746 is mounted upward between the chip 401 and the chip 402. As a result, it is possible to suppress a decrease in the signal transmission speed between the chips 401-404 and 701, and to expand the data processing function or storage function related to the imaging function, and to suppress an increase in the mounting area of ​​the light detection element 700.

[0320] <10. Tenth Implementation Method>

[0321] In the sixth embodiment described above, the through electrode 427 extends to the outside via the embedding layer 418 in which the chips 403 and 404 mounted face down on the upper chip are embedded. In the tenth embodiment, the through electrodes having different lengths extend to the outside via the lower chip on which the chips 403 and 404 embedded in the embedding layer 418 are mounted face down.

[0322] Fig.32 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the tenth embodiment.

[0323] exist Fig.32, the light detecting element 800 includes a chip 801 and through electrodes 837 and 847 instead of the chip 402 and the through electrodes 427 and 457 of the sixth embodiment. In addition, in the light detecting element 800, the chip 802 is added to the light detecting element 400 of the sixth embodiment. The other configurations of the light detecting element 800 of the tenth embodiment are similar to those of the light detecting element 400 of the sixth embodiment.

[0324] The chip 801 is laminated on the chip 401. The planar size and shape of the chip 801 may be equal to the planar size and shape of the chip 401. The chip 801 includes a semiconductor layer 811 and a wiring layer 841.

[0325] The wiring layer 841 is formed on the front side of the semiconductor layer 811. The wiring layer 841 is provided with a wiring 851 embedded in an insulating layer and a pad electrode 871. The pad electrode 871 can be used for direct bonding on the front surface side of the chip 801. At this time, the pad electrode 871 of the chip 801 and the pad electrode 471 of the chip 401 can be Cu-Cu bonded.

[0326] The chip 802 is arranged at the lowermost layer of the light detecting element 800. The planar size and shape of the chip 802 may be equal to the planar size and shape of the chip 401. The chip 802 includes a semiconductor layer 812 and a wiring layer 842.

[0327] The wiring layer 842 is formed on the front surface side of the semiconductor layer 812. The wiring layer 842 is provided with a wiring 852 and a pad electrode 872 embedded in an insulating layer. The pad electrode 872 can be used for direct bonding on the front surface side of the chip 802. On the wiring layer 842, the chips 403 and 404 are mounted face down. At this time, the pad electrode 872 of the chip 802 can be Cu-Cu bonded to the pad electrode 473 of the chip 403 and the pad electrode 474 of the chip 404.

[0328] Furthermore, on the wiring layer 842, the embedding layer 418 is laminated so that the chips 403 and 404 are embedded therein. The chip 801 is laminated on the embedding layer 418.

[0329] The through electrode 837 penetrates the semiconductor layer 812, is electrically connected to the wiring layer 842, and extends to the rear surface side of the chip 802. In order to insulate the through electrode 837 from the semiconductor layer 812, the insulating layer 827 may be formed to surround the periphery of the through electrode 837.

[0330] The length of the through electrode 847 is longer than that of the through electrode 837. At this time, the through electrode 847 penetrates the chip 802, the embedded layer 418, and the semiconductor layer 811, is electrically connected to the wiring layer 841, and extends to the rear surface side of the chip 802. In order to insulate the through electrode 847 from the semiconductor layers 811 and 812, the insulating layer 817 may be formed to surround the periphery of the through electrode 847.

[0331] Wiring 857 and 867 are formed on the rear surface side of the semiconductor layer 812 via the insulating layer 813. The wiring 857 is connected to the through electrode 837, and the wiring 867 is connected to the through electrode 847. At this time, the wiring 857 can penetrate the semiconductor layer 812 to contact the periphery of the through electrode 837, and the wiring 867 can penetrate the chip 802, the embedded layer 418, and the semiconductor layer 811 to contact the periphery of the through electrode 847. A bump electrode 877 is formed on the wiring 857, and a bump electrode 887 is formed on the wiring 867. Each of the bump electrodes 877 and 887 can be used as an external terminal for electrically connecting the light detection element 800 to the outside.

[0332] As described above, in the tenth embodiment, the through electrodes 837 and 847 having different lengths extend to the outside via the chip 802, and the chips 403 and 404 embedded in the embedding layer 418 are mounted face-down on the chip 802. Thus, the strength of the light detecting element 800 can be ensured, and the through electrodes 847 connected to the upper chip 801 and the through electrodes 837 connected to the lower chips 403 and 404, respectively, can be extended to the mounting surface of the light detecting element 800.

[0333] <11. Eleventh Implementation Method>

[0334] In the sixth embodiment described above, the through electrodes 427, 457 extend to the outside via the embedding layer 418 in which the chips 403, 404 are embedded, and the chips 403, 404 are mounted face down on the rear surface wiring layer 446 of the chip 402 laminated on the chip 401. In the eleventh embodiment, the through electrodes 427, 457 extend to the outside via the embedding layer 418 in which the chips 403, 404 are embedded, and the chips 403, 404 are mounted face down on the wiring layer of the uppermost chip.

[0335] Fig.33 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the eleventh embodiment.

[0336] exist Fig.33, the light detecting element 900 includes a chip 901 instead of the chip 401 of the sixth embodiment. In addition, the light detecting element 900 removes the chip 402 from the light detecting element 400 of the sixth embodiment. The other configurations of the light detecting element 900 of the eleventh embodiment are similar to those of the light detecting element 400 of the sixth embodiment.

[0337] The chip 901 includes a wiring layer 941 instead of the wiring layer 441 of the sixth embodiment. The other configurations of the chip 901 are similar to those of the light detecting element 400 of the sixth embodiment.

[0338] The wiring layer 941 is formed on the front surface side of the semiconductor layer 411. The wiring layer 941 is provided with a wiring 951 embedded in an insulating layer and a pad electrode 971. The pad electrode 971 can be used for direct bonding on the front surface side of the chip 901.

[0339] Chips 403 and 404 are mounted face down on wiring layer 941. At this time, pad electrode 971 of chip 901 may be Cu-Cu bonded to pad electrode 473 of chip 403 and pad electrode 474 of chip 404.

[0340] The through electrode 427 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the wiring layer 443 via the wiring layer 941, and extends to the front surface of the support substrate 428. At this time, the through electrode 427 may be located on the conduction path K1 that establishes conduction between the external terminal of the light detection element 900 and the wiring layer 443. Here, the through hole 921 may be formed in the wiring layer 941, and the through electrode 427 may be electrically connected to the wiring layer 443 via the wiring 911, the through hole 921, and the pad electrode 931.

[0341] The through electrode 457 penetrates the embedded layer 418 and the support substrate 428, is electrically connected to the semiconductor layer 411 via the wiring layer 941, and extends to the front surface of the support substrate 428. At this time, the through electrode 457 can be arranged on the conduction path K2 where the external terminal of the light detection element 900 is connected to the semiconductor layer 411. Here, the wiring layers 443 and 444 can be prevented from being interposed on the conduction path K2.

[0342] As described above, in the above-mentioned eleventh embodiment, the through electrodes 427 and 457 extend to the outside via the embedding layer 418 in which the chips 403 and 404 are embedded, and the chips 403 and 404 are mounted face down on the wiring layer 941 of the uppermost chip 901. At this time, the through electrode 427 can be electrically connected to the chip 403 via the wiring layer 941 of the chip 901. As a result, it is not necessary to form a through electrode on the chip 403 to electrically connect the chip 403 to the outside of the light detection element 900, and the delay of signal transmission caused by the parasitic capacitance formed between the through electrode and the chip 403 can be prevented. In addition, the through electrode 457 can be arranged not only around the light detection element 900, but also in the central part. As a result, not only can power be supplied to the periphery of the light detection element 900, but also power can be supplied to the chip 901 via the through electrode 457 in the central part, and the IR voltage drop caused by the wiring resistance of the chip 901 between the periphery and the central part of the chip 901 can be made uniform. Therefore, the potential difference of the power supply between the periphery and the central portion of the pixel array unit formed in the chip 901 can be reduced, and degradation of image quality such as shading can be suppressed.

[0343] <12. Twelfth Implementation Method>

[0344] In the above-mentioned sixth embodiment, the through electrodes 427, 457 extend to the outside via the embedding layer 418 in which the chips 403, 404 are embedded, and the chips 403, 404 are mounted face down on the rear surface wiring layer 446 of the chip 402 laminated on the chip 401. In the twelfth embodiment, an embedding member is embedded in the semiconductor substrate 413 of the chip 403 in the embedding layer 418 in which the through electrodes 427 are embedded.

[0345] Fig.34 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the twelfth embodiment. Fig.34 In FIG. 1 , a is a longitudinal cross-sectional view showing an example of a configuration of a light detecting element according to the twelfth embodiment, and b is a cross-sectional view showing an example of a configuration of a light detecting element according to the twelfth embodiment. Fig.34 A is cut at the line A1-A1 Fig.34 b. In addition, Fig.34 The a in the Fig.28 The chip 404 and the through electrode 457 in FIG.

[0346] exist Fig.34 , the light detecting element 1000 includes a chip 1101 instead of the chip 403 of the sixth embodiment. The other configurations of the light detecting element 1001 of the twelfth embodiment are similar to those of the light detecting element 400 of the sixth embodiment. However, an embedded component may be formed in the chip 404 in the same manner as in the chip 1101.

[0347] In the chip 1101, the embedding member 1011 is added to the chip 403 of the above-described sixth embodiment. The other configuration of the chip 1101 is similar to that of the chip 403 of the above-described sixth embodiment.

[0348] The embedded member 1011 is embedded in the semiconductor layer 413 of the chip 1101 from the rear surface side. The embedded member 1011 may be embedded in a position insulated from the wiring layer 443. The embedded member 1011 mitigates the non-uniformity of the stress applied to the chip 1101 due to the through electrode 427. In the semiconductor layer 413, the arrangement position and area density of the embedded member 1011 may be selected so that the stress in the region close to the through electrode 427 and the stress in the region far from the through electrode 427 are uniform. At this time, in the semiconductor layer 413, the area density of the embedded member 1011 in the region close to the through electrode 427 is preferably smaller than the area density of the embedded member 1011 in the region far from the through electrode 427. For example, the area density of the embedded member 1011 in the region from the end of the through electrode 427 side of the semiconductor layer 413 to the distance DC may be made smaller than the area density of the embedded member 1011 in the region exceeding the distance DC from the end of the semiconductor layer 413. The distance DC is, for example, 200 μm. In this case, the embedding member 1011 may be omitted from a region extending from the end of the semiconductor layer 413 on the through electrode 427 side to a distance DC.

[0349] The planar shape of the embedding member 1011 may be selected from vertical strips, horizontal strips, inclined strips, crossed strips, circles, n-gons (n ​​is an integer greater than 3), rings, solids, and combinations thereof. For example, the planar shape of the embedding member 1011 may be a lattice shape.

[0350] The material of the embedded member 1011 can be selected from any one of metal, metal oxide, organic substance, inorganic substance and a combination thereof. For example, the material of the embedded member 1011 can be Cu, Al, W, Au, Ag, etc. if it is a metal, Al2O3, etc. if it is a metal oxide, SiO2, SiN, etc. if it is an inorganic substance, and a resin such as polyimide if it is an organic substance. Note that the material of the embedded member 1101 is preferably a material having a tensile stress greater than the tensile stress of the material of the semiconductor layer 413, because the above-mentioned stress non-uniformity can be satisfactorily alleviated.

[0351] Fig.35 It is a diagram showing the relationship between the horizontal position and stress of the photodetection element according to the twelfth embodiment. Fig.35 In the figure, a is a longitudinal cross-sectional view showing an example of arrangement of the light detection element according to the twelfth embodiment, and b is a diagram showing the relationship between the horizontal position and stress of the light detection element according to the twelfth embodiment.

[0352] exist Fig.35 In b, in the case where the embedded member 1011 is not provided, the stress distribution F1 is generated in the chip 1101 due to the through electrode 427. Here, by embedding the embedded member 1011 into the semiconductor layer 413 of the chip 1101 from the rear surface side, it is possible to generate a stress distribution F2 in the chip 1101. At this time, a stress distribution F3 obtained by combining the stress distributions F1 and F2 is applied to the chip 1101, and the uniformity of the stress applied to the chip 1101 can be improved while eliminating the need for a restricted area between the chip 1101 and the through electrode 427.

[0353] In order to improve the uniformity of stress applied to the chip 1101 , at least one of the depth, surface size, and surface shape of the embedding member 1011 may be made different depending on the position of the semiconductor layer 413 .

[0354] Fig.36 and Fig.37 It is a diagram showing another arrangement example of the photodetection element according to the twelfth embodiment.

[0355] exist Fig.36 In a, the light detecting element may be provided with a chip 1020 instead of the chip 1101. The chip 1020 has an embedding member 1021 instead of the embedding member 1011. The plane shape of the embedding member 1021 may be a horizontal strip. At this time, the embedding members 1021 may be arranged side by side in the longitudinal direction.

[0356] exist Fig.36 In b, the light detecting element may have a chip 1030 instead of the chip 1101. The chip 1030 has an embedding member 1031 instead of the embedding member 1011. The plane shape of the embedding member 1031 may be a vertical strip. At this time, the embedding members 1031 may be arranged side by side in the horizontal direction.

[0357] exist Fig.36 In c, the light detecting element may have a chip 1040 instead of the chip 1101. The chip 1040 is provided with an embedding member 1041 instead of the embedding member 1011. The plane shape of the embedding member 1041 may be circular. At this time, the embedding members 1041 may be arranged side by side in the longitudinal direction and the transverse direction.

[0358] exist Fig.36 In the embodiment of the present invention, the light detecting element may be provided with a chip 1050 instead of the chip 1101. The chip 1050 has an embedding member 1051 instead of the embedding member 1011. The plane shape of the embedding member 1051 may be an n-gon. At this time, the embedding members 1051 may be arranged side by side in the longitudinal direction and the transverse direction.

[0359] exist Fig.37 In a, the light detecting element may be provided with a chip 1060 instead of the chip 1101. The chip 1060 has an embedding member 1061 instead of the embedding member 1011. The planar shape of the embedding member 1061 may be a solid pattern.

[0360] exist Fig.37 In b, the light detecting element may have a chip 1070 instead of the chip 1101. The chip 1070 is provided with an embedding member 1071 instead of the embedding member 1011. The planar shape of the embedding member 1071 may be a combination of a circle, a rectangle, and an n-gon. At this time, the sizes of the circle, the rectangle, and the n-gon may be different from each other.

[0361] exist Fig.37 In c, the light detecting element may be provided with a chip 1080 instead of the chip 1101. The chip 1080 is provided with an embedding member 1081 instead of the embedding member 1011. The planar shape of the embedding member 1081 may be a combination of a square, a rectangle, and an inclined pattern.

[0362] As described above, in the twelfth embodiment, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 1101 in the embedding layer 418 in which the through electrode 427 is embedded. As a result, the non-uniformity of the stress applied to the chip 1101 by the through electrode 427 can be reduced, and the restriction on the arrangement position of the through electrode 427 connected to the external terminal of the light detection element can be relaxed.

[0363] <13. Thirteenth Implementation Method>

[0364] In the twelfth embodiment, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 1101 embedded in the embedding layer 418 of the through electrode 427. In the thirteenth embodiment, the position of the embedding member of the semiconductor substrate 413 of the chip is different depending on the arrangement position of the through electrode 427.

[0365] Fig.38 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the thirteenth embodiment.

[0366] exist Fig.38 In a of the embodiment, the first embodiment of the light detecting element includes a chip 1110 instead of the chip 1101 of the above-mentioned twelfth embodiment. The chip 1110 is embedded in the embedding layer 418. In addition, the through electrodes 427 in the embedding layer 418 are located on both sides of the chip 1110. The other configurations of the first embodiment of the light detecting element of the thirteenth embodiment are similar to the configurations of the light detecting element of the above-mentioned twelfth embodiment.

[0367] The chip 1110 has an embedding member 1111 instead of the embedding member 1011 of the above-described twelfth embodiment. The other configurations of the chip 1110 are similar to those of the light detecting element of the above-described twelfth embodiment.

[0368] The embedded member 1111 is embedded in the semiconductor layer 413 of the chip 1110 from the rear surface side. The embedded member 1111 alleviates the non-uniformity of the stress applied to the chip 1110 due to the through electrode 427. At this time, in the semiconductor layer 413, the area density of the embedded member 1111 in the region close to the through electrode 427 can be made smaller than the area density of the embedded member 1111 in the region far from the through electrode 427. For example, the embedded member 1111 can be omitted from both ends of the semiconductor layer 413 adjacent to the through electrode 427 to the region of the distance DC.

[0369] exist Fig.38 In b, the second embodiment of the light detecting element includes a chip 1120 instead of the chip 1101 of the above-mentioned twelfth embodiment. The chip 1120 is embedded in the embedding layer 418. In addition, the through-electrode 427 in the embedding layer 418 is located near three sides of the chip 1110. The other configurations of the second embodiment of the light detecting element of the thirteenth embodiment are similar to the configurations of the light detecting element of the above-mentioned twelfth embodiment.

[0370] The chip 1120 includes an embedding member 1121 instead of the embedding member 1011 of the above-described twelfth embodiment. The other configurations of the chip 1120 are similar to those of the light detecting element of the above-described twelfth embodiment.

[0371] The embedding member 1121 is embedded in the semiconductor layer 413 of the chip 1120 from the rear surface side. The embedding member 1121 alleviates the non-uniformity of the stress applied to the chip 1120 due to the through electrode 427. At this time, in the semiconductor layer 413, the area density of the embedding member 1121 in the region close to the through electrode 427 can be made smaller than the area density of the embedding member 1121 in the region far from the through electrode 427. For example, the embedding member 1121 may be omitted from each of the three side surfaces of the semiconductor layer 413 adjacent to the through electrode 427 to the region of the distance DC.

[0372] exist Fig.38 In c, the third embodiment of the light detecting element includes a chip 1130 instead of the chip 1101 of the above-mentioned twelfth embodiment. The chip 1130 is embedded in the embedding layer 418. In addition, the through-electrode 427 in the embedding layer 418 is located at the corner of the chip 1110. The other configurations of the third embodiment of the light detecting element of the thirteenth embodiment are similar to the configurations of the light detecting element of the above-mentioned twelfth embodiment.

[0373] The chip 1130 includes an embedding member 1131 instead of the embedding member 1011 of the above-described twelfth embodiment. The other configurations of the chip 1130 are similar to those of the light detecting element of the above-described twelfth embodiment.

[0374] The embedded member 1131 is embedded in the semiconductor layer 413 of the chip 1130 from the rear surface side. The embedded member 1131 reduces the non-uniformity of the stress applied to the chip 1130 due to the through electrode 427. At this time, in the semiconductor layer 413, the area density of the embedded member 1131 in the region close to the through electrode 427 can be made smaller than the area density of the embedded member 1131 in the region far from the through electrode 427. For example, the embedded member 1131 may be omitted from the corner of the semiconductor layer 413 adjacent to the through electrode 427 to the region at a distance DC.

[0375] As described above, in the thirteenth embodiment described above, the position of the embedded member in the semiconductor substrate 413 of the chip is made different according to the arrangement position of the through electrode 427. Therefore, while dealing with the difference in the arrangement position of the through electrode 427 embedded in the embedded layer 418, the uniformity of the stress applied to the chip embedded in the embedded layer 418 can be improved.

[0376] <14. Fourteenth Implementation Method>

[0377] In the twelfth embodiment, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 1101 embedded in the embedding layer 418 of the through electrode 427. In the fourteenth embodiment, a stress relaxation film is formed on the bottom and side surfaces of the embedding member of the semiconductor substrate 413 embedded with the chip.

[0378] Fig.39 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the fourteenth embodiment.

[0379] exist Fig.39 In the embodiment, the light detecting element 1200 includes a chip 1201 instead of the chip 1101 of the above-described twelfth embodiment. The other configurations of the light detecting element 1200 of the fourteenth embodiment are similar to those of the light detecting element 1000 of the above-described twelfth embodiment.

[0380] The chip 1201 has an embedding member 1221 instead of the embedding member 1011 of the twelfth embodiment described above. In addition, in the chip 1201, an embedding layer 1211 is added to the chip 1101 of the twelfth embodiment described above. The other configurations of the chip 1201 are similar to those of the chip 1101 of the twelfth embodiment described above.

[0381] The embedded member 1221 is embedded in the semiconductor layer 413 of the chip 1201 from the rear surface side. The bottom surface and the side surface of the embedded member 1221 are covered by the embedded layer 1211. The embedded layer 1211 can be embedded in the semiconductor layer 413 of the chip 1201 from the rear surface side. The embedded layer 1211 alleviates the unevenness of the stress applied to the chip 1201 due to the through electrode 427. The materials of the embedded member 1221 and the embedded layer 1211 can be different from each other. The materials of the embedded member 1221 and the embedded layer 1211 can be selected from any one of metals, metal oxides, organic matter, inorganic matter and combinations thereof. The embedded member 1221 can be hollow.

[0382] As described above, in the fourteenth embodiment, the embedded layer 1211 embedded in the semiconductor layer 413 of the chip 1201 from the rear surface side is used as a stress relaxation film. As a result, the non-uniformity of the stress applied to the chip 1201 due to the through electrode 427 can be reduced, and the uniformity of the stress applied to the chip 1201 can be improved by adjusting the film thickness of the embedded layer 1211.

[0383] <15. Fifteenth Implementation Method>

[0384] In the twelfth embodiment, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 403 embedding the embedding layer 418 of the through electrode 427. In the fifteenth embodiment, the embedding member of the semiconductor substrate 413 of the chip is formed using the embedding layer 418 of the chip.

[0385] Fig.40 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the fifteenth embodiment.

[0386] exist Fig.40 In the embodiment, the light detecting element 1300 includes a chip 1301 instead of the chip 1101 of the above-described twelfth embodiment. The other configurations of the light detecting element 1300 of the fifteenth embodiment are similar to those of the light detecting element 1000 of the above-described twelfth embodiment.

[0387] The chip 1301 has an embedding member 1311 in place of the embedding member 1011 of the above-described twelfth embodiment. The other configurations of the chip 1301 are similar to those of the chip 1101 of the above-described twelfth embodiment.

[0388] The chip 1301 is embedded in the embedding layer 418. The embedding member 1311 is embedded in the semiconductor layer 413 of the chip 1301 from the rear surface side. The embedding member 1311 alleviates the unevenness of the stress applied to the chip 1301 due to the through electrode 427. The embedding member 1311 is formed using the embedding layer 418. Here, when the chip 1301 is embedded in the embedding layer 418, the embedding member 1311 may be embedded in the chip 1301. At this time, before the chip 1301 is embedded in the embedding layer 418, a recess 1312 in which the embedding member 1311 is embedded may be formed on the rear surface side of the semiconductor layer 413.

[0389] As described above, in the fifteenth embodiment, the embedding layer 418 in which the chip 1301 is embedded is used to form the embedding member 1311 embedded in the semiconductor substrate 413 of the chip 1301. Thus, unlike the step of embedding the chip 1301 in the embedding layer 418, there is no need to provide a step of embedding the embedding member 1311 in the semiconductor substrate 413 of the chip 1301. Therefore, it is possible to suppress an increase in the number of steps and to alleviate the non-uniformity of the stress applied to the chip 1301 by the through electrode 427.

[0390] <16. Sixteenth Implementation>

[0391] In the twelfth embodiment described above, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 403 embedding the embedding layer 418 of the through electrode 427. In the sixteenth embodiment, a functional film is formed on the bottom and side surfaces of the embedding member of the semiconductor substrate 413 embedding the chip.

[0392] Fig.41 It is a cross-sectional view showing an example of arrangement of a photodetection element according to the sixteenth embodiment.

[0393] exist Fig.41 In the embodiment 14, the light detecting element 1400 includes a chip 1401 instead of the chip 1101 of the above-described twelfth embodiment. The other configurations of the light detecting element 1400 of the fourteenth embodiment are similar to the configurations of the light detecting element 1000 of the above-described twelfth embodiment.

[0394] The chip 1401 has an embedding member 1411 instead of the embedding member 1011 of the twelfth embodiment described above. Furthermore, in the chip 1401, functional films 1421, 1431, and 1441 are added to the chip 1101 of the twelfth embodiment described above. The other configuration of the chip 1401 is similar to that of the chip 1101 of the twelfth embodiment described above.

[0395] The embedded member 1411 is embedded in the semiconductor layer 413 of the chip 1401 from the rear surface side. The embedded member 1411 alleviates the unevenness of the stress applied to the chip 1401 due to the through electrode 427. The bottom surface and the side surface of the embedded member 1411 are covered with at least one of the functional films 1421, 1431 and 1441. At this time, the functional films 1421, 1431 and 1441 may be a single layer or may be laminated. The functional films 1421, 1431 and 1441 may be embedded in the semiconductor layer 413 of the chip 1401 from the rear surface side. The functional films 1421, 1431 and 1441 may be dielectric films, protective films or barrier metal films.

[0396] As described above, in the above-mentioned sixteenth embodiment, the functional films 1421, 1431 and 1441 are formed on the bottom surface and the side surface of the embedded member 1411 embedded in the semiconductor substrate 413 of the chip. Thus, the non-uniformity of the stress applied to the chip 1401 by the through electrode 427 can be reduced while ensuring the adaptability of the embedded member 1411.

[0397] In addition, in the above-mentioned sixteenth embodiment, an example is described in which the embedding member 1411 is embedded in the semiconductor layer 413 at a position insulated from the wiring layer 443 from the rear surface side. A capacitor can be formed in the embedding member 1411. The above-mentioned capacitor can reduce the noise contained in the signal input to the above-mentioned light detection element. In this case, the capacitor can be connected to the input terminal of the light detection element via the wiring layer 443.

[0398] <17. Seventeenth Implementation Method>

[0399] In the twelfth embodiment described above, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 403 embedding the embedding layer 418 of the through electrode 427. In the seventeenth embodiment, a functional film is formed on the rear surface side of the chip in which the embedding member 1011 is embedded.

[0400] Fig.42 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the seventeenth embodiment.

[0401] exist Fig.42 In the embodiment, the light detecting element 1500 includes a chip 1501 instead of the chip 1101 of the above-described twelfth embodiment. The other configurations of the light detecting element 1500 of the fifteenth embodiment are similar to those of the light detecting element 1000 of the above-described twelfth embodiment.

[0402] In the chip 1501, a functional film 1502 is added to the chip 1101 of the above-described twelfth embodiment. The other configuration of the chip 1501 is similar to that of the chip 1101 of the above-described twelfth embodiment.

[0403] A functional film 1502 is formed on the rear surface side of the semiconductor substrate 413 so as to cover the surface of the embedding member 1011. The functional film 1502 may be a heat dissipation film, a protective film, or a warpage correction film. The functional film 1502 may be a single layer, or films having different functions may be laminated.

[0404] As described above, in the seventeenth embodiment, the functional film 1502 is formed on the rear surface side of the chip 1501 in which the embedding member 1011 is embedded. As a result, the non-uniformity of the stress applied to the chip 1501 by the through electrode 427 can be reduced, the complication of the manufacturing steps can be suppressed, and the characteristics and reliability of the chip 1501 can be improved.

[0405] <18. Eighteenth Implementation Method>

[0406] In the twelfth embodiment, embedding member 1011 is embedded in semiconductor substrate 413 of chip 403 embedding layer 418 of through electrode 427. In the eighteenth embodiment, a portion of the embedding member embedded in semiconductor substrate 413 of the chip embedded in embedding layer 418 is configured to penetrate semiconductor substrate 413.

[0407] Fig.43 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the eighteenth embodiment.

[0408] exist Fig.43 In the embodiment 18, the light detecting element 1600 includes a chip 1601 instead of the chip 1101 of the above-described twelfth embodiment. The other configurations of the light detecting element 1600 of the eighteenth embodiment are similar to those of the light detecting element 1000 of the above-described twelfth embodiment.

[0409] In the chip 1601, an embedding member 1611 and a dummy electrode 1621 are added to the chip 1101 of the above-described twelfth embodiment. The other configuration of the chip 1601 is similar to that of the chip 1101 of the above-described twelfth embodiment.

[0410] The dummy electrode 1621 is embedded in the wiring layer 443. The dummy electrode 1621 may be formed as an isolated electrode insulated from the wiring 453. The dummy electrode 1621 may be formed in the same layer as the pad electrode 473. At this time, the material of the dummy electrode 1621 may be the same as that of the pad electrode 473.

[0411] The embedded member 1611 is embedded in the semiconductor layer 413 of the chip 1601 from the rear surface side. At this time, the embedded member 1611 can penetrate the semiconductor layer 413 and be connected to the dummy electrode 1621. The embedded member 1611 alleviates the non-uniformity of the stress applied to the chip 1601 due to the through electrode 427. The embedded member 1011 and the embedded member 1611 may have different effects of alleviating the non-uniformity of the stress applied to the chip 1601. At this time, the arrangement position of the embedded member 1611 may be set so as to improve the uniformity of the stress applied to the chip 1601. The material of the embedded member 1611 may be the same as that of the embedded member 1011. Note that any configuration of the above-mentioned fourteenth to sixteenth embodiments can also be applied to the embedded member 1611.

[0412] As described above, in the above-mentioned eighteenth embodiment, the embedding member 1611 in the chip 1601 embedded in the embedding layer 418 penetrates the semiconductor substrate 413. As a result, even if there is a peculiarity in the stress applied to the chip 1601, the non-uniformity of the stress applied to the chip 1601 due to the through electrode 427 can be alleviated.

[0413] <19. Nineteenth Implementation Method>

[0414] In the twelfth embodiment, the embedding member 1011 is embedded in the semiconductor substrate 413 of the chip 403 embedded in the embedding layer 418 of the through electrode 427. In the nineteenth embodiment, different functional films are formed on the bottom surface, side surface and surface of the embedding member embedded in the semiconductor substrate 413 of the chip embedded in the embedding layer 418.

[0415] Figures 44 to 48 It is a diagram showing an example of the arrangement of a light detecting element according to the nineteenth embodiment.

[0416] exist Fig.44 In a, for each portion into which the chip 401 is cut, a pixel array unit and a peripheral circuit are formed on the semiconductor wafer 411'. Next, a wiring layer 441 provided with wiring 451 and pad electrode 471 is formed on the semiconductor wafer 411'. A plurality of chips 401 used for a plurality of light detecting elements 1700 can be cut out from the semiconductor wafer 411'. For example, the semiconductor wafer 411' can be divided along a cutting line for separation of light detecting elements.

[0417] In addition, for each portion into which the chip 402 is cut, a semiconductor element such as a transistor is formed on the semiconductor wafer 412'. Next, a wiring layer 442 provided with wirings 452 and pad electrodes 472 is formed on the semiconductor wafer 412'. A plurality of chips 402 used for a plurality of light detecting elements 1700 can be cut out from the semiconductor wafer 412'. For example, the semiconductor wafer 412' can be cut along a cutting line used to cut the light detecting elements 1700.

[0418] Next, the wiring layer 441 and the wiring layer 442 are directly bonded so that the wiring layers 441 and 442 face each other. At this time, the pad electrode 471 of the wiring layer 441 and the pad electrode 472 of the wiring layer 442 may be Cu-Cu bonded.

[0419] Next, the semiconductor wafer 412' is thinned from the rear surface side. Then, the via 422 is embedded in the semiconductor wafer 412' so as to be electrically connected to the wiring 452. The insulating layer 423 may cover the periphery of the via 422 to insulate the via 422 from the semiconductor wafer 412'.

[0420] Next, a rear surface wiring layer 446 having the rear surface wiring 416, the pad electrode 436, and the rear surface wiring 416 is formed on the rear surface side of the semiconductor wafer 412'. At this time, the via 422 may be electrically connected to the rear surface wiring 416.

[0421] Next, a singulated chip 1701 is prepared. The chip 1701 is provided with a semiconductor layer 413, and a wiring layer 443 is formed on the surface side of the semiconductor layer 413. The wiring layer 443 is provided with a wiring 453 embedded in an insulating layer and a pad electrode 473. Then, the wiring layer 443 is directly bonded to the rear surface wiring layer 446 so that the wiring layer 443 faces the rear surface wiring layer 446. At this time, the pad electrode 473 of the wiring layer 443 can be bonded to the pad electrode 436 of the rear surface wiring layer 446 by Cu-Cu bonding.

[0422] Next, if Fig.44 As shown in FIG. 1B , a recess 1704 is formed on the rear surface side of the semiconductor layer 413 by using a photolithography technique and a dry etching technique. The recess 1704 may be formed at a position where the embedding member 1711 is embedded.

[0423] Then, if Fig.45 As shown, a functional film 1712 is formed on the rear surface side of the semiconductor layer 413 in a manner covering the bottom surface and the side surface of the recess 1704. The functional film 1712 may be a single layer or may be laminated. The functional film 1712 may be a dielectric film, a protective film, or a barrier metal film. The functional film 1712 may be omitted. In order to form the functional film 1712, for example, CVD, PVD, atomic layer deposition (ALD), or electroplating may be used.

[0424] Then, if Fig.45 As shown in b, a filling material for embedding member 1711 is deposited on the rear surface side of semiconductor layer 413. For example, CVD or electroplating may be used to deposit the filling material for embedding member 1711. Then, by planarizing the filling material for embedding member 1711, embedded member 1711 is embedded in recess 1704. In order to planarize the filling material for embedding member 1711, for example, CMP may be used.

[0425] Then, if Fig.46 As shown in a, a functional film 1713 covering the front surface of the embedded member 1711 is formed on the rear surface side of the semiconductor layer 413. The functional film 1713 may be a single layer or may be laminated. The functional film 1713 may be a heat dissipation film, a protective film, or a warpage correction film. The functional film 1713 may be omitted. In order to form the functional film 1713, for example, CVD, PVD, ALD, or electroplating may be used.

[0426] Then, if Fig.46 As shown in FIG. 1 , an embedding layer 418 is laminated on the rear surface wiring layer 446, and the chip 1701 is embedded therein. For lamination of the embedding layer 418, in the case of an inorganic material, CVD, ALD, vapor deposition, sputtering, etc. may be used, and in the case of an organic material, coating, dipping, spraying, etc. may be used. The embedding layer 418 may be planarized. In planarization of the embedding layer 418, a grinder or CMP may be used.

[0427] Next, if Fig.47 As shown in FIG. 1 a, a support substrate 428 is bonded to the embedding layer 418. The planar size and shape of the support substrate 428 may be equal to the planar size and shape of the semiconductor wafer 411 ′.

[0428] Then, if Fig.47 As shown in FIG. 2 b, the conductor wafer 411' is thinned from the rear surface side. In this thinning, for example, a grinder, CMP, dry etching, or wet etching can be used. In the case where a back-illuminated individual imaging element is formed on the semiconductor wafer 411', the rear surface side of the thinned semiconductor wafer 411' becomes a light receiving surface.

[0429] Next, a color filter 415 is formed for each pixel on the rear surface side of the semiconductor wafer 411 ′. Furthermore, an on-chip lens 425 is formed on the color filter 415 for each pixel.

[0430] Next, if Fig.48As shown, a through hole 429 reaching the rear surface wiring layer 446 is formed in the support substrate 428, the embedded layer 418, and the functional films 1712 and 1713. The through hole 429 may be formed at a position where the through electrode 427 is embedded. Then, the wiring 417 is formed on the support substrate 428 to cover the side surface of the through hole 429.

[0431] Next, a through electrode 427 is formed in the through hole 429 to penetrate the embedded layer 418 and connect to the rear surface wiring layer 446. The diameter of the through electrode 427 can be set according to the number of IOs extracted outside the light detection element 1700, for example, can be set in the range of 3 μmΦ to 100 μmΦ. An insulating film such as SiO2 or SiN can be formed on the side wall of the through electrode 427.

[0432] Next, a bump electrode 437 connected to the wiring 417 is formed on the support substrate 428. The bump electrode 437 may be used as an external terminal connected to a mounting substrate on which the light detection element 1700 is mounted. The bump electrode 437 may be a solder ball.

[0433] Next, the laminated wafer of the semiconductor wafers 411 ′ and 412 ′ is singulated together with the embedding layer 418 in which the chip 1701 is embedded, thereby forming the light detecting element 1700 having a laminated structure provided with the chips 401 , 402 , and 1701 . In this singulation, a blade dicing may be used.

[0434] As described above, in the above-mentioned nineteenth embodiment, the functional films 1712 and 1713 are formed which are different from the bottom surface, the side surface, and the front surface of the embedding member 1711 in the semiconductor substrate 413 embedded in the embedding layer 418 of the chip 1701. As a result, the non-uniformity of the stress applied to the chip 1701 due to the through electrode 427 can be reduced, and the applicability of the embedding member 1711 can be ensured, and the characteristics and reliability of the chip 1701 can be improved.

[0435] Note that in the above-described twelfth to nineteenth embodiments, the chip 403 embedded in the embedding layer 418 in which the through electrode 427 is embedded is laminated on the chip 402, and the chip 402 is laminated on the chip 401. The structure in which the embedding member 1011 is embedded in the chip 403 in the embedding layer 418 in which the through electrode 427 is embedded can also be applied to a light detecting element without the chips 401, 402.

[0436] <20. Twentieth Implementation>

[0437] In the sixth embodiment described above, the through electrodes 427 and 457 extend to the outside via the embedding layer 418 in which the chips 403 and 404 are embedded, and the chips 403 and 404 are mounted face down on the rear surface wiring layer 446 of the chip 402 laminated on the chip 401. In the twentieth embodiment, a part of the through electrodes embedded in the embedding layer 418 in which the chips 403 and 404 are embedded is configured by a columnar electrode.

[0438] Fig.49 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the twentieth embodiment.

[0439] exist Fig.49 In the embodiment, the light detecting element 2100 includes a chip 2101 instead of the chip 402 of the sixth embodiment. In addition, the light detecting element 2100 includes a wiring 2105 and a through electrode 2106 instead of the wiring 417 and 447 and the through electrodes 427 and 457 of the sixth embodiment. In addition, in the light detecting element 2100, a columnar electrode 2104 is added to the light detecting element 400 of the sixth embodiment. Therefore, it is possible to better suppress warping caused by the difference in thermal expansion coefficient in the laminated structure of the light detecting element 2100. The other configurations of the light detecting element 2100 of the twentieth embodiment are similar to the configurations of the light detecting element 400 of the sixth embodiment.

[0440] The chip 2101 includes a rear surface wiring layer 2102 in place of the rear surface wiring layer 446 of the above-described sixth embodiment. The other configuration of the chip 2101 is similar to that of the chip 402 of the above-described sixth embodiment.

[0441] In the rear surface wiring layer 2102, a pad electrode 2103 is added to the rear surface wiring layer 446 of the above-described sixth embodiment. The other configuration of the rear surface wiring layer 2102 is similar to that of the rear surface wiring layer 446 of the above-described sixth embodiment.

[0442] The pad electrode 2103 is bonded to the columnar electrode 2104. The pad electrode 2103 may include the same material as the pad electrode 474. At this time, the pad electrode 2103 and the columnar electrode 2104 may be bonded simultaneously with the bonding between the pad electrode 436 and the pad electrode 437. For example, the pad electrode 2103 and the columnar electrode 2104 may be directly bonded based on Cu-Cu bonding.

[0443] The columnar electrode 2104 is embedded in the embedded layer 418 so as to be separated from the chips 403 and 404. At this time, the columnar electrode 2104 may be bonded to the pad electrode 2103. The height of the columnar electrode 2104 may be made smaller than the thickness of the embedded layer 418. Therefore, the columnar electrode 2104 may be prevented from being exposed from the embedded layer 418 when the embedded layer 418 is flattened, and metal contamination caused by the columnar electrode 2104 may be prevented. For example, Cu may be used as a material for the columnar electrode 2104. The columnar electrode 2104 may be formed before forming the embedded layer 418. Therefore, the need for processing the embedded layer 418 to form the columnar electrode 2104 may be eliminated.

[0444] The through electrode 2106 penetrates the embedded layer 418 and the supporting substrate 428 at the position of the columnar electrode 2104 and is electrically connected to the rear surface wiring layer 2102 via the columnar electrode 2104. At this time, the depth of the through hole of the embedded layer 418 penetrated by the through electrode 2106 can be made smaller than the thickness of the embedded layer 418.

[0445] The wiring 2105 is formed on the support substrate 428. The wiring 2105 is connected to the through electrode 2106. At this time, the wiring 2105 may be formed on the support substrate 428 to cover the side surface of the through hole in which the through electrode 2106 is embedded.

[0446] Figures 50 to 58 It is a cross-sectional view showing an example of a method for manufacturing a light detecting element according to a twentieth embodiment.

[0447] exist Fig.50 In the embodiment, for each portion into which the chip 401 is cut, a pixel array unit and a peripheral circuit are formed on the semiconductor wafer 411'. Next, a wiring layer 441 provided with wirings 451 and pad electrodes 471 is formed on the semiconductor wafer 411'.

[0448] Furthermore, for each portion into which the chip 2101 is cut, a semiconductor element such as a transistor is formed on the semiconductor wafer 412'. Next, a wiring layer 442 provided with wirings 452 and pad electrodes 472 is formed on the semiconductor wafer 412'.

[0449] Next, the wiring layer 441 and the wiring layer 442 are directly bonded so that the pad electrodes 471 and 472 face each other.

[0450] Next, the semiconductor wafer 412' is thinned from the rear surface side. Then, the via 422 is embedded in the semiconductor wafer 412' so as to be electrically connected to the wiring 452. The insulating layer 423 may cover the periphery of the via 422 to insulate the via 422 from the semiconductor wafer 412'.

[0451] Next, a rear surface wiring layer 2102 having rear surface wirings 416, pad electrodes 436, 2103, and rear surface wirings 416, 456 is formed on the rear surface side of the semiconductor wafer 412'. At this time, the via 422 may be electrically connected to the rear surface wiring 456.

[0452] Next, a semiconductor wafer divided into individual chips 403, 404 is prepared. Then, the wiring layers 443, 444 are directly bonded to the rear surface wiring layer 2102 so that the wiring layers 443, 444 are opposite to the rear surface wiring layer 2102. Next, the semiconductor wafer directly bonded to the rear surface wiring layer 2102 is divided into individual chips 403, 404.

[0453] Next, if Fig.51 As shown, a resist pattern RA provided with an opening KA is formed on the rear surface wiring layer 2102 based on the photolithography technology. The opening KA may be arranged at a position where the columnar electrode 2104 is formed. Then, the columnar electrode 2104 is formed in the opening KA by a method such as electroplating. At this time, the columnar electrode 2104 may be formed by a semi-additive method.

[0454] Then, if Fig.52 As shown, the resist pattern RA is removed from the rear surface wiring layer 2102 by ashing or the like.

[0455] Next, if Fig.53 As shown in FIG. 2 , the embedded layer 418 is deposited on the rear surface wiring layer 2102 so as to cover the chips 403 , 404 and the columnar electrodes 2104 by a method such as CVD.

[0456] Next, if Fig.54 As shown, the embedded layer 418 is thinned by a method such as CMP so that the embedded layer 418 is planarized.

[0457] Next, if Fig.55 As shown, support substrate 428 is bonded to embedding layer 418. An adhesive may be used to bond support substrate 428.

[0458] Next, if Fig.56 As shown, the semiconductor wafer 411 ′ is thinned by a method such as CMP.

[0459] Next, if Fig.57 As shown, a color filter 415 is formed for each pixel on the rear surface side of the semiconductor wafer 411'. In addition, an on-chip lens 425 is formed on the color filter 415 for each pixel.

[0460] Then, a through hole 2107 reaching the columnar electrode 2104 is formed in the support substrate 428 and the embedding layer 418. The through hole 2107 may be formed at a position where the through electrode 2106 is embedded. Then, a wiring 2105 is formed on the support substrate 428 to cover the side surface of the through hole 2107.

[0461] Next, if Fig.58 As shown in FIG. 4 , a through electrode 2106 penetrating the support substrate 428 and the embedded layer 418 and connected to the columnar electrode 2104 is formed in the through hole 2107. Then, a bump electrode 437 connected to the wiring 2105 is formed on the support substrate 428.

[0462] Then, if Fig.49 As shown, the laminated wafer of semiconductor wafers 411' and 412' is singulated together with the embedding layer 418 in which the chips 403 and 404 are embedded, thereby forming a light detecting element 2100 having a laminated structure provided with the chips 401, 2101, 403, and 404. In this singulation, a blade dicing may be used.

[0463] Fig.59 4 is a flowchart showing an example of a method of manufacturing a light detecting element of the twentieth embodiment. Note that in the following description, an example is shown in which the chip 401 is a sensor chip, the chips 2101 and 403 are logic chips, and the chip 404 is a memory chip.

[0464] exist Fig.59 In the process, a sensor wafer of the first layer, a logic wafer of the second layer, a logic wafer of the third layer, and a storage wafer are prepared (S101 to S103). In addition, a supporting substrate is prepared (S112). In the sensor wafer, a sensor is formed for each chip. In the logic wafer, a logic circuit is formed for each chip. In the storage wafer, a memory is formed for each chip.

[0465] Next, the sensor wafer of the first layer and the logic wafer of the second layer are F2F-bonded ( S104 ). In the F2F bonding, the front surface of the sensor wafer and the front surface of the logic wafer are bonded.

[0466] Next, the second-layer logic wafer is thinned from the rear surface side ( S105 ).

[0467] Next, a through hole penetrating the semiconductor layer of the second-layer logic wafer is formed ( S106 ).

[0468] Next, NEOL formation is performed (S107). In the NEOL formation, a wiring layer connected to a via formed in the logic wafer of the second layer is formed on the rear surface side of the logic wafer (S107).

[0469] Next, CC3 formation is performed ( S108 ). In CC3 formation, a Cu electrode for Cu-Cu bonding with the logic wafer and the memory wafer of the third layer is formed on the logic wafer of the second layer.

[0470] In addition, CC4 formation is performed ( S109 ). In CC4 formation, Cu electrodes for Cu-Cu bonding with the logic wafer of the second layer are formed on the logic wafer and the memory wafer of the third layer.

[0471] Next, the logic wafer and the memory wafer of the third layer are cut into chips, and logic chips and memory chips of the third layer are formed ( S110 ).

[0472] Next, CoW is performed ( S111 ). In CoW, the logic chip and the memory chip of the third layer are bonded to the logic wafer of the second layer.

[0473] Next, pillar electrodes are formed on the logic wafer of the second layer to be separated from the logic chip and the memory chip of the third layer ( S121 ).

[0474] Next, an embedding layer is formed on the logic wafer of the second layer so that the logic chip and the memory chip of the third layer are embedded therein, and the embedding layer is planarized ( S113 ).

[0475] Next, a support substrate is bonded to the embedding layer in which the logic chip and the memory chip of the third layer are embedded ( S114 ).

[0476] Next, the sensor wafer of the first layer is thinned from the rear surface side ( S115 ).

[0477] Next, REOL / OCCF is performed (S116). In REOL / OCCF, a pixel separation layer and the like are formed on the rear surface side of the sensor wafer. After that, after a color filter is formed for each pixel on the rear surface side of the sensor wafer, an on-chip lens is formed for each pixel on the color filter.

[0478] Next, TSV / RDL / bump formation is performed (S117). In TSV / RDL / bump formation, a through electrode connected to the columnar electrode is formed in an embedded layer in which a logic chip and a memory chip of the third layer are embedded. Then, after a rewiring line connected to the through electrode is formed on the embedded layer, a bump electrode connected to the rewiring line is formed.

[0479] As described above, in the above-mentioned twentieth embodiment, a part of the through electrode 2106 embedded in the embedding layer 418 in which the chips 403 and 404 are embedded is configured by the pillar-shaped electrode 2104. As a result, the depth of the through hole of the embedding layer 418 through which the through electrode 2106 penetrates can be made smaller than the thickness of the embedding layer 418, and the load on the formation of the through electrode 2106 can be reduced.

[0480] <21. Twenty-first Implementation Method>

[0481] In the twentieth embodiment, part of the through electrode 2106 embedded in the embedding layer 418 embedding the chips 403 and 404 is configured by the pillar electrode 2104. In the twenty-first embodiment, a through electrode penetrating a dummy chip embedded in the wiring layer in the embedding layer 418 embedding the chips 403 and 404 is provided.

[0482] Fig.60 It is a cross-sectional view showing an example of arrangement of a light detection element according to the twenty-first embodiment.

[0483] exist Fig.60 , the light detecting element 2200 includes a dummy chip 2201 instead of the columnar electrode 2104 of the above-mentioned twentieth embodiment. In addition, the light detecting element 2200 includes a wiring 2206 and a through electrode 2207 instead of the wiring 2105 and the through electrode 2106 of the above-mentioned twentieth embodiment. In addition, the other configurations of the light detecting element 2200 of this embodiment are similar to the configurations of the light detecting element 2100 of the above-mentioned twentieth embodiment. In addition, in this case, as in the case of the light detecting element 2100, warping and the like caused by the difference in thermal expansion coefficient in the laminated structure of the light detecting element 2200 can be more effectively suppressed.

[0484] In the embedding layer 418, the dummy chip 2201 is embedded in a manner separated from the chips 403, 404. At this time, the dummy chip 2201 may be directly bonded to the rear surface wiring layer 2102. Here, the dummy chip 2201 may be mounted on the rear surface wiring layer 2102 of the chip 2101 face down.

[0485] The dummy chip 2201 includes a dummy substrate 2202 and a dummy wiring layer 2203. The dummy wiring layer 2203 is formed on the front surface side of the dummy substrate 2202. The dummy wiring layer 2203 has a dummy wiring 2204 and a pad electrode 2205 embedded in an insulating layer. The pad electrode 2205 can be used for direct bonding of the front surface side of the dummy chip 2201. For example, the dummy chip 2201 can be directly bonded to the chip 2101 by hybrid bonding. At this time, the pad electrode 2205 can be bonded to the pad electrode 2103 based on Cu-Cu bonding.

[0486] The through electrode 2207 penetrates the dummy substrate 2202, the embedded layer 418 and the support substrate 428 at the position of the dummy chip 2201 and is electrically connected to the dummy wiring layer 2203. At this time, the depth of the through hole of the embedded layer 418 penetrated by the through electrode 2207 can be made smaller than the thickness of the embedded layer 418.

[0487] The wiring 2206 is formed on the support substrate 428. The wiring 2206 is connected to the through electrode 2207. At this time, the wiring 2206 may be formed on the support substrate 428 to cover the side surface of the through hole in which the through electrode 2207 is embedded.

[0488] Fig.61 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-first embodiment.

[0489] exist Fig.61 In the manufacturing method, step S203 is provided instead of step S103 of the above-mentioned twentieth embodiment. In step S203, in addition to the logic wafer and the memory wafer of the third layer, a dummy wafer with wiring is also prepared. At this time, in step S109, the Cu electrode for Cu-Cu bonding with the logic wafer of the second layer is formed not only on the logic wafer and the memory wafer of the third layer, but also on the dummy wafer using wiring. In addition, in step S110, not only the logic chip and the memory chip of the third layer are formed, but also the dummy chip with wiring is formed.

[0490] In this manufacturing method, step S121 of the twentieth embodiment is omitted. At this time, in step S117, through electrodes connected to the wiring of the dummy chip with wiring are formed in the embedding layer in which the third-layer logic chip and memory chip are embedded and the semiconductor layer of the dummy chip with wiring.

[0491] As described above, in the above-mentioned twenty-first embodiment, the through electrode 2207 is provided which penetrates the dummy substrate 2202 of the dummy chip 2201 in which the dummy wiring layer 2203 is embedded in the embedded layer 418. As a result, the depth of the through hole of the embedded layer 418 through which the through electrode 2207 penetrates can be made smaller than the thickness of the embedded layer 418, and the load on the formation of the through electrode 2207 can be reduced.

[0492] <22. Twenty-second Implementation Method>

[0493] In the above-mentioned twenty-first embodiment, the through electrode 2207 is provided to penetrate the semiconductor layer 2202 of the dummy chip 2201 in which the dummy wiring layer 2203 is embedded in the embedding layer 418. In the twenty-second embodiment, the through electrode is provided to penetrate the dummy chip in which the wiring layer is not embedded in the embedding layer 418.

[0494] Fig.62 It is a cross-sectional view showing an example of arrangement of a light detecting element according to the twenty-second embodiment.

[0495] exist Fig.62 In the light detecting element 2300, a dummy chip 2301 is added to the light detecting element 400 of the sixth embodiment. The other configurations of the light detecting element 2300 of the twenty-second embodiment are similar to the configurations of the light detecting element 400 of the sixth embodiment. In addition, in this case, as in the case of the light detecting element 2100, warping caused by the difference in thermal expansion coefficient in the laminated structure of the light detecting element 2300 can be more effectively suppressed.

[0496] The dummy chip 2301 is embedded in the embedding layer 418 so as to be separated from the chips 403 and 404. At this time, the dummy chip 2301 may be directly bonded to the rear surface wiring layer 446.

[0497] The dummy chip 2301 includes a semiconductor layer 2302 and an insulating layer 2303. The insulating layer 2303 can be used for direct bonding of the front surface side of the dummy chip 2301.

[0498] The through electrode 427 penetrates the dummy chip 2301, the embedded layer 418, and the support substrate 428, and is electrically connected to the wiring layer 446. At this time, the depth of the through hole of the embedded layer 418 through which the through electrode 427 penetrates can be made smaller than the thickness of the embedded layer 418.

[0499] Fig.63 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-second embodiment.

[0500] exist Fig.63 In the manufacturing method, step S303 is provided instead of step S103 of the above-mentioned twentieth embodiment. In step S303, in addition to the logic wafer and the memory wafer of the third layer, a dummy wafer without wiring is also prepared. At this time, in step S109, the Cu electrode for Cu-Cu bonding with the logic wafer of the second layer is formed not only on the logic wafer and the memory wafer of the third layer, but also on the dummy wafer without wiring. In addition, in step S110, not only the logic chip and the memory chip of the third layer are formed, but also the dummy chip without wiring is formed. In addition, in step S117, a through electrode connected to the logic chip of the second layer is formed in the embedded layer in which the logic chip and the memory chip of the third layer are embedded and in the dummy chip without wiring.

[0501] As described above, in the above-mentioned twenty-second embodiment, the through electrode 427 that penetrates the dummy chip 2301 without the wiring layer embedded in the embedding layer 418 is provided. As a result, the depth of the through hole formed in the embedding layer 418 can be made thinner than the thickness of the embedding layer 418, and the burden of processing the embedding layer 418 can be reduced. At this time, the dry etching time for forming the through hole in the embedding layer 418 can be shortened. In addition, it is not necessary to form a wiring layer on the dummy chip 2301, and the manufacturing cost of the dummy chip 2301 can be reduced.

[0502] <23. Twenty-third Implementation Method>

[0503] In the above-mentioned twenty-second embodiment, the through electrode 427 is provided to penetrate the dummy chip 2301 embedded in the embedding layer 418 without a wiring layer. In the twenty-third embodiment, the through electrode penetrating the dummy chip embedded in the embedding layer also penetrates the semiconductor layer of the chip laminated on the embedding layer and is connected to the wiring layer.

[0504] Fig.64 It is a cross-sectional view showing an example of the arrangement of a light detecting element according to the twenty-third embodiment.

[0505] exist Fig.64 , the light detecting element 2400 includes a chip 2401 instead of the chip 802 of the tenth embodiment. In addition, the light detecting element 2400 adds a dummy chip 2301 to the light detecting element 800 of the tenth embodiment. The other configurations of the light detecting element 2400 of the twenty-fourth embodiment are similar to those of the light detecting element 800 of the tenth embodiment.

[0506] The chip 2401 is arranged at the lowermost layer of the light detecting element 2400. The planar size and shape of the chip 2401 may be equal to the planar size and shape of the chip 401. The chip 2401 includes a semiconductor layer 2402 and a wiring layer 2403.

[0507] The wiring layer 2403 is formed on the surface side of the semiconductor layer 2402. In the wiring layer 2403, a wiring 2405 is formed instead of the wiring 852 of the above-described tenth embodiment. The other configuration of the wiring layer 2403 is similar to that of the wiring layer 842 of the above-described tenth embodiment.

[0508] The dummy chip 2301 is bonded onto the wiring layer 2403. The dummy chip 2301 may be directly bonded onto the wiring layer 2403. Furthermore, on the wiring layer 2403, an embedding layer 418 is laminated so that the chips 403 and 404 are embedded therein. The dummy chip 2301 is embedded in the embedding layer 418.

[0509] The through electrode 2411 penetrates the semiconductor layer 2402, is electrically connected to the wiring layer 2403, and extends to the rear surface side of the chip 2401. In order to insulate the through electrode 2411 from the semiconductor layer 2402, an insulating layer may be formed so as to surround the outer peripheral edge of the through electrode 2411. Here, by providing the through electrode 2411, the wiring path for connecting the chips 403 and 404 to the external terminals can be shortened, and data transmission can be accelerated.

[0510] The length of the through electrode 2412 is longer than that of the through electrode 2411. At this time, the through electrode 2412 penetrates the chip 2401, the dummy chip 2301, the embedded layer 418, and the semiconductor layer 811, is electrically connected to the wiring layer 841, and extends to the rear surface side of the chip 2401. In order to insulate the through electrode 2412 from the semiconductor layers 811 and 2402, an insulating layer may be formed so as to surround the outer peripheral edge of the through electrode 2412. Here, by providing the through electrode 2412, the wiring path for connecting the chip 801 to the external terminal can be shortened, and data transmission can be accelerated.

[0511] A wiring 2406 is formed on the rear surface side of the semiconductor layer 2402 via an insulating layer. The wiring 2406 is connected to the through electrodes 2411 and 2412. At this time, the wiring 2406 may be formed to surround the outer periphery of the through electrodes 2411 and 2412. A bump electrode 887 is formed on the wiring 2406.

[0512] Fig.65 This is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-third embodiment.

[0513] exist Fig.65 In this manufacturing method, steps S207, S208, S211, S213 and S214 are provided to replace steps S106, S107, S108, S111, S113 and S114 of the above-mentioned twenty-second embodiment.

[0514] In step S207, BEOL formation (S107) is performed. In BEOL formation, a wiring layer is formed on a supporting substrate.

[0515] Next, CC3 formation is performed ( S208 ). In CC3 formation, Cu electrodes for Cu-Cu bonding with the logic wafer and the memory wafer of the third layer are formed on the wiring layer of the support substrate.

[0516] Next, CoW is performed ( S211 ). In CoW, the logic chip and the memory chip of the third layer are bonded to the support substrate.

[0517] Next, an embedded layer is formed on the wiring layer of the support substrate so that the logic chip and the memory chip of the third layer are embedded, and the embedded layer is planarized ( S213 ).

[0518] Next, the logic wafer of the second layer is bonded to the embedding layer in which the logic chip and the memory chip of the third layer are embedded (S214), and the process proceeds to step S115. In this bonding, oxide film bonding can be used. In oxide film bonding, bonding can be performed via an oxide film provided on a bonding surface.

[0519] As described above, in the above-mentioned twenty-third embodiment, the through electrode 2412 penetrating the dummy chip 2301 embedded in the embedding layer 418 also penetrates the semiconductor layer 811 laminated on the embedding layer 418 and is connected to the wiring layer 841. As a result, the depth of the through hole formed in the embedding layer 418 can be made thinner than the thickness of the embedding layer 418, and the burden of processing the embedding layer 418 can be reduced. In this case, the dry etching time for forming the through hole in the embedding layer 418 can be shortened.

[0520] <24. Twenty-fourth Implementation Method>

[0521] In the above-mentioned twenty-third embodiment, the through-electrode 2412 penetrating the dummy chip 2301 embedded in the embedding layer 418 also penetrates the semiconductor layer 811 laminated on the embedding layer 418 and is connected to the wiring layer 841. In the twenty-fourth embodiment, the through-electrode 2412 penetrating the dummy chip 2301 embedded in the embedding layer 418 is connected to the wiring layer 841 via a through hole in the chip embedded in the embedded layer 418.

[0522] Fig.66 is a cross-sectional view showing a configuration example of a light detecting element according to a twenty-fourth embodiment.

[0523] exist Fig.66 In the embodiment 24, the light detecting element 2500 includes a chip 2502 instead of the chip 801 of the above-mentioned embodiment 23. The other configurations of the light detecting element 2500 of the embodiment 24 are similar to the configurations of the light detecting element 2400 of the above-mentioned embodiment 23.

[0524] The chip 2502 is laminated on the chip 401. The planar size and shape of the chip 2502 may be equal to those of the chip 401. In the chip 2502, a rear surface wiring layer 2503 and a through-hole 2505 are added to the chip 801 of the above-described twenty-third embodiment.

[0525] The rear surface wiring layer 2503 is formed on the rear surface side of the semiconductor layer 811. The rear surface wiring 2504 embedded in the insulating layer is provided on the rear surface wiring layer 2503. At this time, the through electrode 2512 penetrates the chip 2401, the dummy chip 2301, and the embedded layer 418, is electrically connected to the rear surface wiring layer 2503, and extends to the rear surface side of the chip 2401. In order to insulate the through electrode 2512 from the semiconductor layer 2402, an insulating layer may be formed so as to surround the periphery of the through electrode 2512.

[0526] The through hole 2505 is embedded in the semiconductor layer 811. The through hole 2505 penetrates the semiconductor layer 811 of the chip 2502, and can establish conduction between the wiring layer 841 and the rear surface wiring layer 2503. In order to insulate the through hole 2505 from the semiconductor layer 811, an insulating layer 2506 may be formed around the through hole 2505. At this time, the through electrode 2512 is connected to the wiring layer 841 of the chip 2502 via the rear surface wiring 2504 and the through hole 2505.

[0527] Fig.67 is a flowchart showing an example of a method for manufacturing a light detecting element according to the twenty-fourth embodiment.

[0528] exist Fig.67 In this manufacturing method, steps S201 and S202 are added to the manufacturing method of the above-mentioned twenty-third embodiment. In step S201, after the second-layer logic wafer is thinned, a through hole penetrating the semiconductor layer of the second-layer logic wafer is formed.

[0529] Next, in step S202, NEOL formation is performed. In the NEOL formation, a rear surface wiring layer connected to the via formed in the logic wafer of the second layer is formed on the rear surface side of the logic wafer, and the process proceeds to step S214.

[0530] As described above, in the above-mentioned twenty-fourth embodiment, the through electrode 2512 that penetrates the dummy chip 2301 embedded in the embedding layer 418 is connected to the wiring layer 841 via the through hole 2505 in the chip 2502 embedded on the embedding layer 418. As a result, the depth of the through hole formed in the embedding layer 418 can be made thinner than the thickness of the embedding layer 418, and the burden of processing the embedding layer 418 can be reduced. At this time, the dry etching time for forming the through hole in the embedding layer 418 can be shortened. In addition, in order to connect the through electrode 2512 to the wiring layer 841 of the chip 2502, it is not necessary to embed the through electrode 2512 in the semiconductor layer 811. Therefore, it is possible to facilitate the processing of the through hole of the through electrode 2512 and improve the stability of the shape of the through electrode 2512.

[0531] <25. Twenty-fifth Implementation Method>

[0532] In the above-described twenty-fourth embodiment, the through-electrode 2512 penetrating the dummy chip 2301 embedded in the embedding layer 418 is connected to the wiring layer 841 via the through-hole 2505 in the chip 2502 embedded on the embedding layer 418. In the twenty-fifth embodiment, the through-electrode 2512 penetrating the embedding layer 418 is connected to the wiring layer 841 via the through-hole 2505 in the chip 2502 embedded on the embedding layer 418.

[0533] Fig.68 It is a cross-sectional view showing an example of the arrangement of a light detection element according to the twenty-fifth embodiment.

[0534] exist Fig.68 , the dummy chip 2301 of the above-mentioned twenty-fourth embodiment is removed from the light detecting element 2600. At this time, the through electrode 2512 penetrates the chip 2401 and the embedded layer 418, and is connected to the wiring layer 841 of the chip 2502 via the rear surface wiring 2504 and the through hole 2505. The other configurations of the light detecting element 2600 of the twenty-fifth embodiment are similar to the configurations of the light detecting element 2500 of the above-mentioned twenty-fourth embodiment.

[0535] As described above, in the above-mentioned twenty-fifth embodiment, the through electrode 2512 penetrating the embedded layer 418 is connected to the wiring layer 841 via the through hole 2505 embedded in the chip 2502 on the embedded layer 418. Thus, it is not necessary to embed the through electrode 2512 in the semiconductor layer 811 in order to connect the through electrode 2512 to the wiring layer 841 of the chip 2502. Therefore, it is possible to facilitate processing of the through hole of the through electrode 2512 and improve the stability of the shape of the through electrode 2512.

[0536] <26. Example of application for moving objects>

[0537] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure can be implemented in the form of a device installed on any kind of mobile object, such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0538] Fig.69 is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0539] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.69In the illustrated embodiment, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0540] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0541] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls a door lock device, a power window device, lights, etc. of the vehicle.

[0542] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the image outside the vehicle and receive the imaged image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface based on the received image, or detect the distance thereof.

[0543] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0544] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that images the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0545] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0546] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0547] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0548] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.69 In the embodiment of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0549] Fig.70 12031 is a diagram illustrating an embodiment of the installation position of the imaging unit 12031.

[0550] exist Fig.70 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0551] The imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 provided at the front nose in the interior of the vehicle and the imaging unit 12105 provided at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the side surfaces of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The imaging unit 12105 provided at the upper portion of the windshield in the interior of the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0552] By the way, Fig.70 An embodiment of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 represents the imaging range of the imaging unit 12101 provided to the front nose. The imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 provided to the side mirrors. The imaging range 12114 represents the imaging range of the imaging unit 12104 provided to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0553] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0554] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the leading vehicle, which specifically exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / hour) in the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to keep in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Thus, coordinated control for automatic driving that allows the vehicle to automatically travel without relying on the driver's operation, etc., can be performed.

[0555] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0556] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether or not there is a pedestrian in the imaged image of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a process of extracting feature points in the imaged image of the imaging units 12101 to 12104 as infrared cameras and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether or not it is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the imaged image of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0557] An embodiment of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied not only to the imaging unit 12031 and the driver state detection unit 12041 in the above-mentioned configuration, but also can realize at least some functions of the electronic control unit. Specifically, for example, the above-mentioned light detection elements 100, 600, etc. can be applied to the imaging unit 12031, and can realize at least part of the functions of the electronic control device. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to obtain a captured image while suppressing an increase in the installation area, and realize at least some functions of the vehicle control.

[0558] It should be noted that the above-mentioned embodiments illustrate examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the gist of the present technology. In addition, the effects described in this specification are only embodiments and are not limited, and other effects can be provided.

[0559] It should be noted that the present technology may also have the following configurations.

[0560] (1) A light detection element comprising:

[0561] a first chip, forming a first wiring layer on the first chip;

[0562] a second chip laminated on the first chip and forming a second wiring layer on the second chip;

[0563] A third chip is arranged side by side with the second chip at an interval and laminated on the first chip, and a third wiring layer is formed on the third chip;

[0564] an embedding layer laminated on the first chip such that the second chip and the third chip are embedded in the embedding layer; and

[0565] The through-electrode, located between the second chip and the third chip, penetrates the embedded layer and is connected to the first wiring layer.

[0566] (2) The light detecting element according to (1), wherein:

[0567] The first wiring layer is directly bonded to the second wiring layer and the third wiring layer.

[0568] (3) The light detecting element according to (1) or (2), further comprising: a supporting substrate disposed on the embedding layer, wherein:

[0569] The through-electrode penetrates the supporting substrate and the embedded layer, and is connected to the first wiring layer.

[0570] (4) The light detection element according to any one of (1) to (3), further including: a sensor chip on which the first chip is laminated, and the sensor chip has a fourth wiring layer formed on the front surface side and pixels formed on the rear surface side.

[0571] (5) The light detecting element according to (4), wherein:

[0572] The first wiring layer includes:

[0573] a front surface wiring layer formed on the front surface side of the first chip, and

[0574] a rear surface wiring layer formed on the rear surface side of the first chip;

[0575] The front surface wiring layer is directly bonded to the fourth wiring layer;

[0576] the rear surface wiring layer is directly bonded to the second wiring layer and the third wiring layer; and

[0577] The through-electrode penetrates the embedded layer and is connected to the rear surface wiring layer.

[0578] (6) The light detection element according to (5) further includes: a transparent substrate disposed on the sensor chip.

[0579] (7) The light detection element according to (6) further includes: a cavity that separates the imaging area of ​​the sensor chip from the transparent substrate.

[0580] (8) A light detection element comprising:

[0581] a first chip, forming a first wiring layer on the first chip;

[0582] a second chip laminated on the first chip and forming a second wiring layer on the second chip;

[0583] an embedding layer laminated on the first chip such that the second chip is embedded in the embedding layer;

[0584] a redistribution layer formed on the embedded layer; and

[0585] The through electrode penetrates the embedded layer and connects the redistribution layer and the first wiring layer.

[0586] (9) A light detection element comprising:

[0587] a first chip, forming a first wiring layer on the first chip;

[0588] a second chip mounted face-down on the first wiring layer, and a second wiring layer formed on the second chip;

[0589] an embedding layer laminated on the first chip such that the second chip is embedded in the embedding layer; and

[0590] The first through electrode penetrates the embedded layer and is connected to the second wiring layer via the first wiring layer.

[0591] (10) The light detection element according to (9), further including: a second through electrode that penetrates the embedded layer and is connected to the first wiring layer without interposing the second wiring layer.

[0592] (11) The light detection element according to (9) or (10), wherein:

[0593] The first wiring layer is directly bonded to the second wiring layer.

[0594] (12) The light detection element according to any one of (9) to (11), further including: a sensor chip on which the first chip is laminated, and the sensor chip has a third wiring layer formed on the front surface side and pixels formed on the rear surface side.

[0595] (13) The light detection element according to (12), wherein:

[0596] The first wiring layer includes:

[0597] a front surface wiring layer formed on the front surface side of the first chip, and

[0598] a rear surface wiring layer formed on the rear surface side of the first chip;

[0599] The front surface wiring layer is directly bonded to the third wiring layer;

[0600] The rear surface wiring layer is directly bonded to the second wiring layer; and

[0601] The first through electrode penetrates the embedded layer and is connected to the second wiring layer via the rear surface wiring layer.

[0602] (14) The light detection element according to (13), further including: a fourth chip laminated between the sensor chip and the first chip, and a fourth wiring layer is formed on the fourth chip.

[0603] (15) A light detection element comprising:

[0604] a first chip, forming a first wiring layer on the first chip;

[0605] a second chip forming a laminated structure with the first chip, and forming a second wiring layer on the second chip;

[0606] a third chip, forming a laminated structure with the first chip and the second chip, and forming a third wiring layer on the third chip;

[0607] an embedding layer forming a laminate structure with the first chip and the second chip such that the third chip is embedded in the embedding layer; and

[0608] The first through electrode penetrates the embedded layer and is connected to the second wiring layer.

[0609] (16) The light detection element according to (15), wherein:

[0610] The first chip is located at the first layer, the second chip is located at the second layer, and the third chip is located at the third layer; and

[0611] The light detection element further includes a second through electrode that penetrates the embedded layer, is connected to the third wiring layer, and is shorter than the first through electrode.

[0612] (17) The light detection element according to (15), wherein:

[0613] The first chip is located on the first layer, the second chip is located on the third layer, and the third chip is located on the second layer;

[0614] The light detection element further includes a second through electrode that penetrates the semiconductor layer of the second chip, is connected to the second wiring layer, and is shorter than the first through electrode; and

[0615] The first through-electrode penetrates the embedded layer and the semiconductor layer of the second chip, and is connected to the second wiring layer.

[0616] (18) The light detecting element according to any one of (15) to (17), wherein:

[0617] At least a portion of the first through-electrode includes a columnar electrode.

[0618] (19) The light detecting element according to any one of (15) to (17), wherein:

[0619] The second chip includes:

[0620] a semiconductor layer, forming a second wiring layer on the semiconductor layer, and

[0621] a through hole penetrating the semiconductor layer and connected to the second wiring layer; and

[0622] The first through-electrode penetrates the embedded layer and is connected to the second wiring layer via a through hole.

[0623] (20) The light detecting element according to any one of (15) to (17), further comprising: a dummy chip embedded in the embedding layer, wherein:

[0624] The first through-electrode penetrates the embedded layer and the dummy chip and is connected to the second wiring layer.

[0625] (21) The light detection element according to any one of (15) to (17), wherein:

[0626] The second chip includes a semiconductor layer having a second wiring layer formed thereon, and

[0627] The first through-electrode penetrates the embedded layer, the dummy chip, and the semiconductor layer, and is connected to the second wiring layer.

[0628] (22) The light detection element according to any one of (15) to (17), wherein:

[0629] The second chip includes:

[0630] a semiconductor layer, forming a second wiring layer on the semiconductor layer, and

[0631] a through hole penetrating the semiconductor layer and connected to the second wiring layer; and

[0632] The first through-electrode penetrates the embedded layer and the dummy chip, and is connected to the second wiring layer via a through hole.

[0633] (23) The light detecting element according to any one of (15) to (17), further comprising: a dummy chip embedded in the embedding layer, and the dummy chip has a dummy wiring layer formed on the dummy substrate, wherein

[0634] The first through-electrode penetrates the embedded layer and the dummy substrate, and is connected to the second wiring layer via the dummy wiring layer.

[0635] (24) The light detecting element according to any one of (15) to (23), further comprising: a supporting substrate supporting the embedding layer in which the third chip is embedded, wherein:

[0636] The first through electrode penetrates the support substrate.

[0637] (25) A light detection element comprising:

[0638] a first chip, in which a first wiring layer is formed on a first semiconductor substrate;

[0639] An embedding layer, in which the first chip is embedded;

[0640] Through-electrodes penetrate the embedded layer; and

[0641] The embedding member is embedded in the first semiconductor substrate at a position insulated from the first wiring layer.

[0642] (26) The light detecting element according to (25) further includes: a second chip forming a laminated structure with the first chip, and a second wiring layer extending onto the embedded layer is formed on the second chip, wherein

[0643] The embedding layer and the second chip form a laminate structure such that the first chip is embedded in the embedding layer.

[0644] (27) The light detecting element according to (25) or (26), further comprising: a supporting substrate supporting the embedding layer in which the first chip is embedded, wherein:

[0645] The through-electrode penetrates the supporting substrate.

[0646] (28) The light detecting element according to any one of (25) to (27), wherein:

[0647] In the first semiconductor substrate, an area density of the embedded members in a region close to the through-electrodes is smaller than an area density of the embedded members in a region far from the through-electrodes.

[0648] (29) The light detecting element according to any one of (25) to (28), wherein:

[0649] The area density of the embedded members in a region up to 200 μm from the end on the through-electrode side of the first semiconductor substrate is smaller than the area density of the embedded members in a region exceeding 200 μm from the end of the first semiconductor substrate.

[0650] (30) The light detecting element according to any one of (23) to (29), wherein:

[0651] Any one of a heat dissipation film, a protective film, a warpage correction film, and a laminate film obtained by combining these films is formed on the rear surface side of the first chip.

[0652] (31) A method for manufacturing a light detecting element, the method comprising:

[0653] a step of forming a laminated wafer in which a second wafer to be singulated into a second chip is laminated on a first wafer to be singulated into a first chip;

[0654] a step of laminating a third chip on the lamination wafer;

[0655] forming an embedding layer laminated on the laminated wafer so that the third chip is embedded in the embedding layer;

[0656] a step of forming a through electrode, the through electrode being electrically connected to the second chip via the embedding layer; and

[0657] A step of forming a light detecting element in which the laminated wafer is singulated together with the embedding layer in which the third chip is embedded.

[0658] (32) The method for manufacturing a light detecting element according to (31) further includes: a step of laminating a supporting substrate wafer on the embedding layer, wherein:

[0659] The through electrode penetrates the supporting substrate wafer, and

[0660] The laminate wafer and the supporting substrate wafer are singulated along the same cutting surface together with the embedding layer in which the third chip is embedded.

[0661] (33) A method for manufacturing a light detecting element according to (31), wherein:

[0662] The first chip includes a sensor chip having a wiring layer formed on a front surface side and pixels formed on a rear surface side;

[0663] The method further includes the step of laminating a transparent substrate wafer on the pixel forming surface side; and

[0664] The laminate wafer and the transparent substrate wafer are singulated along the same cutting surface together with the embedding layer in which the third chip is embedded.

[0665] Reference Symbols List

[0666] 100 light detection elements

[0667] 101 to 104 chips

[0668] 111 to 114 semiconductor layers

[0669] 121 pixels

[0670] 131 pixel transistor

[0671] 115 Color Filter

[0672] 125 On-chip lens

[0673] 135 Transparent resin

[0674] 145 Transparent substrate

[0675] 141 to 144 wiring layers

[0676] 151 to 154 wiring

[0677] 161 Barrier Metal Film

[0678] 171 to 174, 176 pad electrodes

[0679] 126, 136 through holes

[0680] 181 to 184, 186 vias

[0681] 146 Rear surface wiring layer

[0682] 156 Rear surface wiring

[0683] 116 Protective film

[0684] 196 Insulation layer

[0685] 117 Embedding Layer

[0686] 127 Through electrode

[0687] 137 Bump electrode.

Claims

1. A light detection element, comprising: a first chip, forming a first wiring layer on the first chip; a second chip laminated on the first chip and forming a second wiring layer on the second chip; A third chip is arranged side by side with the second chip at an interval and laminated on the first chip, and a third wiring layer is formed on the third chip; an embedding layer, laminated on the first chip, such that the second chip and the third chip are embedded in the embedding layer; as well as A through electrode, located between the second chip and the third chip, penetrates the embedded layer and is connected to the first wiring layer.

2. The light detecting element according to claim 1, wherein The first wiring layer is directly bonded to the second wiring layer and the third wiring layer.

3. The light detecting element according to claim 1, further comprising: A supporting substrate is disposed on the embedding layer, wherein: The through-electrode penetrates the support substrate and the embedded layer, and is connected to the first wiring layer.

4. The light detecting element according to claim 1, further comprising: A sensor chip on which the first chip is laminated and which has a fourth wiring layer formed on the front surface side and pixels formed on the rear surface side.

5. The light detecting element according to claim 4, wherein The first wiring layer comprises: a front surface wiring layer formed on the front surface side of the first chip, and a rear surface wiring layer formed on the rear surface side of the first chip; The front surface wiring layer is directly bonded to the fourth wiring layer; the rear surface wiring layer is directly bonded to the second wiring layer and the third wiring layer; and The through-electrode penetrates the embedded layer and is connected to the rear surface wiring layer.

6. The light detecting element according to claim 5, further comprising: A transparent substrate is arranged on the sensor chip.

7. The light detecting element according to claim 6, further comprising: A cavity separates the imaging area of ​​the sensor chip from the transparent substrate.

8. A light detection element, comprising: a first chip, forming a first wiring layer on the first chip; a second chip laminated on the first chip and forming a second wiring layer on the second chip; an embedding layer, laminated on the first chip, such that the second chip is embedded in the embedding layer; a redistribution layer formed on the embedded layer; as well as The through electrode penetrates the embedded layer and connects the redistribution layer and the first wiring layer.

9. A light detection element, comprising: a first chip, forming a first wiring layer on the first chip; a second chip mounted face-down on the first wiring layer, and a second wiring layer formed on the second chip; an embedding layer, laminated on the first chip, such that the second chip is embedded in the embedding layer; as well as A first through electrode penetrates the embedded layer and is connected to the second wiring layer via the first wiring layer.

10. The light detecting element according to claim 9, further comprising: A second through electrode penetrates the embedded layer and is connected to the first wiring layer without interposing the second wiring layer.

11. The light detecting element according to claim 9, wherein The first wiring layer is directly bonded to the second wiring layer.

12. The light detecting element according to claim 9, further comprising: A sensor chip on which the first chip is laminated and which has a third wiring layer formed on the front surface side and pixels formed on the rear surface side.

13. The light detecting element according to claim 12, wherein The first wiring layer comprises: a front surface wiring layer formed on the front surface side of the first chip, and a rear surface wiring layer formed on the rear surface side of the first chip; The front surface wiring layer is directly bonded to the third wiring layer; the rear surface wiring layer is directly bonded to the second wiring layer; and The first through-electrode penetrates the embedded layer and is connected to the second wiring layer via the rear surface wiring layer.

14. The light detecting element according to claim 13, further comprising: A fourth chip is laminated between the sensor chip and the first chip, and a fourth wiring layer is formed on the fourth chip.

15. A light detection element, comprising: a first chip, forming a first wiring layer on the first chip; a second chip, forming a laminated structure with the first chip, and forming a second wiring layer on the second chip; a third chip, forming a laminated structure with the first chip and the second chip, and forming a third wiring layer on the third chip; an embedding layer, forming a laminated structure with the first chip and the second chip, such that the third chip is embedded in the embedding layer; as well as The first through electrode penetrates the embedded layer and is connected to the second wiring layer.

16. The light detecting element according to claim 15, wherein The first chip is located at a first layer, the second chip is located at a second layer, and the third chip is located at a third layer; and The light detection element further includes a second through electrode that penetrates the embedded layer, is connected to the third wiring layer, and is shorter than the first through electrode.

17. The light detecting element according to claim 15, wherein The first chip is located on the first layer, the second chip is located on the third layer, and the third chip is located on the second layer; The light detection element further includes a second through electrode that penetrates the semiconductor layer of the second chip, is connected to the second wiring layer, and is shorter than the first through electrode; and The first through-electrode penetrates the embedded layer and the semiconductor layer of the second chip and is connected to the second wiring layer.

18. The light detecting element according to claim 15, wherein At least a portion of the first through-electrode includes a columnar electrode.

19. The light detecting element according to claim 15, wherein The second chip comprises: a semiconductor layer on which the second wiring layer is formed, and a through hole penetrating the semiconductor layer and connected to the second wiring layer; and The first through-electrode penetrates the embedded layer and is connected to the second wiring layer via the through hole.

20. The light detecting element according to claim 15, further comprising: A dummy chip is embedded in the embedding layer, wherein: The first through-electrode penetrates the embedded layer and the dummy chip, and is connected to the second wiring layer.

21. The light detecting element according to claim 15, wherein The second chip includes a semiconductor layer on which the second wiring layer is formed, and the first through-electrode penetrates the embedded layer, the dummy chip, and the semiconductor layer, and is connected to the second wiring layer.

22. The light detecting element according to claim 15, wherein The second chip comprises: a semiconductor layer on which the second wiring layer is formed, and a through hole penetrating the semiconductor layer and connected to the second wiring layer; and The first through-electrode penetrates the embedded layer and the dummy chip, and is connected to the second wiring layer via the through hole.

23. The light detecting element according to claim 15, further comprising: A dummy chip is embedded in the embedding layer, and the dummy chip has a dummy wiring layer formed on a dummy substrate, wherein: The first through-electrode penetrates the embedded layer and the dummy substrate, and is connected to the second wiring layer via the dummy wiring layer.

24. The light detecting element according to claim 15, further comprising: A supporting substrate supports the embedding layer in which the third chip is embedded, wherein: The first through-electrode penetrates the support substrate.

25. A light detection element, comprising: a first chip in which a first wiring layer is formed on a first semiconductor substrate; an embedding layer, in which the first chip is embedded; A through electrode penetrates the embedded layer; as well as An embedding member is embedded in the first semiconductor substrate at a position insulated from the first wiring layer.

26. The light detecting element according to claim 23, further comprising: A second chip is formed into a laminated structure with the first chip, and a second wiring layer extending onto the embedded layer is formed on the second chip, wherein: The embedding layer and the second chip form a laminated structure such that the first chip is embedded in the embedding layer.

27. The light detecting element according to claim 23, further comprising: A supporting substrate supports the embedding layer in which the first chip is embedded, wherein: The through-electrode penetrates the support substrate.

28. The light detecting element according to claim 23, wherein In the first semiconductor substrate, an area density of the embedded members in a region close to the through-electrodes is smaller than an area density of the embedded members in a region far from the through-electrodes.

29. The light detecting element according to claim 23, wherein An area density of embedded members in a region up to 200 μm from an end portion on the through-electrode side of the first semiconductor substrate is smaller than an area density of the embedded members in a region exceeding 200 μm from the end portion of the first semiconductor substrate.

30. The light detecting element according to claim 23, wherein Any one of a heat dissipation film, a protective film, a warpage correction film, and a laminate film obtained by combining these films is formed on the rear surface side of the first chip.

31. A method for manufacturing a light detection element, the method comprising: a step of forming a laminated wafer in which a second wafer to be singulated into a second chip is laminated on a first wafer to be singulated into a first chip; a step of laminating a third chip on the laminated wafer; forming an embedding layer laminated on the laminated wafer so that the third chip is embedded in the embedding layer; a step of forming a through electrode, wherein the through electrode is electrically connected to the second chip via the embedded layer; as well as a step of forming a light detecting element in which the laminated wafer is singulated together with the embedding layer in which the third chip is embedded.

32. The method for manufacturing a light detecting element according to claim 31, further comprising: The step of laminating a supporting substrate wafer on the embedding layer, wherein: The through electrode penetrates the supporting substrate wafer, and The laminate wafer and the support substrate wafer are singulated along the same cutting surface together with the embedding layer in which the third chip is embedded.

33. The method for manufacturing a light detecting element according to claim 31, wherein: The first chip includes a sensor chip having a wiring layer formed on a front surface side and pixels formed on a rear surface side; The method further includes the step of laminating a transparent substrate wafer on the pixel forming surface side; and The laminate wafer and the transparent substrate wafer are singulated along the same cutting surface together with the embedding layer in which the third chip is embedded.

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