Signal envelope detection circuit and chip

Abstract

The embodiment of the invention provides a signal envelope detection circuit and a chip, the signal envelope detection circuit comprises N cascaded first amplification circuits, the input end of the first-stage first amplification circuit is used for receiving a target input signal; m cascaded attenuation circuits, wherein the input end of the first-stage attenuation circuit is used for receiving a target input signal; m second amplification circuits, wherein the input end of each second amplification circuit is correspondingly connected with the output end of one attenuation circuit; the output end of each first amplifying circuit and the output end of each second amplifying circuit are connected with the input end of one rectifier; the output ends of all the rectifiers are connected together and are used for outputting a target output signal; wherein N and M are integers greater than 1; the N first amplification circuits and the M second amplification circuits have the same amplification factor. According to the embodiment of the invention, the dynamic range of the signal envelope detection circuit can be expanded, and the detection accuracy is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a signal envelope detection circuit and chip. Background Art

[0002] In communication systems, signal detection circuits and chips play an important role in extracting information and restoring original data to ensure the accuracy and integrity of information during transmission. In radar systems, signal detection circuits and chips are used to detect reflected signals and analyze key information such as the target's position, speed, and direction.

[0003] From the functional division, the functions of signal detection circuits and chips include signal envelope detection and effective value detection. Signal envelope detection can accurately capture the amplitude envelope of the RF signal, thereby extracting useful signal information. Among them, the dynamic range of the detectable signal is one of the key indicators of the signal envelope detection chip. Expanding the dynamic range of the signal envelope detection circuit is conducive to further promotion of its application in communication and radar systems, providing stronger support for modern communication technology and radar technology. Summary of the invention

[0004] The embodiments of the present disclosure provide a signal envelope detection circuit and chip with a large dynamic range and high linearity.

[0005] In a first aspect, an embodiment of the present disclosure provides a signal detection circuit, including: N cascaded first amplifier circuits, the input end of the first amplifier circuit of the first stage is used to receive the target input signal, and the input ends of the first amplifier circuits of the second to N stages are used to receive the output signal of the first amplifier circuit of the previous stage; M cascaded attenuation circuits, the input end of the first attenuation circuit is used to receive the target input signal, and the input ends of the second to Mth attenuation circuits are used to receive the output signal of the previous attenuation circuit; M second amplifying circuits, the input end of each second amplifying circuit being connected to the output end of the corresponding attenuation circuit; A plurality of rectifiers, wherein the output end of each first amplifying circuit is connected to the input end of the corresponding rectifier, and the output end of each second amplifying circuit is connected to the input end of the corresponding rectifier; the output ends of all rectifiers are connected together to output a target output signal; Wherein, N and M are both integers greater than 1; and the amplification factors of the first amplifying circuit and the second amplifying circuit are the same.

[0006] In a second aspect, an embodiment of the present disclosure provides a signal envelope detection chip, comprising a signal envelope detection circuit as in any one of the first aspect.

[0007] The beneficial effects of the disclosed embodiment are as follows: each amplifier circuit (the first amplifier circuit and the second amplifier circuit) adopts exactly the same amplification factor, and an attenuation circuit is connected before each second amplifier circuit, so that each second amplifier circuit receives an attenuated signal, and then amplifies it and gives it to the rectifier, so that in the case of a high-power input signal, although the output of the amplifier chain composed of the cascaded N first amplifier circuits reaches saturation, the attenuation circuit can attenuate the signal first, so that the high-power input signal can fall into the working range of the rectifier corresponding to the attenuation circuit, and then the second amplifier circuit and the rectifier convert the high-power part to achieve logarithmic conversion and increase the dynamic range; Furthermore, since the attenuation circuit substantially does not affect the linearity, and the amplification factors of the first amplifier circuit and the second amplifier circuit are the same, the linearity of the first amplifier circuit and the second amplifier circuit are the same, so that the output linearity of the rectifier connected to the first amplifier circuit and the second amplifier circuit is substantially consistent, thereby improving the deviation due to the gain difference and improving the detection accuracy; At the same time, an attenuation circuit is also connected before the first-stage second amplifier circuit, which can offset the amplification factor of the first-stage second amplifier circuit, so that the power of the output signal of the first second amplifier circuit falls within the range of the rectifier, ensuring the integrity of the current splicing. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 1 ; Figure 2 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 2 ; Figure 3 A schematic diagram of the structure of a limiting amplifier provided in an embodiment of the present disclosure Figure 1 ; Figure 4 A schematic diagram of the structure of a limiting amplifier provided in an embodiment of the present disclosure Figure 2 ; Figure 5 A curve showing the change of the output current of a rectifier step by step with the input power provided in the embodiment of the present disclosure Figure 1 ; Figure 6 A comparison diagram of an ideal logarithmic curve and an actual logarithmic curve provided in an embodiment of the present disclosure Figure 1 ; Figure 7 A comparison diagram of an ideal logarithmic curve error and an actual logarithmic curve error provided in an embodiment of the present disclosure Figure 1 ; Figure 8 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 3 ; Fig. 9 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 4 ; Fig.10 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 5 ; Fig.11 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 6 ; Fig.12 A schematic diagram of the structure of a signal envelope detection circuit provided in an embodiment of the present disclosure Figure 7 ; Fig.13 A schematic diagram of the structure of a rectifier provided in an embodiment of the present disclosure; Fig.14 A curve showing the change of the output current of a rectifier step by step with the input power provided in the embodiment of the present disclosure Figure 2 ; Fig.15 A comparison diagram of an ideal logarithmic curve and an actual logarithmic curve provided in an embodiment of the present disclosure Figure 2 ; Fig.16 A comparison diagram of an ideal logarithmic curve error and an actual logarithmic curve error provided in an embodiment of the present disclosure Figure 2 . DETAILED DESCRIPTION

[0009] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for the convenience of description, only the parts related to the relevant disclosure are shown in the drawings.

[0010] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0011] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0012] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0013] Before further describing the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are described first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations: decibel milliwatt (dBm); decibel (dB); Microampere (μA); Ampere (A); Volt (V); Bipolar Junction Transistor (BJT); Supply voltage (VDD).

[0014] The common structure of the signal envelope detection circuit (also known as logarithmic envelope detection circuit, detection circuit, detector, etc.) is the architecture of cascaded limiting amplifier and rectifier. Figure 1 As shown, the signal envelope detection circuit includes N cascaded limiting amplifiers (limiting amplifier 1 to limiting amplifier N), N+1 rectifiers (rectifier 1 to rectifier N+1) and a load resistor, where N is a positive integer. The output of each limiting amplifier is connected to the input of a rectifier, the input of limiting amplifier 1 is also connected to the input of a rectifier, and the outputs of N+1 rectifiers are connected together to output the signal obtained by envelope detection. Usually, the output signal of the rectifier is a current signal. Figure 1 In the embodiment, the signal envelope detection circuit also includes a load resistor, so that the current signal can be converted into a voltage signal to obtain Figure 1 The output voltage in. The limiting amplifier and rectifier are both double-ended inputs, and N limiting amplifiers form an amplification chain. The low end of the dynamic range of the signal envelope detection circuit is the sensitivity, and the high end is the input power limit. How to effectively expand the dynamic range of the signal envelope detection circuit is a problem that needs to be solved.

[0015] exist Figure 1 On the basis of Figure 2 As shown, the amplifier stage consists of Figure 1 The limiting amplifiers and rectifiers in Figure 2 In the figure, each limiting amplifier in the amplifier stage is represented by A1, and the serial number of the rectifier is not shown. At the same time, the number of rectifiers in the amplifier stage is the same as the number of limiting amplifiers A1. DETrepresents the load resistance, V DET represents the output voltage; the output signals of the 1st to the Nth limiting amplifier A1 are denoted as V p1 、V p2 ,…,V pN In order to increase the upper limit of the dynamic range, the embodiment of the present disclosure adds an attenuation stage based on the amplification link. Figure 2 As shown, the attenuation stage includes a plurality of attenuation circuits B0, a plurality of limiting amplifiers A0 and a plurality of rectifiers, and the number of attenuation circuits B0 is one less than the number of limiting amplifiers A0. Assuming that the number of limiting amplifiers A0 is M in total, M is a positive integer, and the input signals of the 1st to the Mth limiting amplifiers A0 are denoted as V att1 、V att2 ,…,V attM , the output signals of the 1st to the Mth limiting amplifier A0 are denoted as V n1 、V n2 ,…,V nM Among them, the first limiting amplifier A0 is a unit limiting amplifier with an amplification factor of 1, which directly receives the input signal V of the signal envelope detection circuit. IN The remaining limiting amplifiers A0 receive the signal attenuated by the attenuation circuit B0. The output end of each limiting amplifier A0 is also connected to the input end of a rectifier. The output ends of the rectifier in the amplification stage and the rectifier in the attenuation stage are connected together to output the output signal V DET In this way, when dealing with high-power signals, when the amplification stage is saturated, the envelope detection of the high-power signal can be performed through the attenuation stage.

[0016] It should be noted that the principle of the attenuation stage to increase the upper limit of the dynamic range is as follows: The limiting amplifier A1 behaves as a linear amplifier within the input range. When the output reaches the designed limiting value, the output will remain unchanged, that is, the dynamic range is limited. However, the dynamic range of the signal envelope detection circuit usually has a lower limit. When the input is less than the lower limit, the signal envelope detection circuit outputs the minimum value; when the input is greater than the lower limit and is within the linear working range, the signal envelope detection circuit converts the input into a logarithmic form output; when the input is greater than the linear working range, the output may still increase with the input, but it is no longer a logarithmic relationship. At this time, an attenuation circuit is required. When the input power is greater than the upper limit of the amplification stage, the attenuation circuit in the attenuation stage attenuates the excess power to detect the attenuated power signal. The rectifier is used to convert the voltage output by the limiting amplifier into current, and all currents are added together to complete the splicing.

[0017] For example: Assume Figure 2The input dynamic range of the signal envelope detection circuit is 80dBm (-50dBm~30dBm), and the output current range is 100μA~900μA, where the output current changes linearly with the dBm value of the power, which is equivalent to the logarithm of the absolute value of the power. The working range of the rectifier is assumed to be 0~10dBm; when the input signal of the rectifier is below 0dBm, the rectifier has no output; when the input signal of the rectifier is above 10dBm, the rectifier output is saturated; only when the input signal of the rectifier is between 0~10dBm, the current output by the rectifier changes linearly. Therefore, each level of limiting amplifier A1 needs to amplify the signal input to the rectifier to the range of 0~10dBm before it can be detected by the rectifier.

[0018] Assume that the amplifier stage includes 5 limiting amplifiers A1, each limiting amplifier A1 has a dynamic range of 10dBm, the dynamic range of the amplifier stage is 50dBm (-50dBm~0dBm), and the gain of each stage is 10dB; the first limiting amplifier A1 amplifies -10~0dBm to 0dBm~10dBm, and the corresponding first rectifier can output the corresponding current; the first limiting amplifier A1 and the second limiting amplifier A1 amplify -20dBm~-10dBm to 0~10dBm, and the corresponding second The first to third limiting amplifiers A1 amplify -30dBm~-20dBm to 0~10dBm, and the corresponding third rectifier can output the corresponding current; the first to fourth limiting amplifiers A1 amplify -40dBm~-30dBm to 0~10dBm, and the corresponding fourth rectifier can output the corresponding current; the first to fifth limiting amplifiers A1 amplify -50dBm~-40dBm to 0~10dBm, and the corresponding fifth rectifier can output the corresponding current.

[0019] When the input dynamic range is 0dBm~30dBm, it exceeds the dynamic range of the amplification stage. Therefore, after the attenuation circuit attenuates the input signal, it falls within the dynamic range of the attenuation stage (the attenuation stage can handle a larger signal power).

[0020] Assume that the attenuation stage includes 3 limiting amplifiers A0, correspondingly, it also includes 2 attenuation circuits B0 and 3 rectifiers; because when the power of the input signal is 0dBm~10dBm, it just falls within the working range of the rectifier, so the first limiting amplifier A0 in the attenuation stage directly outputs 0dBm~10dBm to the corresponding rectifier input end at a multiple of unit gain (corresponding to an amplification factor of 1), and then the rectifier converts it into a corresponding current, that is, the first limiting amplifier A0 is a single gain with an amplification factor of 1. The first attenuation circuit B0 attenuates 10dBm~20dBm to 0~10dBm, and the second limiting amplifier A0 outputs to the corresponding rectifier input end at a multiple of unit gain, and then the rectifier converts it into a corresponding current; the first attenuation circuit B0 and the second attenuation circuit B0 attenuate 20dBm~30dBm to 0dBm~10dBm, and the third limiting amplifier A0 outputs to the corresponding rectifier input end at a multiple of unit gain, and then the rectifier converts it into a corresponding current. It can be seen that the limiting amplifiers A0 in the attenuation stage are all unit limiting amplifiers with an amplification factor of 1, and the attenuation circuit B0 can be a passive attenuation network.

[0021] Finally, the attenuation stage + amplifier stage complete the conversion from -50dBm to 30dBm together and splice to get the final output signal. In this example, each stage corresponds to a dynamic range of 10dBm, so the gain of each stage in the amplifier stage and attenuation stage is required to be 10dB and -10dB. In the attenuation stage, except for the first limiting amplifier A0, the remaining stages are attenuated by 10dB through the attenuation circuit B0, and each limiting amplifier A0 is a unit gain.

[0022] Alternatively, in the attenuation stage, the gain of the first limiting amplifier A0 is 0dB (corresponding to an amplification factor of 1), and the gain of each subsequent attenuation circuit B0 + the gain of the limiting amplifier A0 = -10dB. That is, the structure of the limiting amplifier A0 in the attenuation stage can be kept consistent, and the gain is 0dB. In this way, only the attenuation circuit B0 needs to be designed.

[0023] In summary, in the above scheme, the first-stage limiting amplifier A0 in the attenuation stage of the signal envelope detection circuit directly receives the input signal V IN , without passing through the attenuation circuit B0, the reason is to achieve complete splicing of the current.

[0024] Specifically, in the signal envelope detection circuit with attenuation stage, the amplification factor of each limiting amplifier A1 in the amplification stage is uniform A1 (A1 is greater than 1), and the first stage in the attenuation stage is a unit gain limiting amplifier, that is, the amplification factor of the first limiting amplifier A0 is A0=1, and then it is attenuated step by step through the attenuation circuit B0, and after attenuation, it is still output to the rectifier through a unit gain limiting amplifier A0. When the input signal of the rectifier enters its linear region, it will begin to respond to the output of the corresponding current, and finally the output current of all rectifiers can be spliced ​​into a complete logarithmic curve corresponding to different signal power values. It can be understood that increasing the number of limiting amplifiers in the amplification stage can expand the lower limit of the dynamic range of the detector, and increasing the number of limiting amplifiers in the attenuation stage can expand the upper limit of the dynamic range of the detector.

[0025] The structures of the limiting amplifier A1 in the amplification stage and the limiting amplifier A0 in the attenuation stage are as follows: Figure 3 and Figure 4 As shown, the limiting amplifier A1 is composed of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a first tail current source I1; the limiting amplifier A0 is composed of a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a third transistor M3, a fourth transistor M4, and a second tail current source I2. Among them, the limiting amplifier A1 and the limiting amplifier A0 can both have a double-ended input and a double-ended output, V IN+ Represents its positive input signal, V IN- Represents its inverting input signal, V OUT+ Represents its positive phase output signal, V OUT- represents its inverted output signal, and the first tail current source I1 and the second tail current source I2 are used to provide tail current. Wherein, each transistor can be a BJT tube.

[0026] Combination Figure 3 and Figure 4 As shown in the figure, the limiting amplifier A0 has the same structure as the limiting amplifier A1, that is, the circuit topology, the types and quantities of components, and the connection relationship between the components are the same, but the resistance value, current and other parameters are changed to form different gains (the swing amplitude remains the same). At the same time, for easy distinction, Figure 3 and Figure 4 The device numbers are different.

[0027] The limiting values ​​of the limiting amplifier A1 and the limiting amplifier A0 are achieved by keeping the tail current and the load resistance (i.e., the resistance connected to the collector of each BJT tube: the first resistor R1 and the second resistor R2, the fifth resistor R5 and the sixth resistor R6) consistent, and the difference in gain between the two is mainly achieved by changing the resistance of the negative feedback resistor (i.e., the fourth resistor R3 and the fourth resistor R4, the seventh resistor R7 and the eighth resistor R8) connected to the emitter stage of each BJT tube.

[0028] Based on the previous example, Figure 5 shows the rectifier output current (I DET , unit is A) with the input power (Pin, unit is dBm) of the signal envelope detection circuit, where the solid line is the output of the 5 amplification stage rectifiers and the dotted line is the output of the 3 attenuation stage rectifiers; Figure 6 The figure shows the comparison diagram of the corresponding ideal logarithmic curve and the actual logarithmic curve, where the horizontal axis is the input power (Pin, in dBm) of the signal envelope detection circuit and the vertical axis is the output voltage (V DET , unit is V); Figure 7 A schematic diagram comparing the corresponding ideal logarithmic curve error and the actual logarithmic curve error is shown, wherein the horizontal axis is the input power (Pin, in dBm) of the signal envelope detection circuit, and the vertical axis is the dB linear error after the output of the signal envelope detection circuit is subtracted from the ideal output, in dB.

[0029] The inventors have found that due to the different gains of the amplifiers used in the attenuation stage and the amplification stage, the linearity of the two amplifiers is different. Generally, the smaller the gain of an amplifier, the better the linearity, and the larger the gain, the worse the linearity. Therefore, the linearity of the attenuation stage is significantly better than that of the amplification stage. Better linearity will be reflected in the fact that the amplifier can still maintain a gain similar to that of a small signal when the signal is large, which cannot be maintained when the linearity is poor. Therefore, the limiting amplifier of the attenuation stage can still maintain a large gain when the input power Pin is large, so that the current slope of the rectifier output is still relatively large; conversely, the amplifier of the amplification stage cannot maintain a high gain when the input power Pin is large. Therefore, if Figure 5 As shown, the output current slope of the rectifier in the amplification stage will be lower than that of the rectifier in the attenuation stage, and the final spliced ​​shape will appear as follows Figure 5 The depression shown. Figure 5 The depression in the signal envelope detection circuit causes the logarithmic curve and logarithmic curve error to be Figure 6 and Figure 7 As shown, there is a big difference from the ideal state.

[0030] For example, in the above-mentioned logarithmic envelope detection circuit with attenuation stage, the attenuation stage and the amplifier stage use limiting amplifiers with different gains (same swing). Although the rectifier input voltage shows a step-by-step A1 relationship on small signals, due to the difference in linearity between the attenuation stage and the amplifier stage limiting amplifiers on large signals (usually the larger the gain, the worse the linearity), there will be a splicing depression phenomenon. This ultimately leads to a large logarithmic error in the actual logarithmic curve, reducing the accuracy of signal detection.

[0031] In order to expand the dynamic range of the signal envelope detection circuit, ensure the accuracy of signal detection, and avoid the occurrence of depressions in current splicing, the embodiment of the present disclosure also provides a signal envelope detection circuit. Figure 8 As shown, the signal envelope detection circuit 10 includes: N cascaded first amplifier circuits 101, the input end of the first amplifier circuit 101 of the first stage is used to receive the target input signal, and the input ends of the second to Nth first amplifier circuits 101 of the second stage to the Nth stage are used to receive the output signal of the first amplifier circuit 101 of the previous stage; M cascaded attenuation circuits 102, the input end of the first attenuation circuit 102 is used to receive the target input signal, and the input ends of the second to Mth attenuation circuits 102 are used to receive the output signal of the previous attenuation circuit 102; M second amplifier circuits 103, the input end of each second amplifier circuit 103 is connected to the output end of the corresponding attenuation circuit 102; wherein each second amplifier circuit 103 may correspond to one attenuation circuit 102; A plurality of rectifiers 104, wherein the output end of each first amplifying circuit 101 and the output end of each second amplifying circuit 103 are connected to the input end of the corresponding rectifier 104; the output ends of all rectifiers 104 are connected together to output a target output signal; wherein each first amplifying circuit 101 may correspond to one rectifier 104, and each second amplifying circuit 103 may correspond to one rectifier 104; Wherein, N and M are both integers greater than 1; the amplification factors of the first amplifying circuit 101 and the second amplifying circuit 103 are the same.

[0032] It should be noted that if Figure 8 As shown, only one serial number 101 is shown, and the first-stage first amplifier circuit 101 is recorded as the first amplifier circuit 1, the second-stage first amplifier circuit 101 is recorded as the first amplifier circuit 2, ..., the Nth-stage first amplifier circuit 101 is recorded as the first amplifier circuit N, and the output signals of the first amplifier circuits 101 are recorded as V p1 、V p2 、V p3 ,……,V pN Only one serial number 102 is shown, and the first attenuation circuit 102 is recorded as attenuation circuit 1, the second attenuation circuit 102 is recorded as attenuation circuit 2, ..., the Mth attenuation circuit 102 is recorded as attenuation circuit M, and the output signals of the attenuation circuits 102 are recorded as V att1 、V att2 、V att3 ,……,V attMOnly one serial number 103 is shown, and the first-stage second amplifier circuit 103 is recorded as the second amplifier circuit 1, the second-stage second amplifier circuit 103 is recorded as the second amplifier circuit 2, ..., the M-th-stage second amplifier circuit 103 is recorded as the second amplifier circuit M, and the output signals of the second amplifier circuits 103 are recorded as V n1 、V n2 、V n3 ,……,V nM .

[0033] It should also be noted that, in order to distinguish from the input signal and output signal of the internal components of the circuit, the entire input signal of the signal envelope detection circuit 10 is recorded as the target input signal, and the entire output signal is recorded as the target output signal.

[0034] In this example, the output end of each first amplifier circuit 101 is connected to a rectifier 104. In other examples, the input end of the first-stage first amplifier circuit 101 may also be connected to a rectifier 104, which is not specifically limited. Figure 8 The signal envelope detection circuit 10 shown includes N+M rectifiers 104 (only two serial numbers 104 are shown), N first amplifying circuits 101 and the connected N rectifiers 104 form an amplifying stage, and the N rectifiers 104 in the amplifying stage are sequentially recorded as rectifier 1, rectifier 2, ..., rectifier N; M second amplifying circuits 103 and the connected M attenuation circuits 102, M rectifiers 104 (rectifier N+1 to rectifier N+M) form an attenuation stage.

[0035] Here, the first amplifier circuit 101 and the second amplifier circuit 103 are both limiting amplifiers. The limiting amplifier amplifies the received signal and limits the amplitude of the output signal to a fixed value, so it is called a limiting amplifier, that is, the function of the limiting amplifier is to amplify the signal by a certain multiple, and the swing amplitude will be subject to a fixed limit. The main function of the rectifier 104 is to convert the step-by-step output signal (AC voltage) of the limiting amplifier into a DC current, and has the characteristic that the output current and the amplitude of its own input voltage are in a logarithmic relationship, that is, the main function of the rectifier is to convert the AC voltage into a DC current output.

[0036] It should also be noted that in the embodiment of the present disclosure, the amplification factors of the N first amplifying circuits 101 and the M second amplifying circuits 103 are equal, that is, the gains are equal, and the swing amplitudes of the N first amplifying circuits 101 and the M second amplifying circuits 103 are also equal, so that the output current slopes of all rectifiers are equal, thereby avoiding the problem of uneven splicing of the output current of the rectifier 104; avoiding the situation where the splicing appears concave or protruding due to the unequal amplification factors of each amplifier circuit.

[0037] At the same time, an attenuation circuit 102 is connected before the first second amplifier circuit 103 to attenuate the signal to offset the amplification factor of the second amplifier circuit 103, so that the output of the first second amplifier circuit 103 can fall within the dynamic range of the rectifier N+1, ensuring the integrity of the splicing.

[0038] Since the amplifier circuits (the first amplifier circuit 101 and the second amplifier circuit 103) of the attenuation stage and the amplifier stage in the embodiment of the present disclosure both use exactly the same amplification factor (i.e., the same gain), and each second amplifier circuit 103 in the attenuation stage is connected to an attenuation circuit 102, each second amplifier circuit 103 receives an attenuated signal, which is then amplified and given to the rectifier 104. Therefore, in the case of a high-power input signal, although the output of the amplifier stage reaches saturation, the signal can be first attenuated by the attenuation circuit 102 at the attenuation stage, and then converted by the second amplifier circuit 103 and the rectifier 104 to achieve logarithmic conversion; further, since the attenuation circuit 102 basically does not affect the linearity, and the gains of the first amplifier circuit 101 and the second amplifier circuit 103 are the same, the linearity of the first amplifier circuit 101 and the second amplifier circuit 103 are the same, so that the output linearity of the rectifier 104 of the amplifier stage and the attenuation stage is basically consistent, which improves the deviation due to the gain difference and improves the detection accuracy.

[0039] In some embodiments, the amplification factors of the first amplifying circuit 101 and the second amplifying circuit 103 are both A1, and the amplification factor of the attenuation circuit 102 is 1 / A1; wherein A1 is greater than 1.

[0040] It should be noted that, in the disclosed embodiment, the amplification factors A1 of the first amplifier circuit 101 and the second amplifier circuit 103 are both greater than 1, that is, the first amplifier circuit 101 and the second amplifier circuit 103 are not unit gain amplifiers, but have a practical amplification effect on the signal. At the same time, in order to ensure that effective detection can be performed even when a large signal is input, the input signal of each stage of the second amplifier circuit 103 is attenuated via the attenuation circuit 102 connected to its input end, and the high-power signal is attenuated to the dynamic range of the second amplifier circuit 103, so that detection can be successfully achieved.

[0041] It should also be noted that, in order to better perform splicing, the amplification factor of each attenuation circuit is 1 / A1. Thus, in the signal envelope detection circuit 10 (or logarithmic envelope detection circuit) with attenuation stage provided in the embodiment of the present disclosure, the amplification factor of each first amplifier circuit 101 in the amplifier stage is uniformly A1, and the input end of each second amplifier circuit 103 in the attenuation stage is connected to the attenuation circuit 102, that is, the input end of the first second amplifier circuit 103 is also connected to the attenuation circuit 102, rather than directly receiving the target input signal, in the attenuation stage, each stage is first attenuated by A1 times step by step (that is, the amplification factor B0 of the attenuation circuit 102 is B0=1 / A1, because A1 is greater than 1, and thus 1 / A1 is less than 1, attenuation is achieved), and after attenuation, it is output to the rectifier 104 through a limiting amplifier with an amplification factor of A1 (that is, the second amplifier circuit 103, which is consistent with the first amplifier circuit 101 in the amplifier stage). Finally, the voltage signal before each rectifier 104 can be realized to present a gain relationship of A1 times, that is, (with V p3 For example): V p3 =A1V p2 =A1 2 V p1 =A1 3 V n1 =A1 4 V n2 =A1 5 V n3 When the input signal of the rectifier 104 enters its linear region, it will start to respond and output the corresponding current. Finally, the output currents of all rectifiers can be spliced ​​into a complete logarithmic curve corresponding to different signal power values.

[0042] Assume that the input dynamic range of the signal envelope detection circuit is 80dBm (-50dBm~30dBm), the working range of the rectifier is 0~10dBm, the amplifier stage includes 5 first amplifier circuits 101, the dynamic range of each first amplifier circuit 101 is 10dBm, the dynamic range of the amplifier stage is 50dBm (-50dBm~0dBm), and the gain of each stage is 10dB; the first first amplifier circuit 101 of the first stage amplifies -10~0dBm to 0dBm~10dBm, and the corresponding rectifier 104 can output the corresponding current; the first first amplifier circuit 101 of the first stage and the second first amplifier circuit 101 of the second stage amplify -10~0dBm to 0dBm~10dBm. The first amplifier circuit 101 of the first stage to the third stage amplifies -30dBm~-20dBm to 0~10dBm, and the corresponding rectifier 104 can output the corresponding current; the first amplifier circuit 101 of the first stage to the fourth stage amplifies -40dBm~-30dBm to 0~10dBm, and the corresponding rectifier 104 can output the corresponding current; the first amplifier circuit 101 of the first stage to the fifth stage amplifies -50dBm~-40dBm to 0~10dBm, and the corresponding rectifier 104 can output the corresponding current.

[0043] When the input dynamic range is 0dBm~30dBm, it exceeds the dynamic range of the amplifier stage, so after the attenuation circuit 102 attenuates the input signal, it falls within the dynamic range of the attenuation stage. Assume that the attenuation stage includes three second amplifier circuits 103, and correspondingly, also includes three attenuation circuits B0 and three rectifiers 104; the first-stage attenuation circuit 102 attenuates 0dBm~10dBm to -10dBm~0dBm, the first-stage second amplifier circuit 102 amplifies it to 0dBm~10dBm, and then the rectifier 104 converts it into a corresponding current; the first-stage attenuation circuit 102 and the second-stage attenuation circuit 102 convert 10dBm~20dBm to -10dBm~0dBm. Bm is attenuated to -10dBm~0dBm, the second-stage second amplifier circuit 102 amplifies it to 0dBm~10dBm, and then the rectifier 104 converts it into a corresponding current; the first attenuation circuit 102 to the third attenuation circuit 102 attenuates 10dBm~20dBm to -10dBm~0dBm, the third-stage second amplifier circuit 102 amplifies it to 0dBm~10dBm, and then the rectifier 104 converts it into a corresponding current. Finally, the attenuation stage + the amplifier stage jointly complete the conversion of -50dBm~30dBm, and splice to obtain the final target output signal.

[0044] In this way, since the amplification factors and swing amplitudes of the first amplifier circuit 101 and the second amplifier circuit 103 are equal, the output current slopes of all rectifiers are equal, thereby avoiding the problem of uneven splicing of the output current of the rectifier 104. In addition, the first second amplifier circuit 103 is connected to an attenuation circuit 102, which is used to attenuate the signal to offset the amplification factor of the second amplifier circuit 103, so that the output of the first second amplifier circuit 103 can fall within the dynamic range of the rectifier 104, ensuring the integrity of the splicing.

[0045] exist Figure 8 On the basis of Fig. 9 As shown, in some embodiments, each first amplifier circuit 101, each second amplifier circuit 103, and each attenuation circuit 102 has a double-ended input and a double-ended output; each rectifier 104 has a double-ended input and a single-ended output; the target input signal V IN Including the positive input signal V IN+ and the inverting input signal V IN- ; The positive phase input terminal (+) of the first stage first amplifier circuit 101 and the first input terminal of the first stage attenuation circuit 102 are both used to receive the positive phase input signal V IN+ The inverting input terminal (-) of the first amplifier circuit 101 of the first stage and the second input terminal of the first attenuation circuit 102 are both used to receive the inverting input signal V IN- ; The first input terminal of the second to Mth attenuation circuit 102 is connected to the first output terminal of the previous attenuation circuit 102; the second input terminal of the second to Mth attenuation circuit 102 is connected to the second output terminal of the previous attenuation circuit 102; The non-inverting input terminal of any second amplifier circuit 103 is connected to the first output terminal of the corresponding attenuation circuit 102 ; the inverting input terminal of any second amplifier circuit 103 is connected to the second output terminal of the corresponding attenuation circuit 102 .

[0046] It should be noted that if Fig. 9 As shown, for any first amplifier circuit 101 (denoted as the i-th stage, i is a positive integer greater than or equal to 1 and less than or equal to N), it is a differential double-ended input and output, and its output signal V pi is the output signal V at its positive phase output terminal (+) pi+ and its inverting output terminal (-) output signal V pi- difference.

[0047] For any second amplifier circuit 103 (denoted as the jth, where j is an integer greater than or equal to 1 and less than or equal to M), which is a differential double-ended input and output, attenuation circuits 1 to j convert the positive phase input signal V IN+ Attenuates to the first attenuated signal Vattj+ , the inverting input signal V IN- Attenuates to the second attenuated signal V attj- , the input signal V of the second amplifier circuit j attj is the first attenuated signal V attj+ With the second attenuation signal V attj- The output signal V of the second amplifier circuit j is nj is the output signal V at its positive phase output terminal (+) nj+ The output signal V nj- difference.

[0048] like Fig. 9 As shown, the logarithmic detection circuit 10 may also include a load resistor R DET , used to convert the current signal output by all rectifiers into a voltage signal as the target output signal V DET Furthermore, filters, buffers, output resistors, etc. may be connected behind all rectifiers to filter and enhance the drive of the target output signal, so as to obtain an output signal with a frequency within a suitable range and strong drive capability.

[0049] exist Fig. 9 On the basis of Fig.10 As shown, in some embodiments, the attenuation circuit 102 includes a first sub-attenuation circuit s1 and a second sub-attenuation circuit s2; wherein the input end of the first sub-attenuation circuit s1 serves as the first input end of the attenuation circuit 102, and the output end of the first sub-attenuation circuit s1 serves as the first output end of the attenuation circuit 102; the input end of the second sub-attenuation circuit s2 serves as the second input end of the attenuation circuit 102, and the output end of the second sub-attenuation circuit s2 serves as the second output end of the attenuation circuit 102; In the first-stage attenuation circuit 102, the first sub-attenuation circuit s1 is connected in series between the non-inverting input terminal of the first-stage second amplifier circuit 103 and the non-inverting input signal V IN+ The second sub-attenuation circuit s2 is connected in series between the inverting input terminal of the first-stage second amplifier circuit 103 and the inverting input signal V IN- between; In the 2nd to Mth attenuation circuits 102 , the first sub-attenuation circuit s1 is connected in series between the non-inverting input terminals of two adjacent second amplifying circuits 103 , and the second sub-attenuation circuit s2 is connected in series between the inverting input terminals of two adjacent second amplifying circuits 103 .

[0050] It should be noted that the target input signal V IN Including the positive input signal V IN+ and the inverting input signal V IN- Correspondingly, the M first sub-attenuation circuits s1 form a positive phase attenuation link for the positive phase input signal VIN+ The M second sub-attenuation circuits s2 form an inverting attenuation link for attenuating the inverting input signal V IN- The attenuation is performed step by step. The amplification factor of each first sub-attenuation circuit s1 and each second sub-attenuation circuit s2 is 1 / A1.

[0051] Furthermore, in the embodiment of the present disclosure, each sub-attenuation circuit may be of a capacitive type or a resistive type. Fig.11 As shown, the first sub-attenuation circuit s1 and the second sub-attenuation circuit s2 are both resistors.

[0052] It should be noted that if Fig.11 As shown, for the resistance type attenuation circuit, the first sub-attenuation circuit s1 in the attenuation circuit 1 to the attenuation circuit M is respectively recorded as the resistor R11 to the resistor RM1, and the second sub-attenuation circuit s2 in the attenuation circuit 1 to the attenuation circuit M is respectively recorded as the resistor R12 to the resistor RM2. The resistance ratio of each level of resistance is designed according to the required attenuation multiple.

[0053] Taking the attenuation circuit 1 as an example, the first end of the resistor R11 serves as the input end of the first sub-attenuation circuit s1, and the second end of the resistor R11 serves as the output end of the first sub-attenuation circuit s1; the first end of the resistor R12 serves as the input end of the second sub-attenuation circuit s2, and the second end of the resistor R12 serves as the output end of the second sub-attenuation circuit s2.

[0054] It should also be noted that if Fig.11 As shown, in addition to the 2×M resistors, resistors R(M+1)1 and R(M+1)2 are also included, wherein the first end of resistor R(M+1)1 is connected to the second end of resistor RM1, the first end of resistor R(M+1)2 is connected to the second end of resistor RM2, and the second end of resistor R(M+1)1 is connected to the second end of resistor R(M+1)2, so as to ensure that the output common mode voltage of each level in the attenuation stage is consistent. In other words, for the positive phase attenuation link (resistor R11~resistor RM1) or the reverse phase attenuation link (resistor R12~resistor RM2), the voltage is divided by M+1 levels of resistors connected in series, and the number of resistors in the link is one more than the number of attenuation circuits, so that attenuation can be formed. The resistance ratio of resistors R(M+1)1 and resistor R(M+1)2 and each resistor in the attenuation circuit is designed according to the attenuation multiple required for each level.

[0055] In this way, the resistor-based attenuation circuit (or attenuator) can achieve step-by-step attenuation of A1 times, and then amplification of A1 times, so that the voltage signal before each rectifier can present a gain relationship of A1 times, that is, V p3 =A1V p2 =A1 2 V p1 =A13 V n1 =A1 4 V n2 =A1 5 V n3 At the same time, since the attenuation circuit has little effect on the linearity, the linearity of the rectifier input signal in the attenuation stage is mainly affected by the limiting amplifier. Since the same limiting amplifier is used in the amplification stage and the attenuation stage, the linearity can be kept consistent.

[0056] like Fig.12 As shown, the first sub-attenuation circuit s1 and the second sub-attenuation circuit s2 are both capacitors, and the signal envelope detection circuit 10 also includes M first bias circuits 105, each of which is connected to the input end of the corresponding second amplifier circuit 103 to provide a bias voltage for the second amplifier circuit 103.

[0057] It should be noted that if Fig.12 As shown, for the capacitive attenuation circuit, the first sub-attenuation circuit s1 in the attenuation circuit 1 to the attenuation circuit M is recorded as capacitors C11 to CM1, respectively, and the second sub-attenuation circuit s2 in the attenuation circuit 1 to the attenuation circuit M is recorded as capacitors C12 to CM2, respectively. The capacitance ratio of all capacitors is designed according to the attenuation multiple required for each stage.

[0058] Taking the attenuation circuit 1 as an example, the first end of the capacitor C11 serves as the input end of the first sub-attenuation circuit s1, and the second end of the capacitor C11 serves as the output end of the first sub-attenuation circuit s1; the first end of the capacitor C12 serves as the input end of the second sub-attenuation circuit s2, and the second end of the capacitor C12 serves as the output end of the second sub-attenuation circuit s2.

[0059] It should also be noted that if Fig.12 As shown, in addition to the 2×M capacitors, capacitor C(M+1)1 and capacitor C(M+1)2 are also included, wherein the first end of capacitor C(M+1)1 is connected to the second end of capacitor CM1, the first end of capacitor C(M+1)2 is connected to the second end of capacitor CM2, and the second end of capacitor C(M+1)1 and the second end of capacitor C(M+1)2 are connected or both grounded. In other words, for the positive phase attenuation link (capacitor C11~capacitor CM1) or the reverse phase attenuation link (capacitor C12~capacitor CM2), the voltage is divided by M+1 levels of capacitors connected in series, and the number of capacitors in the link is one more than the number of attenuation circuits, so that attenuation can be formed. The capacitance ratio of capacitor C(M+1)1 and capacitor C(M+1)2 and each capacitor in the attenuation circuit is designed according to the attenuation multiple required for each level.

[0060] In this way, the capacitor-based attenuation circuit can achieve step-by-step attenuation of A1 times, and then amplification of A1 times, so that the voltage signal before each rectifier can present a gain relationship of A1 times, that is, Vp3=A1Vp2=A12Vp1=A13Vn1=A14Vn2=A15Vn3. At the same time, since the attenuation circuit basically does not affect the linearity, the linearity of the rectifier input signal in the attenuation stage is mainly affected by the limiting amplifier. Since the same limiting amplifier is used in the amplification stage and the attenuation stage, the linearity can be kept consistent.

[0061] It should also be noted that if Fig.12 As shown in FIG. 1 , for a capacitive attenuation circuit, a first bias circuit 105 needs to be provided at the input end of each second amplifier circuit 103 to provide an input bias for the second amplifier circuit 103. For a resistive attenuation circuit, as shown in FIG. Fig.11 As shown, the resistor can act as a bias circuit, and no additional bias circuit is required.

[0062] For the second amplifier circuit 103 with dual-end input, Fig.12 As shown, the first bias circuit 105 includes a first sub-bias circuit b1 and a second sub-bias circuit b2; The first sub-bias circuit b1 is connected to the non-inverting input terminal of the second amplifier circuit 103; The second sub-bias circuit b2 is connected to the inverting input terminal of the second amplifier circuit 103 .

[0063] It should be noted that, taking the first bias circuit 105 connected to the second amplifier circuit 1 as an example, the first sub-bias circuit b1 is used to provide a positive phase bias for the second amplifier circuit 1, and the second sub-bias circuit b2 is used to provide a negative phase bias for the second amplifier circuit 1. The first sub-bias circuit b1 and the second sub-bias circuit b2 can both be resistors. The first end of the first sub-bias circuit b1 is connected to the positive phase bias voltage V CM1 , the second end is connected to the non-inverting input end of the second amplifier circuit 1; the first end of the second sub-bias circuit b2 is connected to the reverse bias voltage V CM2 , the second end is connected to the inverting input end of the second amplifier circuit 1.

[0064] It should also be noted that the positive bias voltage V CM1 and reverse bias voltage V CM2 It can be set according to actual needs, and there is no limitation on its specific value; the positive phase bias voltage V CM1 and reverse bias voltage V CM2 It is also set according to the needs, and may be the same or different, and there is no specific limitation on this.

[0065] In this way, the bias voltage is connected by a resistor to provide a bias for the second amplifier circuit 103, thereby ensuring that the second amplifier circuit 103 works normally.

[0066] Further, such as Fig.11 or Fig.12 As shown, the signal envelope detection circuit 10 may further include a second bias circuit 106 for providing a bias voltage for the first amplifier circuit 101 of the first stage. For the first amplifier circuit 101 with double-ended input, the second bias circuit 106 includes a third sub-bias circuit b3 and a fourth sub-bias circuit b4; The third sub-bias circuit b3 is connected to the non-inverting input terminal of the first-stage first amplifier circuit 101; The fourth sub-bias circuit b4 is connected to the inverting input terminal of the first-stage first amplifier circuit 101 .

[0067] It should be noted that the third sub-bias circuit b3 is used to provide a positive phase bias for the first stage first amplifier circuit 1, and the fourth sub-bias circuit b4 is used to provide a negative phase bias for the first stage first amplifier circuit 1. The third sub-bias circuit b3 and the fourth sub-bias circuit b4 can both be resistors. The first end of the third sub-bias circuit b3 is connected to the positive phase bias voltage V CM3 , the second end is connected to the non-inverting input end of the first amplifier circuit 1 of the first stage; the first end of the fourth sub-bias circuit b4 is connected to the reverse bias voltage V CM4 , and the second end is connected to the inverting input end of the first amplifier circuit 1 of the first stage. Among them, the positive phase bias voltage V CM3 and reverse bias voltage V CM4 It can be set according to actual needs, and there is no limitation on its specific value.

[0068] In this way, the bias voltage is connected by resistors to provide bias for the first-stage first amplifier circuit 101, thereby ensuring the normal operation of the amplifier circuit link.

[0069] It should also be noted that, in the embodiment of the present disclosure, the first amplifier circuit 101 and the second amplifier circuit 103 have the same structure. That is, the first amplifier circuit 101 and the second amplifier circuit 103 are both limiting amplifiers, which have the same structure and the same amplification factor. That is, each first amplifier circuit 101 and each second amplifier circuit 103 are actually exactly the same amplifiers (ignoring the inevitable differences caused by process reasons), and their circuit topology, types and quantities of devices, connection relationships between devices are the same, and the parameters of the devices are completely consistent, except that they are located in the attenuation stage and the amplification stage respectively. Their structures can refer to the aforementioned Figure 3 or Figure 4 ,by Figure 3As shown in the figure, the limiting amplifier (i.e., the first amplifier circuit 101 / the second amplifier circuit 103) includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor M1, a second transistor M2, and a first tail current source I1; V IN+ Represents the positive-phase input signal of the limiting amplifier, V IN- represents the inverting input signal of the limiting amplifier, V OUT+ Represents the positive phase output signal of the limiting amplifier, V OUT- represents the inverted output signal of the limiting amplifier; First ends of the first resistor R1 and the second resistor R2 both receive a power supply voltage VDD; The base of the first transistor M1 serves as the positive input terminal of the limiting amplifier; the base of the second transistor M2 serves as the negative input terminal of the limiting amplifier; The second end of the first resistor R1 and the collector of the first transistor M1 are connected as the inverting output end of the limiting amplifier; the second end of the second resistor R2 and the collector of the second transistor M2 are connected as the non-inverting output end of the limiting amplifier; A first end of the third resistor R3 is connected to the emitter of the first transistor M1; A first end of the fourth resistor R4 is connected to the emitter of the second transistor M2; The second end of the third resistor R3 and the second end of the fourth resistor R4 are both connected to the first end of the first tail current source I1; A second terminal of the first tail current source I1 is grounded.

[0070] It should be noted that, in the limiting amplifier, each resistor is optional, that is, the limiting amplifier may not include resistors or only include a part of the resistors, which is specifically related to the gain requirement of the limiting amplifier.

[0071] The structure of the rectifier 104 can be referred to Fig.13 ,like Fig.13 As shown, the rectifier includes a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11', a fifth transistor M5, a sixth transistor M6 and a seventh transistor M7; V IN+ represents the positive phase input signal directly received by the first amplifier circuit 101 / the second amplifier circuit 103 / to which the rectifier is connected, V IN- Indicates the inverting input signal directly received by the first amplifier circuit 101 / the second amplifier circuit 103 / to which the rectifier is connected, I OUT Represents the output signal (current signal) of the rectifier; The first end of the ninth resistor R9 and the base of the fifth transistor M5 are connected as the first input end (or the positive input end) of the rectifier; the first end of the tenth resistor R10 and the base of the sixth transistor M6 are connected as the second input end (or the negative input end) of the rectifier; The second end of the ninth resistor R9, the second end of the tenth resistor R10, and the base of the seventh transistor M7 are connected; The first end of the eleventh resistor R11' receives the supply voltage VDD; the second end of the eleventh resistor R11' is connected to the collector of the seventh transistor M7; the emitter of the fifth transistor M5, the emitter of the sixth transistor M6, and the emitter of the seventh transistor M7 are all connected to the first end of the third tail current source I3; A second end of the third tail current source I3 is grounded; The collector of the fifth transistor M5 and the collector of the sixth transistor M6 are connected as the output end of the rectifier, and the output signal is a current signal I OUT .

[0072] It should be noted that the first transistor M1 to the seventh transistor M7 involved here can all be BJT transistors. The first tail current source I1 to the third tail current source I3 are used to provide tail current.

[0073] Based on the above Figure 8~Figure 13 The logarithmic envelope detection circuit provided takes 5 amplification stages and 3 attenuation stages as an example. Fig.14 shows a schematic diagram of the output current of the corresponding rectifier; Fig.15 Schematic diagram for comparing the corresponding ideal logarithmic curve and the actual logarithmic curve; Fig.16 Schematic diagram for comparing the corresponding ideal logarithmic curve error and the actual logarithmic curve error.

[0074] and Figure 5 In comparison, Fig.14 In the example, since the gain of the amplifiers in the attenuation stage and the amplification stage is the same, the slope of the rectifier output current is the same, and the notch is significantly improved when spliced. Figure 6 In comparison, Fig.15 In the example, the actual logarithmic curve is close to the ideal logarithmic curve; Figure 7 In comparison, Fig.16 In the figure, the actual logarithmic curve error is close to the ideal logarithmic curve error.

[0075] In summary, the embodiments of the present disclosure propose a large dynamic signal envelope detection circuit architecture, which uses the same limiting amplifier for the attenuation stage and the amplification stage to ensure that the step-by-step gain, swing amplitude, and linearity of the attenuation stage and the amplification stage are consistent, thereby solving the key problem of logarithmic error caused by uneven splicing of the rectifier curves of the amplification stage and the attenuation stage, improving the detection accuracy, and ultimately enabling the detection circuit to effectively widen the dynamic range.

[0076] In another embodiment of the present disclosure, a logarithmic envelope detection chip is provided. The logarithmic envelope detection chip includes the logarithmic envelope detection circuit 10 described in any one of the aforementioned embodiments.

[0077] Thus, since the logarithmic envelope detection circuit 10 is a logarithmic envelope detection circuit with an attenuation stage, and the attenuation stage and the amplification stage thereof use limiting amplifiers with the same gain, swing, and linearity, and the attenuation circuit in the attenuation stage basically does not affect the linearity, the rectifier input voltage presents a step-by-step A1-fold relationship for both small and large signals. Finally, as mentioned above, Figure 14~Figure 16 As shown, the splicing of the amplification stage and the attenuation stage does not cause a concave phenomenon, but maintains the splicing shape in the amplification stage, so that the actual logarithmic curve does not produce additional logarithmic errors due to the splicing, thereby improving the detection accuracy.

[0078] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0079] It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0080] The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

[0081] The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0082] The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0083] The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0084] The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure.

Claims

1. A signal envelope detection circuit, characterized in that: include: N cascaded first amplifier circuits, the input end of the first amplifier circuit of the first stage is used to receive the target input signal, and the input ends of the first amplifier circuits of the second to Nth stages are used to receive the output signal of the first amplifier circuit of the previous stage; M cascaded attenuation circuits, the input end of the attenuation circuit of the first stage is used to receive the target input signal, and the input ends of the attenuation circuits of the second to Mth stages are used to receive the output signal of the attenuation circuit of the previous stage; M second amplifying circuits, wherein an input end of each of the second amplifying circuits is connected to an output end of a corresponding attenuation circuit; A plurality of rectifiers, wherein the output end of each of the first amplifying circuits is connected to the input end of the corresponding rectifier, and the output end of each of the second amplifying circuits is connected to the input end of the corresponding rectifier; the output ends of all the rectifiers are connected together to output a target output signal; Wherein, N and M are both integers greater than 1; and the amplification factors of the first amplifying circuit and the second amplifying circuit are the same.

2. The signal envelope detection circuit according to claim 1, characterized in that: The amplification factors of the first amplifying circuit and the second amplifying circuit are both A1, and the amplification factor of the attenuation circuit is 1 / A1.

3. The signal envelope detection circuit according to claim 2, characterized in that: A1 is greater than 1.

4. The signal envelope detection circuit according to claim 1, characterized in that: Each of the first amplifying circuits, each of the second amplifying circuits, and each of the attenuating circuits has a double-ended input and a double-ended output; each of the rectifiers has a double-ended input and a single-ended output; the target input signal includes a positive-phase input signal and a negative-phase input signal; The non-phase input terminal of the first amplifier circuit of the first stage and the first input terminal of the attenuation circuit of the first stage are both used to receive the non-phase input signal; the inverting input terminal of the first amplifier circuit of the first stage and the second input terminal of the attenuation circuit of the first stage are both used to receive the inverting input signal; The first input end of the attenuation circuit of the second to Mth stages is connected to the first output end of the attenuation circuit of the previous stage; the second input end of the attenuation circuit of the second to Mth stages is connected to the second output end of the attenuation circuit of the previous stage; The non-inverting input terminal of any second amplifier circuit is connected to the first output terminal of the corresponding attenuation circuit; the inverting input terminal of any second amplifier circuit is connected to the second output terminal of the corresponding attenuation circuit.

5. The signal envelope detection circuit according to claim 4, characterized in that: The attenuation circuit comprises a first sub-attenuation circuit and a second sub-attenuation circuit; In the attenuation circuit of the first stage, the first sub-attenuation circuit is connected in series between the non-phase input terminal of the second amplifier circuit of the first stage and the non-phase input signal, and the second sub-attenuation circuit is connected in series between the inverting input terminal of the second amplifier circuit of the first stage and the inverting input signal; In the attenuation circuits of the 2nd to Mth stages, the first sub-attenuation circuit is connected in series between the non-inverting input terminals of the second amplifier circuits of two adjacent stages, and the second sub-attenuation circuit is connected in series between the inverting input terminals of the second amplifier circuits of two adjacent stages.

6. The signal envelope detection circuit according to claim 5, characterized in that: The first sub-attenuation circuit and the second sub-attenuation circuit are both resistors.

7. The signal envelope detection circuit according to claim 5, characterized in that: The first sub-attenuation circuit and the second sub-attenuation circuit are both capacitors. The signal envelope detection circuit also includes M first bias circuits. Each of the first bias circuits is connected to the input end of the corresponding second amplifier circuit to provide a bias voltage for the second amplifier circuit.

8. The signal envelope detection circuit according to claim 7, characterized in that: The first bias circuit includes a first sub-bias circuit and a second sub-bias circuit; The first sub-bias circuit is connected to the non-inverting input terminal of the second amplifier circuit; The second sub-bias circuit is connected to the inverting input terminal of the second amplifier circuit.

9. The signal envelope detection circuit according to any one of claims 1 to 8, characterized in that: The first amplifier circuit and the second amplifier circuit have the same structure.

10. The signal envelope detection circuit according to any one of claims 1 to 8, characterized in that: The first amplifying circuit and the second amplifying circuit are both limiting amplifiers.

11. A signal envelope detection chip, characterized in that: The method comprises the signal envelope detection circuit as claimed in any one of claims 1 to 10.

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