Instruction sequence generation method for verifying floating point operation of processor

Abstract

The invention relates to the technical field of processor design and test, and discloses an instruction sequence generation method for verifying floating point operation of a processor, which comprises the following steps: constructing a floating point test coverage model, generating a floating point test database, and constructing a basic RISC-V instruction sequence generator; adding a register updating mechanism bound with a memory on the basis of the basic instruction RISC-V sequence generator, and generating initialized data of the memory; and injecting the generated instruction machine code and the memory initialization data into the memory of the processor to be verified for simulation, and comparing the execution track obtained by simulation with the execution track of the instruction set simulator to find potential errors in the processor. According to the method, an efficient coverage model is constructed to generate representative floating point test data, a floating point data path of the processor can be verified more comprehensively, the defects of an existing method in the aspect of floating points in the RISC-V instruction generation process are overcome, and potential design defects in the processor are found.

Description

Technical Field

[0001] The invention belongs to the technical field of processor design and testing, and in particular relates to a method for generating an instruction sequence for verifying a processor floating-point operation. Background Art

[0002] With the development of integrated circuit technology and the continuous evolution of modern processor architecture, the complexity of processors, as the core and key components of modern computer systems, is increasing dramatically. This complexity places higher demands on the functional verification of processors, especially in the verification of floating-point units. Since floating-point operations have special data encoding formats and complex calculation processes, they are prone to various boundary conditions and potential errors. Therefore, ensuring the correctness and reliability of floating-point operations is a key task in processor design and verification.

[0003] At present, processor verification mainly adopts simulation-based verification methods. This method usually uses an instruction set simulator as a reference model, inputs the instruction sequence used for verification into the instruction set simulator and the processor to be tested, and compares the execution results of the two to find potential errors. The verification efficiency of this method depends largely on the quality and diversity of the input instruction sequence. Therefore, generating high-quality and high-coverage instruction sequences has become one of the core technologies of verification. In order to solve the problem of instruction sequence generation, random instruction sequence generation technology has been widely studied.

[0004] As an open source reduced instruction set architecture, RISC-V has been widely used in industry and academia for its modular design features. The RISC-V instruction set architecture consists of a basic instruction set and several optional extended instruction sets. The extended instruction sets for floating-point operations mainly include F extension (single precision), D extension (double precision) and Q extension (quadruple precision). At present, for the verification of RISC-V, the commonly used instruction sequence generators include RISC-V DV, RISC-V Torture, etc., which use constrained random generation methods to generate instruction sequences in assembly format. However, these RISC-V instruction sequence generators have certain limitations in terms of floating points. They often only perform constrained randomness at the floating-point instruction level, and usually only initialize floating-point registers to special values ​​in terms of floating-point data. There is a lack of further control during the instruction generation process, which leads to insufficient coverage of floating-point data functions. In addition, there are few verification methods specifically for the floating-point operation unit of the RISC-V instruction set in existing patents. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a method for generating an instruction sequence for verifying a processor's floating-point operation, so as to perform efficient and comprehensive verification on the processor's floating-point data path.

[0006] In order to solve the above technical problems, the present invention provides a method for generating an instruction sequence for comprehensively verifying the floating-point operation of a processor, including the following specific processes:

[0007] S1. Build a floating-point test coverage model and generate a floating-point test database;

[0008] S2, build a basic RISC-V instruction sequence generator;

[0009] S3. Add a memory-bound register update mechanism based on the basic instruction RISC-V sequence generator to generate memory initialization data;

[0010] S4. Inject the generated instruction machine code and memory initialization data into the memory of the processor to be verified for simulation, and compare the execution trace obtained by the simulation with the execution trace of the instruction set simulator to find out potential errors in the processor.

[0011] As an improvement of the instruction sequence generation method for comprehensively verifying the floating-point operation of the processor of the present invention:

[0012] The method for constructing a floating-point test coverage model and generating a floating-point test database is as follows:

[0013] The floating-point test coverage model includes the coverage model of floating-point data and the coverage model of floating-point operation characteristics. The coverage model of floating-point data is to first classify the floating-point data according to the basic type and boundary value, and then generate all possible combinations of floating-point data types for the input and output operands of each floating-point operation, and each combination is a verification task; the coverage model of floating-point operation characteristics is a verification task built for the boundary conditions of floating-point operation rounding and overflow, underflow and other boundary conditions;

[0014] The representative floating-point tests obtained by solving the constraints of the verification task of the floating-point test coverage model constitute a floating-point test database.

[0015] As a further improvement of the instruction sequence generation method for comprehensively verifying the floating-point operation of the processor of the present invention:

[0016] The method for constructing a basic RISC-V instruction sequence generator is:

[0017] First, the RISC-V instructions are modeled, and instruction sequences are generated based on the templates input by the user. Then, each generated instruction is sent to the instruction set simulator for simulation, and the state information in the model is updated according to the instruction simulation results. After the obtained execution trajectory is fed back to the instruction sequence generator, the state information is updated.

[0018] The basic RISC-V instruction sequence generator will output instruction machine code and execution traces simulated by the instruction set simulator.

[0019] As a further improvement of the instruction sequence generation method for comprehensively verifying the floating-point operation of the processor of the present invention:

[0020] The method for adding a memory-bound register update mechanism is:

[0021] Step S3.1: After each instruction in the basic RISC-V instruction sequence generator is generated, register update detection is performed;

[0022] Step S3.2: After detecting that the floating-point register update mechanism needs to be triggered, randomly select a floating-point register to be updated; for each floating-point register to be updated, insert a flw instruction, each flw instruction corresponds to a section of unused memory and a floating-point register to be updated; after generating each flw instruction for floating-point register update, the generator records the binding information of the floating-point register and the memory address;

[0023] Step S3.3, continue to generate the instruction sequence, when the source register of the generated instruction is selected as a floating point register, perform floating point test selection, including instruction-independent floating point test and instruction-dependent floating point test;

[0024] Step S3.4, instruction operand selection: for each source register selected for floating-point test, a bound floating-point register is selected from the binding relationship between the floating-point register and the memory address as the source register; if the source register for the floating-point test is not selected, a source register is randomly selected according to the method of the basic instruction sequence generator;

[0025] Step S3.5, update the data in the memory and registers in the simulator, after determining the source register and the corresponding floating-point test information, it is necessary to directly update the values ​​in the registers and bound memory addresses corresponding to each updated floating-point test data in the instruction set simulator to the corresponding values;

[0026] Step S3.6, output memory initialization information and update the generator status. After each instruction executes the above steps, output the bound memory address and floating-point value corresponding to the updated source register as memory initialization information; at the same time, delete the updated register from the floating-point register and memory binding list, and record the floating-point registers in the source register and destination register of the instruction into the used register list, waiting for subsequent updates.

[0027] As a further improvement of the instruction sequence generation method for comprehensively verifying the floating-point operation of the processor of the present invention:

[0028] The instruction-independent floating-point test selects floating-point values ​​from the types of the coverage model of the floating-point data for updating for some floating-point source registers;

[0029] The instruction-related floating-point test is to select a floating-point test from the floating-point test database, and all floating-point source registers need to be updated to corresponding floating-point values ​​in the floating-point test.

[0030] The beneficial effects of the present invention are mainly reflected in:

[0031] The present invention constructs an efficient coverage model to generate representative floating-point test data, and uses a memory-bound register update mechanism to combine floating-point testing with instruction generation. Compared with the existing RISC-V instruction sequence generation method, it achieves comprehensive coverage of floating-point operation data types, and can perform more comprehensive verification of the floating-point data path of the processor, so as to overcome the shortcomings of the existing methods in the floating-point aspect during the RISC-V instruction generation process and discover potential design defects in the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The specific implementation modes of the present invention are further described in detail below with reference to the accompanying drawings.

[0033] Figure 1 A flowchart of a method for generating an instruction sequence for verifying a floating-point operation of a processor according to the present invention;

[0034] Figure 2 Flowchart of the memory-bound register update mechanism. DETAILED DESCRIPTION

[0035] The present invention is further described below in conjunction with specific embodiments, but the protection scope of the present invention is not limited thereto:

[0036] Embodiment 1: A method for generating an instruction sequence for verifying a processor floating point operation, such as Figure 1 As shown, an efficient coverage model and a memory-bound register update mechanism are introduced, and floating-point data are combined with the instruction sequence generation process to generate a floating-point instruction sequence that can achieve comprehensive coverage of floating-point data types, thereby efficiently and comprehensively verifying the floating-point data path of the processor, in order to overcome the shortcomings of existing methods in floating-point aspects during the RISC-V instruction generation process.

[0037] Step 1: Build a floating-point test coverage model and generate a floating-point test database.

[0038] Corresponding coverage models are built for the 11 floating-point operations of addition (fadd.s), subtraction (fsub.s), multiplication (fmul.s), division (fdiv.s), square root (fsqrt.s), maximum value (fmax.s), minimum value (fmin.s), multiplication and addition (fmadd.s, fnmadd.s, fmsub.s, fnmsub.s) in the RV32F extended instruction set, and the five rounding modes (RNE, RTZ, RDN, RUP, RMM). There are two types of coverage models for each operation:

[0039] The first category is the coverage model for floating-point data. For each floating-point operand of floating-point operations, its type can be divided into 17 categories according to the basic type and boundary value, so as to cover all floating-point types and boundaries during verification. These 17 types of floating-point data are shown in Table 1, namely ±0, ±denormalized number and its boundary, ±normalized number and its boundary, ±infinity and non-number.

[0040] Table 1. Types of floating-point data

[0041]

[0042]

[0043] According to the IEEE 754 standard, the binary encoding of floating-point numbers consists of three parts: the sign bit, the exponent field, and the mantissa field. For a 32-bit single-precision floating-point number, the lengths of these three parts are 1, 8, and 23, respectively. The different values ​​of these three parts determine the type of the floating-point number. Table 1 shows the encoding range of these 17 floating-point types in the case of binary floating-point encoding. The coverage model for floating-point data takes all type combinations of the input and output operands of floating-point operations as a verification task. For example, for single-precision floating-point addition operations, there are 2 input operands and 1 output operand, a total of 3 operands. Each operand has the above 17 types, so there are 17 type combinations under each rounding mode. 3 =4913, but in the actual operation process, the possible combinations are far less than this number. The SMT solver is used to solve the floating-point tests of all possible combinations and store them in the floating-point test database, thus obtaining a representative floating-point test for floating-point data.

[0044] The second type of coverage model is a coverage model for floating-point operation characteristics, which mainly constructs verification tasks for the boundary conditions of rounding and overflow, underflow, etc. When solving, it is achieved by constraining the intermediate results. Each floating-point operation that needs to be rounded will have an intermediate result, which is regarded as having infinite precision and infinite range. After rounding it to meet the target format, the final result can be obtained. In the actual implementation process, it is impossible to obtain a value with infinite precision and infinite range, so it can be represented by a value with a wider exponent domain and a wider mantissa domain. Different floating-point operation units have different implementations of intermediate results. The exponent domain, mantissa and length can be adjusted according to the floating-point operation unit implementation of the processor to be verified. When constraining, the intermediate results are constrained to rounding boundary conditions, overflow and underflow boundary conditions, etc., and solved using the SMT solver, and the corresponding floating-point tests can be obtained to build a floating-point test database.

[0045] Step 2: Build a basic RISC-V instruction sequence generator

[0046] The basic RISC-V instruction sequence generator adopts a model-based test generation method to separate the instruction set architecture model from the instruction generation. First, it is necessary to build a corresponding architecture model for the instruction set to be generated, including instruction type, instruction encoding format, instruction operand type, etc. When generating instructions, it is necessary to enter a test template, which describes the number of instructions to be generated and the instructions to be generated. The basic RISC-V instruction sequence generator will randomly generate floating-point instruction sequences according to requirements and subject to constraints. Then, after each instruction is generated, it will be sent to the instruction set simulator for simulation. After the execution trajectory is fed back to the instruction sequence generator, the status information (including program counter value, register value, instruction history data, etc.) is updated to guide the subsequent instructions to be generated in compliance.

[0047] The basic RISC-V instruction sequence generator will output instruction machine code and execution traces simulated by the instruction set simulator.

[0048] Step 3: Add a memory-bound register update mechanism based on the basic RISC-V instruction sequence generator

[0049] The memory-bound register update mechanism is used to combine the generation of floating-point test data with the generation of floating-point instruction sequences. Only one flw instruction can be used to update the value in a floating-point register. At the same time, the floating-point register update instruction is separated from the floating-point data selection, and the updated value is not determined until it is used. Furthermore, after adding the memory-bound register update mechanism, the instruction generation process is as follows Figure 2 As shown, the specific steps are as follows:

[0050] Step 3.1: After each instruction is generated, register update detection is performed. For the RV32F extended instruction set, there are 32 32-bit floating-point registers. As the number of floating-point registers used as source registers or destination registers in the previous instruction generation process increases, the probability of triggering the register update mechanism also gradually increases.

[0051] Step 3.2: After the register update mechanism is triggered, a portion of the used registers is randomly selected as the floating-point registers to be updated. After the floating-point registers to be updated are selected, a floating-point register update instruction sequence needs to be generated, and each floating-point register to be updated corresponds to a flw instruction. For example, a flw f20,1732 (x21) instruction is used to update the floating-point register f20. At the same time, this instruction corresponds to an uninitialized memory 1732 (x21). Through this instruction, the floating-point register can be bound to the corresponding memory and recorded in the floating-point register-memory address binding list of the generator. Each instruction in the floating-point register update instruction sequence also needs to be simulated using an instruction set simulator. However, since the updated register and the corresponding memory initialization value are not determined until the subsequent use process, the value of the destination register in the execution trajectory during the simulation and the value in the memory are not the real values, and are not used for the generator state update and execution trajectory comparison. If the register update mechanism is not triggered, jump directly to step 3.3 for normal instruction generation.

[0052] Step 3.3: Continue to generate instruction sequence

[0053] When generating each instruction, the instruction selection must be performed first. If the source register of the generated instruction is a floating-point register, a floating-point test selection must be performed. There are two types of floating-point tests selected here, namely instruction-independent floating-point tests and instruction-dependent floating-point tests. For instruction-independent floating-point tests, the specific semantics of the instruction are not taken into account, but some floating-point source registers are randomly selected from 17 basic types, and these special floating-point values ​​are used as their updated values. For instruction-dependent floating-point tests, the 11 floating-point operation instructions in RV32F are mainly targeted. It is necessary to select from the floating-point test database in step 1 according to the specific semantics of the instruction. The value of each floating-point source register in the instruction will be updated to the corresponding floating-point value in the selected floating-point test. At the same time, it should be noted that the selection of the floating-point test is not triggered every time. In order to ensure that the register dependency between instructions can be covered normally, an activation probability can be set to control the probability of the selector being triggered. If the source register of the generated instruction is not a floating-point register, there is no need to select a floating-point test, and the instruction operand selection in step 3.4 is performed directly.

[0054] Step 3.4, instruction operand selection

[0055] If the source register of the instruction is a floating-point register, the source register of the instruction needs to be selected according to the selected floating-point test. For each operand selected with a floating-point test, such as the corresponding floating-point source register that needs to be updated to a special value in the instruction-independent floating-point test and all the corresponding floating-point source registers in the instruction-dependent floating-point test, one needs to be selected from the register-memory address binding list as the source register. If the operand does not have a corresponding floating-point test or the source register is not a floating-point register, constrained random selection is performed according to the method in the basic instruction sequencer.

[0056] Step 3.5: Update the data in the memory and registers in the simulator

[0057] Since the floating-point register update instruction sequence generated in step 3.2 is only used to bind the register to the memory, the memory initialization value and the register value are not determined. For each operand in the instruction that selects the floating-point test, the selected register, the bound memory address, and the selected floating-point test data can be obtained. Only at this time can the memory value and the floating-point register update value corresponding to the previous flw instruction be determined. At this time, the corresponding register and memory initialization values ​​in the simulator need to be updated to the corresponding floating-point test values ​​so that the simulator can obtain the correct execution trajectory after simulation. For operands that do not select floating-point tests, skip this step. For example, in step 3.3, the fmul.s instruction in the RV32F extended instruction set is selected. In step 3.4, according to the semantics of the instruction, a floating-point test (op1=0xb5f98400op2=0x879c4000res=0x001dee64) is selected from the floating-point test database. From the floating-point test, the values ​​0xb5f98400 and 0x879c4000 that need to be updated in the two source registers of the instruction can be obtained. Therefore, two registers bound by the register update instruction sequence need to be selected. For example, the first source register selects f20 bound in step 3.2. At this time, the register in the simulator and its bound memory need to be updated to the required value 0xb5f98400, and the other source register is also operated similarly.

[0058] Step 3.6: Output memory initialization value and update generator status

[0059] After the above steps 3.2 to 3.5, a complete register update process is completed. After updating the registers and bound memory values ​​in the simulator in step 3.5, it is necessary to output the corresponding memory address and the memory initialization value to be stored in the address, that is, the floating-point test value corresponding to the operand. In this way, the correct execution trajectory of the processor can be obtained during the simulation process after the memory initialization value is injected into the actual processor memory. Next, the generated instruction is simulated to obtain the correct simulation execution trajectory, and the state of the generator is updated according to the execution trajectory. For operands that use floating-point tests, when updating the generator state, the corresponding registers need to be deleted from the register-memory address binding list, and the used memory address needs to be recorded as already used to prevent the binding relationship from being used again and causing errors.

[0060] Step 3.7, repeat the above steps until the number of generated instructions reaches the requirement, and then end the generation. Finally, the generated instruction sequence, the instruction execution trace simulated by the simulator, and the memory initialization information are obtained.

[0061] Step 4: Inject the instruction machine code generated by the instruction sequence generator and the memory initialization information generated by the register update mechanism directly into the memory of the processor to be verified for simulation. The execution trace of the processor obtained by simulation is compared with the execution trace obtained by the simulator during the generation process of the instruction sequence generator. If there is any inconsistency, further analysis is performed to find out the potential errors in the processor.

[0062] experiment:

[0063] In order to verify the beneficial results of the present invention, the instruction sequence generation method for verifying the floating-point operation of the processor of the present invention is applied to the verification of the CV32E40P open source processor, and the instruction sequence generated by Example 1 is compared with the advanced RISC-V instruction sequence generator RISCV-DV [1] for comparison.

[0064] In the experiment, the method of the present invention was used to generate 24 instruction sequences in the RISC-V RV32F instruction set except for the memory access instruction, and compared with the floating-point arithmetic test instruction sequence generated by RISCV-DV, and the coverage information related to the floating-point instruction was collected using the functional coverage model of RISCV-DV. The experimental results show that the generation method of the present invention achieves a maximum coverage of 98.34% when generating about 2500 instructions, while RISCV-DV achieves a maximum coverage of 94.86% when generating about 7500 instructions. The method has a relative improvement of 3.67% in terms of functional coverage, and the number of instructions required to achieve the maximum coverage of RISCV-DV is reduced by 66.67%.

[0065] In addition, the present invention achieves more comprehensive coverage of floating-point types in instruction write-back data. For instructions in the RV32F instruction set where both the source register and the destination register are floating-point registers, 5,000 sets of valid data are obtained using the method in the present invention and RISCV-DV. The experimental results show that the coverage rate of floating-point types written back by the method in the present invention reaches 100%, while RISCV-DV does not cover most of the boundary values ​​in the floating-point data type.

[0066] In order to verify the effectiveness of the present invention in actual processor verification, five representative floating-point related errors were injected into the open source processor CV32E40P, including floating-point instruction decoding, floating-point operations, rounding mode, exception flags, and errors related to intermediate results. The experimental results show that the present method successfully detects representative floating-point related errors injected into the CV32E40P processor, proving its effectiveness in identifying potential problems of the processor.

[0067] Finally, it should be noted that the above examples are only some specific embodiments of the present invention. Obviously, the present invention is not limited to the above embodiments, and there are many variations. All variations that can be directly derived or associated with the content disclosed by a person skilled in the art should be considered as the protection scope of the present invention.

[0068] References

[0069] [1]Google,Random Instruction Generator for RISC-V ProcessorVerification.[Online].Available:

[0070] https: / / github.com / google / riscv-dv .

Claims

1. A method for generating an instruction sequence for verifying a processor floating-point operation, characterized in that The specific process includes: S1. Build a floating-point test coverage model and generate a floating-point test database; S2, build a basic RISC-V instruction sequence generator; S3. Add a memory-bound register update mechanism based on the basic instruction RISC-V sequence generator to generate memory initialization data; S4. Inject the generated instruction machine code and memory initialization data into the memory of the processor to be verified for simulation, and compare the execution trace obtained by the simulation with the execution trace of the instruction set simulator to find out potential errors in the processor.

2. The method for generating an instruction sequence for fully verifying processor floating-point operations according to claim 1, characterized in that: The method for constructing a floating-point test coverage model and generating a floating-point test database is as follows: The floating-point test coverage model includes the coverage model of floating-point data and the coverage model of floating-point operation characteristics. The coverage model of floating-point data is to first classify the floating-point data according to the basic type and boundary value, and then generate all possible combinations of floating-point data types for the input and output operands of each floating-point operation, and each combination is a verification task; the coverage model of floating-point operation characteristics is a verification task built for the boundary conditions of floating-point operation rounding and overflow, underflow and other boundary conditions; The representative floating-point tests obtained by solving the constraints of the verification task of the floating-point test coverage model constitute a floating-point test database.

3. The method for generating an instruction sequence for verifying a processor floating-point operation according to claim 2, characterized in that: The method for constructing a basic RISC-V instruction sequence generator is: First, the RISC-V instructions are modeled, and instruction sequences are generated based on the templates input by the user. Then, each generated instruction is sent to the instruction set simulator for simulation, and the state information in the model is updated according to the instruction simulation results. After the obtained execution trajectory is fed back to the instruction sequence generator, the state information is updated. The basic RISC-V instruction sequence generator will output instruction machine code and execution traces simulated by the instruction set simulator.

4. The method for generating an instruction sequence for verifying a processor floating-point operation according to claim 3, characterized in that: The method for adding a memory-bound register update mechanism is: Step S3.1, after each instruction in the basic RISC-V instruction sequence generator is generated, register update detection is performed; Step S3.2: After detecting that the floating-point register update mechanism needs to be triggered, randomly select a floating-point register to be updated; for each floating-point register to be updated, insert a flw instruction, each flw instruction corresponds to a section of unused memory and a floating-point register to be updated; After generating each flw instruction for floating-point register update, the binding information between the floating-point register and the memory address is recorded in the generator; Step S3.3, continue to generate the instruction sequence, when the source register of the generated instruction is selected as a floating point register, perform floating point test selection, including instruction-independent floating point test and instruction-dependent floating point test; Step S3.4, instruction operand selection: for each source register selected for floating-point test, a bound floating-point register is selected from the binding relationship between the floating-point register and the memory address as the source register; if the source register for the floating-point test is not selected, a source register is randomly selected according to the method of the basic instruction sequence generator; Step S3.5, update the data in the memory and registers in the simulator, after determining the source register and the corresponding floating-point test information, it is necessary to directly update the values ​​in the registers and bound memory addresses corresponding to each updated floating-point test data in the instruction set simulator to the corresponding values; Step S3.6, output memory initialization information and update the generator status. After each instruction executes the above steps, output the bound memory address and floating-point value corresponding to the updated source register as memory initialization information; at the same time, delete the updated register from the floating-point register and memory binding list, and record the floating-point registers in the source register and destination register of the instruction into the used register list, waiting for subsequent updates.

5. The method for generating an instruction sequence for verifying a processor floating-point operation according to claim 4, characterized in that: The instruction-independent floating-point test selects floating-point values ​​from the types of the coverage model of the floating-point data for updating for some floating-point source registers; The instruction-related floating-point test is to select a floating-point test from the floating-point test database, and all floating-point source registers need to be updated to corresponding floating-point values ​​in the floating-point test.

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