I2C equipment verification method and device, electronic equipment and storage medium

Abstract

The invention provides an I2C equipment verification method and device, electronic equipment and a storage medium, and relates to the technical field of chip verification. The verification method of the I2C equipment comprises the following steps: acquiring a first signal sequence pair of to-be-tested I2C equipment and reference I2C equipment in a transmission process of test data; wherein the first signal sequence pair comprises a clock time sequence signal sequence on a bus on which the to-be-tested I2C equipment and the reference I2C equipment are mounted, and a data time sequence signal sequence output by a serial data line of the reference I2C equipment, and the to-be-tested I2C equipment and the reference I2C equipment are realized based on the same register conversion stage circuit; performing time sequence adjustment on at least one time sequence signal sequence in the first signal sequence pair in a protocol range supported by the to-be-tested I2C equipment to obtain a second signal sequence pair; and testing the to-be-tested I2C equipment by using the second signal sequence pair. According to the invention, the to-be-tested I2C equipment can be verified efficiently and comprehensively.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a verification method, device, electronic device and storage medium for an I2C device. Background Art

[0002] During the verification process of I2C (Inter-Integrated Circuit) devices, it is critical to ensure the correct timing behavior on SCL (serial clock line) and SDA (serial data line), which is directly related to whether the I2C module can operate normally.

[0003] Traditional verification methods usually involve building a master-slave device model or using an existing I2C device to communicate with the device under test. If the communication is successful, the timing behavior of the device under test is considered to meet the requirements. In order to perform verification, the verifier needs to write an I2C module with similar functions according to the specification, which takes a lot of time to write code. Subsequently, the code needs to be compiled, debugged, and simulated to find and correct runtime errors. This repetitive compilation and debugging process consumes a lot of time and significantly reduces verification efficiency. In addition, if a certain specification of I2C module is used to test the module under test, although communication may be successful under this specific configuration, the verification process is difficult to cover all possible communication scenarios and timing behaviors, and cannot guarantee that the module under test can communicate normally with other I2C devices of different specifications, which may cause problems in the interaction between the module under test and certain I2C devices in actual applications.

[0004] Therefore, how to efficiently and comprehensively verify the I2C device to be tested is a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of the above problems existing in the prior art, the present invention provides an I2C device verification method, apparatus, electronic device and storage medium, which are used to efficiently and comprehensively verify the I2C device to be tested.

[0006] The present invention provides a verification method for an I2C device. The method is applied in a verification environment of a register conversion level circuit and comprises the following steps.

[0007] Acquire a first signal sequence pair during the transmission process of test data of an I2C device to be tested and a reference I2C device; wherein the first signal sequence pair includes a clock timing signal sequence on a bus mounted with the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; and test the I2C device to be tested using the second signal sequence pair.

[0008] According to a verification method for an I2C device provided by the present invention, during the transmission of the test data, the I2C device to be tested is a slave device, and the reference I2C device is a master device; the step of obtaining a first signal sequence pair between the I2C device to be tested and the reference I2C device during the transmission of the test data includes: obtaining a clock timing signal sequence output by a serial clock line of the reference I2C device; obtaining a data timing signal sequence output by a serial data line of the reference I2C device; and obtaining the first signal sequence pair according to the clock timing signal sequence and the data timing signal sequence.

[0009] According to a verification method for an I2C device provided by the present invention, the timing adjustment is performed on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair, including: increasing the length of each signal of the clock timing signal sequence according to a first preset ratio; decreasing the length of each signal of the data timing signal sequence according to a second preset ratio; obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or decreasing the length of each signal of the clock timing signal sequence according to a third preset ratio; increasing the length of each signal of the data timing signal sequence according to a fourth preset ratio. degree; according to the adjusted clock timing signal sequence and the data timing signal sequence, the second signal sequence pair is obtained; or according to the fifth preset ratio, the length of each signal of the clock timing signal sequence is reduced; according to the sixth preset ratio, the length of each signal of the data timing signal sequence is reduced; according to the adjusted clock timing signal sequence and the data timing signal sequence, the second signal sequence pair is obtained; or according to the seventh preset ratio, the length of each signal of the clock timing signal sequence is expanded; according to the eighth preset ratio, the length of each signal of the data timing signal sequence is expanded; according to the adjusted clock timing signal sequence and the data timing signal sequence, the second signal sequence pair is obtained.

[0010] According to a verification method for an I2C device provided by the present invention, during the transmission of the test data, the I2C device to be tested is a master device, and the reference I2C device is a slave device; the step of obtaining a first signal sequence pair of the I2C device to be tested and the reference I2C device during the transmission of the test data includes: obtaining a clock timing signal sequence output by a serial clock line of the I2C device to be tested; obtaining a data timing signal sequence output by a serial data line of the reference I2C device; and obtaining the first signal sequence pair according to the clock timing signal sequence and the data timing signal sequence.

[0011] According to a verification method for an I2C device provided by the present invention, the timing adjustment is performed on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair, including: according to a ninth preset ratio, expanding the signal lengths of each signal of the data timing signal sequence; according to the clock timing signal sequence and the adjusted data timing signal sequence, obtaining the second signal sequence pair; or according to a tenth preset ratio, reducing the signal lengths of each signal of the data timing signal sequence; according to the clock timing signal sequence and the adjusted data timing signal sequence, obtaining the second signal sequence pair.

[0012] According to a verification method for an I2C device provided by the present invention, the use of the second signal sequence pair to test the I2C device to be tested includes: when the I2C device to be tested is a master device, instructing it to initiate transmission of the test data; and in response to the I2C device to be tested sending a start signal, inputting the clock timing signal sequence in the second signal sequence pair to the input end of the serial clock line of the I2C device to be tested, and inputting the data timing signal sequence to the input end of the serial data line of the I2C device to be tested; collecting the clock timing signal sequence of the I2C device to be tested during the data transmission process. The test result timing sequence is obtained by collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the data transmission process to obtain the test result timing sequence; the test result is determined according to the test result timing sequence; or when the I2C device to be tested is a slave device, the second signal sequence is aligned, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested; the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested in the data transmission process to obtain the test result timing sequence; the test result is determined according to the test result timing sequence.

[0013] The present invention also provides a verification device for an I2C device, comprising the following modules: A first acquisition module is used to acquire a first signal sequence pair during the transmission process of the test data between the I2C device to be tested and the reference I2C device; wherein the first signal sequence pair includes a clock timing signal sequence on the bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by the serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; a second acquisition module is used to perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; and a test module is used to test the I2C device to be tested using the second signal sequence pair.

[0014] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the verification method of any of the above-mentioned I2C devices is implemented.

[0015] The present invention also provides a non-transitory computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the verification method of the I2C device as described above is implemented.

[0016] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the verification method of any one of the above I2C devices is implemented.

[0017] The verification method, device, electronic device and storage medium of the I2C device provided by the present invention obtain the first signal sequence pair of the I2C device to be tested and the reference I2C device in the transmission process of the test data; perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within the protocol range supported by the I2C device to be tested to obtain the second signal sequence pair, thereby constructing an I2C timing that fluctuates within a certain range without requiring the verification personnel to write an I2C module with similar functions, rather than being limited to a constant timing of fixed specifications, effectively enhancing the completeness of the verification, so that the I2C device to be tested can be fully tested and verified under diversified timing conditions; using the second signal sequence pair, special fluctuations such as glitches and noise in real scenes can be simulated, thereby greatly improving the accuracy of the verification and ensuring the stability and reliability of the I2C device to be tested in practical applications. Thus, the I2C device to be tested can be verified efficiently and comprehensively. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0019] Figure 1 It is a flow chart of the verification method of the I2C device provided by the present invention.

[0020] Figure 2 This is one of the flow charts of the method for testing an I2C device to be tested by using a second signal sequence provided by the present invention.

[0021] Figure 3 This is the second flow chart of the method for testing the I2C device to be tested by using the second signal sequence provided by the present invention.

[0022] Figure 4 It is a schematic diagram of the I2C device serial port provided by the present invention.

[0023] Figure 5 This is a timing diagram of the I2C bus.

[0024] Figure 6 It is a schematic diagram of the I2C verification environment provided by the present invention.

[0025] Figure 7 It is a schematic diagram of adjusting the clock timing signal sequence and the data timing signal sequence provided by the present invention.

[0026] Figure 8 It is a schematic diagram of testing an I2C device to be tested by using a second signal sequence provided by the present invention.

[0027] Fig. 9 It is a schematic diagram of the timing of the I2C master device sending a start signal.

[0028] Fig.10 It is a structural schematic diagram of the verification device of the I2C device provided by the present invention.

[0029] Fig.11 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Combine the following Figure 1-Figure 9 The verification method of the I2C device of the present invention is described.

[0032] Figure 1 The present invention is a flowchart of a verification method for an I2C device, which is applied in a verification environment of a register conversion level circuit.

[0033] Register Transfer Level (RTL) is an important concept in digital circuit design, which focuses on the description of data transmission and logical relationships between registers. Register Transfer Level is widely used in various digital circuit designs, especially in the design of complex large-scale integrated circuits (ASICs) and field programmable gate arrays (FPGAs). In these designs, RTL-level code is the key bridge between high-level algorithm description and underlying physical implementation.

[0034] The verification environment is implemented using computer-aided design software and is a design tool used to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large scale integrated circuit (VLSI) chips. It can compile and simulate the input register transfer level (RTL) code and confirm whether the design is correct by combining waveform information analysis.

[0035] I2C (Inter-Integrated Circuit) is a serial communication bus that uses a multi-master-slave architecture. It was developed by Philips in the 1980s to allow motherboards, embedded systems or mobile phones to connect to low-speed peripheral devices.

[0036] like Figure 1 As shown, the verification method of the I2C device includes the following: Step 101: Acquire a first signal sequence pair during a transmission process of test data between an I2C device to be tested and a reference I2C device.

[0037] The I2C device to be tested and the reference I2C device are I2C devices described using a register conversion stage circuit, and both are implemented based on the same register conversion stage circuit.

[0038] I2C is a two-wire serial communication protocol. The transmission bus consists of two data lines: the serial clock line (SCL) and the serial data line (SDA). Figure 4 As shown, the I2C device implemented by the register conversion stage circuit includes a serial data line input terminal (sda_in), a serial data line output terminal (sda_o), a serial clock line input terminal (scl_in) and a serial clock line output terminal (scl_o).

[0039] I2C devices use a master-slave structure. During the communication process of multiple I2C devices, there is a master device (Master) and one or more slave devices (Slave). The master device controls the communication process, while the slave device passively accepts the control of the master device and sends and receives data. Figure 5 As shown, the following are the basic steps of I2C communication: 1. The master device sends a start signal to start communication.

[0040] 2. The master device sends a slave device address and read / write bit. The address is used to select a specific slave device, and the read / write bit is used to indicate the direction of the data (read or write).

[0041] 3. The selected slave device confirms receipt of the address and sends an acknowledge signal.

[0042] 4. The master device continues to send or receive data.

[0043] 5. After the data transmission is completed, the master device sends a stop signal to indicate the end of communication.

[0044] The first signal sequence pair includes a clock timing signal sequence on the bus on which the I2C device to be tested and the reference I2C device are mounted, and a data timing signal sequence output by the serial data line of the reference I2C device.

[0045] In the specific implementation process, you can build a verification environment such as Figure 6 In the I2C verification environment shown, the I2C device to be tested and the reference I2C device are started to transmit test data (for example, a data read operation or a data write operation), and during the transmission process, a monitoring component is used to obtain a first signal sequence pair.

[0046] In some embodiments, during the transmission of test data, the I2C device to be tested is a slave device, and the reference I2C device is a master device. In this embodiment, a clock timing signal sequence output by a serial clock line of the reference I2C device can be obtained, and a data timing signal sequence output by a serial data line of the reference I2C device can be obtained; a first signal sequence pair is obtained according to the clock timing signal sequence and the data timing signal sequence.

[0047] In some embodiments, during the transmission of test data, the I2C device to be tested is a master device, and the reference I2C device is a slave device. In this embodiment, a clock timing signal sequence output by a serial clock line of the I2C device to be tested can be obtained, and a data timing signal sequence output by a serial data line of the reference I2C device can be obtained; a first signal sequence pair is obtained according to the clock timing signal sequence and the data timing signal sequence.

[0048] In a specific implementation process, the collected first signal sequence pair can be saved in a variety of ways, for example, in the form of a waveform file, which is not limited by the description of this specification.

[0049] Step 102: Perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested to obtain a second signal sequence pair.

[0050] The I2C protocol supports multiple data transfer rates to meet the needs of different devices and applications. Standard mode is up to 100 kilobits per second, fast mode is 400 kilobits per second, and fast mode plus can even reach 1 kilobits per second.

[0051] As an example only, if the I2C device to be tested supports the standard mode, the signal sequence in the first signal sequence pair can be adjusted within a rate range of 100 kilobits per second to simulate I2C devices of different models from different manufacturers, and special fluctuations such as glitches and noise in real scenarios can also be added.

[0052] In some embodiments, during the acquisition of the first signal sequence pair, the I2C device to be tested is a slave device, and the reference I2C device is a master device. In this embodiment, the timing of the clock timing signal sequence and the data timing signal sequence in the first signal sequence pair can be adjusted in a variety of ways to obtain the second signal sequence pair.

[0053] For example, the length of each signal in the clock timing signal sequence can be enlarged according to a first preset ratio; the length of each signal in the data timing signal sequence can be reduced according to a second preset ratio; and a second signal sequence pair can be obtained based on the adjusted clock timing signal sequence and data timing signal sequence.

[0054] For another example, the length of each signal in the clock timing signal sequence can be shortened according to a third preset ratio; the length of each signal in the data timing signal sequence can be expanded according to a fourth preset ratio; and a second signal sequence pair can be obtained based on the adjusted clock timing signal sequence and data timing signal sequence.

[0055] For another example, the length of each signal in the clock timing signal sequence can be reduced according to the fifth preset ratio; the length of each signal in the data timing signal sequence can be reduced according to the sixth preset ratio; and a second signal sequence pair can be obtained based on the adjusted clock timing signal sequence and data timing signal sequence.

[0056] For another example, the length of each signal in the clock timing signal sequence may be enlarged according to the seventh preset ratio; the length of each signal in the data timing signal sequence may be enlarged according to the eighth preset ratio; and a second signal sequence pair may be obtained based on the adjusted clock timing signal sequence and data timing signal sequence.

[0057] In the specific implementation process, the values ​​of the first preset ratio, the second preset ratio, the third preset ratio, the fourth preset ratio, the fifth preset ratio, the sixth preset ratio and the seventh preset ratio can be set according to test requirements and are not limited to the description of this specification.

[0058] The above-mentioned ratio values ​​may be the same or different, and are not limited by the description of this specification.

[0059] In some embodiments, during the acquisition of the first signal sequence pair, the I2C device to be tested is a master device, and the reference I2C device is a slave device. During the I2C device communication process, the serial clock signal is sent by the master device. Therefore, in this embodiment, the timing of the data timing signal sequence in the first signal sequence pair can be adjusted in a variety of ways to obtain the second signal sequence pair.

[0060] For example, the length of each signal of the data timing signal sequence may be enlarged according to a ninth preset ratio; and a second signal sequence pair may be obtained according to the clock timing signal sequence and the adjusted data timing signal sequence.

[0061] For another example, the length of each signal in the data timing signal sequence may be reduced according to a tenth preset ratio; and a second signal sequence pair may be obtained according to the clock timing signal sequence and the adjusted data timing signal sequence.

[0062] In a specific implementation process, the values ​​of the ninth preset ratio and the tenth preset ratio may be set according to test requirements and are not limited by the description of this specification.

[0063] The above-mentioned ratio values ​​may be the same or different, and are not limited by the description of this specification.

[0064] Step 103: Use the second signal sequence pair to test the I2C device to be tested.

[0065] In the specific implementation process, Figure 8 As shown, a test bus B can be established, and the input end of the serial clock line and the input end of the serial data line of the I2C device to be tested are connected to the test bus, and the clock timing signal sequence in the second signal sequence pair is used to drive the serial clock line of the test bus, and the data timing signal sequence is used to drive the serial data line, so as to test the I2C device to be tested.

[0066] By using different second signal sequence pairs to drive the test bus B, it is equivalent to simulating I2C devices of different models and different application scenarios to test the I2C device to be tested.

[0067] For two embodiments of testing the I2C device to be tested using the second signal sequence pair, see Figure 2 and Figure 3 The relevant content in will not be repeated here.

[0068] Just as an example, Figure 7 As shown, when the length of each signal in the data timing signal sequence is proportionally reduced, and the length of each signal in the clock timing signal sequence is proportionally extended, the rising edge of the serial clock signal may change the sampling of the serial data signal, resulting in transmission failure. Therefore, using the adjusted second signal sequence pair, various potential problems of the I2C device to be tested can be conveniently and accurately tested.

[0069] Figure 2 This is one of the flow charts of the method for testing an I2C device to be tested by using a second signal sequence provided by the present invention.

[0070] In this embodiment, the I2C device to be tested is a master device, such as Figure 2 As shown, the method includes the following: Step 201: Instruct the I2C device to be tested to initiate transmission of test data.

[0071] In the specific implementation process, a specific test script or program can be written to control the I2C device to be tested to initiate data transmission.

[0072] Step 202: In response to the I2C device to be tested sending a start signal, the second signal sequence is aligned, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested.

[0073] In the specific implementation process, when the I2C device to be tested sends a start signal (such as Fig. 9 After that, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested through the test bus, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested.

[0074] Step 203: collect the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested during the current data transmission process to obtain a test result timing sequence.

[0075] Step 204: Determine the test result according to the test result timing sequence.

[0076] In a specific implementation process, it can be determined according to the test result timing sequence whether the I2C device to be tested has made a correct response during the test, thereby determining whether the I2C device to be tested has passed the test.

[0077] In the embodiment provided by the present invention, when the I2C device to be tested is a master device, it is instructed to initiate transmission of test data; and in response to the I2C device to be tested sending a start signal, the second signal sequence is centered, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested. The second signal sequence is used to simulate the timing signals output by multiple different I2C slave devices, so that rich and diverse test scenarios can be generated, so as to efficiently and comprehensively verify the I2C device to be tested as the master device.

[0078] Figure 3 This is the second flow chart of the method for testing the I2C device to be tested by using the second signal sequence provided by the present invention.

[0079] In this embodiment, the I2C device to be tested is a slave device, such as Figure 3 As shown, the method includes the following: Step 301: center the second signal sequence, input the clock timing signal sequence to the input end of the serial clock line of the I2C device to be tested, and input the data timing signal sequence to the input end of the serial data line of the I2C device to be tested.

[0080] In this step, the second signal sequence is used to simulate the timing signals output by various I2C master devices to initiate data transmission.

[0081] Step 302: Collect the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested during the current data transmission process to obtain a test result timing sequence.

[0082] Step 303: Determine the test result according to the test result timing sequence.

[0083] In a specific implementation process, it can be determined according to the test result timing sequence whether the I2C device to be tested has made a correct response during the test, thereby determining whether the I2C device to be tested has passed the test.

[0084] In the embodiment provided by the present invention, when the I2C device to be tested is a slave device, the second signal sequence is centered, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested. The second signal sequence is used to simulate the timing signals output by a variety of different I2C master devices, thereby generating rich and diverse test scenarios, so as to efficiently and comprehensively verify the I2C device to be tested as a slave device.

[0085] The verification device of the I2C device provided by the present invention is described below. The verification device of the I2C device described below and the verification method of the I2C device described above can be referred to each other.

[0086] Fig.10 : is a schematic diagram of the structure of the verification device of the I2C device provided by the present invention, such as Fig.10 As shown, the device 1000 includes the following modules.

[0087] The first acquisition module 1010 is used to acquire a first signal sequence pair during the transmission process of the test data of the I2C device to be tested and the reference I2C device; wherein the first signal sequence pair includes a clock timing signal sequence on the bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by the serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit.

[0088] The second acquisition module 1020 is configured to perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested, to obtain a second signal sequence pair.

[0089] The testing module 1030 is configured to test the I2C device to be tested by using the second signal sequence pair.

[0090] Fig.11 An example of a physical structure diagram of an electronic device is shown in FIG. Fig.11As shown, the electronic device may include: a processor (processor) 1110 , a communication interface (Communications Interface) 1120 , a memory (memory) 1130 and a communication bus 1140 , wherein the processor 1110 , the communication interface 1120 , and the memory 1130 communicate with each other via the communication bus 1140 . The processor 1110 can call the logic instructions in the memory 1130 to execute the verification method of the I2C device, which includes: obtaining a first signal sequence pair of the I2C device to be tested and the reference I2C device during the transmission process of test data; wherein the first signal sequence pair includes a clock timing signal sequence on the bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by the serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; for at least one timing signal sequence in the first signal sequence pair, timing adjustment is performed within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; and the I2C device to be tested is tested using the second signal sequence pair.

[0091] In addition, the logic instructions in the above-mentioned memory 1130 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when it is sold or used as an independent product. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0092] On the other hand, the present invention also provides a computer program product, which includes a computer program, which can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the I2C device verification method provided by the above methods, the method including: obtaining a first signal sequence pair of the I2C device to be tested and the reference I2C device during the transmission process of test data; wherein the first signal sequence pair includes a clock timing signal sequence on a bus mounted with the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; for at least one timing signal sequence in the first signal sequence pair, timing adjustment is performed within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; and the I2C device to be tested is tested using the second signal sequence pair.

[0093] On the other hand, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented when the processor executes the verification method of the I2C device provided by the above methods, the method comprising: obtaining a first signal sequence pair of the I2C device to be tested and the reference I2C device during the transmission process of test data; wherein the first signal sequence pair includes a clock timing signal sequence on a bus mounted with the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; for at least one timing signal sequence in the first signal sequence pair, timing adjustment is performed within the protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; and the I2C device to be tested is tested using the second signal sequence pair.

[0094] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Those of ordinary skill in the art may understand and implement it without creative effort.

[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0096] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A verification method for an I2C device, characterized in that: The method is applied in a verification environment of a register conversion stage circuit, and the method comprises: Acquire a first signal sequence pair during the transmission process of the test data of the I2C device to be tested and the reference I2C device; wherein the first signal sequence pair includes a clock timing signal sequence on the bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by the serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; Performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested to obtain a second signal sequence pair; The I2C device to be tested is tested using the second signal sequence pair.

2. The verification method of the I2C device according to claim 1, characterized in that: During the transmission of the test data, the I2C device to be tested is a slave device, and the reference I2C device is a master device; The step of obtaining a first signal sequence pair between the I2C device to be tested and the reference I2C device during the transmission process of the test data comprises: Obtaining a clock timing signal sequence output by a serial clock line of the reference I2C device; Acquire a data timing signal sequence output by a serial data line of the reference I2C device; The first signal sequence pair is obtained according to the clock timing signal sequence and the data timing signal sequence.

3. The verification method of the I2C device according to claim 2, characterized in that: The step of performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested to obtain a second signal sequence pair includes: According to a first preset ratio, enlarging the length of each signal of the clock timing signal sequence; According to a second preset ratio, shortening the length of each signal of the data timing signal sequence; Obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or According to a third preset ratio, shortening the length of each signal of the clock timing signal sequence; According to a fourth preset ratio, enlarging the length of each signal of the data timing signal sequence; Obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or According to a fifth preset ratio, shortening the length of each signal of the clock timing signal sequence; According to a sixth preset ratio, shortening the length of each signal of the data timing signal sequence; Obtaining the second signal sequence pair according to the adjusted clock timing signal sequence and the data timing signal sequence; or According to a seventh preset ratio, increasing the length of each signal of the clock timing signal sequence; According to an eighth preset ratio, enlarging the length of each signal of the data timing signal sequence; The second signal sequence pair is obtained according to the adjusted clock timing signal sequence and the data timing signal sequence.

4. The verification method of the I2C device according to claim 1, characterized in that: During the transmission of the test data, the I2C device to be tested is a master device, and the reference I2C device is a slave device; The step of obtaining a first signal sequence pair between the I2C device to be tested and the reference I2C device during the transmission process of the test data comprises: Obtaining a clock timing signal sequence output by a serial clock line of the I2C device to be tested; Acquire a data timing signal sequence output by a serial data line of the reference I2C device; The first signal sequence pair is obtained according to the clock timing signal sequence and the data timing signal sequence.

5. The verification method of the I2C device according to claim 4, characterized in that: The step of performing timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested to obtain a second signal sequence pair includes: According to a ninth preset ratio, enlarging the length of each signal of the data timing signal sequence; Obtaining the second signal sequence pair according to the clock timing signal sequence and the adjusted data timing signal sequence; or According to a tenth preset ratio, shortening the length of each signal of the data timing signal sequence; The second signal sequence pair is obtained according to the clock timing signal sequence and the adjusted data timing signal sequence.

6. The verification method of the I2C device according to any one of claims 1 to 5, characterized in that: The step of testing the I2C device to be tested by using the second signal sequence pair includes: In case that the I2C device to be tested is a master device, instructing it to initiate transmission of the test data; and In response to the I2C device to be tested sending a start signal, the second signal sequence is aligned, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested; Collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested during the data transmission process to obtain a test result timing sequence; Determine the test result according to the test result timing sequence; or In the case where the I2C device to be tested is a slave device, the second signal sequence is centered, the clock timing signal sequence is input to the input end of the serial clock line of the I2C device to be tested, and the data timing signal sequence is input to the input end of the serial data line of the I2C device to be tested; Collecting the clock timing signal sequence and the data timing signal sequence of the I2C device to be tested during the data transmission process to obtain a test result timing sequence; The test result is determined according to the test result timing sequence.

7. A verification device for an I2C device, characterized in that: The device is arranged in a verification environment of a register conversion stage circuit, and the device comprises: A first acquisition module is used to acquire a first signal sequence pair during the transmission process of the I2C device to be tested and the reference I2C device for test data; wherein the first signal sequence pair includes a clock timing signal sequence on a bus mounted by the I2C device to be tested and the reference I2C device, and a data timing signal sequence output by a serial data line of the reference I2C device, and the I2C device to be tested and the reference I2C device are implemented based on the same register conversion stage circuit; A second acquisition module, configured to perform timing adjustment on at least one timing signal sequence in the first signal sequence pair within a protocol range supported by the I2C device to be tested, to obtain a second signal sequence pair; The testing module is used to test the I2C device to be tested by using the second signal sequence pair.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the verification method of the I2C device according to any one of claims 1 to 6 is implemented.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the verification method of the I2C device according to any one of claims 1 to 6 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the verification method of the I2C device according to any one of claims 1 to 6 is implemented.

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