Heterogeneous information processing microsystem for space compact sighting telescope

Abstract

The invention provides a heterogeneous information processing microsystem for a space compact sighting telescope, which is integrated in a single package by adopting a microsystem integration process: a data processing module used for data calculation processing and algorithm implementation; the multi-element mixed storage module is used for providing large-capacity storage space support for starting and running of the microsystem; and the information interaction interface module is used for information interaction inside and outside the microsystem, and has abundant and flexible communication modes such as interfaces or buses and the like. The system has the advantages of high integration level, high performance, flexible interaction mode, high reliability and the like, and can meet the requirements of miniaturization and informatization of future observation and aiming equipment.

Description

Technical Field

[0001] The invention relates to a heterogeneous information processing microsystem for space compact aiming equipment, belonging to the technical field of computer microelectronics. Background Art

[0002] The lightweight and information processing level of the new generation of sights have become the determining factors for improving the integration of autonomous target detection, identification and tracking functions. The existing sight system has insufficient information processing capabilities and only has the traditional "sighting and viewing" function. It is highly dependent on back-end computing and is difficult to get rid of the "man in the loop" situation information analysis and processing mode; it is not miniaturized enough and uses discrete device board-level solutions with low integration and difficulty in miniaturization. The separation of software and hardware leads to a slow information closure, and the redundancy of functions leads to insufficient energy utilization, which is inconsistent with the low power consumption resources of typical unmanned equipment; it is not universal enough, and the compatibility between traditional sight information processing system platforms is poor, resulting in a long development cycle and high cost. Therefore, there is an urgent need for a space-compact sight information processing microsystem that is lighter, smaller, more accurate, and less integrated. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide a heterogeneous information processing microsystem for space compact aiming devices, which has the characteristics of universality, strong information processing capability, high integration and small area through the integrated design of data processing modules, multi-hybrid storage modules and information interaction interface modules.

[0004] The technical solution of the present invention is: a heterogeneous information processing microsystem for space compact aiming, including: a data processing module, a multi-hybrid storage module, and an information interaction interface module, each module is integrated in a single package, wherein:

[0005] The data processing module receives and preprocesses external data to realize communication protocol conversion; uses the adaptation algorithm to process the preprocessed data to realize the corresponding functions. The resulting data can be converted through the communication protocol and transmitted to other external systems;

[0006] The multi-hybrid storage module provides flexible storage space for data processing module code loading and execution, meeting the storage capacity requirements for microsystem power-on startup and normal operation;

[0007] The information interaction interface module provides an information interaction interface between external data and the microsystem according to the information interaction requirements inside and outside the microsystem, and provides an internal information interaction interface for the microsystem within the data processing module and between the data processing module and the multi-hybrid storage module.

[0008] Preferably, the structural composition and data transmission process of the data processing module, the multi-hybrid storage module, and the information interaction interface module are as follows:

[0009] The data processing module includes a programmable logic storage unit and a processor;

[0010] The multi-hybrid storage module includes internal SRAM storage unit, internal FLASH storage unit, SDRAM memory, parallel NOR FLASH memory, SPI FLASH memory, PROM memory, and SMC external storage interface unit;

[0011] The information interaction interface module includes: a digital interface unit, an analog interface unit, and an extended interface unit, wherein the digital interface unit includes: serial port, CAN, SPI, I2C, Ethernet, 1553B, GPIO, SMC bus, four-way differential line driver, four-way differential line receiver; the analog interface unit includes: ADC, DAC;

[0012] The programmable logic storage unit of the data processing module and the processor transmit information through the SMC bus of the information interaction interface module;

[0013] The programmable logic storage unit in the data processing module is started by the code stream stored in the PROM memory of the multi-hybrid storage module; the processor in the data processing module is started by implementing a multiple backup startup scheme through the internal FLASH storage unit, SPI FLASH memory or parallel NOR FLASH memory of the multi-hybrid storage module;

[0014] The data transmission between the processor in the data processing module and the SDRAM memory and the parallel NOR FLASH memory in the multi-hybrid storage module is realized through the SMC bus, and the processor in the data processing module transmits data to the SPI FLASH memory in the multi-hybrid storage module through the SPI unit;

[0015] After the microsystem is started, the internal SRAM storage unit and SDRAM memory in the multi-hybrid storage module provide code execution or data storage space for the processor in the data processing module, the internal FLASH storage unit, parallel NOR FLASH memory, and SPI FLASH memory provide code execution space for the processor in the data processing module, and the SMC external storage interface unit provides additional extended storage resources for the microsystem;

[0016] External instructions and data are transmitted to the programmable logic storage unit in the data processing module through the digital interface unit or the extended interface unit; external instructions and data can be transmitted to the processor in the data processing module through the digital interface unit or the analog interface unit; result instructions and data are transmitted from the processor in the data processing module to other systems outside the microsystem through the digital interface unit or the analog interface unit, and can also be transmitted from the programmable logic storage unit in the data processing module to other systems outside the microsystem through the digital interface unit or the extended interface unit.

[0017] Preferably, the bare chips in each module are arranged on a multi-layer plastic substrate through a wire bonding process to achieve electrical connection, and conduct heat to the plastic package housing through conductive adhesive.

[0018] Preferably, when the sheet is placed on a plastic substrate:

[0019] The SDRAM memory bare chip, the parallel NOR FLASH memory bare chip and the SPIFLASH memory bare chip in the multi-hybrid storage module are directly adjacent to the processor bare chip in the data processing module, and the adjacent distance range with the processor bare chip is 2.5mm to 7.5mm;

[0020] The PROM memory bare chip in the multi-hybrid storage module is directly adjacent to the programmable logic unit bare chip in the data processing module, and the adjacent distance range is 3.5mm to 4.0mm;

[0021] The bare chip in the information interaction interface module is arranged at the package edge of the plastic substrate.

[0022] Preferably, the programmable logic unit bare chip in the data processing module, the SDRAM memory bare chip in the multi-hybrid storage module and the parallel NOR FLASH memory bare chip are placed in a straight line from top to bottom on the plastic substrate, and the processor bare chip in the data processing module is arranged in the vertical direction of the bottom of the straight line. The above four bare chips are placed in an L shape on the plastic substrate.

[0023] Preferably, the programmable logic unit bare chip and processor bare chip in the data processing module, the SDRAM memory bare chip in the multi-hybrid storage module, and the parallel NOR FLASH memory bare chip, each bare chip's own data buses are designed to be of equal length, and each bare chip's own address bus and control bus are designed to be of equal length.

[0024] Preferably, the discrete ground signals of all bare chips in the microsystem are combined to form a complete ground plane.

[0025] Preferably, the plastic substrate of the microsystem is preset to have a specified number of layers and is disposed in a packaging shell.

[0026] Compared with the prior art, the present invention has the following advantages:

[0027] (1) The present invention provides a heterogeneous information processing microsystem for space compact aiming equipment. The microsystem architecture has the advantages of high integration, high performance, flexible interaction mode, high reliability, etc. through the packaging and integration design of data processing module, multi-hybrid storage module, and information interaction interface module. It can meet the needs of miniaturization, informatization, and generalization of future sighting equipment.

[0028] (2) The present invention adopts the bare core wire bonding process of each module to form an electrical connection with the multi-layer plastic package substrate and complete the pin interconnection, integrating all the components on the original single machine or circuit printed board into a single chip, greatly reducing the system volume, reducing the signal transmission distance, reducing the influence of additional parasitic parameters caused by the long interconnection wiring of the device, improving the signal integrity, and providing a guarantee for the miniaturization of the aiming system;

[0029] (3) The programmable logic resources in the present invention can realize functions such as dynamic reconstruction, storage expansion, interface expansion, high-performance parallel processing, fault-tolerant redundancy, etc., thereby improving the versatility and reliability of the sight system;

[0030] (4) The present invention adopts a programmable logic unit + processor to form a heterogeneous computing processing architecture, which has rich computing processing resources, can achieve high-performance computing processing, provide sufficient and diverse external ports, can perform multi-architecture cascading, external device control, and multiple data storage unit mounting, etc., to achieve system function expansion and performance extension, and provide sufficient information processing capabilities for the sight system

[0031] (5) The present invention adopts three non-volatile storage media, namely, internal FLASH unit, SPI FLASH memory, and parallel NOR FLASH memory, as redundant backup of the boot code, thereby ensuring the reliability of system power-off restart or system update. Through the SMC interface, the microsystem can realize external non-volatile memory or random access memory expansion, further improving the stability and compatibility of the microsystem and providing storage support for the high information processing capability of the aiming system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of the microsystem functional modules and units of the present invention;

[0033] Figure 2 It is a schematic diagram of the functional units and interactions of the microsystem of the present invention;

[0034] Figure 3 A schematic diagram of the distribution of bare chips inside the microsystem package of the present invention;

[0035] Figure 4It is a schematic diagram of the information flow of the microsystem of the present invention. DETAILED DESCRIPTION

[0036] A heterogeneous information processing microsystem for space compact aiming equipment includes a data processing module, a multi-hybrid storage module, and an information interaction interface module integrated in a single package. The bare core of each module is electrically connected to a multi-layer plastic package substrate by a wire bonding process and the pins are interconnected. The information interaction interface module is used to send and receive data or instructions. The external port introduced by the information interaction interface module can also realize multi-architecture cascading, external device control, etc. The data processing module completes calculation processing on the received data or instructions. The multi-hybrid storage module provides the data processing module with storage resources required for startup and operation. The information interaction interface module is used to realize the construction of internal interconnection links in the data processing module, thereby ensuring the feasibility and fluency of the data processing solution.

[0037] The heterogeneous information processing microsystem for space compact aiming equipment includes a data processing module, a multi-hybrid storage module, and an information interaction interface module, among which:

[0038] The data processing module receives and preprocesses external data to realize communication protocol conversion; uses the adaptation algorithm to further process the preprocessed data to obtain the final result data and realize the corresponding functions. The result data can also be converted through the communication protocol and transmitted to other external systems;

[0039] The multi-hybrid storage module provides flexible storage space for data processing module code loading and execution, meeting the storage capacity requirements for microsystem power-on startup and normal operation;

[0040] The information interaction interface module provides an information interaction interface between external data and the microsystem according to the information interaction requirements inside and outside the microsystem, and provides an internal information interaction interface for the microsystem within the data processing module, between the data processing module and the multi-hybrid storage module, etc.

[0041] The data processing module and the multi-hybrid storage module realize information exchange transmission through the digital port provided by the information exchange interface module. The bare chip in each module is arranged on a multi-layer plastic substrate through wire bonding and other processes to realize electrical connection. Heat is transferred through conductive glue and the plastic packaging shell to provide heat dissipation for the microsystem.

[0042] The SDRAM memory bare chip, parallel NOR FLASH memory bare chip and SPIFLASH memory bare chip in the multi-hybrid storage module are directly adjacent to the processor bare chip in the data processing module, and the adjacent distance range is 2.5mm to 7.5mm; the PROM memory bare chip in the multi-hybrid storage module is directly adjacent to the programmable logic unit bare chip in the data processing module, and the adjacent distance range is 3.5mm to 4.0mm, so as to shorten the signal propagation path, and the bare chip form in the information interaction interface module needs to be set at the package edge position of the plastic substrate.

[0043] Taking into account the smoothness of the data bus, address bus and control bus signal directions, the programmable logic unit bare chip in the data processing module, the SDRAM memory bare chip and parallel NOR FLASH memory bare chip in the multi-hybrid storage module, and the processor bare chip in the data processing module are arranged in an L shape on the plastic substrate in the above order.

[0044] For all bare chips in the data processing module, the SDRAM memory bare chips and the parallel NOR FLASH memory bare chips in the multi-hybrid storage module, the data buses of each bare chip are designed to be of equal length, and the address bus and control bus of each bare chip are designed to be of equal length to reduce the relative delay between signals.

[0045] In order to ensure signal integrity, the discrete ground signals of all bare chips in the microsystem are merged to form a complete ground plane; the digital signals on the plastic substrate are routed according to the preset path, the plastic substrate is preset to a specified number of layers, and is set in the packaging shell.

[0046] The multi-hybrid storage module includes internal SRAM storage unit, internal FLASH storage unit, SDRAM memory, SPI FLASH memory, parallel NOR FLASH memory, PROM memory, and SMC external storage interface unit, specifically:

[0047] The programmable logic storage unit in the data processing module is started by the code stream stored in the PROM memory, and the processor in the data processing module is started by implementing a multiple backup startup scheme through an internal FLASH storage unit, an SPI FLASH memory or a parallel NOR FLASH memory.

[0048] After the microsystem is started, the internal SRAM storage unit and SDRAM memory in the multi-hybrid storage module can provide code execution or data storage space for the processor in the data processing module, the internal FLASH storage unit, parallel NORFLASH memory, and SPI FLASH memory can provide code execution space for the processor in the data processing module, and the SMC external storage interface unit can provide additional extended storage resources for the microsystem.

[0049] The information interaction interface module includes digital interface units such as serial port, CAN, SPI, I2C, Ethernet, 1553B, GPIO, SMC bus, four-way differential line driver, four-way differential line receiver, analog interface units such as ADC, DAC, and expansion interface units, specifically:

[0050] External instructions and data can be transmitted to the programmable logic storage unit in the processing module through digital interface units such as four-way differential line drivers and four-way differential line receivers or extended interface units; external instructions and data can also be transmitted to the processor in the data processing module through digital interface units or analog interface units. The result instructions and data are transmitted from the processor in the data processing module to other systems outside the microsystem through digital interface units or analog interface units; the result instructions and data can also be transmitted from the programmable logic storage unit in the data processing module to other systems outside the microsystem through digital interface units such as four-way differential line drivers and four-way differential line receivers or extended interface units.

[0051] Data transmission between data processing modules and between data processing modules and multiple hybrid storage modules is realized through digital interface units such as SMC bus units and SPI units in the information interaction interface module. Among them, data transmission between the programmable logic unit and the processor in the data processing module is realized through the SMC bus, data transmission between the processor in the data processing module and the SDRAM memory and parallel NOR FLASH memory in the multiple hybrid storage module is realized through the SMC bus, and data transmission between the processor in the data processing module and the SPI FLASH memory in the multiple hybrid storage module is realized through the SPI unit.

[0052] The following is further described in conjunction with the accompanying drawings and preferred embodiments of the specification:

[0053] In the current embodiment, the heterogeneous information processing microsystem for space compact aiming equipment has the following functional modules: Figure 1 As shown, it includes: a data processing module, a multi-hybrid storage module, and an information interaction interface module. The bare core of each module is packaged at the system level through a microsystem integration process to achieve a reduction in the structural size.

[0054] The contents of system-level packaging include: the bare cores of each module are electrically connected on a multi-layer plastic substrate by wire bonding; according to the interconnection relationship of the bare chips, the SDRAM memory bare chips, parallel NOR FLASH memory bare chips and SPI FLASH memory bare chips that are highly dependent on the functions of the processor bare chips are placed near the processor bare chips; the PROM memory bare chips that are highly dependent on the functions of the programmable logic unit bare chips are placed near the programmable logic unit bare chips to shorten the bus signal propagation path.

[0055] For the bare chips with external pins, such as SPI FLASH memory bare chip, PROM memory bare chip, four-way differential line driver bare chip, four-way differential line receiver bare chip, processor bare chip and programmable logic unit bare chip, the lead-out end should be as close to the edge as possible. Among them, the four-way differential line driver bare chip and the four-way differential line receiver bare chip are placed at the edge of the plastic substrate package and located between the processor bare chip and the programmable logic unit bare chip, which is convenient for the expansion design of lead interconnection.

[0056] Programmable logic unit bare chips, SDRAM memory bare chips, parallel NOR FLASH memory bare chips, and processor bare chips are arranged in an L shape from top to bottom on the plastic substrate, and the data bus, address bus, and control bus signals have smooth paths.

[0057] The data buses of the processor bare chip, the programmable logic unit bare chip, the SDRAM memory bare chip and the parallel NOR FLASH memory bare chip are of equal length, and the address buses and control buses are of equal length, so as to reduce the relative delay between signals.

[0058] The programmable logic resource bare chip has rich IO resources, supports multiple single-ended and differential protocols under multi-voltage conditions, has large-capacity block memory and digital clock management unit, can realize dynamic reconstruction, storage expansion, interface expansion, high-performance parallel processing, fault-tolerant redundancy and other functions, and improves the versatility and reliability of the system.

[0059] The processor bare chip has a high-performance processor core, FFT operation unit, Cordic operation unit, DMA unit, supports multiple digital and analog bus interfaces, and reduces the number of pins and improves functional density through pin multiplexing.

[0060] The programmable logic unit + processor heterogeneous computing processing architecture can perform multi-architecture cascading, external device control, and mounting of multiple data storage units, etc., to achieve system function expansion and performance extension.

[0061] The processor bare chip uses three non-volatile storage media: internal FLASH unit, SPI FLASH memory, and parallel NOR FLASH memory, as redundant backup of the boot code, ensuring the reliability of system power-off restart or system update. Through the SMC interface, the microsystem can realize external non-volatile memory or random access memory expansion, further improving the stability and compatibility of the microsystem.

[0062] Example:

[0063] This embodiment provides a heterogeneous information processing microsystem for space compact aiming devices, which has excellent system compatibility and can be widely used in various aiming devices. The main functional units and interconnection relationships of the architecture are as follows: Figure 2 As shown:

[0064] All bare chips inside the microsystem require an external power supply to provide power for normal operation. The processor bare chip and the programmable logic unit bare chip also require a microsystem external clock to provide stimulation for normal operation; the debugging interface needs to be led to the outside of the microsystem so that during the debugging phase, the simulator can be used to perform online debugging of software and hardware or software loading. The processor bare chip external stimulation can also use the internal clock of the processor bare chip.

[0065] The processor bare chip provides a variety of digital interfaces and analog interfaces to the outside of the microsystem, such as: serial port, CAN, SPI, I2C, Ethernet, 1553B, GPIO, SMC, ADC, DAC, etc. The SMC bus is used to connect the mounted devices inside or outside the microsystem. Inside the microsystem, SDRAM bare chips, parallel NOR FLASH bare chips and programmable logic unit bare chips are mounted on the bus, occupying a total of 3 independent chip select signals, sharing the data bus, address bus and control bus. SDRAM is mounted on the SDRAM space of the processor bare chip, the parallel NOR FLASH bare chip is mounted on the SRAM space of the processor bare chip, and the programmable logic unit bare chip is mounted on the SRAM space of the processor bare chip as an IO device. SRAM, PSRAM, NOR FLASH and SDRAM resources can be flexibly mounted outside the microsystem to realize external non-volatile memory or random access memory expansion, further improving the stability and compatibility of the microsystem.

[0066] SPI FLASH leads to the SPI interface outside the microsystem for interconnection with the processor bare chip. Since SPI FLASH may be used for system startup of the processor bare chip, it must be interconnected with the specific SPI interface of the processor bare chip.

[0067] The programmable logic unit bare chip, through rich internal resources and external I / O user interface, can realize dynamic reconstruction, storage expansion, interface expansion, high-performance parallel processing, fault-tolerant redundancy and other functions, thereby improving the versatility and reliability of the system.

[0068] PROM provides a JTAG interface for injecting and storing the code stream of the programmable logic unit bare chip. The main string function interface is used to inject the stored code stream into the programmable logic unit bare chip to realize the system startup of the programmable logic unit bare chip.

[0069] The four-way differential line driver and the four-way differential line receiver lead out four-way output and input interfaces to the outside of the microsystem respectively, which are used to connect with the interface of the programmable logic unit bare chip or the processor bare chip, and can also be interconnected with other external devices of the microsystem.

[0070] like Figure 3 As shown in the distribution diagram of each bare chip inside the microsystem package, each module is electrically connected on a multi-layer plastic substrate by wire bonding, wherein the SDRAM memory bare chip, parallel NOR FLASH memory bare chip and SPIFLASH memory bare chip are placed near the processor bare chip, the PROM memory bare chip is placed near the programmable logic unit bare chip to shorten the signal propagation path, and the four-way differential line driver and four-way differential line receiver bare chips are set at the edge of the plastic substrate package. The programmable logic unit bare chip, SDRAM memory bare chip, parallel NOR FLASH memory bare chip and processor bare chip are placed in an L-shaped order from top to bottom on the plastic substrate to ensure that the data bus, address bus and control bus signals are smooth and the path is reasonable.

[0071] like Figure 4 As shown in the figure, there are 6 types of information flows, and the following uses ①②③④⑤⑥ to distinguish the types of information flows. In information flow ①, data / instructions are input to the programmable logic unit of the data processing module through the expansion interface of the information interaction interface module or the digital interface such as the four-way differential line receiver for processing, and then flow to the processor through the SMC bus for further processing.

[0072] Information flow ② and information flow ③ are both executed after information flow ①. Information flow ② transmits the processor calculation result data or instruction feedback to the programmable logic processing unit through the SMC bus, and then sends it to the outside of the microsystem through the expansion interface or digital interface such as the four-way differential line driver. Information flow ③ sends the processor calculation result data or instruction feedback directly to the outside of the microsystem through the digital interface or analog interface of the information interaction interface module.

[0073] Information flow ④ transmits the external instructions of the microsystem to the processor through a digital interface or an analog interface. After the processor processes the instructions, it transmits the microsystem feedback to the outside of the microsystem through a digital interface or an analog interface.

[0074] It can be seen from information flows ①②③④ that the rich computing and processing resources of the programmable logic unit + processor heterogeneous computing and processing architecture can realize high-performance computing and processing, provide sufficient and diverse external ports, and can perform multi-architecture cascading, external device control, and mounting of multiple data storage units, etc., to achieve functional expansion and performance extension of the system.

[0075] Information flows ⑤⑥ are mainly storage support provided by the multi-hybrid storage module for the data processing module. PROM stores the programmable logic unit code stream and supports programmable logic unit code stream injection. Internal SRAM and SDRAM provide sufficient storage space for processor execution and data cache. Internal FLASH unit, SPI FLASH memory, parallel NOR FLASH memory, a total of 3 non-volatile storage media, as redundant backup of the startup code, ensure the reliability of system power-off restart or system update.

[0076] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

[0077] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. A heterogeneous information processing microsystem for space compact aiming equipment, characterized by include: Data processing module, multi-hybrid storage module, information interaction interface module, each module is integrated in a single package, including: The data processing module receives and preprocesses external data to realize communication protocol conversion; uses the adaptation algorithm to process the preprocessed data to realize the corresponding functions. The resulting data can be converted through the communication protocol and transmitted to other external systems; The multi-hybrid storage module provides flexible storage space for data processing module code loading and execution, meeting the storage capacity requirements for microsystem power-on startup and normal operation; The information interaction interface module provides an information interaction interface between external data and the microsystem according to the information interaction requirements inside and outside the microsystem, and provides an internal information interaction interface for the microsystem within the data processing module and between the data processing module and the multi-hybrid storage module.

2. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 1, characterized in that: The structural composition and data transmission process of the data processing module, multi-hybrid storage module, and information interaction interface module are as follows: The data processing module includes a programmable logic storage unit and a processor; The multi-hybrid storage module includes internal SRAM storage unit, internal FLASH storage unit, SDRAM memory, parallel NOR FLASH memory, SPI FLASH memory, PROM memory, and SMC external storage interface unit; The information interaction interface module includes: a digital interface unit, an analog interface unit, and an extended interface unit, wherein the digital interface unit includes: serial port, CAN, SPI, I2C, Ethernet, 1553B, GPIO, SMC bus, four-way differential line driver, four-way differential line receiver; the analog interface unit includes: ADC, DAC; The programmable logic storage unit of the data processing module and the processor transmit information through the SMC bus of the information interaction interface module; The programmable logic storage unit in the data processing module is started by the code stream stored in the PROM memory of the multi-hybrid storage module; the processor in the data processing module is started by implementing a multiple backup startup scheme through the internal FLASH storage unit, SPI FLASH memory or parallel NOR FLASH memory of the multi-hybrid storage module; The data transmission between the processor in the data processing module and the SDRAM memory and the parallel NOR FLASH memory in the multi-hybrid storage module is realized through the SMC bus, and the processor in the data processing module transmits data to the SPI FLASH memory in the multi-hybrid storage module through the SPI unit; After the microsystem is started, the internal SRAM storage unit and SDRAM memory in the multi-hybrid storage module provide code execution or data storage space for the processor in the data processing module, the internal FLASH storage unit, parallel NOR FLASH memory, and SPI FLASH memory provide code execution space for the processor in the data processing module, and the SMC external storage interface unit provides additional extended storage resources for the microsystem; External instructions and data are transmitted to the programmable logic storage unit in the data processing module through the digital interface unit or the extended interface unit; external instructions and data can be transmitted to the processor in the data processing module through the digital interface unit or the analog interface unit; result instructions and data are transmitted from the processor in the data processing module to other systems outside the microsystem through the digital interface unit or the analog interface unit, and can also be transmitted from the programmable logic storage unit in the data processing module to other systems outside the microsystem through the digital interface unit or the extended interface unit.

3. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 2, characterized in that: The bare chips in each module are placed on a multi-layer plastic substrate through a wire bonding process to achieve electrical connection, and conduct heat to the plastic package shell through conductive adhesive.

4. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 3, characterized in that: When laying sheets on plastic substrates: The SDRAM memory bare chip, the parallel NOR FLASH memory bare chip and the SPIFLASH memory bare chip in the multi-hybrid storage module are directly adjacent to the processor bare chip in the data processing module, and the adjacent distance range with the processor bare chip is 2.5mm to 7.5mm; The PROM memory bare chip in the multi-hybrid storage module is directly adjacent to the programmable logic unit bare chip in the data processing module, and the adjacent distance range is 3.5mm to 4.0mm; The bare chip in the information interaction interface module is arranged at the package edge of the plastic substrate.

5. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 4, characterized in that: The programmable logic unit bare chip in the data processing module, the SDRAM memory bare chip in the multi-hybrid storage module and the parallel NOR FLASH memory bare chip are placed in a straight line from top to bottom on the plastic substrate, and the processor bare chip in the data processing module is arranged in the vertical direction of the bottom of the straight line. The above four bare chips are placed in an L shape on the plastic substrate.

6. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 5, characterized in that: The programmable logic unit bare chip and processor bare chip in the data processing module, the SDRAM memory bare chip in the multi-hybrid storage module, and the parallel NOR FLASH memory bare chip, each bare chip's own data buses are designed to be of equal length, and each bare chip's own address bus and control bus are designed to be of equal length.

7. A heterogeneous information processing microsystem for space-oriented compact aiming equipment according to claim 6, characterized in that: The discrete ground signals of all bare chips in the microsystem are combined to form a complete ground plane.

8. The heterogeneous information processing microsystem for space compact aiming equipment according to claim 3 is characterized by: The plastic substrate of the microsystem is preset to have a specified number of layers and is arranged in a packaging shell.

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