Electronic paper display panel and display device

Abstract

The invention discloses an electronic paper display panel and a display device. The electronic paper display panel comprises a plurality of data lines and a plurality of scanning lines; the pixels are defined by crossing of the data lines and the scanning lines; every N adjacent columns of pixels are connected with one data line, and each row of pixels is provided with N scanning lines. According to the embodiment of the invention, the number of data lines can be reduced, so that the usage amount of source driving chips is reduced, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an electronic paper display panel and a display device. Background Art

[0002] Electronic paper not only has the advantages of full viewing angle, ultra-low power consumption, high reflectivity, eye protection, but also has the advantages of storage, mobility, convenience, etc. required by electronic products, which makes its application field wide.

[0003] The existing electronic paper display panel includes scan lines extending in the row direction and data lines extending in the column direction. The scan lines and the data lines are insulated and cross-defined to form a plurality of pixel areas. Each pixel area is provided with a pixel. All pixels in the same row are connected to the same scan line, and all pixels in the same column are connected to the same data line. As a result, the electronic paper display panel requires more data lines, and thus requires more source driver chips, which in turn leads to a higher cost of the electronic paper display panel. Summary of the invention

[0004] The present invention provides an electronic paper display panel and a display device, which can reduce the number of data lines, thereby reducing the usage of source driving chips and reducing costs.

[0005] In a first aspect, an embodiment of the present invention provides an electronic paper display panel, comprising: a plurality of data lines and a plurality of scan lines; and pixels defined by the intersection of the data lines and the scan lines; each adjacent N columns of pixels are connected to a data line, and each row of pixels is provided with N scan lines, where N is an integer greater than or equal to 3.

[0006] Optionally, when N=3, the electronic paper display panel also includes multiple first connecting lines, multiple second connecting lines and multiple third connecting lines; the pixels located in the k+1th row and the 3j+1th column are connected to the j+1th data line through the corresponding first connecting line; the pixels located in the k+1th row and the 3j+2th column are connected to the j+1th data line through the corresponding second connecting line; the pixels located in the k+1th row and the 3j+3th column are connected to the j+1th data line through the corresponding third connecting line; the data lines extend along the first direction, the scan lines extend along the second direction, the first direction intersects the second direction, wherein the first direction is the column direction, and the second direction is the row direction; k and j are both integers greater than or equal to zero.

[0007] Optionally, when N=4, the electronic paper display panel also includes multiple first connecting lines, multiple second connecting lines, multiple third connecting lines and multiple fourth connecting lines; the pixels located in the k+1th row and the 4j+1th column are connected to the j+1th data line through the corresponding first connecting line; the pixels located in the k+1th row and the 4j+2th column are connected to the j+1th data line through the corresponding second connecting line; the pixels located in the k+1th row and the 4j+3th column are connected to the j+1th data line through the corresponding third connecting line; the pixels located in the k+1th row and the 4j+4th column are connected to the j+1th data line through the corresponding third fourth connecting line; the data lines extend along the first direction, the scan lines extend along the second direction, the first direction intersects the second direction, wherein the first direction is the column direction, and the second direction is the row direction; wherein k and j are both integers greater than or equal to zero.

[0008] Optionally, the data line includes a main data line, a first auxiliary data line and a second auxiliary data line; the electronic paper display panel also includes a fifth connecting line and a sixth connecting line; the first auxiliary data line, the main data line and the second auxiliary data line are arranged in sequence at intervals and are interconnected through the fifth connecting line and the sixth connecting line; the main data line, the first auxiliary data line and the second auxiliary data line extend along a first direction, and the fifth connecting line and the sixth connecting line extend along a second direction; the first direction intersects with the second direction, wherein the first direction is a column direction and the second direction is a row direction.

[0009] Optionally, when N=3, the pixels in the 3j+1th column and the pixels in the 3j+2th column are enclosed by the first auxiliary data line, the second auxiliary data line, the fifth connection line and the sixth connection line.

[0010] Optionally, when N=4, the pixels in the 4j+2th column and the pixels in the 4j+3th column are enclosed by the first auxiliary data line, the second auxiliary data line, the fifth connection line and the sixth connection line.

[0011] Optionally, when N=3, the pixel located in the k+1th row and the 3j+1th column is connected to the first auxiliary data line of the j+1th data line; the pixel located in the k+1th row and the 3j+2th column is connected to the main data line of the j+1th data line; the pixel located in the k+1th row and the 3j+3th column is connected to the second auxiliary data line of the j+1th data line; wherein k and j are both integers greater than or equal to zero.

[0012] Optionally, when N=4, the pixels located in the k+1th row and the 4j+1th column are connected to the first auxiliary data line of the j+1th data line; the pixels located in the k+1th row and the 4j+2th column are connected to the main data line of the j+1th data line; the pixels located in the k+1th row and the 4j+3th column are connected to the main data line of the j+1th data line; the pixels located in the k+1th row and the 4j+4th column are connected to the second auxiliary data line of the j+1th data line; wherein k and j are both integers greater than or equal to zero.

[0013] Optionally, when N=3, the pixels located at the k+1th row and the 3j+1th column are connected to the 4k+1th scan line; the pixels located at the k+1th row and the 3j+2th column are connected to the 4k+2th scan line; the pixels located at the k+1th row and the 3j+3th column are connected to the 3k+3th scan line; or, when N=4, the pixels located at the k+1th row and the 4j+4th column are connected to the 4k+1th scan line; the pixels located at the k+1th row and the 4j+3th column are connected to the 4k+2th scan line; the pixels located at the k+1th row and the 4j+2th column are connected to the 4k+3th scan line; the pixels located at the k+1th row and the 4j+1th column are connected to the 4k+4th scan line; wherein k and j are both integers greater than or equal to zero.

[0014] In a second aspect, an embodiment of the present invention provides a display device, including the electronic paper display panel provided by any embodiment of the present invention.

[0015] The electronic paper display panel provided by the embodiment of the present invention includes multiple data lines and multiple scan lines, and pixels defined by the intersection of the data lines and the scan lines; by setting a data line to connect every N adjacent columns of pixels, the number of data lines can be reduced, thereby reducing the use of source driver chips and reducing costs.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a structural schematic diagram of an electronic paper display panel provided by an embodiment of the present invention;

[0019] Figure 2 is a partial structural schematic diagram of an electronic paper display panel provided by an embodiment of the present invention;

[0020] Figure 3 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0021] Figure 4 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0022] Figure 5 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0023] Figure 6 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0024] Figure 7 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0025] Figure 8 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0026] Fig. 9 is a partial structural schematic diagram of another electronic paper display panel provided by an embodiment of the present invention;

[0027] Fig.10 This is a schematic diagram of the working timing of an electronic paper display panel provided by an embodiment of the present invention;

[0028] Fig.11 This is a schematic diagram of the working timing of another electronic paper display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Figure 114 is a structural schematic diagram of an electronic paper display panel provided by an embodiment of the present invention. As shown in FIG14 , the electronic paper display panel includes a plurality of data lines 10 and a plurality of scan lines 20, wherein the data lines 10 extend along the column direction Y, and the scan lines 20 extend along the row direction X. The data signal and the scan signal of the pixel are provided by a driver chip 30 located at the lower frame of the electronic paper display panel, and the pixel is connected to the driver chip 30 through the connection wiring of the scan line and the connection wiring of the data line. The gold finger of the driver chip 30 is welded on a flexible printed circuit 40 (Flexible Printed Circuit, FPC), and the ports connected to the scan line 20 are located on the left and right sides of the driver chip 30, and the ports connected to the data line 10 are located in the middle of the driver chip 30. The driver chip 30 can be a source driver chip or a gate driver chip. The gate driver chip provides a scan signal to the scan line 20, and the source driver chip provides a data signal to the data line 10.

[0032] Figure 2 It is a schematic diagram of a partial structure of an electronic paper display panel provided by an embodiment of the present invention. Figure 3 Schematic diagram of a partial structure of an electronic paper display panel provided by an embodiment of the present invention. Figure 2 and Figure 3 The electronic paper display panel includes: a plurality of data lines 10 and a plurality of scan lines 20.

[0033] And pixels defined by the intersection of data lines 10 and scan lines 20; each adjacent N columns of pixels 30 are connected to a data line 10, and each row of pixels is provided with N scan lines 20, where N is an integer greater than or equal to 3. Figure 2 The case of N=3 is shown schematically. Figure 3 The case where N=4 is schematically shown.

[0034] Specifically, the pixel includes a pixel electrode 50 and a driving circuit 51. Under the control of the scan line signal, the driving circuit 51 receives the data signal from the data line 10, processes and transmits it to control the potential of the pixel electrode 51, thereby controlling the display state of the pixel.

[0035] When N=3, the three rows and six columns of pixels on the electronic paper display panel are used for illustration. The three rows and six columns of pixels are driven by nine scanning lines and two data lines, that is, one data line is used to provide data signals for three rows of pixels 300. The first data line S1 connects the first column of pixels, the second column of pixels, and the third column of pixels, and the second data line S2 connects the fourth column of pixels, the fifth column of pixels, and the sixth column of pixels. The data signal provided by the first data line S1 is input to the first column of pixels, the second column of pixels, and the third column of pixels, and the data signal provided by the second data line S2 is input to the fourth column of pixels, the fifth column of pixels, and the sixth column of pixels. Therefore, the actual number of data lines is 1 / 3 of the original number; taking the display with a resolution of 600 (G)*900 (S) as an example, only 300 data lines are needed in the design. The display of one row of pixels requires three scan lines for coordinated driving; taking the display process of the first row of pixels as an example: the scan signal provided by the first scan line G1 controls the display of the first row and the first column of pixels and the fourth column of pixels in the first row, the scan signal provided by the second scan line G2 controls the display of the second row and the fifth column of pixels in the first row, and the scan signal provided by the third scan line G3 controls the display of the third row and the sixth column of pixels in the first row.

[0036] When the scanning signal on the corresponding scanning line 20 of each row of pixels is at an effective level, the data signal from the data line 10 is received, and after being transmitted by the driving circuit 51, the potential of the pixel electrode 50 is finally changed. After the pixel electrode 50 receives the data signal, it combines with the common electrode to form an electric field between the pixel electrode 50 and the common electrode. According to the specific display technology (such as electrophoresis, electrowetting, etc.) adopted by the electronic paper, the electric field drives the display medium (such as the pigment particles in the electrophoretic display) to move, thereby changing the display state of the pixel and realizing the display of the image or text. For example, in the electrophoretic display, particles of different colors or polarities move near or away from the pixel electrode under the action of the electric field, so that the pixel presents different colors or grayscales. After a row of pixels completes data reception and display state update, the scanning signal of the corresponding scanning line 20 of the next row of pixels jumps to an effective level, and the above process is repeated until the pixels of the entire screen are updated and the display of a frame of image is completed.

[0037] The pixel electrode 50 is an electrode located inside each pixel and is directly related to the display state of the pixel. It is connected to the corresponding data line 10 through a driving circuit to receive a data signal from the data line 10. Taking electrophoretic electronic paper as an example, when the pixel electrode 50 receives a data signal, an electric field is formed between the pixel electrode and the common electrode. If the potential of the pixel electrode 50 is higher than that of the common electrode, the electric field drives the charged pigment particles in the electrophoretic liquid to move. Assuming that the white pigment particles are positively charged, when the pixel electrode 50 is positively charged and the voltage is appropriate, the white pigment particles move toward the pixel electrode, making the pixel appear white visually. Different data signals can cause the pixel electrode 50 to produce different electric field effects, thereby controlling the distribution of the pigment particles and achieving different grayscale or color displays.

[0038] The common electrode is an electrode that provides a reference potential for the entire display area. It covers a certain area of ​​the display panel and works together with each pixel electrode 50. In electronic paper display, the potential of the common electrode is usually relatively fixed. It is precisely because of the potential difference between the pixel electrode 50 and the common electrode that an electric field is generated in the pixel, driving the display medium (such as electrophoretic particles, liquid in electrowetting, etc.) to move, thereby realizing display.

[0039] In some embodiments, the common electrode is located at the bottom layer of the display panel or in a different layer structure from the pixel electrode 50, but regardless of its position, its relative position and potential relationship with the pixel electrode 50 determines the distribution and intensity of the electric field, thereby affecting the display effect.

[0040] It should be noted that the effective level is a control signal that turns on the transistor in the driving circuit. When the transistor included in the driving circuit is an N-type transistor, the effective level is a high level, and when the transistor included in the driving circuit is a P-type transistor, the effective level is a low level.

[0041] The electronic paper display panel provided by the embodiment of the present invention includes multiple data lines and multiple scan lines, and pixels defined by the intersection of the data lines and the scan lines; by setting a data line to connect every N adjacent columns of pixels, the number of data lines can be reduced, thereby reducing the use of source driver chips and reducing costs.

[0042] Optionally, when N=3, the pixel located at the k+1th row and the 3j+1th column is connected to the 4k+1th scan line 20; the pixel located at the k+1th row and the 3j+2th column is connected to the 4k+2th scan line 20; the pixel located at the k+1th row and the 3j+3th column is connected to the 3k+3th scan line 20.

[0043] Or, when N=4, the pixel located at the k+1th row and the 4j+4th column is connected to the 4k+1th scan line 20; the pixel located at the k+1th row and the 4j+3th column is connected to the 4k+2th scan line 20; the pixel located at the k+1th row and the 4j+2th column is connected to the 4k+3th scan line 20; the pixel located at the k+1th row and the 4j+1th column is connected to the 4k+4th scan line 20; wherein k and j are both integers greater than or equal to zero.

[0044] For example, continue to refer to Figure 2 , when k=0, j=0, that is, the pixels located in the 1st row and the 1st column are connected to the first scan line G1, the pixels located in the 1st row and the 2nd column are connected to the second scan line G2, and the pixels located in the 1st row and the 3rd column are connected to the third scan line G3. When k=0, j=1, that is, the pixels located in the 1st row and the 4th column are connected to the first scan line G1, the pixels located in the 1st row and the 5th column are connected to the second scan line G2, and the pixels located in the 1st row and the 6th column are connected to the third scan line G3.

[0045] When k=1 and j=0, the pixels located in the 2nd row and the 1st column are connected to the fourth scan line G4, the pixels located in the 2nd row and the 2nd column are connected to the fifth scan line G5, and the pixels located in the 2nd row and the 3rd column are connected to the sixth scan line G6.

[0046] When k=1, j=1, the pixels located in the 2nd row and the 4th column are connected to the fourth scan line G4, the pixels located in the 2nd row and the 5th column are connected to the fifth scan line G5, and the pixels located in the 2nd row and the 6th column are connected to the sixth scan line G6.

[0047] When k=2 and j=0, the pixel located in the 3rd row and the 1st column is connected to the seventh scan line G7, the pixel located in the 3rd row and the 2nd column is connected to the eighth scan line G8, and the pixel located in the 3rd row and the 3rd column is connected to the ninth scan line G9.

[0048] When k=2 and j=1, the pixels located in the 3rd row and 4th column are connected to the seventh scan line G7, the pixels located in the 3rd row and 5th column are connected to the eighth scan line G8, and the pixels located in the 3rd row and 6th column are connected to the ninth scan line G9.

[0049] For example, continue to refer to Figure 3 , when k=0, j=0, the pixels located in the 1st row and the 1st column are connected to the fourth scan line G4, the pixels located in the 1st row and the 2nd column are connected to the third scan line G3, the pixels located in the 1st row and the 3rd column are connected to the second scan line G2, and the pixels located in the 1st row and the 3rd column are connected to the first scan line G1.

[0050] When k=0 and j=1, the pixels located in the 1st row and 5th column are connected to the fourth scan line G4, the pixels located in the 1st row and 6th column are connected to the third scan line G3, the pixels located in the 1st row and 7th column are connected to the second scan line G2, and the pixels located in the 1st row and 8th column are connected to the first scan line G1.

[0051] When k=1 and j=0, the pixels located in the 2nd row and 1st column are connected to the eighth scan line G8, the pixels located in the 2nd row and 2nd column are connected to the seventh scan line G7, the pixels located in the 2nd row and 3rd column are connected to the sixth scan line G6, and the pixels located in the 2nd row and 4th column are connected to the fifth scan line G5.

[0052] When k=1 and j=1, the pixels located in the 2nd row and 5th column are connected to the eighth scan line G8, the pixels located in the 2nd row and 6th column are connected to the seventh scan line G7, the pixels located in the 2nd row and 7th column are connected to the sixth scan line G6, and the pixels located in the 2nd row and 8th column are connected to the fifth scan line G5.

[0053] Optionally, continue to refer to Figure 2 , when N=3, the electronic paper display panel further includes a plurality of first connection lines 11, a plurality of second connection lines 12 and a plurality of third connection lines 13; the pixel located in the k+1th row and the 3j+1th column is connected to the j+1th data line 10 through the corresponding first connection line 11; the pixel located in the k+1th row and the 3j+2th column is connected to the j+1th data line 10 through the corresponding second connection line 12; the pixel located in the k+1th row and the 3j+3th column is connected to the j+1th data line 10 through the corresponding third connection line 13; the data line 10 extends along the first direction Y, the scanning line 20 extends along the second direction X, the first direction Y intersects with the second direction X, wherein the first direction Y is the column direction, and the second direction X is the row direction; k, j are both integers greater than or equal to zero. Through the first connection line 11, the second connection line 12 and the third connection line 13, the pixels located in specific rows and columns can be accurately connected to the corresponding data lines. For pixels in the k+1th row and different columns (3j+1, 3j+2, 3j+3), each corresponding connection line is connected to the j+1th data line. This ensures that the transmission path of the data signal from the data line to each pixel is clear and accurate, avoiding confusion in signal transmission, thereby ensuring the correctness of the displayed content.

[0054] Specifically, when k=0 and j=0, the pixels located in the 1st row and the 1st column are connected to the first data line S1 through the corresponding first connection line 11, the pixels located in the 1st row and the 2nd column are connected to the first data line S1 through the corresponding second connection line 12, and the pixels located in the 1st row and the 3rd column are connected to the first data line S1 through the corresponding third connection line 13.

[0055] When k=0 and j=1, the pixels located in the 1st row and the 4th column are connected to the second data line S2 through the corresponding first connection line 11, the pixels located in the 1st row and the 5th column are connected to the second data line S2 through the corresponding second connection line 12, and the pixels located in the 1st row and the 6th column are connected to the second data line S2 through the corresponding third connection line 13.

[0056] When k=1 and j=0, the pixel located in the 2nd row and the 1st column is connected to the first data line S1 through the corresponding first connection line 11, the pixel located in the 2nd row and the 2nd column is connected to the first data line S1 through the corresponding second connection line 12, and the pixel located in the 2nd row and the 3rd column is connected to the first data line S1 through the corresponding third connection line 13.

[0057] When k=1 and j=1, the pixels located in the 2nd row and the 4th column are connected to the second data line S2 through the corresponding first connection line 11, the pixels located in the 2nd row and the 5th column are connected to the second data line S2 through the corresponding second connection line 12, and the pixels located in the 2nd row and the 6th column are connected to the second data line S2 through the corresponding third connection line 13.

[0058] When k=2 and j=0, the pixel located in the 3rd row and the 1st column is connected to the first data line S1 through the corresponding first connection line 11, the pixel located in the 3rd row and the 2nd column is connected to the first data line S1 through the corresponding second connection line 12, and the pixel located in the 3rd row and the 3rd column is connected to the first data line S1 through the corresponding third connection line 13.

[0059] When k=2 and j=1, the pixels located in the 3rd row and 4th column are connected to the second data line S2 through the corresponding first connection line 11, the pixels located in the 3rd row and 5th column are connected to the second data line S2 through the corresponding second connection line 12, and the pixels located in the 3rd row and 6th column are connected to the second data line S2 through the corresponding third connection line 13.

[0060] Continue to refer Figure 2 Optionally, the third connection line 13 is in a serpentine shape. The serpentine third connection line 13 can better adapt to the spatial relationship between the pixel and the data line 10. Since each three adjacent columns of pixels are connected to a data line 10, and the pixels are arranged in an array, the serpentine shape can cleverly bypass other pixels and establish a connection between the pixel located in the k+1th row and the 3j+3th column and the j+1th data line 10 in a limited two-dimensional space, effectively utilizing the pixel gap and the remaining space in the panel, and avoiding space waste caused by the third connection line 13 being too long or over-extended in the plane.

[0061] Continue to refer Figure 2Optionally, the j+1th data line 10 is located between the pixels in the 3j+1th column and the pixels in the 3j+2th column.

[0062] Specifically, when j=0, the first data line S1 is located between the first column of pixels and the second column of pixels. When j=1, the second data line S2 is located between the fourth column of pixels and the fifth column of pixels. The location of the data line 10 between two columns of pixels allows the data signal to be more evenly transmitted to the pixels connected thereto. For pixels connected to the data line 10 via connecting lines (such as pixels in different columns connected by the first connecting line 11, the second connecting line 12, and the third connecting line 13), this uniform signal distribution helps to ensure that each pixel receives a stable and consistent signal strength, thereby achieving a more uniform display effect and avoiding display brightness or color differences caused by uneven signal strength.

[0063] Optionally, continue to refer to Figure 3 , when N=4, the electronic paper display panel further includes a plurality of first connection lines 11, a plurality of second connection lines 12, a plurality of third connection lines 13 and a plurality of fourth connection lines 14. The pixel located in the k+1th row and the 4j+1th column is connected to the j+1th data line 10 through the corresponding first connection line 11; the pixel located in the k+1th row and the 4j+2th column is connected to the j+1th data line 10 through the corresponding second connection line 12; the pixel located in the k+1th row and the 4j+3th column is connected to the j+1th data line 10 through the corresponding third connection line 13; the pixel located in the k+1th row and the 4j+4th column is connected to the j+1th data line 10 through the corresponding third fourth connection line 14; the data line 10 extends along the first direction, the scan line 20 extends along the second direction, the first direction intersects the second direction, wherein the first direction is the column direction, and the second direction is the row direction; wherein k, j are both integers greater than or equal to zero.

[0064] Specifically, when k=0 and j=0, the pixels located in the 1st row and the 1st column are connected to the first data line S1 through the corresponding first connection line 11, the pixels located in the 1st row and the 2nd column are connected to the first data line S1 through the corresponding second connection line 12, the pixels located in the 1st row and the 3rd column are connected to the first data line S1 through the corresponding third connection line 13, and the pixels located in the 1st row and the 4th column are connected to the first data line S1 through the corresponding fourth connection line 14.

[0065] When k=0 and j=1, the pixels located in the 1st row and 5th column are connected to the second data line S2 through the corresponding first connection line 11, the pixels located in the 1st row and 6th column are connected to the second data line S2 through the corresponding second connection line 12, the pixels located in the 1st row and 7th column are connected to the second data line S2 through the corresponding third connection line 13, and the pixels located in the 1st row and 8th column are connected to the second data line S2 through the corresponding fourth connection line 14.

[0066] When k=1 and j=0, the pixels located in the 2nd row and the 1st column are connected to the first data line S1 through the corresponding first connection line 11, the pixels located in the 2nd row and the 2nd column are connected to the first data line S1 through the corresponding second connection line 12, the pixels located in the 2nd row and the 3rd column are connected to the first data line S1 through the corresponding third connection line 13, and the pixels located in the 2nd row and the 4th column are connected to the first data line S1 through the corresponding fourth connection line 14.

[0067] When k=1 and j=1, the pixels located in the 2nd row and the 5th column are connected to the second data line S2 through the corresponding first connection line 11, the pixels located in the 2nd row and the 6th column are connected to the second data line S2 through the corresponding second connection line 12, the pixels located in the 2nd row and the 7th column are connected to the second data line S2 through the corresponding third connection line 13, and the pixels located in the 2nd row and the 8th column are connected to the second data line S2 through the corresponding fourth connection line 14.

[0068] Figure 4 It is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Figure 5 FIG. 1 is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Figure 4 and Figure 5 Optionally, the data line 10 includes a main data line 100 , a first auxiliary data line 101 and a second auxiliary data line 102 ; the electronic paper display panel also includes a fifth connection line 15 and a sixth connection line 16 .

[0069] The first auxiliary data line 101, the main data line 100, and the second auxiliary data line 102 are arranged in sequence and are connected to each other through the fifth connection line 15 and the sixth connection line 16. The main data line 100, the first auxiliary data line 101, and the second auxiliary data line 102 extend along the first direction Y, and the fifth connection line 15 and the sixth connection line 16 extend along the second direction X. The first direction Y intersects with the second direction X, wherein the first direction Y is a column direction, and the second direction X is a row direction.

[0070] Specifically, the data signals transmitted on the main data line 100, the first auxiliary data line 101 and the second auxiliary data line 102 are all output by a port of the source driver chip. The design that the main data line 100, the first auxiliary data line 101 and the second auxiliary data line 102 are connected to each other through the fifth connecting line 15 and the sixth connecting line 16 can make the data line 10 and the scanning line 20 not overlap, and ensure that the voltage drop of the scanning signal transmitted on each scanning line 20 is the same, thereby improving the uniformity of the color displayed on each row. In addition, ensuring that the parasitic capacitance between the data line 10 and each pixel is consistent is conducive to improving the uniformity of the color displayed by each pixel.

[0071] Continue to refer Figure 4 Optionally, when N=3, the pixels in the 3j+1th column and the pixels in the 3j+2th column are enclosed by the first auxiliary data line 101 , the second auxiliary data line 102 , the fifth connection line 15 and the sixth connection line 16 .

[0072] Specifically, when j=0, the pixels in the first column and the pixels in the second column are enclosed by the first auxiliary data line 101, the second auxiliary data line 102, the fifth connection line 15, and the sixth connection line 16. When j=1, the pixels in the fourth column and the pixels in the fifth column are enclosed by the first auxiliary data line 101, the second auxiliary data line 102, the fifth connection line 15, and the sixth connection line 16.

[0073] Continue to refer Figure 4 , optionally, when N=3, the pixel located in the k+1th row and the 3j+1th column is connected to the first auxiliary data line 101 of the j+1th data line 10. The pixel located in the k+1th row and the 3j+2th column is connected to the main data line 100 of the j+1th data line 10. The pixel located in the k+1th row and the 3j+3th column is connected to the second auxiliary data line 102 of the j+1th data line 10. Wherein, k and j are both integers greater than or equal to zero.

[0074] Specifically, when k=0 and j=0, the pixels located in the first row and the first column are connected to the first auxiliary data line 101 of the first data line S1. The pixels located in the first row and the second column are connected to the main data line 100 of the first data line S1. The pixels located in the first row and the third column are connected to the second auxiliary data line 102 of the first data line S1.

[0075] When k=0 and j=1, the pixels located in the 1st row and the 4th column are connected to the first auxiliary data line 101 of the second data line S2. The pixels located in the 1st row and the 5th column are connected to the main data line 100 of the second data line S2. The pixels located in the 1st row and the 6th column are connected to the second auxiliary data line 102 of the second data line S2.

[0076] When k=1 and j=0, the pixel located in the 2nd row and the 1st column is connected to the first auxiliary data line 101 of the first data line S1. The pixel located in the 2nd row and the 2nd column is connected to the main data line 100 of the first data line S1. The pixel located in the 2nd row and the 3rd column is connected to the second auxiliary data line 102 of the first data line S1.

[0077] When k=1 and j=1, the pixels located in the 2nd row and the 4th column are connected to the first auxiliary data line 101 of the second data line S2. The pixels located in the 2nd row and the 5th column are connected to the main data line 100 of the second data line S2. The pixels located in the 2nd row and the 6th column are connected to the second auxiliary data line 102 of the second data line S2.

[0078] When k=2 and j=0, the pixel located in the 3rd row and the 1st column is connected to the first auxiliary data line 101 of the first data line S1. The pixel located in the 3rd row and the 2nd column is connected to the main data line 100 of the first data line S1. The pixel located in the 3rd row and the 3rd column is connected to the second auxiliary data line 102 of the first data line S1.

[0079] When k=2 and j=1, the pixels located in the 3rd row and the 4th column are connected to the first auxiliary data line 101 of the second data line S2. The pixels located in the 3rd row and the 5th column are connected to the main data line 100 of the second data line S2. The pixels located in the 3rd row and the 6th column are connected to the second auxiliary data line 102 of the second data line S2.

[0080] Continue to refer Figure 5 Optionally, when N=4, the pixels in the 4j+2th column and the 4j+3th column are enclosed by the first auxiliary data line 101 , the second auxiliary data line 102 , the fifth connection line 15 and the sixth connection line 16 .

[0081] Specifically, when j=0, the pixels in the second column and the pixels in the third column are enclosed by the first auxiliary data line 101, the second auxiliary data line 102, the fifth connection line 15, and the sixth connection line 16. When j=1, the pixels in the sixth column and the pixels in the seventh column are enclosed by the first auxiliary data line 101, the second auxiliary data line 102, the fifth connection line 15, and the sixth connection line 16.

[0082] Continue to refer Figure 5 Optionally, when N=4, the pixels located in the k+1th row and the 4j+1th column are connected to the first auxiliary data line 101 of the j+1th data line; the pixels located in the k+1th row and the 4j+2th column are connected to the main data line 100 of the j+1th data line; the pixels located in the k+1th row and the 4j+3th column are connected to the main data line 100 of the j+1th data line; the pixels located in the k+1th row and the 4j+4th column are connected to the second auxiliary data line 102 of the j+1th data line; wherein k and j are both integers greater than or equal to zero.

[0083] Specifically, when k=0 and j=0, the pixels located in the 1st row and the 1st column are connected to the first auxiliary data line 101 of the first data line S1. The pixels located in the 1st row and the 2nd column are connected to the main data line 100 of the first data line S1. The pixels located in the 1st row and the 3rd column are connected to the main data line 100 of the first data line S1. The pixels located in the 1st row and the 4th column are connected to the second auxiliary data line 102 of the first data line S1.

[0084] When k=0 and j=1, the pixels located in the 1st row and the 5th column are connected to the first auxiliary data line 101 of the second data line S2. The pixels located in the 1st row and the 6th column are connected to the main data line 100 of the second data line S2. The pixels located in the 1st row and the 7th column are connected to the main data line 100 of the second data line S2. The pixels located in the 1st row and the 8th column are connected to the second auxiliary data line 102 of the second data line S2.

[0085] When k=1 and j=0, the pixels located in the 2nd row and the 1st column are connected to the first auxiliary data line 101 of the first data line S1. The pixels located in the 2nd row and the 2nd column are connected to the main data line 100 of the first data line S1. The pixels located in the 2nd row and the 3rd column are connected to the main data line 100 of the first data line S1. The pixels located in the 2nd row and the 4th column are connected to the second auxiliary data line 102 of the first data line S1.

[0086] When k=1 and j=1, the pixels located in the 2nd row and the 5th column are connected to the first auxiliary data line 101 of the second data line S2. The pixels located in the 2nd row and the 6th column are connected to the main data line 100 of the second data line S2. The pixels located in the 2nd row and the 7th column are connected to the main data line 100 of the second data line S2. The pixels located in the 2nd row and the 8th column are connected to the second auxiliary data line 102 of the second data line S2.

[0087] Figure 6 It is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Figure 7 It is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Figure 8 It is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Fig. 9 FIG. 1 is a partial structural diagram of another electronic paper display panel provided by an embodiment of the present invention. Figures 6 to 9The pixel includes a first transistor T1, a second transistor T2 and a pixel electrode 50, the first electrode of the first transistor T1 is connected to the corresponding data line 10, the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is connected to the pixel electrode 50, and the gate of the first transistor T1 and the gate of the second transistor T2 are connected to the same corresponding scan line 20.

[0088] Specifically, the first transistor T1 and the second transistor T2 constitute a driving circuit. The driving circuit is used to receive the data signal of the data line 10 and transmit it to the pixel electrode 50 to control the display state. The above transistor can be an N-type transistor or a P-type transistor; the first electrode of the above transistor can be a source electrode, and the second electrode can be a drain electrode, or the first electrode of the above transistor can be a drain electrode, and the second electrode can be a source electrode, and the present invention does not limit this.

[0089] Optionally, the electronic paper display panel further includes a common electrode, and a storage capacitor and a parasitic capacitor are formed between the pixel electrode 50 and the common electrode.

[0090] Fig.10 This is a schematic diagram of the working timing of an electronic paper display panel provided by an embodiment of the present invention. This working timing diagram can be applied to Figure 6 and Figure 7 The electronic paper display panel shown. Figure 6 and Fig.10 , the data signals required for different colors in the electronic paper display panel are as follows: black = +15V; white = -7V; red = +7V; yellow = -15V and all transistors are N-type transistors. Exemplarily, the driving process of the electronic paper display panel includes multiple stages.

[0091] In the first stage t01, the scanning signal on the first scanning line G1 is in a high level state, the scanning signals on the second scanning line G2 to the ninth scanning line G9 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row and the 3j+1 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the first row and the 3j+1 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 15V and the data signal on the second data line S2 is -15V at this time, the pixel in the first row and the first column is displayed as black, and the pixel in the first row and the fourth column is displayed as yellow.

[0092] In the second stage t02, the scanning signal on the second scanning line G2 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row, the first row, the 3j+2 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the first row, the 3j+2 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -7V and the data signal on the second data line S2 is 15V at this time, the pixel in the first row and the second column is displayed as white, and the pixel in the first row and the fifth column is displayed as black.

[0093] In the third stage t03, the scanning signal on the third scanning line G3 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row and the 3j+3 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the first row and the 3j+3 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 7V and the data signal on the second data line S2 is -7V at this time, the pixel in the third column of the first row is displayed as red, and the pixel in the sixth column of the first row is displayed as white.

[0094] In the fourth stage t04, the scanning signal on the fourth scanning line G4 is in a high level state, the scanning signals on the other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 3j+1 column are turned on, and the first transistor T1 and the second transistor T2 of the other pixels are turned off. The pixel electrode 50 in the second row and the 3j+1 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -7V and the data signal on the second data line S2 is 15V at this time, the pixel in the first column of the second row is displayed as white, and the pixel in the fourth column of the second row is displayed as black.

[0095] In the fifth stage t05, the scanning signal on the fifth scanning line G5 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 3j+2 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 3j+2 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 7V and the data signal on the second data line S2 is -7V at this time, the pixel in the second row and the second column is displayed as red, and the pixel in the second row and the fifth column is displayed as white.

[0096] In the sixth stage t06, the scanning signal on the sixth scanning line G6 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 3j+3 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 3j+3 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -15V and the data signal on the second data line S2 is 7V at this time, the pixel in the second row and the third column is displayed in yellow, and the pixel in the second row and the sixth column is displayed in red.

[0097] In the seventh stage t07, the scanning signal on the seventh scanning line G7 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the third row and the 3j+1 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the third row and the 3j+1 column starts to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 7V and the data signal on the second data line S2 is -7V at this time, the pixel in the first column of the third row is displayed as red, and the pixel in the fourth column of the third row is displayed as white.

[0098] In the eighth stage t08, the scanning signal on the eighth scanning line G8 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the third row and the 3j+2 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the third row and the 3j+2 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -15V and the data signal on the second data line S2 is 7V at this time, the pixel in the third row and the second column is displayed in yellow, and the pixel in the third row and the fifth column is displayed in red.

[0099] In the ninth stage t09, the scanning signal on the ninth scanning line G9 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the third row and the 3j+3 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the third row and the 3j+3 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 15V and the data signal on the second data line S2 is -15V at this time, the pixel in the third row and the third column is displayed as black, and the pixel in the third row and the sixth column is displayed as yellow.

[0100] Fig.11This is a schematic diagram of the working timing of an electronic paper display panel provided by an embodiment of the present invention. This working timing diagram can be applied to Figure 8 and Fig. 9 The electronic paper display panel shown. Figure 8 and Fig.11 , the data signals required for different colors in the electronic paper display panel are as follows: black = +15V; white = -7V; red = +7V; yellow = -15V and all transistors are N-type transistors. Exemplarily, the driving process of the electronic paper display panel includes multiple stages.

[0101] In the first stage t01, the scanning signal on the first scanning line G1 is in a high level state, the scanning signals on the second scanning line G2 to the eighth scanning line G8 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row and the 4j+4th column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the first row and the 4j+4th column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -15V and the data signal on the second data line S2 is -15V at this time, the pixel in the fourth column of the first row is displayed as yellow, and the pixel in the eighth column of the first row is displayed as yellow.

[0102] In the second stage t02, the scanning signal on the second scanning line G2 is in a high level state, and the scanning signals on other scanning lines 20 are in a low level state. The first transistor T1 and the second transistor T2 of the pixel in the first row, the first row, the 4j+3 column are turned on, and the first transistor T1 and the second transistor T2 of other pixels are turned off. The pixel electrode 50 in the first row, the 4j+3 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 7V and the data signal on the second data line S2 is 7V at this time, the pixel in the third column of the first row is displayed in red, and the pixel in the seventh column of the first row is displayed in red.

[0103] In the third stage t03, the scanning signal on the third scanning line G3 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row and the 4j+2 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the first row and the 4j+2 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -7V and the data signal on the second data line S2 is -7V at this time, the pixel in the first row and the second column is displayed as white, and the pixel in the first row and the sixth column is displayed as white.

[0104] In the fourth stage t04, the scanning signal on the fourth scanning line G4 is in a high level state, the scanning signals on the other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the first row and the 4j+1th column are turned on, and the first transistor T1 and the second transistor T2 of the other pixels are turned off. The pixel electrode 50 in the first row and the 4j+1th column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 15V and the data signal on the second data line S2 is 15V at this time, the pixel in the first row and the first column is displayed as black, and the pixel in the first row and the fifth column is displayed as black.

[0105] In the fifth stage t05, the scanning signal on the fifth scanning line G5 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 4j+4th column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 4j+4th column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 15V and the data signal on the second data line S2 is 15V at this time, the pixel in the fourth column of the second row is displayed as black, and the pixel in the eighth column of the second row is displayed as black.

[0106] In the sixth stage t06, the scanning signal on the sixth scanning line G6 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 4j+3 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 4j+3 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -15V and the data signal on the second data line S2 is -15V at this time, the pixel in the second row and the third column is displayed in yellow, and the pixel in the second row and the seventh column is displayed in yellow.

[0107] In the seventh stage t07, the scanning signal on the seventh scanning line G7 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 4j+2 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 4j+2 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is 7V and the data signal on the second data line S2 is 7V at this time, the pixel in the second row and the second column is displayed in red, and the pixel in the second row and the sixth column is displayed in red.

[0108] In the eighth stage t08, the scanning signal on the eighth scanning line G8 is in a high level state, the scanning signals on other scanning lines 20 are in a low level state, the first transistor T1 and the second transistor T2 of the pixel in the second row and the 4j+1 column are turned on, and the first transistors T1 and the second transistors T2 of other pixels are turned off. The pixel electrode 50 in the second row and the 4j+1 column begins to charge, that is, the data signal is written into the pixel electrode 50. Since the data signal on the first data line S1 is -7V and the data signal on the second data line S2 is -7V at this time, the pixel in the first column of the second row is displayed as white, and the pixel in the fifth column of the second row is displayed as white.

[0109] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including the electronic paper display panel provided by any embodiment of the present invention. The display device also has the beneficial effects of the electronic paper display panel in the above-mentioned embodiment. The similarities can be understood by referring to the above explanation of the electronic paper display panel, which will not be repeated below.

[0110] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An electronic paper display panel, characterized in that: include: Multiple data lines and multiple scan lines; and pixels defined by the intersection of the data lines and the scan lines; Each adjacent N columns of pixels are connected to one data line, and each row of pixels is provided with N scan lines, wherein N is an integer greater than or equal to 3.

2. The electronic paper display panel according to claim 1, characterized in that: When N=3, the electronic paper display panel further includes a plurality of first connecting lines, a plurality of second connecting lines and a plurality of third connecting lines; The pixel located at the k+1th row and the 3j+1th column is connected to the j+1th data line through the corresponding first connecting line; The pixel located at the k+1th row and the 3j+2th column is connected to the j+1th data line through the corresponding second connecting line; The pixel located at the k+1th row and the 3j+3th column is connected to the j+1th data line through the corresponding third connecting line; The data line extends along a first direction, the scan line extends along a second direction, the first direction intersects the second direction, wherein the first direction is a column direction, and the second direction is a row direction; k and j are both integers greater than or equal to zero.

3. The electronic paper display panel according to claim 1, characterized in that: When N=4, the electronic paper display panel further includes a plurality of first connecting lines, a plurality of second connecting lines, a plurality of third connecting lines and a plurality of fourth connecting lines; The pixel located at the k+1th row and the 4j+1th column is connected to the j+1th data line through the corresponding first connecting line; The pixel located at the k+1th row and the 4j+2th column is connected to the j+1th data line through the corresponding second connecting line; The pixel located at the k+1th row and the 4j+3th column is connected to the j+1th data line through the corresponding third connecting line; The pixel located at the k+1th row and the 4j+4th column is connected to the j+1th data line through the corresponding third fourth connection line; The data line extends along a first direction, the scan line extends along a second direction, the first direction intersects the second direction, wherein the first direction is a column direction, and the second direction is a row direction; wherein k and j are both integers greater than or equal to zero.

4. The electronic paper display panel according to claim 1, characterized in that: The data line includes a main data line, a first auxiliary data line and a second auxiliary data line; the electronic paper display panel also includes a fifth connecting line and a sixth connecting line; The first auxiliary data line, the main data line and the second auxiliary data line are arranged in sequence and spaced apart from each other, and are connected to each other through the fifth connection line and the sixth connection line; The main data line, the first auxiliary data line and the second auxiliary data line extend along a first direction, and the fifth connection line and the sixth connection line extend along a second direction; The first direction intersects with the second direction, wherein the first direction is a column direction and the second direction is a row direction.

5. The electronic paper display panel according to claim 4, characterized in that: When N=3, the pixels in the 3j+1th column and the pixels in the 3j+2th column are closed and enclosed by the first auxiliary data line, the second auxiliary data line, the fifth connection line, and the sixth connection line.

6. The electronic paper display panel according to claim 4, characterized in that: When N=4, the pixels in the 4j+2th column and the pixels in the 4j+3th column are closed and enclosed by the first auxiliary data line, the second auxiliary data line, the fifth connection line and the sixth connection line.

7. The electronic paper display panel according to claim 4, characterized in that: When N=3, the pixel located at the k+1th row and the 3j+1th column is connected to the first auxiliary data line of the j+1th data line; The pixel located at the k+1th row and the 3j+2th column is connected to the main data line of the j+1th data line; The pixel located at the k+1th row and the 3j+3th column is connected to the second auxiliary data line of the j+1th data line; wherein k and j are both integers greater than or equal to zero.

8. The electronic paper display panel according to claim 4, characterized in that: When N=4, the pixel located in the k+1th row and the 4j+1th column is connected to the first auxiliary data line of the j+1th data line; The pixel located at the k+1th row and the 4j+2th column is connected to the main data line of the j+1th data line; The pixel located at the k+1th row and the 4j+3th column is connected to the main data line of the j+1th data line; The pixel located at the k+1th row and the 4j+4th column is connected to the second auxiliary data line of the j+1th data line; wherein k and j are both integers greater than or equal to zero.

9. The electronic paper display panel according to claim 1, characterized in that: When N=3, the pixel located at the k+1th row and the 3j+1th column is connected to the 4k+1th scanning line; The pixel located at the k+1th row and the 3j+2th column is connected to the 4k+2th scanning line; The pixel located at the k+1th row and the 3j+3th column is connected to the 3k+3th scanning line; Or, when N=4, The pixel located at the k+1th row and the 4j+4th column is connected to the 4k+1th scan line; The pixel located at the k+1th row and the 4j+3th column is connected to the 4k+2th scanning line; The pixel located at the k+1th row and the 4j+2th column is connected to the 4k+3th scanning line; The pixel located at the k+1th row and the 4j+1th column is connected to the 4k+4th scanning line; Wherein, k and j are both integers greater than or equal to zero.

10. A display device, characterized in that: The electronic paper display panel comprises any one of claims 1 to 9.

Images