Memory, operation method of memory and storage system

Abstract

The embodiment of the invention provides a memory, an operation method of the memory and a storage system, and relates to but not limited to the technical field of storage. The memory includes a peripheral circuit, a plurality of word lines, and a plurality of rows of memory cells, each row of memory cells coupled with one word line, the peripheral circuit configured to apply a first voltage to a first word line of the plurality of word lines at each of a plurality of first time periods. And in a second time period between every two adjacent first time periods in the plurality of first time periods, applying a second voltage to the first word line, the second voltage being configured to conduct the memory cells coupled to the first word line. Therefore, the accuracy of data reading can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of storage technology, and more particularly to a memory, a method for operating a memory, and a storage system. Background Art

[0002] With the advancement of storage technology, computer flash memory devices (NAND) are becoming more and more widely used, such as in mobile phones, computers and other devices.

[0003] With the development of NAND memory, the number of bits stored in each storage unit is increasing. For example, each storage unit of triple-level cell (TLC) flash memory particles can store 3 bits of data, corresponding to three logical pages: lower page (LP), middle page (MP) and upper page (UP).

[0004] When reading data in a NAND memory, a read voltage may be applied to a word line (WL). If the read voltage is greater than a threshold voltage of a memory cell coupled to the word line, the memory cell coupled to the word line is turned on. The data stored in the turned-on memory cell may be obtained based on the current on the bit line (BL) coupled to the turned-on memory cell. Summary of the invention

[0005] The embodiments of the present application provide a memory, a memory operation method and a storage system, which solve the problem of easily reading wrong data.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a memory is provided, the memory comprising a peripheral circuit, a plurality of word lines, and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, the peripheral circuit being configured to: apply a first voltage to a first word line among the plurality of word lines in each first time period of a plurality of first time periods, and apply a second voltage to the first word line in a second time period between each two adjacent first time periods in the plurality of first time periods, the second voltage being configured to turn on the memory cell coupled to the first word line.

[0008] In the above technical solution, in each first time period of multiple first time periods, a first voltage is applied to the first word line of the multiple word lines, and in the second time period between each two adjacent first time periods in the multiple first time periods, a second voltage is applied to the first word line, and the second voltage is configured to turn on the storage unit coupled to the first word line. The supercharge voltage of the storage unit coupled to the first word line is increased to "the second voltage configured to turn on the storage unit coupled to the first word line", so that, on the one hand, the channel can be better cleaned. On the other hand, the voltage on the first word line can quickly reach the first voltage, thereby reducing the voltage climbing time and shortening the reading time. On the other hand, random telegraph noise can be reduced, thereby increasing the threshold edge statistical summary model (edge ​​sum, ESUM), reducing the probability of reading wrong data, and improving data reliability. On the other hand, the solution only needs to change the timing of electrical control without increasing hardware costs.

[0009] In a possible implementation of the first aspect, the second voltage applied in each second time period is equal. In the above possible implementation, the second voltage applied in each second time period is equal, so that the same voltage source can be used to provide the second voltage without increasing hardware cost.

[0010] In a possible implementation of the first aspect, the peripheral circuit is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In the above possible implementation, before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In this way, the same voltage source can be used to provide the pre-pulse voltage and the second voltage without increasing hardware costs.

[0011] In a possible implementation of the first aspect, the peripheral circuit is further configured to: apply a recovery pulse voltage to the first word line after the last first voltage is applied, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In the above possible implementation, after the last first voltage is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In this way, the same voltage source can be used to provide the recovery pulse voltage and the second voltage without increasing hardware costs.

[0012] In a possible implementation of the first aspect, the first voltage is configured to read data of a storage unit coupled to the first word line. In the above possible implementation, the first voltage is configured to read data of a storage unit coupled to the first word line. Therefore, the solution can be applied to an application scenario where a memory reads data, and when reading data of a storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0013] In a possible implementation of the first aspect, the first voltage is configured to verify the data of the storage unit coupled to the first word line during programming. In the above possible implementation, the first voltage is configured to verify the data of the storage unit coupled to the first word line during programming. Therefore, the solution can be applied to the application scenario of verifying data during memory programming, and when verifying the data of the storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0014] In a possible implementation of the first aspect, the multiple first voltages are increased sequentially. In the above possible implementation, the multiple first voltages are increased sequentially. In this way, the scheme can be applied to the application scenario of forward reading or forward verification, and in the process of forward reading or forward verification, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0015] In a possible implementation of the first aspect, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the peripheral circuit is further configured to: apply a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on the storage unit coupled to the second word line. Apply a fourth voltage to the second word line in each of the second time periods, the fourth voltage being less than the third voltage. In the above possible implementation, a third voltage is applied to the second word line adjacent to the first word line in each of the first time periods, and a fourth voltage less than the third voltage is applied to the second word line in each of the second time periods. Since the second word line is coupled to the first word line in each of the second time periods (when the first word line is overcharged), the voltage of the second word line actually increases. By reducing the voltage applied to the second word line in the second time period, the read conduction voltage interference caused by the coupling of the second word line with the first word line is offset, and the ESUM and E0 of the storage unit coupled to the second word line are prevented from becoming smaller, where E0 refers to the space between the threshold voltage corresponding to the peak value of the number of storage units in the erased state and the read voltage corresponding to the storage unit in the erased state, thereby ensuring the data reliability of the memory.

[0016] In a possible implementation of the first aspect, the plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the peripheral circuit is further configured to: apply a fifth voltage to the third word line in each of the first time period and each of the second time period, the fifth voltage being configured to turn on a storage unit coupled to the third word line. In the above possible implementation, the fifth voltage is applied to the third word line that is not adjacent to the first word line, and the fifth voltage is configured to turn on a storage unit coupled to the third word line. In this way, the storage unit coupled to the third word line can be turned on, providing a basis for the bit line to detect current.

[0017] In a second aspect, a memory is provided, the memory comprising a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, the peripheral circuit being configured to: apply a first voltage to a first word line among the plurality of word lines in each first time period of a plurality of first time periods, apply a second voltage to the first word line in a second time period between each two adjacent first time periods in the plurality of first time periods, and the second voltage applied in each second time period is equal.

[0018] In the above technical solution, in each first time period of multiple first time periods, a first voltage is applied to the first word line of the multiple word lines, and in the second time period between each two adjacent first time periods in the multiple first time periods, a second voltage is applied to the first word line, and the second voltage applied in each second time period is equal. In this way, on the one hand, the channel can be better cleaned. On the other hand, the voltage on the first word line can quickly reach the first voltage, thereby reducing the voltage climbing time and shortening the reading time. On the other hand, random telegraph noise can be reduced, thereby increasing ESUM, reducing the probability of reading wrong data, and improving data reliability. On the other hand, the solution only needs to change the timing of electrical control, and the same voltage source can be used to provide the second voltage without increasing hardware costs.

[0019] In a possible implementation of the second aspect, the second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage. In the above possible implementation, the second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage. Increasing the second voltage to "greater than the maximum value of the plurality of first voltages" provides a basis for increasing the second voltage to achieve effects such as clearing the channel, shortening the read time, and improving data reliability.

[0020] In a possible implementation of the second aspect, the second voltage is configured to turn on the memory cell coupled to the first word line. In the above possible implementation, the second voltage is configured to turn on the memory cell coupled to the first word line. Increasing the supercharge voltage of the memory cell coupled to the first word line to "the second voltage configured to turn on the memory cell coupled to the first word line" provides a basis for increasing the supercharge voltage to achieve effects such as clearing the channel, shortening the reading time, and improving data reliability.

[0021] In a possible implementation of the second aspect, the peripheral circuit is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In the above possible implementation, before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In this way, the same voltage source can be used to provide the pre-pulse voltage and the second voltage without increasing hardware costs.

[0022] In a possible implementation of the second aspect, the peripheral circuit is further configured to: apply a recovery pulse voltage to the first word line after the last first voltage is applied, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In the above possible implementation, after the last first voltage is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In this way, the same voltage source can be used to provide the recovery pulse voltage and the second voltage without increasing hardware costs.

[0023] In a possible implementation of the second aspect, the first voltage is configured to read data of a storage unit coupled to the first word line. In the above possible implementation, the first voltage is configured to read data of a storage unit coupled to the first word line. Therefore, the solution can be applied to an application scenario where a memory reads data, and when reading data of a storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0024] In a possible implementation of the second aspect, the first voltage is configured to verify the data of the storage cell coupled to the first word line during programming. In the above possible implementation, the first voltage is configured to verify the data of the storage cell coupled to the first word line during programming. Therefore, this solution can be applied to the application scenario of verifying data during memory programming, and when verifying the data of the storage cell coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0025] In a possible implementation of the second aspect, the multiple first voltages are increased sequentially. In the above possible implementation, the multiple first voltages are increased sequentially. In this way, the solution can be applied to the application scenario of forward reading or forward verification, and in the process of forward reading or forward verification, the channel can be better cleaned, the reading time can be shortened, and the data reliability can be improved.

[0026] In a possible implementation of the second aspect, the multiple word lines also include a second word line, which is adjacent to the first word line, and the peripheral circuit is further configured to: apply a third voltage to the second word line in each of the first time periods, and the third voltage is configured to turn on the storage unit coupled to the second word line. Apply a fourth voltage to the second word line in each of the second time periods, and the fourth voltage is configured to turn on the storage unit coupled to the second word line, and the fourth voltage is less than the third voltage. In the above possible implementation, a third voltage is applied to the second word line adjacent to the first word line in each of the first time periods, and a fourth voltage less than the third voltage is applied to the second word line in each of the second time periods. Since the second word line will be coupled to the first word line in each of the second time periods (when the first word line is overcharged), the voltage of the second word line will actually increase. By reducing the voltage applied to the second word line in the second time period, the read-on voltage interference caused by the coupling of the second word line and the first word line is offset, and the ESUM and E0 of the storage unit coupled to the second word line are prevented from becoming smaller. E0 refers to the space between the threshold voltage corresponding to the peak value of the number of storage units in the erased state and the read voltage corresponding to the storage unit in the erased state, thereby ensuring the data reliability of the memory.

[0027] In a possible implementation of the second aspect, the plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the peripheral circuit is further configured to: apply a fifth voltage to the third word line in each of the first time period and each of the second time period, the fifth voltage being configured to turn on a storage unit coupled to the third word line. In the above possible implementation, the fifth voltage is applied to the third word line that is not adjacent to the first word line, and the fifth voltage is configured to turn on a storage unit coupled to the third word line. In this way, the storage unit coupled to the third word line can be turned on, providing a basis for the bit line to detect current.

[0028] In a third aspect, a method for operating a memory is provided, the memory comprising a peripheral circuit, a plurality of word lines, and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, the method comprising: applying a first voltage to a first word line of the plurality of word lines in each first time period of a plurality of first time periods, and applying a second voltage to the first word line in a second time period between each two adjacent first time periods in the plurality of first time periods, the second voltage being configured to turn on the memory cell coupled to the first word line.

[0029] In a possible implementation manner of the third aspect, the second voltage applied in each second time period is equal.

[0030] In a possible implementation of the third aspect, the method further includes: before applying the first first voltage, applying a pre-pulse voltage to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

[0031] In a possible implementation of the third aspect, the method further includes: applying a recovery pulse voltage to the first word line after applying the last of the first voltage, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

[0032] In a possible implementation manner of the third aspect, the multiple first voltages increase sequentially.

[0033] In a possible implementation manner of the third aspect, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the method further includes: applying a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and applying a fourth voltage to the second word line in each of the second time periods, the fourth voltage being configured to turn on a memory cell coupled to the second word line, the fourth voltage being less than the third voltage.

[0034] In a possible implementation of the third aspect, the multiple word lines also include a third word line, which is not adjacent to the first word line, and the method also includes: applying a fifth voltage to the third word line in each of the first time period and each of the second time period, and the fifth voltage is configured to turn on the storage unit coupled to the third word line.

[0035] In a fourth aspect, a method for operating a memory is provided, the memory comprising a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, the method comprising: applying a first voltage to a first word line of the plurality of word lines in each first time period of a plurality of first time periods, applying a second voltage to the first word line in a second time period between each two adjacent first time periods in the plurality of first time periods, and the second voltage applied in each second time period is equal.

[0036] In a possible implementation manner of the fourth aspect, the second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage.

[0037] In a possible implementation manner of the fourth aspect, the second voltage is configured to turn on a storage unit coupled to the first word line.

[0038] In a possible implementation of the fourth aspect, the method further includes: before applying the first first voltage, applying a pre-pulse voltage to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

[0039] In a possible implementation of the fourth aspect, the method further includes: applying a recovery pulse voltage to the first word line after applying the last of the first voltage, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

[0040] In a possible implementation manner of the fourth aspect, the multiple first voltages increase sequentially.

[0041] In a possible implementation manner of the fourth aspect, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the method further includes: applying a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and applying a fourth voltage to the second word line in each of the second time periods, the fourth voltage being configured to turn on a memory cell coupled to the second word line, the fourth voltage being less than the third voltage.

[0042] In a fifth aspect, a storage system is provided, which includes a controller and a memory provided by the first aspect or any possible implementation of the first aspect.

[0043] In a sixth aspect, a storage system is provided, which includes a controller and a memory provided by the second aspect or any possible implementation of the second aspect.

[0044] In a seventh aspect, an electronic device is provided, which includes a processor and the storage system provided in the fifth aspect.

[0045] In an eighth aspect, an electronic device is provided, which includes a processor and the storage system provided in the sixth aspect.

[0046] In another aspect of the present application, a computer-readable storage medium is provided. When the computer-readable storage medium is run on a computer, the computer executes the memory operation method provided by the third aspect or any possible implementation of the third aspect.

[0047] In another aspect of the present application, a computer-readable storage medium is provided. When the computer-readable storage medium is run on a computer, the computer executes the memory operation method provided by the fourth aspect or any possible implementation of the fourth aspect.

[0048] It can be understood that any of the above-mentioned memory operation methods, storage systems, electronic devices or computer-readable storage media are applied to the above-mentioned memory or through the memory to achieve corresponding functions. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the corresponding memory provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 A schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0050] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of the structure of a storage cell array provided in an embodiment of the present application;

[0052] Figure 4 A normal distribution diagram of data states of a memory provided in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of a reading voltage provided in an embodiment of the present application Figure 1 ;

[0054] Figure 6 A schematic diagram of a reading voltage provided in an embodiment of the present application Figure 2 ;

[0055] Figure 7 A schematic diagram of a memory provided in an embodiment of the present application Figure 1 ;

[0056] Figure 8 A voltage diagram provided in the embodiment of the present application Figure 1 ;

[0057] Fig. 9 A voltage diagram provided in the embodiment of the present application Figure 2 ;

[0058] Fig.10 A voltage diagram provided in the embodiment of the present application Figure 3 ;

[0059] Fig.11 A voltage diagram provided in the embodiment of the present application Figure 4 ;

[0060] Fig.12 A schematic diagram of a memory provided in an embodiment of the present application Figure 2 ;

[0061] Fig.13 A voltage diagram provided in the embodiment of the present application Figure 5 ;

[0062] Fig.14 A schematic diagram of a memory operation method provided in an embodiment of the present application Figure 1 ;

[0063] Fig.15 A schematic diagram of a memory operation method provided in an embodiment of the present application Figure 2 ;

[0064] Fig.16 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0065] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0066] In the description of the present application, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "multiple" means two or more.

[0067] When describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0068] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B. The use of "suitable for" or "configured to" herein is meant to be open and inclusive language that does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0069] Before introducing the embodiments of the present application, the relevant technical terms and relevant technical background involved in the embodiments of the present application are first introduced and explained.

[0070] The memory may include a memory cell array. The memory cell array may include a plurality of memory blocks, each memory block including a plurality of memory cells. The memory may store data in the memory blocks in a sequential order or a random order. The memory in this embodiment may include a computer flash memory device (NAND). The memory may receive a command (command, CMD), an address (address, ADD) and data (data) from a controller. The memory may receive an address sent by the controller and perform an operation corresponding to the command on an area selected according to the address. For example, the memory may perform a write operation (programming operation), a read operation and an erase operation. During a programming operation, the memory may program data into an area selected according to an address. During a read operation, the memory may read data from an area selected according to an address. During an erase operation, the memory may erase data stored in an area selected according to an address.

[0071] Figure 1A schematic diagram of the structure of a storage system provided in an embodiment of the present application. Generally, the storage system 10 can be applied to various electronic devices. Among them, the storage system 10 may include a coupled memory 200 and a controller 100, and the memory 200 may have one or more. For example, in one example, the controller 100 and the single memory 200 may be integrated into a memory card. The memory card may include a personal computer memory card international association (PCMCIA) card, a compact flash card (CF card), a smart media card (SM card), a memory stick (memory stick), a multimedia card (MMC), a secure digital card (SD card), a universal flash storage (UFS), etc. Among them, the multimedia card can be divided into MMC, reduced-size MMC (RS-MMC), mini MMC (MMCmicro), etc.; the secure digital card includes SD, mini SD card (miniSD), micro SD card (microSD), high-capacity SD card (secure digital high capacity, SDHC), etc. Further, the memory card may also include a memory card connector for coupling the memory card to the host. In one example, the controller 100 and the plurality of memories 200 may be integrated into a solid state disk (SSD). The SSD may also include an SSD connector for coupling the SSD to the host. In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card. In addition, the above-mentioned electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc., and the embodiments of the present application do not impose specific restrictions on this.

[0072] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of the present application. Generally, the memory 200 includes a memory cell array 210 and a peripheral circuit. The peripheral circuit includes an input / output circuit 221, a control circuit 222, a register 223, a voltage generator 224, a row decoder 225, a column decoder 226, and a page buffer 227.

[0073] The input / output circuit 221 is mainly used to receive read instructions and write instructions sent by the controller 100 and to send the read data to the controller 100. The input / output circuit 221 can be coupled to the control circuit 222 and act as a control buffer to buffer the control command received from the host and relay it to the control circuit 222, and to buffer the status information received from the control circuit 222 and relay it to the host. The input / output circuit 221 can also be coupled to the column decoder 226 via the data bus and act as a data interface and data buffer to buffer the data and relay it to the memory cell array 210 or relay or buffer the data from the memory cell array 210.

[0074] The control circuit 222 may be configured to control the operation of the memory cell array 210 and the page buffer 227. The control circuit 222 is mainly used to control the row decoder 225 to conduct the voltage generator 224 with the corresponding word line and control the column decoder 226 to conduct the voltage generator 224 with the corresponding bit line according to the received read instruction, so as to read the corresponding data.

[0075] The register 223 includes an address register, a status register, etc. Among them, the address register is used to store the word line address (word line address) and the string address (string address) in the read request instruction. The status register is used to store the current state of the memory 200, including two states: ready and busy. When the control circuit 222 is reading data from the memory cell array 210 or writing data to the memory cell array 210, the state stored in the status register is a "busy" state, and the next read or write operation cannot be performed. When the memory cell array 210 completes the reading process or the writing process, the state stored in the status register switches to the "ready" state, and the next read or write operation can be performed.

[0076] The column decoder 226 may be configured to be controlled by the control circuit 222 , and select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 224 .

[0077] The row decoder 225 can be configured to be controlled by the control circuit 222, and select / deselect the storage block of the memory cell array 210 and select / deselect the word line of the storage block. The row decoder 225 can also be configured to drive the word line using the word line voltage generated from the voltage generator 224. In some embodiments, the row decoder 225 can also select / deselect and drive the source selection gate line and the drain selection gate line. For example, the row decoder 225 is configured to perform an erase operation on the memory cell coupled to (one or more) selected word lines. The voltage generator 224 can be configured to be controlled by the control circuit 222, and generate a word line voltage (e.g., a read voltage, a write voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 210.

[0078] The page buffer 227 can be configured to read data from the memory cell array 210 or write (program) data to the memory cell array 210 according to the control signal from the control circuit 222. Specifically, in one example, the page buffer 227 can store a page of write data (programming data) to be programmed into a memory page of the memory cell array 210. In another example, the page buffer 227 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer 227 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell, and amplify a small voltage swing to a recognizable logic level in a read operation.

[0079] Figure 3 A schematic diagram of the structure of a memory cell array provided in an embodiment of the present application. The memory cell array 210 of the memory includes a plurality of bit lines (BL): BL1, BL2, BL3, BL4, BL5, BL6, BL7, etc., and a plurality of word lines (WL): WL1, WL2, WL3, etc. Each memory cell is coupled to a word line and a bit line. When data needs to be read from a selected memory cell, a read voltage can be applied to the WL coupled to the selected memory cell, and a turn-on voltage can be applied to the WL of the unselected memory cell.

[0080] With the development of NAND memory, the number of bits of data stored in the storage unit has increased from 1 bit to 2 bits, 3 bits, and 4 bits. Correspondingly, the storage unit has evolved from a single level cell (SLC) to a multiple level cell (MLC), a triple level cell (TLC), and a quad level cell (QLC). Correspondingly, the data states in the memory have increased from 2 to 4, 8, and 16, thereby increasing the capacity of the memory and reducing the cost.

[0081] The storage cell of the SLC memory stores 1 bit of data. The data state of the storage cell of the SLC memory includes 1 erased state and 1 programmed state, the erased state is recorded as E, the programmed state is recorded as P, and the threshold voltage corresponding to the storage cell in the programmed state P is greater than the threshold voltage of the storage cell in the erased state E. The storage cell of the MLC memory stores 2 bits of data. The data state of the storage cell of the MLC memory includes 1 erased state and 3 programmed states, the erased state is recorded as E, and the programmed states are recorded as P1, P2 and P3 from the 1st state to the 3rd state, and the threshold voltage gradually increases from the P1 state to the P3 state. The storage cell of the TLC memory stores 3 bits of data. The data state of the storage cell of the TLC memory includes 1 erased state and 7 programmed states, the erased state is recorded as E, and the programmed states are recorded as P1, P2, P3, P4, P5, P6 and P7 from the 1st state to the 7th state, and the threshold voltage of the storage cell from the P1 state to the P7 state gradually increases. The storage cell of the QLC memory stores 4 bits of data. The data states of the storage cell of the QLC memory include 1 erased state and 15 programmed states. The erased state is denoted as E, and the programmed states are denoted as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 from the 1st state to the 15th state, and the threshold voltage of the storage cell from the P1 state to the P15 state gradually increases.

[0082] When the storage unit is a QLC flash memory particle, each storage unit can store 4 bits of data, corresponding to four logical pages: lower logical page (LP), middle logical page (MP), upper logical page (UP) and extra page (XP). In the memory, the data stored in the storage unit is read in units of logical pages.

[0083] When data is read from a plurality of storage cells coupled to a word line, a read voltage corresponding to each logical page may be applied to the word line in the order of each logical page. The order of reading each logical page may be: first read LP, then read MP, then read UP, and finally read XP. The order of each logical page may also be: first read LP, then read UP, then read XP, and finally read MP. The embodiment of the present application does not limit this.

[0084] Figure 4 A normal distribution diagram of data states of a memory provided in an embodiment of the present application. Figure 4 (a) in the figure is the normal distribution diagram of the data state of the QLC memory. Figure 4 (b) in FIG. 1 is a normal distribution diagram of the data state of the TLC memory. Figure 4 (a) and Figure 4 In (b), the horizontal axis is the threshold voltage, and the vertical axis is the number of memory cells. Figure 5 A schematic diagram of a reading voltage provided in an embodiment of the present application Figure 1 . Figure 5 The read voltage of the QLC memory is shown, and the horizontal axis is time. Figure 5 As shown, RB is the timing reference line, the read voltages corresponding to LP are V1, V4, V6, and V11, the read voltages corresponding to MP are V3, V7, V9, and V13, the read voltages corresponding to UP are V2, V8, and V14, and the read voltages corresponding to XP are V5, V10, V12, and V15.

[0085] After applying any read voltage corresponding to any logic page to the word line each time, the data of the corresponding bit stored in the memory cell can be determined according to the conduction state of the memory cell under different read voltages. In this way, after applying each read voltage corresponding to each logic page to the word line, the read result can be determined according to the data of each bit stored in the determined memory cell.

[0086] Before reading, a pre-pulse voltage may be applied to the word line to clean the channel and solve the hot carrier injection (HCI) problem. After the sensing is completed, a recovery pulse voltage may be applied to the word line to clean the channel again.

[0087] like Figure 4 As shown in (b), for the adjacent first data state (such as E state) and second data state (such as P1 state), the first read voltage corresponds to the first threshold edge space. The first threshold edge space refers to the space between the threshold voltage corresponding to the peak value of the number of memory cells in the first data state and the first read voltage.

[0088] For example, in Figure 4In the TLC memory shown in (b), the first threshold edge space between the E state and the P1 state is E0, the first threshold edge space between the P1 state and the P2 state is E2, the first threshold edge space between the P2 state and the P3 state is E4, the first threshold edge space between the P3 state and the P4 state is E6, the first threshold edge space between the P4 state and the P5 state is E8, the first threshold edge space between the P5 state and the P6 state is E10, and the first threshold edge space between the P6 state and the P7 state is E12.

[0089] The second threshold edge space refers to the space between the first read voltage and the minimum threshold voltage of the memory cell in the second data state. Figure 4 In the TLC memory shown in (b), the second threshold edge space between the E state and the P1 state is E1, the second threshold edge space between the P1 state and the P2 state is E3, the second threshold edge space between the P2 state and the P3 state is E5, the second threshold edge space between the P3 state and the P4 state is E7, the second threshold edge space between the P4 state and the P5 state is E9, the second threshold edge space between the P5 state and the P6 state is E11, and the second threshold edge space between the P6 state and the P7 state is E13.

[0090] The edge sum model (ESUM) is the sum of the first threshold edge space and the second threshold edge space except E0. Figure 4 In the TLC memory shown in (b), ESUM=E1+E2+E3+E4+E5+E6+E7+E8+E9+E10+E11+E12 E13.

[0091] In the actual reading process, the read voltage applied to the word line may have errors. The smaller the ESUM, the smaller the range of the read voltage, and the easier it is to read the wrong data. When applying multiple read voltages to the word line, a forward read (forward read) method can be used, that is, multiple read voltages increase in sequence, or a reverse read (reverse read) method can be used, that is, multiple read voltages decrease in sequence. Forward read has a longer time (time of read, tR) than reverse read, and ESUM is smaller, such as ESUM is 100 millivolts smaller.

[0092] Figure 6 A schematic diagram of a reading voltage provided in an embodiment of the present application Figure 2 . Figure 6The horizontal axis is time. VCC is the initial voltage. sel WLn is the selected (sel) word line, WLn+ / -1 is the word line adjacent to WLn among the unselected (unsel) word lines, and unsel WL is the other unselected word lines except WLn+ / -1. When reading the memory cell coupled to WLn, voltages are applied to WLn, WLn+ / -1, and unsel WL. Taking the reading of LP as an example, V1, V4, V6, and V11 are applied to the word line in multiple time periods by the read voltage (Vread) source, and the supercharge voltage is applied in the time period between each application of two adjacent read voltages by the read voltage (Vread) source.

[0093] Specifically, a pre-pulse voltage (such as VpassN) is applied to WLn during the T1 period. A read voltage V1 is applied to WLn during the T2 period, a read voltage V4 is applied to WLn during the T4 period, a read voltage V6 is applied to WLn during the T6 period, and a read voltage V11 is applied to WLn during the T8 period. An overcharge voltage V4+Δ is applied to WLn during the T3 period, an overcharge voltage V6+Δ is applied to WLn during the T5 period, and an overcharge voltage V11+Δ is applied to WLn during the T7 period. A recovery pulse voltage (such as VpassN) is applied to WLn during the T9 period. A turn-on voltage (such as VpassP) is applied to WLn+ / -1 during the T1 to T9 period, and a turn-on voltage (such as VpassN) is applied to the unsel WL during the T1 to T9 period.

[0094] The supercharge voltage is slightly larger than the read voltage to be applied, for example, V4+Δ, which is slightly larger than V4, is applied between V1 and V4. Since there is a capacitive load on the word line, applying V4+Δ to the word line can make the word line reach V4 faster, thereby reducing the read time. However, the ESUM of this method is small, and it is easy to read wrong data.

[0095] Based on this, an embodiment of the present application provides a memory. Figure 7 A schematic diagram of a memory provided in an embodiment of the present application Figure 1 The memory 200 includes a peripheral circuit 220, a plurality of word lines, and a plurality of rows of memory cells, each row of memory cells being coupled to a word line. The peripheral circuit 220 is configured as follows:

[0096] In each of the plurality of first time periods, a first voltage is applied to a first word line of the plurality of word lines.

[0097] In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage is configured to turn on a memory cell coupled to the first word line.

[0098] The peripheral circuit 220 may include at least Figure 2 The peripheral circuit 220 includes an input / output circuit 221, a control circuit 222, a register 223, a voltage generator 224, a row decoder 225, a column decoder 226, and a page buffer 227. The peripheral circuit 220 may also be configured to receive a request from the controller 100, the request being used to indicate the determination of the data of the memory cell coupled to the first word line. The first word line may be a selected word line (selWLn) in the plurality of time periods determined according to the request.

[0099] Furthermore, the number of the first voltages is greater than or equal to 2. The first voltages may be configured to determine data stored in a memory cell coupled to the first word line.

[0100] The second voltage may be: a turn-on voltage for turning on a memory cell coupled to the first word line when the first word line is a non-selected word line. In each second time period of the plurality of time periods, the second voltage may be used as a supercharge voltage for the memory cell coupled to the first word line.

[0101] Figure 8 A voltage diagram provided in the embodiment of the present application Figure 1 .by Figure 8 For example, the first time period may include: T2 time period, T4 time period, T6 time period, T8 time period. The second time period may include: T3 time period, T5 time period, T7 time period. The first voltage may include: La, Lb, Lc, Ld. The second voltage may include Vpass1, Vpass2, Vpass3.

[0102] Before Lb is applied to the first word line in the T4 time period, Vpass1 is applied to the first word line in the T3 time period. Before Lc is applied to the first word line in the T6 time period, Vpass2 is applied to the first word line in the T5 time period. Before Ld is applied to the first word line in the T8 time period, Vpass3 is applied to the first word line in the T7 time period. In this way, the supercharge voltage can be increased to be greater than or equal to the turn-on voltage, so that the voltage value before the first voltage is very large. Not only can the channel be turned on, but also the voltage on the first word line can quickly reach the first voltage, reduce the reading time (such as reducing 10 microseconds for each reading), and reduce random telegraph noise (RTN), thereby increasing the ESUM of the memory cell coupled to the first word line (such as increasing by 100 millivolts).

[0103] In the memory 200 provided in the embodiment of the present application, in each first time period of multiple first time periods, a first voltage is applied to the first word line of the multiple word lines, and in the second time period between each two adjacent first time periods in the multiple first time periods, a second voltage is applied to the first word line, and the second voltage is configured to turn on the memory cell coupled to the first word line. The supercharge voltage of the memory cell coupled to the first word line is increased from "slightly greater than the read voltage to be applied" to "the second voltage configured to turn on the memory cell coupled to the first word line", so that, on the one hand, the channel can be better cleaned. On the other hand, the voltage on the first word line can quickly reach the first voltage, thereby reducing the voltage climbing time and shortening the reading time. On the other hand, random telegraph noise can be reduced, thereby increasing ESUM, reducing the probability of reading wrong data, and improving data reliability. On the other hand, the solution only needs to change the timing of electrical control without increasing hardware costs.

[0104] In a possible implementation manner, the second voltage applied in each second time period is not equal. Figure 8 For example, Vpass1, Vpass2, and Vpass3 are all unequal. Alternatively, the second voltages applied in at least two second time periods are unequal, for example, Vpass1 and Vpass2 are unequal.

[0105] In another possible implementation manner, the second voltage applied in each second time period is equal. Figure 8 For example, Vpass1, Vpass2, and Vpass3 are all equal. In the memory 200 provided in the embodiment of the present application, the second voltage applied in each second time period is equal, so the same voltage source can be used to provide the second voltage without increasing the hardware cost.

[0106] In a possible implementation, the peripheral circuit 220 may include a first voltage source and a second voltage source. Figure 6 In the illustrated scheme, the first voltage source can be used to output a read voltage and an overcharge voltage, for example, the first voltage source can be a read voltage (Vrd) source, and the second voltage source can be used to output a pass voltage, for example, the second voltage source can be a pass voltage (Vpass) source.

[0107] The second voltage source may be a bypass power supply, and the second voltage source may be designed for the purpose of simultaneously providing a conduction voltage for a plurality of unselected word lines. The driving capability of the second voltage source is stronger than that of the first voltage source, and the voltage provided by the second voltage source is higher than the voltage provided by the first voltage source.

[0108] In the memory 200 provided in the embodiment of the present application, the first voltage source is used to output the first voltage in multiple first time periods, and the second voltage source is used to output the second voltage in multiple second time periods. Exemplarily, the first word line is coupled to both the first voltage source and the second voltage source. In the first first time period, a first voltage is applied to the first word line by the first voltage source. In the first second time period, it is switched to the second voltage source applying a second voltage to the first word line. In the second first time period, it is switched to the first voltage source applying a first voltage to the first word line. In this way, a basis for applying the second voltage can be provided.

[0109] In a possible implementation, the peripheral circuit 220 is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

[0110] like Figure 8 As shown, in the T1 time period, a pre-pulse voltage (such as VpassN) is applied to the first word line to clean the channel. The second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage, and can be: at least one of Vpass1, Vpass2, and Vpass3 is equal to VpassN.

[0111] In the memory 200 provided in the embodiment of the present application, before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In this way, the same voltage source can be used to provide the pre-pulse voltage and the second voltage without increasing the hardware cost.

[0112] In a possible implementation, the peripheral circuit 220 is further configured to: apply a recovery pulse voltage to the first word line after applying the last first voltage, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

[0113] like Figure 8 As shown, in the T9 time period, a recovery pulse voltage (such as VpassM) is applied to the first word line to clean the channel. The second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage, which may be: at least one of Vpass1, Vpass2, and Vpass3 is equal to VpassM. Exemplarily, the recovery pulse voltage may be equal to the pre-pulse voltage.

[0114] In the memory 200 provided in the embodiment of the present application, after the last first voltage is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In this way, the same voltage source can be used to provide the recovery pulse voltage and the second voltage without increasing hardware cost.

[0115] In a possible implementation, the peripheral circuit 220 is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage. Apply a recovery pulse voltage to the first word line after applying the last first voltage. The second voltages applied in at least one of the second time periods are equal. The second voltage applied in at least one of the second time periods is not equal to the pre-pulse voltage, and / or the second voltage is not equal to the recovery pulse voltage. Figure 8 As shown, Vpass1, Vpass2, and Vpass3 are all equal, Vpass1 and VpassN are not equal, and / or Vpass1 and VpassM are not equal.

[0116] In a possible implementation, the first voltage is configured to read data of a storage unit coupled to the first word line. Specifically, the peripheral circuit 220 may be configured to receive a read request from the controller 100, the read request being used to instruct to read data of a storage unit coupled to the first word line, the read request including an address of the data to be read. The peripheral circuit 220 receives the read request, determines the selected first word line according to the address in the read request, and applies a corresponding voltage to the first word line. Figure 8 For example, the first voltages La, Lb, Lc, and Ld may be read voltages for reading data of a memory cell coupled to the first word line.

[0117] In the memory 200 provided in the embodiment of the present application, the first voltage is configured to read the data of the storage unit coupled to the first word line. Therefore, the solution can be applied to the application scenario of the memory 200 reading data, and when reading the data of the storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0118] In a possible implementation, the first voltage is configured to verify the data of the storage unit coupled to the first word line during programming. Specifically, the peripheral circuit 220 can be configured to receive a programming request from the controller 100, the programming request is used to instruct to write data in the data of the storage unit coupled to the first word line, and the programming request includes the address of the data to be written. The peripheral circuit 220 receives the programming request, determines the selected first word line according to the address in the programming request, and applies a corresponding voltage to the first word line during the verification phase of programming. The first voltage can be a verification voltage, which is used to verify the data of the storage unit coupled to the first word line.

[0119] Fig. 9 A voltage diagram provided in the embodiment of the present application Figure 2 .by Fig. 9 For example, the first time period may include: T2 time period, T4 time period, T6 time period, T8 time period. The second time period may include: T3 time period, T5 time period, T7 time period. The first voltage may include: Vpv a, Vpv b, Vpv c, Vpv d, and the first voltage may be a verification voltage. The second voltage may include Vpass1, Vpass2, and Vpass3. Before applying the verification voltage Vpv b in the T4 time period, Vpass1 is applied in the T3 time period. Before applying the verification voltage Vpv c in the T6 time period, Vpass2 is applied in the T5 time period. Before applying the verification voltage Vpv d in the T8 time period, Vpass3 is applied in the T7 time period.

[0120] In the memory 200 provided in the embodiment of the present application, the first voltage is configured to verify the data of the storage unit coupled to the first word line during programming. Therefore, the solution can be applied to the application scenario of verifying data during programming of the memory 200, and when verifying the data of the storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0121] In a possible implementation, the multiple first voltages are increased in sequence. That is, the scheme adopts a forward read or forward verification method. In the memory 200 provided in the embodiment of the present application, the multiple first voltages are increased in sequence. In this way, the scheme can be applied to the application scenario of forward reading or forward verification. In the process of forward reading or forward verification, the supercharge voltage can be increased to be greater than or equal to the turn-on voltage to better clean the channel, shorten the reading time, and improve data reliability.

[0122] Furthermore, a pass voltage (such as VpassP) is applied to the word line WLn+ / -1 adjacent to the first word line to turn on the memory cell coupled to WLn+ / -1, thereby providing a basis for the bit line to detect the current. Fig.10A voltage diagram provided in the embodiment of the present application Figure 3 In each second time period, a pass voltage VpassP is applied to WLn+ / -1. Since WLn+ / -1 is adjacent to the first word line, WLn+ / -1 is coupled high by the first word line, and the actual voltage of WLn+ / -1 is VpassP+X as shown by the dotted line.

[0123] When the WLn+ / -1 is coupled by the first word line, the read vpass disturbance will increase and the block level read (BLRD) voltage in the reliability test will be reduced. When the page of WLn+ / -1 is read continuously for 1.5M times, the single page read disturbance of WLn+ / -1 is particularly serious. Similar to ESUM, the smaller the E0, the easier it is to read the wrong data. The larger the read vpass disturbance, the smaller the ESUM and E0 of the memory cell coupled to WLn+ / -1.

[0124] In a possible implementation, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the peripheral circuit 220 is further configured to: apply a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and apply a fourth voltage to the second word line in each of the second time periods, the fourth voltage being less than the third voltage.

[0125] The second word line may be a word line among the unselected word lines WLn+ / -1 adjacent to the first word line. Fig.11 A voltage diagram provided in the embodiment of the present application Figure 4 . In order to ensure that ESUM and E0 of the second word line will not lose too much, a fourth voltage (such as VpassP-X) is applied to the second word line in each second time period, so that the actual voltage of the second word line can be the third voltage (such as VpassP) or other conduction voltage. In this way, the read conduction voltage interference caused by the coupling of the second word line and the first word line can be offset. The embodiment of the present application does not limit the magnitude relationship between the third voltage and the fourth voltage.

[0126] In the memory 200 provided in the embodiment of the present application, a third voltage is applied to the second word line adjacent to the first word line in each of the first time periods, and a fourth voltage less than the third voltage is applied to the second word line in each of the second time periods. Since the second word line is coupled to the first word line in each of the second time periods (when the first word line is overcharged), the voltage of the second word line will actually increase. By reducing the voltage applied to the second word line in the second time period, the read-on voltage interference caused by the coupling of the second word line with the first word line is offset, and the ESUM and E0 of the storage unit coupled to the second word line are prevented from becoming smaller, thereby ensuring the data reliability of the memory 200.

[0127] In a possible implementation, the plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the peripheral circuit 220 is further configured as follows:

[0128] A fifth voltage is applied to the third word line in each of the first time period and each of the second time period, and the fifth voltage is configured to turn on a memory cell coupled to the third word line.

[0129] The third word line may be one of the unselected word lines that is not adjacent to the first word line. The fifth voltage may be a turn-on voltage (eg, VpassQ).

[0130] In the memory 200 provided in the embodiment of the present application, a fifth voltage is applied to a third word line not adjacent to the first word line, and the fifth voltage is configured to turn on the memory cell coupled to the third word line. In this way, the memory cell coupled to the third word line can be turned on, providing a basis for the bit line to detect the current.

[0131] In one possible implementation, at least two of VpassN, VpassM, VpassP, VpassQ, Vpass1, Vpass2, and Vpass3 may be equal. In another possible implementation, none of VpassN, VpassM, VpassP, VpassQ, Vpass1, Vpass2, and Vpass3 may be equal.

[0132] The embodiment of the present application also provides a memory. Fig.12 A schematic diagram of a memory provided in an embodiment of the present application Figure 2 The memory 200 includes a peripheral circuit 230, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells is coupled to a word line, and the peripheral circuit 230 is configured as follows:

[0133] In each of the plurality of first time periods, a first voltage is applied to a first word line of the plurality of word lines.

[0134] In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage applied in each of the second time periods is equal.

[0135] The first voltage may be configured to determine data of a storage unit coupled to the first word line. The description of the peripheral circuit 230, the first word line, the first voltage, and the second voltage may refer to the description of the peripheral circuit 230, the first word line, the first voltage, and the second voltage in the aforementioned embodiment, and the embodiments of the present application will not be repeated here.

[0136] Fig.13 A voltage diagram provided in the embodiment of the present application Figure 5 .by Fig.13 For example, the first time period may include: T2 time period, T4 time period, T6 time period, T8 time period. The second time period may include: T3 time period, T5 time period, T7 time period. The first voltage may include: La, Lb, Lc, Ld. The second voltage may include Vpass4. It can be seen that the second voltage applied in each second time period is equal.

[0137] Before Lb is applied to the first word line in the T4 time period, Vpass4 is applied to the first word line in the T3 time period. Before Lc is applied to the first word line in the T6 time period, Vpass4 is applied to the first word line in the T5 time period. Before Ld is applied to the first word line in the T8 time period, Vpass4 is applied to the first word line in the T7 time period. In this way, the overcharge voltage can be increased, so that the voltage value before the first voltage is very large. Not only can the channel be turned on, but also the voltage on the first word line can quickly reach the first voltage, reduce the reading time (such as reducing 10 microseconds for each reading), and can generate random telegraph noise, thereby increasing the ESUM of the memory cell coupled to the first word line (such as increasing by 100 millivolts).

[0138] In the memory 200 provided in the embodiment of the present application, in each first time period of a plurality of first time periods, a first voltage is applied to the first word line of the plurality of word lines, and in the second time period between each two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage applied in each second time period is equal. In this way, on the one hand, the channel can be cleaned better. On the other hand, the voltage on the first word line can be made to reach the first voltage quickly, thereby reducing the voltage climbing time and shortening the reading time. On the other hand, random telegraph noise can be reduced, thereby increasing ESUM, reducing the probability of reading wrong data, and improving data reliability. On the other hand, the scheme only needs to change the timing of the electrical control, and the same voltage source can be used to provide the second voltage without increasing the hardware cost.

[0139] In a possible implementation, the second voltage applied in each second time period is greater than any first voltage adjacent to the second voltage. The second voltage may be an overcharge voltage, and each second voltage is greater than the first voltage to be applied. Fig.13 For example, Vpass4 is greater than the maximum value among La, Lb, Lc, and Ld.

[0140] In the memory 200 provided in the embodiment of the present application, the second voltage applied in each second time period is greater than any first voltage adjacent to the second voltage. Increasing the second voltage from "slightly greater than the read voltage to be applied" to "greater than the maximum value of the plurality of first voltages" provides a basis for increasing the second voltage to achieve effects such as clearing the channel, shortening the read time, and improving data reliability.

[0141] In a possible implementation, the second voltage is configured to turn on the memory cell coupled to the first word line. The description of the second voltage may refer to the description of the second voltage in the above embodiment, and the present embodiment will not be repeated here.

[0142] In the memory 200 provided in the embodiment of the present application, the second voltage is configured to turn on the memory cell coupled to the first word line. Increasing the supercharge voltage of the memory cell coupled to the first word line from "slightly greater than the read voltage to be applied" to "the second voltage configured to turn on the memory cell coupled to the first word line" provides a basis for increasing the supercharge voltage to achieve the effects of clearing the channel, shortening the read time, and improving data reliability.

[0143] In a possible implementation, the peripheral circuit 230 may include a first voltage source and a second voltage source. The description of the first voltage source and the second voltage source may refer to the description in the above embodiment, and the embodiments of the present application will not be repeated here.

[0144] In a possible implementation, the peripheral circuit 230 is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. The description of the pre-pulse voltage can refer to the description of the pre-pulse voltage in the aforementioned embodiment, and the embodiments of the present application will not be repeated here.

[0145] In the memory 200 provided in the embodiment of the present application, before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the pre-pulse voltage. In this way, the same voltage source can be used to provide the pre-pulse voltage and the second voltage without increasing the hardware cost.

[0146] In a possible implementation, the peripheral circuit 230 is further configured to: apply a recovery pulse voltage to the first word line after applying the last first voltage, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. The description of the pre-pulse voltage can refer to the description of the pre-pulse voltage in the aforementioned embodiment, and the embodiment of the present application will not be repeated here.

[0147] In the memory 200 provided in the embodiment of the present application, after the last first voltage is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one second time period is equal to the recovery pulse voltage. In this way, the same voltage source can be used to provide the recovery pulse voltage and the second voltage without increasing hardware cost.

[0148] In a possible implementation, the peripheral circuit 230 is further configured to: apply a pre-pulse voltage to the first word line before applying the first first voltage. Apply a recovery pulse voltage to the first word line after applying the last first voltage. The second voltages applied in at least one of the second time periods are equal. The second voltage applied in at least one of the second time periods is not equal to the pre-pulse voltage, and / or the second voltage is not equal to the recovery pulse voltage.

[0149] In a possible implementation, the first voltage is configured to read data of a storage unit coupled to the first word line. The description of the reading process may refer to the description in the above embodiment, and the embodiment of the present application will not be repeated here.

[0150] In the memory 200 provided in the embodiment of the present application, the first voltage is configured to read the data of the storage unit coupled to the first word line. Therefore, the solution can be applied to the application scenario of the memory 200 reading data, and when reading the data of the storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0151] In a possible implementation, the first voltage is configured to verify data of a memory cell coupled to the first word line during programming. The description of the programming verification process may refer to the description in the aforementioned embodiment, and the embodiments of the present application will not be repeated here.

[0152] In the memory 200 provided in the embodiment of the present application, the first voltage is configured to verify the data of the storage unit coupled to the first word line during programming. Therefore, the solution can be applied to the application scenario of verifying data during programming of the memory 200, and when verifying the data of the storage unit coupled to the first word line, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0153] In a possible implementation, the multiple first voltages are increased sequentially. In the memory 200 provided in the embodiment of the present application, the multiple first voltages are increased sequentially. In this way, the scheme can be applied to the application scenario of forward reading or forward verification, and in the process of forward reading or forward verification, the channel is better cleaned, the reading time is shortened, and the data reliability is improved.

[0154] In a possible implementation, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the peripheral circuit 230 is further configured to: apply a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and apply a fourth voltage to the second word line in each of the second time periods, the fourth voltage being configured to turn on a memory cell coupled to the second word line, and the fourth voltage being less than the third voltage.

[0155] Among them, the description of the second word line, the third voltage, and the fourth voltage can refer to the description of the second word line, the third voltage, and the fourth voltage in the aforementioned embodiment, and the embodiments of the present application will not be repeated here.

[0156] In the memory 200 provided in the embodiment of the present application, a third voltage is applied to the second word line adjacent to the first word line in each of the first time periods, and a fourth voltage less than the third voltage is applied to the second word line in each of the second time periods. Since the second word line is coupled to the first word line in each of the second time periods (when the first word line is overcharged), the voltage of the second word line will actually increase. By reducing the voltage applied to the second word line in the second time period, the read-on voltage interference caused by the coupling of the second word line with the first word line is offset, and the ESUM and E0 of the storage unit coupled to the second word line are prevented from becoming smaller, thereby ensuring the data reliability of the memory 200.

[0157] In one possible implementation, the plurality of word lines further include a third word line, which is not adjacent to the first word line, and the peripheral circuit 230 is further configured to apply a fifth voltage to the third word line in each of the first time period and each of the second time period, and the fifth voltage is configured to turn on a storage unit coupled to the third word line.

[0158] Among them, the description of the third word line and the fifth voltage can refer to the description of the third word line and the fifth voltage in the aforementioned embodiment, and the embodiments of the present application will not be repeated here.

[0159] In the memory 200 provided in the embodiment of the present application, a fifth voltage is applied to a third word line not adjacent to the first word line, and the fifth voltage is configured to turn on the memory cell coupled to the third word line. In this way, the memory cell coupled to the third word line can be turned on, providing a basis for the bit line to detect the current.

[0160] The present application also provides a memory operation method. Fig.14 A schematic diagram of a memory operation method provided in an embodiment of the present application Figure 1 The memory 200 includes a peripheral circuit 220, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells is coupled to a word line, and the method can be applied to the peripheral circuit 220, and the method includes steps S110 and S120.

[0161] S110: In each of a plurality of first time periods, a first voltage is applied to a first word line among the plurality of word lines.

[0162] S120: In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, where the second voltage is configured to turn on a memory cell coupled to the first word line.

[0163] In a possible implementation manner, the second voltage applied in each second time period is equal.

[0164] In a possible implementation, the method further includes: before applying the first first voltage, applying a pre-pulse voltage to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

[0165] In a possible implementation, the method further includes: applying a recovery pulse voltage to the first word line after applying the last first voltage, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

[0166] In a possible implementation, the first voltage is configured to read data of a memory cell coupled to the first word line.

[0167] In a possible implementation, the first voltage is configured to verify data of a memory cell coupled to the first word line during programming.

[0168] In a possible implementation, the multiple first voltages increase sequentially.

[0169] In a possible implementation, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the method further includes: applying a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and applying a fourth voltage to the second word line in each of the second time periods, the fourth voltage being less than the third voltage.

[0170] In one possible implementation, the plurality of word lines further include a third word line, which is not adjacent to the first word line, and the method further includes: applying a fifth voltage to the third word line in each of the first time period and each of the second time period, and the fifth voltage is configured to turn on a storage unit coupled to the third word line.

[0171] The memory operation method provided in the embodiment of the present application can be applied to the above-mentioned memory 200 to realize the functions and effects of the above-mentioned memory 200. Since it has been described in detail in the aforementioned memory 200 embodiment, it will not be repeated here.

[0172] The present application also provides a memory operation method. Fig.15 A schematic diagram of a memory operation method provided in an embodiment of the present application Figure 2 The memory 200 includes a peripheral circuit 230, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells is coupled to a word line, and the method can be applied to the peripheral circuit 230, and the method includes steps S210 and S220.

[0173] S210: In each first time period of a plurality of first time periods, a first voltage is applied to a first word line among the plurality of word lines.

[0174] S220: In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage applied in each of the second time periods is equal.

[0175] In a possible implementation manner, the second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage.

[0176] In a possible implementation, the second voltage is configured to turn on a memory cell coupled to the first word line.

[0177] In a possible implementation, the method further includes: before applying the first first voltage, applying a pre-pulse voltage to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

[0178] In a possible implementation, the method further includes: applying a recovery pulse voltage to the first word line after applying the last first voltage, wherein the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

[0179] In a possible implementation, the first voltage is configured to read data of a memory cell coupled to the first word line.

[0180] In a possible implementation, the first voltage is configured to verify data of a memory cell coupled to the first word line during programming.

[0181] In a possible implementation, the multiple first voltages increase sequentially.

[0182] In a possible implementation, the plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the method further includes: applying a third voltage to the second word line in each of the first time periods, the third voltage being configured to turn on a memory cell coupled to the second word line, and applying a fourth voltage to the second word line in each of the second time periods, the fourth voltage being configured to turn on a memory cell coupled to the second word line, the fourth voltage being less than the third voltage.

[0183] In one possible implementation, the plurality of word lines further include a third word line, which is not adjacent to the first word line, and the method further includes: applying a fifth voltage to the third word line in each of the first time period and each of the second time period, and the fifth voltage is configured to turn on a storage unit coupled to the third word line.

[0184] The operating method of the memory 200 provided in the embodiment of the present application can be applied to the above-mentioned memory 200 to realize the functions and effects of the above-mentioned memory 200. Since it has been described in detail in the aforementioned memory 200 embodiment, it will not be repeated here.

[0185] The present application also provides a storage system. The structure of the storage system can refer to Figure 1 The storage system 10 in the embodiment includes a controller 100 and the memory 200 in the above embodiment. The number of the memory 200 can be one or more.

[0186] The controller 100 may at least include an interface (I / F) circuit, a read-only memory (ROM), a processing circuit, an accelerator, a buffer, an error checking and correcting engine, a flash controller circuit, and the like.

[0187] The memory 200 may include the peripheral circuit 220 or the peripheral circuit 230 in the above embodiment, and may also include a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line. The peripheral circuit 220 or the peripheral circuit 230 at least includes Figure 2The illustrated circuits include an input / output circuit 221, a control circuit 222, a register 223, a voltage generator 224, a row decoder 225, a column decoder 226, and a page buffer 227. The peripheral circuit 220 or the peripheral circuit 230 may be configured to receive a request from the controller 100, the request being used to indicate determining the data of the memory cell coupled to the first word line.

[0188] The storage system 10 provided in the embodiment of the present application can apply the above-mentioned memory 200 to realize the functions and effects of the above-mentioned memory 200. Since it has been described in detail in the aforementioned memory 200 embodiment, it will not be repeated here.

[0189] The present application also provides an electronic device. The structure of the electronic device can refer to Fig.16 The electronic device 30 may include a processor 20 and one or more Figure 1 The memory system 10 in the electronic device 30, the processor 20 and the memory system 10 may be coupled via a bus. The memory system 10 of the electronic device 30 may include the controller 100 and the memory 200, the memory 200 may include the peripheral circuit 220 or the peripheral circuit 230 in the above embodiment, and may also include multiple word lines and multiple rows of memory cells, each row of memory cells is coupled to a word line. The peripheral circuit 220 or the peripheral circuit 230 may be used to execute the corresponding method in the above method embodiment.

[0190] The electronic device 30 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0191] The electronic device 30 provided in the embodiment of the present application can apply the above-mentioned memory 200 to realize the functions and effects of the above-mentioned memory 200. Since it has been described in detail in the aforementioned memory 200 embodiment, it will not be repeated here.

[0192] Based on this understanding, an embodiment of the present application also provides a computer-readable storage medium containing instructions. The technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or a peripheral circuit 220 or a peripheral circuit 230 in a storage system to perform steps S110 and S120 in the method embodiment of the present application, as well as all or part of other corresponding method steps.

[0193] It should be understood that the "some embodiments" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0194] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0195] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0196] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0197] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately configured as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0198] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: The memory comprises a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, and the peripheral circuit is configured as follows: In each first time period of a plurality of first time periods, applying a first voltage to a first word line among the plurality of word lines; In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage is configured to turn on a memory cell coupled to the first word line.

2. The memory according to claim 1, characterized in that: The second voltage applied in each of the second time periods is equal.

3. The memory according to claim 1, characterized in that: The peripheral circuit is further configured as: Before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

4. The memory according to claim 1, characterized in that: The peripheral circuit is further configured as: After the last of the first voltages is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

5. The memory according to claim 1, characterized in that: The first voltage is configured to read data of a memory cell coupled to the first word line.

6. The memory according to claim 1, characterized in that: The first voltage is configured to verify data of a memory cell coupled to the first word line during programming.

7. The memory according to claim 1, characterized in that: The plurality of first voltages increase sequentially.

8. The memory according to claim 1, characterized in that: The plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the peripheral circuit is further configured as follows: Applying a third voltage to the second word line in each of the first time periods, wherein the third voltage is configured to turn on a memory cell coupled to the second word line; A fourth voltage is applied to the second word line in each of the second time periods, and the fourth voltage is lower than the third voltage.

9. The memory according to claim 1, characterized in that: The plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the peripheral circuit is further configured as: A fifth voltage is applied to the third word line in each of the first time periods and each of the second time periods, and the fifth voltage is configured to turn on a memory cell coupled to the third word line.

10. A memory, characterized in that: The memory comprises a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, and the peripheral circuit is configured as follows: In each first time period of a plurality of first time periods, applying a first voltage to a first word line among the plurality of word lines; In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage applied in each second time period is equal.

11. The memory according to claim 10, characterized in that: The second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage.

12. The memory according to claim 10, characterized in that: The second voltage is configured to turn on a memory cell coupled to the first word line.

13. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: Before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

14. The memory according to claim 10, characterized in that: The peripheral circuit is further configured as: After the last of the first voltages is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

15. The memory according to claim 10, characterized in that: The first voltage is configured to read data of a memory cell coupled to the first word line.

16. The memory according to claim 10, characterized in that: The first voltage is configured to verify data of a memory cell coupled to the first word line during programming.

17. The memory according to claim 10, characterized in that: The plurality of first voltages increase sequentially.

18. The memory according to claim 10, characterized in that: The plurality of word lines further include a second word line, the second word line being adjacent to the first word line, and the peripheral circuit is further configured as follows: Applying a third voltage to the second word line in each of the first time periods, wherein the third voltage is configured to turn on a memory cell coupled to the second word line; A fourth voltage is applied to the second word line in each of the second time periods, and the fourth voltage is lower than the third voltage.

19. The memory according to claim 10, characterized in that: The plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the peripheral circuit is further configured as: A fifth voltage is applied to the third word line in each of the first time periods and each of the second time periods, and the fifth voltage is configured to turn on a memory cell coupled to the third word line.

20. A method for operating a memory, characterized in that: The memory comprises a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, and the method comprises: In each first time period of a plurality of first time periods, applying a first voltage to a first word line among the plurality of word lines; In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage is configured to turn on a memory cell coupled to the first word line.

21. The method according to claim 20, characterized in that The second voltage applied in each of the second time periods is equal.

22. The method according to claim 20, characterized in that The method further comprises: Before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

23. The method according to claim 20, characterized in that The method further comprises: After the last of the first voltages is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

24. The method according to claim 20, characterized in that The plurality of first voltages increase sequentially.

25. The method according to claim 20, characterized in that The plurality of word lines further include a second word line, the second word line being adjacent to the first word line, the method further including: Applying a third voltage to the second word line in each of the first time periods, wherein the third voltage is configured to turn on a memory cell coupled to the second word line; A fourth voltage is applied to the second word line in each of the second time periods, and the fourth voltage is lower than the third voltage.

26. The method according to claim 20, characterized in that The plurality of word lines further include a third word line, the third word line is not adjacent to the first word line, and the method further includes: A fifth voltage is applied to the third word line in each of the first time periods and each of the second time periods, and the fifth voltage is configured to turn on a memory cell coupled to the third word line.

27. A method for operating a memory, characterized in that: The memory comprises a peripheral circuit, a plurality of word lines and a plurality of rows of memory cells, each row of memory cells being coupled to a word line, and the method comprises: In each first time period of a plurality of first time periods, applying a first voltage to a first word line among the plurality of word lines; In a second time period between every two adjacent first time periods in the plurality of first time periods, a second voltage is applied to the first word line, and the second voltage applied in each second time period is equal.

28. The method according to claim 27, characterized in that The second voltage applied in each of the second time periods is greater than any first voltage adjacent to the second voltage.

29. The method according to claim 27, characterized in that The second voltage is configured to turn on a memory cell coupled to the first word line.

30. The method according to claim 27, characterized in that The method further comprises: Before applying the first first voltage, a pre-pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the pre-pulse voltage.

31. The method according to claim 27, characterized in that The method further comprises: After the last of the first voltages is applied, a recovery pulse voltage is applied to the first word line, and the second voltage applied in at least one of the second time periods is equal to the recovery pulse voltage.

32. The method according to claim 27, characterized in that The plurality of first voltages increase sequentially.

33. The method according to claim 27, characterized in that The plurality of word lines further include a second word line, the second word line being adjacent to the first word line, the method further including: Applying a third voltage to the second word line in each of the first time periods, wherein the third voltage is configured to turn on a memory cell coupled to the second word line; A fourth voltage is applied to the second word line in each of the second time periods, and the fourth voltage is lower than the third voltage.

34. A storage system, characterized in that: The storage system comprises a controller and the memory according to any one of claims 1 to 9.

35. A storage system, characterized in that: The storage system comprises a controller and the memory according to any one of claims 10 to 19.

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