Methods to improve the morphology of polysilicon back etching

Abstract

This invention provides a method for improving the morphology of polysilicon after etch-back. The method includes providing a substrate, forming an epitaxial layer on the substrate, forming trenches in the trench gate device region and gate lead-out region of the epitaxial layer, forming a field oxide layer in the trenches and on the surface of the epitaxial layer, and then forming a gate polysilicon layer covering the trenches. A first etching is performed to etch the gate polysilicon layer down to the upper surface of the trenches, followed by the formation of an etching protection layer on the gate lead-out region. A second dry etching is performed, which is anisotropic polysilicon etch-back, resulting in a remaining gate polysilicon layer higher than a predetermined thickness after etching, with V-shaped cracks forming on the upper surface of the gate polysilicon layer. A third dry etching is performed, employing microwave reactive etching and utilizing microwave reactive etching to achieve isotropic etching, to etch the gate polysilicon layer down to the predetermined thickness. This invention improves the morphology of the gate polysilicon layer after etch-back, eliminating V-shaped cracks on the surface of the gate polysilicon layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the etch-back morphology of polysilicon. Background Technology

[0002] Existing polysilicon etch-back methods for SGT (trench gate) products include:

[0003] Step 1: Provide a substrate 101, form an epitaxial layer 102 on the substrate 101, form trenches in the trench gate device region and gate lead-out region on the epitaxial layer 102, form a field oxide layer 104 in the trenches and on the surface of the epitaxial layer 102, and then form a gate polysilicon layer 105 covering the trenches, forming as shown in the figure. Figure 1 The structure shown;

[0004] Step 2: Perform the first etching to etch the gate polysilicon layer 105 up to the upper surface of the trench, forming a shape as shown. Figure 6 The structure shown is followed by the formation of an etch protection layer 106 on the gate lead-out region, forming a structure as shown. Figure 2 The structure shown;

[0005] Step 3: Perform a second dry etching process. This second dry etching is anisotropic polysilicon back etching, ensuring that the remaining gate polysilicon layer 105 after etching is of a predetermined thickness, forming a layer as shown in the image. Figure 3 The structure shown.

[0006] Due to process evolution and the need for product iteration and upgrades, pitch size and trench CD are gradually decreasing, which is increasing the challenge of polysilicon filling in trenches.

[0007] Existing polysilicon etch-back techniques can generate polysilicon defects when the polysilicon filling density is insufficient, resulting in defects such as... Figure 3 The V-shaped crack shown leads to device failure due to IDSS (saturation drain current) / BV (breakdown voltage).

[0008] To address the aforementioned issues, a novel method for improving the morphology of polysilicon back-etching is needed. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the morphology of polysilicon back etching, which solves the problem that polysilicon back etching in the prior art will produce polysilicon defects and form V-shaped cracks when the polysilicon filling density is insufficient.

[0010] To achieve the above and other related objectives, the present invention provides a method for improving the etch-back morphology of polysilicon, comprising:

[0011] Step 1: Provide a substrate, form an epitaxial layer on the substrate, form trenches on the trench gate device region and gate lead-out region on the epitaxial layer, form a field oxide layer in the trenches and on the surface of the epitaxial layer, and then form a gate polysilicon layer covering the trenches.

[0012] Step 2: Perform the first etching to etch the gate polysilicon layer down to the upper surface of the trench, and then form an etch protection layer on the gate lead-out area.

[0013] Step 3: Perform a second dry etching process, which is anisotropic polysilicon back etching, so that the remaining gate polysilicon layer after etching is higher than the preset thickness, and a V-shaped crack is formed on the upper surface of the gate polysilicon layer.

[0014] Step 4: Perform a third dry etching process. The third dry etching process uses microwave reactive etching to achieve isotropic etching, so as to etch the gate polysilicon layer to a preset thickness, so that there are no V-shaped cracks on the gate polysilicon layer.

[0015] Preferably, step one further includes forming a trap region using ion implantation before forming the trench.

[0016] Preferably, the method for forming the etching protection layer in step two includes: forming a photoresist layer covering the gate polysilicon layer; and using photolithography to open the photoresist layer on the trench gate device region.

[0017] Preferably, the etching method in step two is dry etching.

[0018] Preferably, the remaining gate polysilicon layer in step three has a thickness of 1800 to 2200 angstroms higher than a preset thickness.

[0019] Preferably, the microwave reactive etching in step four has no radio frequency power, and the cavity pressure is 0.4 to 0.6 Torr.

[0020] Preferably, the etching gas in step four, the microwave reactive etching, is CF4 and O2, and the ratio of O2 is adjusted to control the reaction rate and etching selectivity.

[0021] Preferably, the gas flow rate of CF4 in step four is 25 to 35 sccm, and the gas flow rate of O2 in step four is 75 to 85 sccm.

[0022] Preferably, after etching the gate polysilicon layer to a preset thickness in step four, the etching loss of the field oxide layer is less than 50 angstroms.

[0023] Preferably, the method is used for the manufacture of power devices.

[0024] As described above, the method for improving the etch-back morphology of polysilicon according to the present invention has the following beneficial effects:

[0025] This invention can improve the morphology of the gate polysilicon layer after etching back, and the surface of the gate polysilicon layer is free of V-shaped cracks. Attached Figure Description

[0026] Figure 1 The diagram shows a schematic representation of the formation of a gate polysilicon layer using existing technology.

[0027] Figure 2 This is a schematic diagram of the first etching process in the prior art.

[0028] Figure 3 This is a schematic diagram of the second etching process in the prior art.

[0029] Figure 4 The diagram shown is a schematic representation of the process flow of the present invention.

[0030] Figure 5 The diagram shown illustrates the formation of the gate polysilicon layer according to the present invention.

[0031] Figure 6 The diagram shown is a schematic diagram of the first etching step of this invention.

[0032] Figure 7 This is a schematic diagram of the second dry etching process of the present invention.

[0033] Figure 8 This is a schematic diagram of the third dry etching process of the present invention. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] Please see Figure 4 The present invention provides a method for improving the morphology of polysilicon back etching, comprising:

[0036] Step 1: Provide a substrate 201, form an epitaxial layer 202 on the substrate 201, form trenches in the trench gate device region and gate lead-out region on the epitaxial layer 202, form a field oxide layer 204 in the trenches and on the surface of the epitaxial layer 202, and then form a gate polysilicon layer 205 covering the trenches, forming as shown in the figure. Figure 5 The structure shown;

[0037] In some embodiments, step one further includes forming a well region 203 by ion implantation before forming the trench.

[0038] Step 2: Perform the first etching to etch the gate polysilicon layer 205 up to the upper surface of the trench, forming a shape as shown. Figure 6 The structure shown is followed by the formation of an etch protection layer 206 on the gate lead-out region, forming a structure as shown. Figure 7 The structure shown;

[0039] In some embodiments, the method of forming the etch protection layer 206 in step two includes: forming a photoresist layer covering the gate polysilicon layer 205; and using photolithography to open the photoresist layer on the trench gate device region.

[0040] In some embodiments, the etching method in step two is dry etching.

[0041] Step 3: Perform a second dry etching process. This second dry etching is anisotropic polysilicon back etching, ensuring that the remaining gate polysilicon layer 205 after etching is higher than the preset thickness, forming a layer as shown in the image. Figure 8 The structure shown, for example, can have a preset thickness of about half the height of the trench; compared to the prior art which directly etches the gate polysilicon to a preset thickness, the present invention etches a gate polysilicon layer 205 of a certain thickness less.

[0042] In some embodiments, the remaining gate polysilicon layer 205 in step three has a thickness of 1800 to 2200 angstroms, for example, 2000 angstroms.

[0043] Step 4: Perform the third dry etching. The third dry etching uses microwave reactive etching to achieve isotropic etching, so as to etch the gate polysilicon layer 205 to the preset thickness. This can improve the morphology of the gate polysilicon layer 205. The surface of the gate polysilicon layer 205 has no V-shaped opening, so that there are no V-shaped cracks on the gate polysilicon layer 205.

[0044] In some embodiments, the microwave reactive etching in step four has no radio frequency power, and the cavity pressure is 0.4 to 0.6 Torr, for example 0.5 Torr.

[0045] In some embodiments, the etching gas in step four, microwave reactive etching, is CF4 and O2, and the ratio of O2 is adjusted to control the reaction rate and etching selectivity.

[0046] In some embodiments, the gas flow rate of CF4 in step four is 25 to 35 sccm, and the gas flow rate of O2 in step four is 75 to 85 sccm. For example, the gas flow rate of CF4 is 30 sccm, and the gas flow rate of O2 in step four is 80 sccm.

[0047] In some embodiments, after etching the gate polysilicon layer 205 to a preset thickness in step four, the etching loss of the field oxide layer 204 is less than 50 angstroms.

[0048] In some embodiments, the method is used for the manufacture of power devices.

[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] In summary, this invention improves the morphology of the gate polysilicon layer after etching back, eliminating V-shaped cracks on the gate polysilicon layer surface. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the morphology of polysilicon back etching, characterized in that, At least including: Step 1: Provide a substrate, form an epitaxial layer on the substrate, form trenches on the trench gate device region and gate lead-out region on the epitaxial layer, form a field oxide layer in the trenches and on the surface of the epitaxial layer, and then form a gate polysilicon layer covering the trenches. Step 2: Perform the first etching to etch the gate polysilicon layer down to the upper surface of the trench, and then form an etch protection layer on the gate lead-out area. Step 3: Perform a second dry etching process, which is anisotropic polysilicon back etching, so that the remaining gate polysilicon layer after etching is higher than the preset thickness, and a V-shaped crack is formed on the upper surface of the gate polysilicon layer. Step 4: Perform a third dry etching process. The third dry etching process uses microwave reactive etching to achieve isotropic etching, so as to etch the gate polysilicon layer to a preset thickness, so that there are no V-shaped cracks on the gate polysilicon layer.

2. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: Step one, before forming the trench, also includes the step of forming a trap region using ion implantation.

3. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The method for forming the etching protection layer in step two includes: forming a photoresist layer covering the gate polysilicon layer; and using photolithography to open the photoresist layer on the trench gate device region.

4. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The etching method described in step two is dry etching.

5. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The remaining gate polysilicon layer in step three has a thickness of 1800 to 2200 angstroms above a preset thickness.

6. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The microwave reactive etching in step four has no radio frequency power, and the cavity pressure is 0.4 to 0.6 Torr.

7. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The etching gases used in step four for microwave reactive etching are CF4 and O2. The ratio of O2 is adjusted to control the reaction rate and etching selectivity.

8. The method for improving the etch-back morphology of polysilicon according to claim 7, characterized in that: The gas flow rate of CF4 in step four is 25 to 35 sccm, and the gas flow rate of O2 in step four is 75 to 85 sccm.

9. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: In step four, after etching the gate polysilicon layer to a preset thickness, the etching loss of the field oxide layer is less than 50 angstroms.

10. The method for improving the etch-back morphology of polysilicon according to claim 1, characterized in that: The method is used for the manufacture of power devices.

Images