Method and structure for packaging hybrid pins of chip

Abstract

The invention discloses a hybrid pin packaging structure and packaging method of a chip, the packaging structure comprises a circuit substrate, a plurality of core particles and a circuit mounting seat, the front surface of the circuit substrate is provided with a plurality of bonding pads corresponding to pins of the core particles, the back surface of the circuit substrate is provided with a plurality of pins correspondingly and electrically connected with the pins, and the bonding pads are electrically connected with the pins. The pins comprise a high-current pin and a signal pin, the pin electrically connected with the high-current pin is a PGA pin, and the pin electrically connected with the signal pin is an LGA pin; the core particles are welded on the front surface of the circuit substrate and enable the pins of the chip to be electrically connected with the corresponding bonding pads; the circuit mounting seat is provided with a PGA pin slot corresponding to the position of the PGA pin and an LGA thimble corresponding to the position of the LGA pin. The circuit substrate is mounted on the circuit mounting base, the PGA pins are inserted into the PGA pin slots to form PGA packaging, and the LGA pins abut against the LGA ejector pins to form LGA packaging. According to the invention, under the condition that the packaging area is not increased, the requirements of a large-current and high-frequency interface of the chip can be better met.

Description

Technical Field

[0001] The present invention relates to a chip package, and in particular to a chip package that meets multiple functional characteristics. Background Art

[0002] The existing technical solutions use a single pin solution when designing chip packaging, and the mainstream ones are LGA, PGA, BGA, etc. The current passing capacity of different pin forms and the support for high-speed signals vary. Because the BGA chip pins are soldered to the circuit board, the flexibility of replacement and maintenance is relatively poor. The following are the main features of LGA and PGA package pins. For high-power chips with high-speed pin requirements, the packaging solution selection needs to make trade-offs:

[0003] 1.LGA, the chip pins are flat contacts, connected to the circuit board through the reed-shaped ejector pins of the socket. LGA can support smaller pin spacing and better support high-frequency signals than PGA. For example, the current Intel high-performance CPU chips all use LGA packaging, which can meet the speed support for PCIe 5.0.

[0004] 2.PGA, the chip pins are pin-type. The pins of PGA can be made thicker and more durable, so the current it can withstand is much larger than that of LGA pins, and the connection between the pins and the socket is more airtight. However, due to the high-frequency loss of the pin structure of PGA, its high-frequency characteristics are poor compared with LGA pins.

[0005] However, as the performance and production process of chips, especially large chips, continue to improve, the power consumption (or power density) of the chip main power supply increases, the power supply voltage decreases, and the corresponding power supply current increases accordingly. The chip needs to provide more power and ground pins, or improve the current flow capacity of a single chip pin to meet the demand for large current. To this end, the existing technology generally meets the demand for larger current by increasing the number of chip pins, or improving the current flow capacity of a single chip pin. Although this can meet the larger current, it obviously increases the cost and chip size.

[0006] Therefore, there is an urgent need for a mixed pin packaging method and packaging structure of a chip that can solve the above problems. Summary of the invention

[0007] The purpose of the present invention is to provide a mixed pin packaging method and packaging method of a chip, which can better meet the requirements of high current and high frequency interface of the chip without increasing the packaging area.

[0008] In order to achieve the above-mentioned purpose, the present invention provides a mixed pin packaging method for a chip, comprising: providing a plurality of core particles; providing a circuit substrate, the front side of the circuit substrate having a plurality of pads corresponding to the pins of the core particles, the back side of the circuit substrate having a plurality of pins electrically connected to the pins, the pins comprising high current pins and signal pins for transmitting signals, the pins electrically connected to the high current pins are set as PGA pins, and the pins electrically connected to the signal pins are set as LGA pins; providing a circuit mounting seat, the circuit mounting seat being provided with a PGA pin slot corresponding to the position of the PGA pin, and an LGA ejector pin corresponding to the position of the LGA pin; soldering the core particles to the front side of the circuit substrate and electrically connecting the pins of the chip to the corresponding pads; mounting the circuit substrate on the circuit mounting seat, and inserting the PGA pins into the PGA pin slots to form a PGA package, and the LGA pins abutting against the LGA ejector pins to form an LGA package.

[0009] Preferably, the pins further include low current pins, the pins electrically connected to the low current pins are configured as LGA pins, and the current requirement of the high current pins is greater than the current requirement of the low current pins. LGA can support smaller pin spacing, effectively reducing the packaging area without requiring high current and high power.

[0010] Specifically, the current demand of the high current pin exceeds a preset current value, and the current demand of the low current pin does not exceed the preset current value, and the preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin.

[0011] Preferably, the back side of the circuit substrate is divided into a first area and a second area, the PGA pins are arranged in the first area, the LGA pins are arranged in the second area, and the chip includes a core chip, and the core chip corresponds to the position of the first area.

[0012] Specifically, the first area is disposed at the center of the second area or the first area is disposed at four corners or around the second area.

[0013] Preferably, the circuit mounting seat has a recess for mounting the circuit substrate, and the PGA pin slot and LGA ejector pin are formed on a pin mounting plate at the bottom of the recess.

[0014] Preferably, the circuit substrate comprises a substrate body, the pads and circuits are formed on the front side of the substrate body, the PGA pins and the LGA pins are formed on the back side of the substrate body, and the circuits electrically connect the pads and the pins.

[0015] Preferably, the circuit substrate includes a first substrate body and a second substrate body, the first substrate body has the pad and the circuit formed on the front, the first substrate body has the first BGA pin and the LGA pin formed on the back, the second substrate body has a plurality of second BGA pins welded corresponding to the first BGA pins on the front, the second substrate body has a plurality of PGA pins on the back, and the first substrate body and the second substrate body are welded through the first BGA pin and the second BGA pin. This solution adopts POP (Package on Package) technology, and can update the circuit substrate of the existing LGA chip at a relatively low cost, thereby supporting this mixed pin solution.

[0016] The present invention also provides a mixed pin packaging structure of a chip, comprising a circuit substrate, a plurality of core particles and a circuit mounting seat, the front side of the circuit substrate having a plurality of solder pads corresponding to the pins of the core particles, the back side of the circuit substrate having a plurality of pins electrically connected to the pins, the pins comprising high current pins and signal pins for transmitting signals, the pins electrically connected to the high current pins are PGA pins, and the pins electrically connected to the signal pins are LGA pins; the core particles are soldered to the front side of the circuit substrate and the pins of the chip are electrically connected to the corresponding solder pads; the circuit mounting seat is provided with a PGA pin slot corresponding to the position of the PGA pin, and an LGA ejector pin corresponding to the position of the LGA pin; the circuit substrate is installed on the circuit mounting seat, and the PGA pins are inserted into the PGA pin slots to form a PGA package, and the LGA pins abut against the LGA ejector pins to form an LGA package.

[0017] Preferably, the pins further include a low current pin, the pin electrically connected to the low current pin is an LGA pin, and the current requirement of the high current pin is greater than the current requirement of the low current pin.

[0018] Specifically, the current demand of the high current pin exceeds a preset current value, and the current demand of the low current pin does not exceed the preset current value, and the preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin.

[0019] Preferably, the back side of the circuit substrate has a first area and a second area, the PGA pins are located in the first area, the LGA pins are located in the second area, and the chip comprises a core chip, and the core chip corresponds to the position of the first area.

[0020] Specifically, the first area is arranged at the center of the second area; the first area is arranged at four corners or four sides of the second area.

[0021] Preferably, the circuit mounting seat has a recess for mounting the circuit substrate, and the PGA pin slot and LGA ejector pin are formed on a pin mounting plate at the bottom of the recess.

[0022] Preferably, the circuit substrate comprises a substrate body, the pads and circuits are formed on the front side of the substrate body, the PGA pins and the LGA pins are formed on the back side of the substrate body, and the circuits electrically connect the pads and the pins.

[0023] Preferably, the circuit substrate includes a first substrate body and a second substrate body, the first substrate body has the pad and the circuit formed on the front, the first substrate body has the first BGA pin and the LGA pin formed on the back, the second substrate body has a plurality of second BGA pins welded corresponding to the first BGA pins on the front, the second substrate body has a plurality of PGA pins on the back, and the first substrate body and the second substrate body are welded through the first BGA pin and the second BGA pin. This solution adopts POP (Package on Package) technology, and can update the circuit substrate of the existing LGA chip at a relatively low cost, thereby supporting this mixed pin solution.

[0024] In the present invention, when performing chip packaging, a mixture of LGA pin packaging and PGA pin packaging is used. The advantages of LGA are used to package signal pins with high-frequency signal requirements to meet their high-frequency characteristics; the advantages of PGA are used to package signal pins with large current requirements to achieve a larger conduction current under the same packaging area, thereby better meeting the requirements for large current and high-frequency interfaces of the chip under the same packaging area. Furthermore, when the circuit mounting seat of the present invention is connected to the circuit substrate, the positioning accuracy, connection stability and reliability of the connection between the circuit mounting seat and the circuit substrate can be effectively increased by means of the pins and sockets of the PGA package. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 to Figure 2 It is a flow chart of the mixed pin packaging method of the chip in embodiment 1 of the present invention.

[0026] Figure 3 It is a structural diagram of the mixed pin packaging structure of the chip in Example 1 of the present invention.

[0027] Figure 4 It is a top view of the circuit substrate and the core particle after welding in the mixed pin packaging structure in Example 1 of the present invention.

[0028] Figure 5 It is a bottom view of the circuit substrate in the mixed pin packaging structure in Example 1 of the present invention.

[0029] Figure 6It is an exploded view of the mixed pin packaging structure in Example 2 of the present invention.

[0030] Figure 7 It is an assembly diagram of a circuit substrate and a circuit mounting seat in a mixed pin packaging structure in Example 2 of the present invention.

[0031] Figure 8 It is a top view of the circuit substrate and the core particle after welding in the mixed pin packaging structure in Example 3 of the present invention.

[0032] Fig. 9 It is a bottom view of the circuit substrate in the mixed pin packaging structure in Example 3 of the present invention.

[0033] Fig.10 It is a side view of the circuit substrate and the core particle after welding in the mixed pin packaging structure in Example 3 of the present invention.

[0034] Fig.11 It is an assembly diagram of a circuit substrate and a circuit mounting seat in a mixed pin packaging structure in Example 3 of the present invention.

[0035] Fig.12 It is a partial structural diagram of the mixed pin packaging structure in Example 4 of the present invention. DETAILED DESCRIPTION

[0036] In order to explain the technical content, structural features, achieved objectives and effects of the present invention in detail, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0037] Embodiment 1:

[0038] refer to Figures 1 to 3 The present invention discloses a mixed pin packaging method for a chip, comprising steps S1 to S4.

[0039] S1, provide a plurality of chiplets 10. In this embodiment, the chiplet 10 is a core chiplet, and the pins of the core chiplet include a power pin and a signal pin for transmitting a chip interface signal, and the signal pin includes a high-speed transmission end and a low-speed transmission end. The power pin includes a VCC pin (power supply pin) and a GND pin (ground pin).

[0040] S2, providing a circuit substrate 20, wherein the front side 201 of the circuit substrate 20 has a plurality of pads corresponding to the pins of the chip 10, and the back side 202 of the circuit substrate 20 has a plurality of pins electrically connected to the pins, wherein the power pins include high current pins as the main power supply of the chip to supply power to the chip, the pins electrically connected to the high current pins are set as PGA pins 21, and the pins electrically connected to the signal pins are set as LGA pins 22. Among them, the high current pins are the pins of the main power supply of the chip, which include VCC pins and GDN pins with high current requirements.

[0041] Preferably, the power pin further includes a low current pin, and the pin electrically connected to the low current pin is set as an LGA pin 22. LGA can support a smaller pin spacing, effectively reducing the package area without requiring high current and high power. The current demand of the high current pin is greater than the current demand of the low current pin.

[0042] The current demand of the high current pin exceeds the preset current value, the current demand of the low current pin does not exceed the preset current value, and the preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin. In this embodiment, the preset current value is 50% of the current limit value of the LGA pin, the current demand value of the high current pin is greater than 50% of the current limit value of the LGA pin, and the current demand value of the low current pin is less than or equal to 50% of the current limit value of the LGA pin.

[0043] The back surface 202 of the circuit substrate 20 is divided into a first area 301 and a second area 302 . The PGA pins 21 are disposed in the first area 301 , and the LGA pins 22 are disposed in the second area 302 .

[0044] The circuit substrate 20 is designed according to the number of core particles 10, the type of pins, and the number of lead pins in the chip design drawing. The design steps are: the pins electrically connected to the high current pins are set as PGA pins 21, and the pins electrically connected to the signal pins are set as LGA pins 22; the back side 202 of the circuit substrate 20 is divided into a first area 301 and a second area 302 according to the number of PGA pins 21 and LGA pins 22, the PGA pins 21 are set in the first area 301, and the LGA pins 22 are set in the second area 302; the line structure and via design between the pins are designed so that the pins are electrically connected to the corresponding pins. Then the circuit substrate 20 is manufactured according to the design drawing of the circuit substrate 20.

[0045] refer to Figure 4 and Figure 5 If the core particle 10 has a plurality of core particles 10, the plurality of core particles 10 are arranged at intervals in the middle of the circuit substrate 20, and the first region 301 is arranged at the center of the second region 302. Of course, the present invention is not limited to the above embodiment, and the layout structure of the core particles 10 on the front side 201 of the circuit substrate 20 can also be arranged according to the requirements.

[0046] Therefore, during design, the core chip 10 is generally located at a position corresponding to the first area 301 , so that the PGA pin 21 can meet the high current / high power requirements of the core chip 10 .

[0047] S3, provide a circuit mounting seat 30, the circuit mounting seat 30 is provided with a recess for mounting the circuit substrate 20, a PGA pin slot 31 corresponding to the position of the PGA pin 21 and an LGA pin 32 corresponding to the LGA pin 22 are formed on the pin mounting plate at the bottom of the recess.

[0048] S4, soldering the chip 10 to the front side 201 of the circuit substrate 20 and electrically connecting the pins of the chip to the corresponding pads.

[0049] S5, the circuit substrate 20 is installed in the recess of the circuit mounting seat 30, and the PGA pin 21 is inserted into the PGA pin slot 31 to form a PGA package, and the LGA pin 22 is abutted against the LGA ejector pin 32 to form an LGA package

[0050] Of course, steps S1, S2 and S3 can be performed simultaneously or interchangeably. Steps S4 and S5 can be interchangeably performed.

[0051] In this embodiment, the circuit substrate 20 includes a substrate body, the front side 201 of the substrate body is formed with the pads and circuits, the back side 202 of the substrate body is formed with the PGA pins 21 and the LGA pins 22, and the circuits electrically connect the pads and pins.

[0052] refer to Figures 3 to 5 The present invention also discloses a mixed pin packaging structure of a chip, including a circuit substrate 20, a plurality of core particles 10 and a circuit mounting seat 30, wherein the front side 201 of the circuit substrate 20 has a plurality of pads corresponding to the pins of the core particles 10, and the back side 202 of the circuit substrate 20 has a plurality of pins electrically connected to the pins, wherein the pins include high current pins and signal pins for transmitting signals, wherein the pins electrically connected to the high current pins are PGA pins 21, and the pins electrically connected to the signal pins are LGA pins 22; the core particles 10 are soldered to the front side 201 of the circuit substrate 20. 1 and electrically connect the pins of the chip with the corresponding pads; the circuit mounting seat 30 is provided with a recess for mounting the circuit substrate 20, and a PGA pin slot 31 corresponding to the position of the PGA pin 21 and an LGA ejector pin 32 corresponding to the LGA pin 22 are formed on the pin mounting plate at the bottom of the recess; the circuit substrate 20 is mounted in the recess of the circuit mounting seat 30, and the PGA pin 21 is inserted into the PGA pin slot 31 to form a PGA package, and the LGA pin 22 is abutted against the LGA ejector pin 32 to form an LGA package. The high current pin serves as the main power supply of the chip to power the chip.

[0053] Preferably, the pins further include a low current pin, and the pin electrically connected to the low current pin is an LGA pin 22. The low current pin includes a VCC pin (power supply pin) and a GND pin (ground pin) with low current or low power requirements. The low current pin and the high current pin are both power pins, and the current requirement of the high current pin is greater than the current requirement of the low current pin.

[0054] The current demand of the high current pin exceeds the preset current value, the current demand of the low current pin does not exceed the preset current value, and the preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin. In this embodiment, the preset current value is 50% of the current limit value of the LGA pin, the current demand value of the high current pin is greater than 50% of the current limit value of the LGA pin, and the current demand value of the low current pin is less than or equal to 50% of the current limit value of the LGA pin.

[0055] Preferably, the back side 202 of the circuit substrate 20 has a first area 301 and a second area 302 , the PGA pins 21 are located in the first area 301 , and the LGA pins 22 are located in the second area 302 .

[0056] If the core particle 10 has a plurality of core core particles 10 , the plurality of core core particles 10 are disposed at intervals in the middle of the circuit substrate 20 , and the first region 301 is disposed at the center of the second region 302 .

[0057] refer to Figure 3 The circuit substrate 20 includes a substrate body, the pads and circuits are formed on the front side 201 of the substrate body, the PGA pins 21 and the LGA pins 22 are formed on the back side 202 of the substrate body, and the circuits electrically connect the pads and pins.

[0058] Embodiment 2:

[0059] refer to Figure 7Different from the embodiment 1, in the embodiment 2, the circuit substrate includes a first substrate body 20a and a second substrate body 20b, the first substrate body 20a has the pad and the circuit formed on the front 201, the first substrate body 20a has the first BGA pin 241 and the LGA pin 22 formed on the back 202, the second substrate body 20b has a plurality of second BGA pins 242 soldered corresponding to the first BGA pin 241 on the front 201, the second substrate body 20b has a plurality of PGA pins 21 on the back 202, and the first substrate body 20a and the second substrate body 20b are soldered through the first BGA pin 241 and the second BGA pin 242. This solution adopts POP (Package on Package) technology, and the circuit substrate 20 of the existing LGA chip can be updated at a relatively low cost, thereby supporting this mixed pin solution.

[0060] Embodiment 3:

[0061] refer to Figures 8 to 11 , different from Example 1, in Example 3, the core particles include an interface core particle 11 for performing signal interface transmission and a plurality of core core particles 12 for performing core calculations.

[0062] On the front side 201 of the circuit substrate 20, the core chip 12 is arranged adjacent to the corresponding position of the PGA pin 21, and the interface chip 11 is arranged adjacent to the corresponding position of the LGA pin 22. In this embodiment, the first region 301 is arranged at the four corners of the second region 302, the core chip 12 is located at the four corners of the front side 201 of the circuit substrate 20, and the interface chip 11 is located in the middle of the front side 201 of the circuit substrate 20. Of course, the first region 301 can also be located around the second region 302, and the core chip 12 is located around the interface chip 11.

[0063] The better, reference Fig.12 Different from Example 3, in Example 4, the circuit substrate 20 includes a first substrate body 20a and a second substrate body 20b, the first substrate body 20a has the pad and the circuit formed on the front 201, the first substrate body 20a has the first BGA pin 241 and the LGA pin 22 formed on the back 202, the second substrate body 20b has a plurality of second BGA pins 242 welded corresponding to the first BGA pin 241 on the front 201, the second substrate body 20b has a plurality of PGA pins 21 on the back 202, and the first substrate body 20a and the second substrate body 20b are welded through the first BGA pin and the second BGA pin.

[0064] In this embodiment, the core chip 12 is a CCD (Core Complex Die), which is a small chip of the Core, and the interface chip 11 is an IO Die, which is a small chip of the chip interface signal.

[0065] Among them, the LGA chip pins are planar contacts, which are connected to the circuit board through the reed-shaped ejector pins of the mounting socket. LGA can support smaller pin spacing and better support high-frequency signals than PGA. For example, the current Intel high-performance CPU chips all use LGA packaging, which can meet the rate support for PCIe 5.0. The PGA chip pins are pin-type. The pins of PGA can be made thicker and more durable, so the current it can withstand is much larger than that of LGA pins, and the connection between the pins and the mounting socket is more airtight, but because the high-frequency loss of the PGA pin structure is relatively high, compared with the LGA pins, its high-frequency characteristics are poor. The present invention mixes LGA chip pins and PGA chip pins when packaging the chip, combining the advantages of the two, so that the packaged chip can meet the requirements of large current and high-power input and output, and can also meet the transmission of high-frequency signals without increasing the pin area.

[0066] The above disclosure is only the preferred embodiment of the present invention, which certainly cannot be used to limit the scope of rights of the present invention. Therefore, equivalent changes made according to the scope of the patent application of the present invention are still within the scope covered by the present invention.

Claims

1. A mixed pin packaging method for a chip, characterized in that: include: Providing a number of core particles; A circuit substrate is provided, wherein the front side of the circuit substrate has a plurality of pads corresponding to the pins of the core particle, and the back side of the circuit substrate has a plurality of pins electrically connected to the pins, wherein the pins include high current pins and signal pins for transmitting signals, the pins electrically connected to the high current pins are set as PGA pins, and the pins electrically connected to the signal pins are set as LGA pins; Providing a circuit mounting seat, wherein the circuit mounting seat is provided with a PGA pin slot corresponding to the position of the PGA pin and an LGA ejector pin corresponding to the position of the LGA pin; Soldering the chip to the front side of the circuit substrate and electrically connecting the pins of the chip to the corresponding pads; The circuit substrate is mounted on the circuit mounting seat, and the PGA pins are inserted into the PGA pin slots to form a PGA package, and the LGA pins are abutted against the LGA ejector pins to form an LGA package.

2. The hybrid pin packaging method according to claim 1, wherein: The pins further include low current pins, and the pins electrically connected to the low current pins are set as LGA pins. The current requirement of the high current pins is greater than the current requirement of the low current pins.

3. The mixed pin packaging method according to claim 2, wherein: The current demand of the high current pin exceeds a preset current value, and the current demand of the low current pin does not exceed the preset current value. The preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin.

4. The mixed pin packaging method according to claim 1, wherein: The back side of the circuit substrate is divided into a first area and a second area, the PGA pins are arranged in the first area, and the LGA pins are arranged in the second area; the chip comprises a core chip, and the core chip corresponds to the position of the first area.

5. The mixed pin packaging method according to claim 1, wherein: The circuit substrate comprises a substrate body, the pads and the circuits are formed on the front side of the substrate body, the PGA pins and the LGA pins are formed on the back side of the substrate body, and the circuits are electrically connected to the pads and the pins; or, The circuit substrate includes a first substrate body and a second substrate body, the solder pad and the circuit are formed on the front side of the first substrate body, the first BGA pin and the LGA pin are formed on the back side of the first substrate body, the front side of the second substrate body has a plurality of second BGA pins welded corresponding to the first BGA pins, the back side of the second substrate body has a plurality of PGA pins, and the first substrate body and the second substrate body are welded through the first BGA pins and the second BGA pins.

6. A mixed pin packaging structure of a chip, characterized in that: The circuit substrate comprises a circuit substrate, a plurality of core particles and a circuit mounting seat, wherein the front side of the circuit substrate has a plurality of pads corresponding to the pins of the core particles, and the back side of the circuit substrate has a plurality of pins electrically connected to the pins, wherein the pins include high current pins and signal pins for transmitting signals, the pins electrically connected to the high current pins are PGA pins, and the pins electrically connected to the signal pins are LGA pins; The core particle is welded to the front side of the circuit substrate and the pins of the chip are electrically connected to the corresponding pads; The circuit mounting seat is provided with a PGA pin slot corresponding to the position of the PGA pin and an LGA ejector pin corresponding to the position of the LGA pin; The circuit substrate is mounted on the circuit mounting seat, and the PGA pins are inserted into the PGA pin slots to form a PGA package, and the LGA pins are abutted against the LGA ejector pins to form an LGA package.

7. The hybrid pin package structure according to claim 6, wherein: The pins further include low current pins, and the pins electrically connected to the low current pins are set as LGA pins. The current requirement of the high current pins is greater than the current requirement of the low current pins.

8. The mixed pin packaging method according to claim 7, wherein: The current demand of the high current pin exceeds a preset current value, and the current demand of the low current pin does not exceed the preset current value. The preset current value is between two-fifths and one-fifth to three-fifths of the current limit value of the LGA pin.

9. The hybrid pin package structure according to claim 6, wherein: The back side of the circuit substrate has a first area and a second area, the PGA pins are located in the first area, and the LGA pins are located in the second area; The core particles include a core core particle, and the core core particle corresponds to the position of the first region.

10. The mixed pin package structure according to claim 6, wherein: The circuit substrate comprises a substrate body, the pads and the circuits are formed on the front side of the substrate body, the PGA pins and the LGA pins are formed on the back side of the substrate body, and the circuits are electrically connected to the pads and the pins; or, The circuit substrate includes a first substrate body and a second substrate body, the solder pad and the circuit are formed on the front side of the first substrate body, the first BGA pin and the LGA pin are formed on the back side of the first substrate body, the front side of the second substrate body has a plurality of second BGA pins welded corresponding to the first BGA pins, the back side of the second substrate body has a plurality of PGA pins, and the first substrate body and the second substrate body are welded through the first BGA pins and the second BGA pins.

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