Wafer test piece and wafer measurement method

Abstract

The invention provides a wafer test piece and a wafer measurement method. The wafer test piece comprises a substrate, a protection layer and at least one layer of test structure, wherein the protection layer and the at least one layer of test structure are sequentially formed on the substrate; and the test structure comprises a barrier layer and an oxide layer which are stacked from bottom to top. In the process of executing the wafer measurement method, only the ion implantation technology needs to be executed on the oxide layer of the test structure located on the top layer, and relevant parameters are measured according to the ion implantation technology. Wherein both the barrier layer and the protective layer can prevent high-energy ions from being injected into the substrate, so that the whole measurement process has no direct influence on the substrate, the substrate or the substrate and a partial layer test structure on the top surface of the substrate can be recycled, and the measurement cost is effectively reduced. In addition, the arrangement of the test structure can also reduce the difference between the parameter front values of the wafer substrates, and facilitates the improvement of the precision of a measurement result.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a wafer testing piece and a wafer measuring method. Background Art

[0002] Ion implantation (Implant, IMP) is a commonly used processing technology in the preparation of integrated circuits. It is to ionize, accelerate and filter the doped atoms to select the target ions, and then inject the target ions into the wafer according to a specific depth and concentration distribution to achieve material modification of the wafer. However, in the actual process, due to the different ion implantation doses and energies, the wafer will be damaged to varying degrees. Therefore, it is necessary to use thermal waves (Thermal waves, TW) to measure the degree of change in the surface damage of the wafer, and to infer the changes in the parameters related to ion implantation based on this.

[0003] However, there are some differences in the previous parameter values ​​of wafers from different batches and the same batch, which will inevitably lead to large deviations in the measurement results and fail to accurately reflect the changes in ion implantation-related parameters. In this regard, the existing process uses bare wafers for measurement. However, if bare wafers are directly ion implanted and then measured, the bare wafers cannot be reused and can only be scrapped, resulting in serious cost waste.

[0004] Therefore, a new wafer measurement method is urgently needed to solve the above technical problems. Summary of the invention

[0005] The object of the present invention is to provide a wafer test piece and a wafer measurement method to solve at least one of the problems of how to improve measurement accuracy and how to reduce measurement cost.

[0006] In order to solve the above technical problems, the present invention provides a wafer measurement method, comprising:

[0007] Step 1: providing a wafer test piece, the wafer test piece comprising a substrate, a protection layer and at least one test structure formed in sequence on the substrate; wherein the test structure comprises a barrier layer and an oxide layer stacked from bottom to top;

[0008] Step 2: performing an ion implantation process on the oxide layer located on the top surface of the wafer test piece;

[0009] Step three: performing parameter measurement on the oxide layer after the ion implantation process.

[0010] Optionally, in the wafer measurement method, after executing step three, the oxide layer located on the top surface of the wafer test piece is removed to expose the adjacent barrier layer; and a layer of oxide layer is re-formed on the surface of the exposed adjacent barrier layer to form a new wafer test piece.

[0011] Optionally, in the wafer measurement method, after executing step three, the at least one layer of the test structure and the protective layer are removed in sequence to expose the substrate; and the protective layer and at least one layer of the test structure are re-formed in sequence on the surface of the substrate to serve as a new wafer test piece.

[0012] Optionally, in the wafer measurement method, the wafer test piece includes multiple layers of the test structure, and after executing step three, some layers of the test structure are removed, and the substrate, the protective layer formed in sequence on the substrate, and the remaining test structure are used as a new wafer test piece.

[0013] Optionally, in the wafer measurement method, the wafer test piece includes multiple layers of the test structure, and after executing the step three, some layers of the test structure are removed; and at least one layer of the test structure is formed on the top surface of the remaining test structure to form a new wafer test piece.

[0014] Optionally, in the wafer measurement method, after executing step three, the wafer measurement method further includes:

[0015] Step 4: Adjust ion implantation process parameters;

[0016] Step 5: Repeat steps 1 to 4 until the parameter measurement is completed for a preset number of times.

[0017] Optionally, in the wafer measurement method, the material of the protection layer and the oxide layer both include silicon dioxide; and the material of the barrier layer includes amorphous silicon.

[0018] Optionally, in the wafer measurement method, in step three, the measurement parameters include thermal wave values.

[0019] Based on the same inventive concept, the present invention also provides a wafer test piece, which includes a substrate and a protective layer and at least one test structure formed in sequence on the substrate; wherein the test structure includes a barrier layer and an oxide layer stacked from bottom to top.

[0020] Optionally, in the wafer test piece, the materials of the protection layer and the oxide layer both include silicon dioxide; and the material of the barrier layer includes amorphous silicon.

[0021] In summary, the present invention provides a wafer test piece and a wafer measurement method. Compared with the prior art, the wafer test piece provided by the present invention includes a substrate, a protective layer and at least one test structure sequentially formed on the substrate; wherein the test structure includes a barrier layer and an oxide layer stacked from bottom to top. And in the process of executing the wafer measurement method, it is only necessary to perform an ion implantation process on the oxide layer of the test structure located on the top layer, and measure the relevant parameters accordingly. Among them, both the barrier layer and the protective layer can block high-energy ions from being implanted into the substrate, so the entire measurement process has no direct impact on the substrate, and thus the substrate or the substrate and the partial layer test structure on its top surface can be recycled, effectively reducing the measurement cost. In addition, the setting of the test structure can also reduce the difference in the previous values ​​of the parameters of each wafer substrate, which is conducive to improving the accuracy of the measurement results. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Those skilled in the art will appreciate that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0023] Figure 1 4 is a flow chart of a wafer measurement method in an embodiment of the present invention.

[0024] Figure 2 Schematic diagram of the structure of a wafer test piece with a single-layer test structure in an embodiment of the present invention.

[0025] Figure 3 Schematic diagram of the structure of a wafer test piece with a multi-layer test structure in an embodiment of the present invention.

[0026] Figure 4 Schematic diagram of performing ion implantation on the top oxide layer in an embodiment of the present invention.

[0027] Figure 5 It is a schematic diagram of the structure after removing the top oxide layer in the first recycling example in an embodiment of the present invention.

[0028] Figure 6 It is a schematic diagram of the structure after removing the film layer on the substrate in the second reuse example in an embodiment of the present invention.

[0029] Figure 7 1 is a schematic diagram of the structure of a wafer test piece with a two-layer test structure in an embodiment of the present invention.

[0030] Figure 8 It is a schematic diagram of performing ion implantation after removing a part of the layer test structure according to the third reuse example in an embodiment of the present invention.

[0031] Fig. 94 is a schematic diagram of performing ion implantation after forming a new test structure according to the fourth reuse example in an embodiment of the present invention.

[0032] Fig.10 1 is a comparison chart of the initial thermal wavefront values ​​and the thermal wavefront values ​​after processing of five types of wafer test pieces in an embodiment of the present invention.

[0033] Fig.11 It is a comparison chart of the post-thermal wave values ​​of five types of wafer test pieces after corresponding types of ion implantation in an embodiment of the present invention.

[0034] Fig.12 It is a measurement comparison diagram of the wafer testing method in the embodiment of the present invention and the prior art testing method.

[0035] And, in the attached drawings:

[0036] 10 - substrate; 11 - protective layer; 12 - test structure; 120 - barrier layer; 121 - oxide layer; 121 ' - detection film layer. DETAILED DESCRIPTION

[0037] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different proportions are used. It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish between the various components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0038] See also Figure 1 , this embodiment provides a wafer measurement method, including:

[0039] Step 1 S10: providing a wafer test piece, the wafer test piece comprising a substrate, a protection layer and at least one test structure formed in sequence on the substrate; wherein the test structure comprises a barrier layer and an oxide layer stacked from bottom to top;

[0040] Step 2 S20: performing an ion implantation process on the oxide layer located on the top surface of the wafer test piece;

[0041] Step three S30: performing parameter measurement on the oxide layer after the ion implantation process.

[0042] It can be understood that the wafer measurement method provided in this embodiment is to form at least one test structure on the basis of the wafer substrate, and use the oxide layer in the test structure as the detection film layer for parameter measurement. That is, ion implantation is performed on the oxide layer, and then parameter measurement is performed. And under the joint action of the protective layer and the barrier layer in the test structure, it is difficult for ions in the ion implantation process to penetrate into the substrate. Therefore, during the entire measurement process, at least the wafer substrate is not affected, and can be recycled, which greatly reduces the measurement cost. In addition, the setting of the test structure can also reduce the difference in the previous parameter values ​​of each wafer substrate, which is conducive to improving the accuracy of the measurement results.

[0043] The following is combined with Figures 1 to 12 , specifically illustrate the wafer measurement method provided in this embodiment.

[0044] Step 1 S10: Please refer to Figure 2 and Figure 3 , providing a wafer test piece, the wafer test piece includes a substrate 10 and a protection layer 11 and at least one test structure 12 sequentially formed on the substrate 10; wherein the test structure 12 includes a barrier layer 120 and an oxide layer 121 stacked from bottom to top.

[0045] It should be noted that the substrate 10 is any base material for carrying semiconductor integrated circuit components known to those skilled in the art, and may be a bare chip or a wafer processed by an epitaxial growth process. Also, the substrate 10 includes but is not limited to a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, or a germanium-on-insulator substrate. Furthermore, in order to avoid damage to the substrate 10 caused by the measurement process, the wafer test piece provided in this embodiment needs to be stacked in sequence on the substrate 10 with a protective layer 11 and at least one test structure 12, so as to perform parameter measurement using the test structure 12. Preferably, the protective layer 11 is a silicon dioxide layer. On the one hand, the silicon dioxide layer can isolate the substrate 10 from the test structure 12 to protect the substrate 10; on the other hand, the silicon dioxide layer can repair the unevenness on the surface of the substrate 10 and improve the flatness of the substrate 10; that is, the top surface of the protective layer 11 has better flatness, which is conducive to forming the test structure 12 with better morphology.

[0046] Furthermore, this embodiment does not limit the specific number of layers of the test structure 12. Figure 2 As shown, only one layer of the test structure 12 is formed on the protective layer 11; Figure 3As shown, a plurality of layers of the test structure 12 are formed on the protective layer 11, and the plurality of layers of the test structure 12 are stacked in sequence. Preferably, each layer of the test structure 12 includes a barrier layer 120 and an oxide layer 121 stacked from bottom to top. Among them, the material of the barrier layer 120 includes amorphous silicon. Amorphous silicon is a disordered silicon material, which can not only effectively block high-energy ions and avoid irreversible damage to the substrate 10 caused by high-energy ions during subsequent ion implantation processes, but also serve as a growth substrate for the oxide layer 121 to ensure the stability of the film structure. In addition, amorphous silicon also has the advantage of low cost. The material of the oxide layer 121 includes silicon dioxide. Silicon dioxide not only has a low preparation cost, but also has good process compatibility. When measuring parameters for the ion implantation process, precise control of ion implantation and precise presentation of implantation distribution can be achieved, which is conducive to improving measurement accuracy.

[0047] It should be noted that the one or more layers of the test structure 12 formed on the substrate 10 can not only avoid the impact on the substrate 10 and realize the recycling of the substrate 10, but also effectively reduce the previous value difference of the measurement parameters between different wafer substrates 10, so as to reduce the initial parameter difference between each wafer test piece performing parameter measurement, which is conducive to improving the measurement accuracy.

[0048] Step 2 S20: Please refer to Figure 2 and Figure 4 , performing an ion implantation process on the oxide layer 121 located on the top surface of the wafer test piece.

[0049] In other words, according to the test requirements, the oxide layer 121 in the test structure 12 located at the top layer is subjected to an ion implantation process with a preset concentration and a preset distribution. Based on this, after the ion implantation, the oxide layer 121 located at the top layer forms a detection film layer 121' with a specific ion distribution. And based on the blocking effect of the blocking layer 120 and the protective layer 11, or the common blocking effect of the blocking layer 120, the protective layer 11 and other layers of the test structure 12, the ion implantation process in step 2 S20 will not affect the substrate 10, which is conducive to the recycling of wafers. In addition, this embodiment does not limit the specific process parameters such as ion concentration and implantation energy in the ion implantation process, nor does it specifically limit the type of ions, which can be N-type ions or P-type ions.

[0050] Step 3 S30: Please refer to Figure 2 and Figure 4, perform parameter measurement on the oxide layer 121 after the ion implantation process. That is, perform parameter measurement on the detection film layer 121' located on the top layer of the wafer test piece. Optionally, the parameter measurement includes but is not limited to thermal wave measurement, that is, the measurement parameter includes a thermal wave value.

[0051] It should be noted that in order to obtain the correlation between process parameters and measurement parameters such as thermal wave values ​​in the ion implantation process, it is necessary to perform ion implantation with different process parameters on multiple wafer test pieces, and then measure the relevant parameters of each wafer test piece. Therefore, based on the fact that at least one layer of the test structure 12 is provided on the substrate 10 in the wafer test piece, the measurement process does not affect the substrate 10, and the substrate 10 can be recycled and reused. Therefore, the wafer measurement method provided in this embodiment can use the wafer test piece after recycling to perform multiple measurements. That is, multiple ion implantations and parameter measurements can be completed using only the same or several wafer test pieces, which greatly reduces the measurement cost.

[0052] Further, the reuse process of the wafer test piece after executing step 3 S30 includes the following four exemplary implementation methods. Figure 2 and Figure 5 In the first example, since step 2 S20 only performs ion implantation on the oxide layer 121 in the test structure 12 located at the top layer, other film layers are not affected by the ion implantation. Therefore, a dry or wet process can be used to remove the oxide layer 121 after ion implantation to form Figure 5 The semiconductor structure shown. After the oxide layer 121 that has been ion-implanted is removed, the barrier layer 120 in the test structure 12 that is also located at the top layer is exposed, and a new oxide layer 121 is regrown on the surface of the exposed barrier layer 120, which can be recombined with the adjacent barrier layer 120 to form a new test structure 12. Therefore, the first example is to reuse the film layers below the oxide layer 121 that has been ion-implanted, so that the wafer test piece with the new test structure 12 can be used as a new wafer test piece to perform new ion implantation and parameter measurement.

[0053] See also Figure 2 , Figure 3 and Figure 6 Although the ion implantation process in step 20 is only for the oxide layer 121 located at the top layer, the film layers below it may also be implanted with high-energy ions. Therefore, in order to improve the accuracy of the detection, in the second example, all film layers located on the substrate 10 can be removed. That is, the test structure 12 and the protective layer 11 are removed in turn by a dry or wet process, and only the film layers 121 are exposed. Figure 6The substrate 10 shown in FIG. Based on this, a new protective layer 11 and at least one layer of the test structure 12 are sequentially formed on the substrate 10 to serve as a new wafer test piece. Therefore, the second example is to reuse the substrate 10 so that the wafer test piece with the new test structure 12 and the protective layer 11 can be used as a new wafer test piece to perform new ion implantation and parameter measurement.

[0054] It should be noted that the above two examples of the method of reusing the wafer test piece are not only applicable to the wafer test piece with only one layer of the test structure 12, but also applicable to the wafer test piece with multiple layers of the test structure 12. The third and fourth methods of reusing the wafer test piece are applicable to the wafer test piece with two or more layers of the test structure 12. For details, please refer to Figure 7 and Figure 8 In the third example, assuming that the wafer test piece is Figure 7 As shown in FIG. 1 , two layers of the test structure 12 are formed. After executing step 3 S30, the test structure 12 located at the top layer is easily affected by high-energy ions. Therefore, the test structure 12 located at the top layer can be directly removed to obtain the following Figure 8 The wafer test piece shown. Figure 8 The wafer test piece shown includes the substrate 10, the protective layer 11 formed in sequence on the substrate 10, and the remaining layer of the test structure 12, which can constitute a complete wafer test piece, so all the film layers after removal are directly used as a new wafer test piece to perform new ion implantation and parameter measurement. Similarly, when the wafer test piece provided in step one S10 includes three, four or more layers of the test structure 12, after executing step three S30, the top layer of the test structure 12 can be removed, or more layers of the test structure 12 at and below the top layer can be removed, and part of the test structure 12 can be retained, and the remaining test structure 12, the protective layer 11 and the substrate 10 can be reconstituted into a new wafer test piece to perform new ion implantation and parameter measurement. Based on this, when the wafer test piece provided in step 1 S10 includes the test structure 12 with a large number of layers, the test structure 12 can be removed layer by layer according to each wafer measurement process, which not only can realize the reuse of the wafer test piece but also has high process implementation efficiency.

[0055] See also Figure 7 and Fig. 9In the fourth example, based on the removal of part of the layers of the test structure 12 in the third example, one or more layers of the test structure 12 can be re-formed on the top surface of the remaining test structure 12 exposed after the removal to form a new wafer test piece, so that each time the wafer measurement process is performed, the number of layers of the test structure 12 in the wafer test piece provided in step 1 S10 is the same or similar, thereby avoiding the difference in the number of layers of the test structure 12 affecting the measurement accuracy.

[0056] Further, according to the wafer test piece after the reuse process, the steps 4 and 5 of the wafer measurement method after the step 3 S30 are continued to be performed, specifically:

[0057] Step 4: Adjusting ion implantation process parameters, wherein the ion implantation process parameters include but are not limited to ion type, ion dose, and implantation energy, etc., and single variable or multi-variable adjustment can be performed according to measurement needs.

[0058] Step 5: Repeat steps 1 to 4 until the parameter measurement is completed for a preset number of times. That is, during the repeated execution, ion implantation with different process parameters can be performed on multiple wafer test pieces, and the corresponding parameter values ​​can be measured, which is conducive to analyzing the correlation between the ion implantation process parameters and the measured parameters. For example, the sensitivity of the implantation dose and the thermal wave value in the ion implantation process can be obtained.

[0059] As can be seen from the above, the wafer test piece provided in this embodiment can not only realize the recycling of the wafer test piece, but also reduce the difference in the previous values ​​of parameters between different wafer substrates 10 and improve the measurement accuracy. To verify this technical effect, the applicant conducted a series of experimental tests, as follows:

[0060] As shown in Table 1 below, the experimental test shown in this embodiment uses five types of wafer test pieces to measure various ion implantation processes and thermal wave values. Among them, the initial state of the wafer test piece numbered 1 is the first cycle piece; that is, Figure 5 As shown, the first reuse example method is used to remove the film structure after the ion-implanted detection film layer 121' is removed. The initial state of the wafer test piece numbered 2 is the second cycle piece; that is, Figure 6 As shown, the substrate 10 remaining after all the film layers above the substrate 10 are removed by the second reuse example method. The initial states of the wafer test pieces numbered 3, 4 and 5 are the first die, the second die and the third die, respectively, and the first die, the second die and the third die are all wafers including only the substrate 10. Among them, the wafer test pieces numbered 1, 2, 4 and 5 are all from the same batch A; and the wafer test piece numbered 3 is from another batch B.

[0061] During the experiment, first, the thermal wavefront values ​​of the five types of wafer test pieces in the initial state were measured, and it was found that the thermal wavefront values ​​of the five types of wafer test pieces in the initial state were quite different. Then, the five types of wafer test pieces in the initial state were processed respectively. That is, an oxide layer 121 was formed on the top surface of the first cycle piece numbered 1; a protective layer 11 and a test structure 12 were formed on the top surfaces of the second cycle piece numbered 2, the first bare chip numbered 3, the second bare chip numbered 4, and the third bare chip numbered 5, respectively. Secondly, the five types of wafer test pieces after the processing technology were measured respectively. Please refer to Fig.10 It can be found that by setting the test structure 12, the difference in thermal wavefront values ​​of each wafer test piece is greatly reduced, and even wafers from completely different batches can achieve basically consistent thermal wavefront values, which is beneficial to improving subsequent measurement accuracy.

[0062] Furthermore, on the basis of processing to form the test structure 12, ion implantation of various doses is performed on the five types of wafer test pieces. Among them, the wafer test pieces numbered 1 and 2 adopt the same first ion implantation dose; the wafer test piece numbered 3 adopts the same second ion implantation dose; the wafer test piece numbered 4 adopts the third ion implantation dose; and the wafer test piece numbered 5 adopts the fourth ion implantation dose. Among them, the first ion implantation dose, the second ion implantation dose, the third ion implantation dose and the fourth ion implantation dose increase in sequence. Finally, the thermal wave values ​​of the five types of wafer test pieces after the corresponding ion implantation processes are respectively performed are measured again to obtain the post-thermal wave values. Please refer to Tables 1 and Fig.11 By comparing the post-thermal wave values ​​of the wafer test pieces numbered 1 and 2, it can be seen that the post-thermal wave values ​​obtained after performing the wafer measurement process using the first reuse example method and the second reuse example method are basically the same, indicating that these two different recycling methods have almost no effect on the wafer measurement process, and also indicating that the wafer test piece provided in this embodiment has a high reuse value. By comparing the post-thermal wave values ​​of the wafer test pieces numbered 2, 3, 4 and 5, it can be seen that the post-thermal wave values ​​measured after processing of various types of wafer test pieces with different initial states are still linearly related, indicating that the wafer test pieces after the growth processing of the protective layer 11 and the test structure 12 meet the monitoring requirements of ion implantation.

[0063] Table 1 Comparison of thermal wave measurement information of five types of wafer test pieces

[0064]

[0065] Furthermore, the applicant also compared the wafer measurement method provided in this embodiment with the wafer measurement method in the prior art. Specifically, three bare chips were used to perform ion implantation processes with implantation doses of 2.00E+13, 3.00E+13 and 4.00E+13, respectively, and three wafer test pieces provided in this embodiment were used, that is, the substrate 10 was formed with a protective layer 11 and at least one test structure 12, and ion implantation processes with implantation doses of 2.00E+13, 3.00E+13 and 4.00E+13 were performed, respectively, and then the three bare chips and three wafer test pieces were measured after thermal wave, respectively, to obtain Fig.12 According to the comparison chart shown. Fig.12 It can be seen that although there is a certain difference in the sensitivity between the ion implantation dose and the thermal wave value obtained by the wafer measurement method provided in this embodiment and the wafer measurement method in the prior art, both are linear changes, and the monitoring of ion implantation changes by thermal wave measurement can be realized. Therefore, the wafer measurement method provided in this embodiment is not only highly feasible, but also can reduce costs and improve measurement accuracy.

[0066] Based on the same inventive concept, this embodiment also provides a wafer test piece for implementing the above-mentioned wafer measurement method. Figure 2 and Figure 3 As shown, the wafer test piece includes a substrate 10, a protective layer 11 and at least one test structure 12 sequentially formed on the substrate 10; wherein the test structure 12 includes a barrier layer 120 and an oxide layer 121 stacked from bottom to top. Preferably, the materials of the protective layer 11 and the oxide layer 121 both include silicon dioxide; and the material of the barrier layer 120 includes amorphous silicon.

[0067] In summary, the wafer test piece and wafer measurement method provided in this embodiment are provided with at least one layer of the test structure 12 on the substrate 10, and the oxide layer 121 of the test structure 12 located on the top layer is used as the implanted film layer for ion implantation, and the relevant parameters are measured accordingly. Therefore, the entire measurement process has no direct impact on the substrate 10, and the substrate 10 or the partial layer test structure 12 on the substrate 10 and its top surface can be recycled, effectively reducing the measurement cost. In addition, the setting of the test structure 12 can also reduce the difference in the previous values ​​of the parameters of each wafer substrate 10, which is conducive to improving the accuracy of the measurement results.

[0068] In addition, it should be recognized that although the present invention has been disclosed as a preferred embodiment, the above embodiment is not intended to limit the present invention. For any technician familiar with the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or modified into equivalent embodiments of equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belongs to the scope of protection of the technical solution of the present invention.

Claims

1. A wafer measurement method, characterized in that: include: Step 1: providing a wafer test piece, the wafer test piece comprising a substrate, a protection layer and at least one test structure formed in sequence on the substrate; wherein the test structure comprises a barrier layer and an oxide layer stacked from bottom to top; Step 2: performing an ion implantation process on the oxide layer located on the top surface of the wafer test piece; Step three: performing parameter measurement on the oxide layer after the ion implantation process.

2. The wafer measurement method according to claim 1, characterized in that: After executing step three, the oxide layer located on the top surface of the wafer test piece is removed to expose the adjacent barrier layer; and a new oxide layer is formed on the surface of the exposed adjacent barrier layer to form a new wafer test piece.

3. The wafer measurement method according to claim 1, characterized in that: After executing step three, the at least one layer of the test structure and the protective layer are removed in sequence to expose the substrate; and the protective layer and at least one layer of the test structure are re-formed in sequence on the surface of the substrate to serve as a new wafer test piece.

4. The wafer measurement method according to claim 1, characterized in that: The wafer test piece includes multiple layers of the test structure, and after executing step three, some layers of the test structure are removed, and the substrate, the protective layer formed in sequence on the substrate, and the remaining test structure are used as a new wafer test piece.

5. The wafer measurement method according to claim 1, characterized in that: The wafer test piece includes multiple layers of the test structure, and after executing the step three, some layers of the test structure are removed; and at least one layer of the test structure is formed on the top surface of the remaining test structure to form a new wafer test piece.

6. The wafer measurement method according to any one of claims 1 to 5, characterized in that: After executing step three, the wafer measurement method further includes: Step 4: Adjust ion implantation process parameters; Step 5: Repeat steps 1 to 4 until the parameter measurement is completed for a preset number of times.

7. The wafer measurement method according to any one of claims 1 to 5, characterized in that: The materials of the protection layer and the oxide layer both include silicon dioxide; the material of the barrier layer includes amorphous silicon.

8. The wafer measurement method according to any one of claims 1 to 5, characterized in that: In step three, the measured parameters include thermal wave values.

9. A wafer test piece, characterized in that: The wafer test piece includes a substrate, a protection layer and at least one test structure formed in sequence on the substrate; wherein the test structure includes a barrier layer and an oxide layer stacked from bottom to top.

10. The wafer testing piece according to claim 9, characterized in that: The materials of the protection layer and the oxide layer both include silicon dioxide; the material of the barrier layer includes amorphous silicon.

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