Silicon wafer testing method, system and equipment and silicon wafer processing method

Abstract

The invention provides a silicon wafer testing method, system and device and a silicon wafer processing method.The silicon wafer testing method comprises the steps that silicon wafers are measured one by one based on first preset measurement parameters to obtain specification parameters of the silicon wafers, and the specification parameters comprise at least one of the particle contamination degree, the edge integrity, the surface flatness, the nanometer morphology and the silicon wafer thickness; judging whether the specification parameter reaches a first target threshold value corresponding to the first target level or not; if the judgment result is that the specification parameter does not reach the first target threshold value, performing a simulation test on the silicon wafer based on the specification parameter to predict whether a predicted specification parameter corresponding to the silicon wafer under a second preset measurement parameter reaches a second target threshold value corresponding to a second target level; and if the prediction result is that the prediction specification parameter does not reach the second target threshold value, reworking or scrapping the silicon wafer. According to the silicon wafer testing method, system and equipment and the silicon wafer processing method disclosed by the invention, the productivity and the effective utilization rate of the equipment are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a silicon wafer testing method, system, equipment and a silicon wafer processing method. Background Art

[0002] In the semiconductor industry, silicon wafers can be classified according to product grades. For example, silicon wafers can be classified from high grade to low grade into prime wafers, test wafers, monitor wafers, and dummy wafers. The higher the grade of the silicon wafer, the better the flatness, thickness, and nano-morphology.

[0003] Usually, the wafer inspection process tests the wafer's flatness, thickness, nano-morphology and other indicators to sort out the wafers that meet the specified grade. Wafers that do not meet the specifications will be reworked (Re-Double Side Polish, Re-DSP) or scrapped (Reject). Rework is time-consuming and labor-intensive, and the success rate of rework is low.

[0004] For such silicon wafers, downgrading is generally adopted. For example, high-quality silicon wafers are downgraded to test silicon wafers, test silicon wafers are downgraded to monitoring silicon wafers, monitoring silicon wafers are downgraded to blank silicon wafers, etc. However, due to different testing requirements and testing methods for different silicon wafers, some silicon wafers to be downgraded need to be retested after downgrading, which affects the equipment production capacity and effective utilization rate. Summary of the invention

[0005] The embodiments of the present disclosure provide a silicon wafer testing method, system, equipment and silicon wafer processing method, which can improve equipment production capacity and effective utilization rate.

[0006] The technical solutions provided by the embodiments of the present disclosure are as follows:

[0007] In a first aspect, an embodiment of the present disclosure provides a silicon wafer testing method, comprising:

[0008] Based on the first preset measurement parameter, the silicon wafers are measured one by one to obtain specification parameters of the silicon wafers, wherein the specification parameters include at least one of particle contamination, edge integrity, surface flatness, nano-morphology and silicon wafer thickness;

[0009] determining whether the specification parameter reaches a first target threshold corresponding to a first target level;

[0010] If the judgment result is that the specification parameter does not reach the first target threshold, a simulation test is performed on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the first target level;

[0011] If the prediction result is that the predicted specification parameter does not reach the second target threshold, the silicon wafer is reworked or scrapped.

[0012] Exemplarily, the simulation test of the silicon wafer based on the specification parameters to predict whether the predicted specification parameters corresponding to the silicon wafer under the second preset measurement parameters reach a second target threshold corresponding to the second target level specifically includes:

[0013] Pre-storing the correspondence between preset measurement parameters and target thresholds for different target levels;

[0014] According to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level;

[0015] The simulation specification parameter is compared with the second target threshold to obtain the prediction result.

[0016] Exemplarily, the method further includes:

[0017] If the prediction result is that the predicted specification parameter reaches the second target threshold, the silicon wafer is pre-degraded and a corresponding post-degradation simulation test is performed on the silicon wafer.

[0018] Exemplarily, the pre-degradation process on the silicon wafer and the corresponding post-degradation simulation test on the silicon wafer specifically include:

[0019] Store all silicon wafer specifications;

[0020] Based on the identification code of the silicon wafer, retrieving specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers;

[0021] Using the retrieved specification parameters as data to be tested;

[0022] Performing simulation test on the data to be tested through a silicon wafer analysis system to make a grade determination;

[0023] If the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determining that the silicon wafer belongs to the second target grade;

[0024] If the result of performing grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

[0025] In a second aspect, the present disclosure also provides a silicon wafer testing system, including:

[0026] A silicon wafer measuring device, used to measure the silicon wafer based on preset measurement parameters for different target levels of the silicon wafer to obtain specification parameters of the silicon wafer;

[0027] Silicon wafer simulation analysis device for:

[0028] Based on the specification parameter, determining whether the specification parameter reaches a first target threshold corresponding to the first target level;

[0029] If the judgment result is that the specification parameter does not reach the first target threshold, a simulation test is performed on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the first target level;

[0030] If the prediction result is that the predicted specification parameter does not reach the second target threshold, a first analysis result indicating that the silicon wafer should be reworked or scrapped is generated.

[0031] Exemplarily, the silicon chip simulation analysis device is specifically used for:

[0032] Pre-storing the correspondence between preset measurement parameters and target thresholds for different target levels;

[0033] According to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level;

[0034] The simulation specification parameter is compared with the second target threshold to obtain the prediction result.

[0035] Exemplarily, the silicon chip simulation analysis device is further used for:

[0036] If the prediction result is that the predicted specification parameter reaches the second target threshold, the silicon wafer is pre-degraded and a corresponding post-degradation simulation test is performed on the silicon wafer.

[0037] Exemplarily, the silicon chip simulation analysis device is further used for:

[0038] Store all silicon wafer specifications;

[0039] Based on the identification code of the silicon wafer, retrieving specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers;

[0040] Using the retrieved specification parameters as data to be tested;

[0041] Performing simulation test on the data to be tested through a silicon wafer analysis system to make a grade determination;

[0042] If the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determining that the silicon wafer belongs to the second target grade;

[0043] If the result of performing grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

[0044] In a third aspect, an embodiment of the present disclosure further provides a computing device, which includes: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the silicon wafer testing method as described above.

[0045] In a fourth aspect, an embodiment of the present disclosure further provides a silicon wafer processing method, the method comprising:

[0046] Processing the silicon wafer by a predetermined method to obtain a plurality of silicon wafers;

[0047] For each of the plurality of silicon wafers, a grade test and determination is performed using the silicon wafer testing method as described above.

[0048] The beneficial effects brought by the embodiments of the present disclosure are as follows:

[0049] In the above scheme, during the silicon wafer processing, when the silicon wafer is graded and sorted, if the specification parameters of the silicon wafer do not meet the requirements of the first target grade, it is not directly reworked, scrapped or downgraded. Instead, based on the measured specification parameters, a simulation test is first performed to determine whether the silicon wafer can be downgraded to the second target grade to predict whether the silicon wafer can be downgraded. If the prediction result shows that it still does not meet the requirements after downgrading, the silicon wafer is reworked or scrapped. In this way, the problem of low equipment production capacity and low utilization rate caused by direct rework, scrapping or downgrading can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A flow chart showing a silicon wafer testing method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0052] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0053] like Figure 1 As shown, the embodiment of the present disclosure provides a silicon wafer testing method, which can be used to grade and process silicon wafers. The silicon wafer testing method includes the following steps:

[0054] Step S01, based on the first preset measurement parameters, measuring the silicon wafers one by one to obtain the specification parameters of the silicon wafers, wherein the specification parameters include at least one of particle contamination, edge integrity, surface flatness, nano-morphology and silicon wafer thickness;

[0055] Step S02, determining whether the specification parameter reaches a first target threshold corresponding to a first target level;

[0056] Step S03: if the judgment result is that the specification parameter does not reach the first target threshold, a simulation test is performed on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the first target level;

[0057] Step S04: if the prediction result is that the predicted specification parameter does not reach the second target threshold, the silicon wafer is reworked or scrapped.

[0058] In the above scheme, during the silicon wafer processing, when the silicon wafer is graded and sorted, if the specification parameters of the silicon wafer do not meet the requirements of the first target grade, it is not directly reworked, scrapped or downgraded. Instead, based on the measured specification parameters, a simulation test is first performed to determine whether the silicon wafer can be downgraded to the second target grade to predict whether the silicon wafer can be downgraded. If the prediction result shows that it still does not meet the requirements after downgrading, the silicon wafer is reworked or scrapped. In this way, the problem of low equipment production capacity and low utilization rate caused by direct rework, scrapping or downgrading can be avoided.

[0059] In the semiconductor industry, silicon wafers can be classified according to product grades. For example, silicon wafers can be classified from high grade to low grade into prime wafers, test wafers, monitor wafers, and dummy wafers. The higher the grade of the silicon wafer, the higher the requirements for specifications such as particle contamination, edge integrity, surface flatness, nano-morphology, and silicon wafer thickness.

[0060] The first target level can be a prime wafer, a test wafer, a monitor wafer, etc., and the second target level can be a test wafer, a monitor wafer, a dummy wafer, etc. whose level is lower than the first target level.

[0061] In addition, it should be noted that the measurement of the specification parameters of the silicon wafer may include but is not limited to the following parameters: at least one of particle contamination, edge integrity, surface flatness, nano-morphology and silicon wafer thickness.

[0062] For example, in some embodiments, the specification parameters may include particle contamination, edge integrity, surface flatness, nano-topography, and silicon wafer thickness. Specifically, the specification parameters may include but are not limited to the following parameters: GBIR, SFQR, E-SFQR, and ZDD.

[0063] The terms are explained as follows:

[0064] GBIR (Global Backsurface-referenced Ideal plane / Range): The difference between the maximum and minimum thickness relative to the back surface as an imaginary reference plane, used to evaluate the flatness of the entire wafer surface.

[0065] SFQR (Site Frontsurface referenced leasts Quares / Range): The sum of the peak-to-valley values ​​when a virtual plane obtained by least squares fitting of each local part of the upper surface of the silicon wafer is used as the virtual reference plane of this local part. It is a part flatness index of the surface reference, and each part is evaluated separately.

[0066] E-SFQR (Edge Site Frontsurface referenced least sQuares / Range): The sum of the peak-to-valley values ​​when a pseudo plane obtained by least squares fitting only at the edge is used as the local pseudo reference plane. It is an indicator of the flatness of the periphery.

[0067] ZDD (Z-Height Double Differentiation): The second-order differential of the surface displacement of the semiconductor wafer relative to the radius of the semiconductor wafer. When the value is positive, it means that the surface is displaced in the direction of warping. On the contrary, when the ZDD is negative, it means that the surface is displaced in the direction of collapsing.

[0068] For example, the measurement of the specification parameters of the silicon wafer can be achieved by a silicon wafer measurement device (Wafer Sight), and the silicon wafer testing device can output the measurement result as a WNT (Wafersight NT wafer) file, and the WNT file includes all the specification parameter information of the silicon wafer.

[0069] For different levels of measurement, the preset measurement parameters (recipe) will be different. For example, in the measurement process of silicon wafers, for the measurement of the first target level, the preset measurement parameters are the first preset measurement parameters; for the measurement of the second target level, the preset measurement parameters are the second preset measurement parameters; and so on.

[0070] By detecting the above specification parameters under the condition of the first preset measurement parameters. If the specification parameters reach the first target threshold, they are classified as the first target level; otherwise, predictions are made based on the above specification parameters to predict whether the corresponding specification parameters under the condition of the second preset measurement parameters can reach the second target threshold. The first target threshold is the specification parameter that meets the first target level; the second target threshold is the specification parameter that meets the second target level. The first target threshold and the second target threshold can be obtained based on empirical values, and the specific values ​​of the first target threshold and the second target threshold are not specifically specified here. For example, taking the first target level as high-quality silicon wafers as an example, the first target threshold can be used as a reference value for high-quality silicon wafers.

[0071] Exemplarily, the above step S03 specifically includes:

[0072] Step S031, pre-storing the correspondence between preset measurement parameters and target thresholds of different target levels;

[0073] Step S032: according to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level;

[0074] Step S033: compare the simulation specification parameter with the second target threshold to obtain the prediction result.

[0075] In the above scheme, when it is determined that the silicon wafer does not meet the first target level (wafer NG), the specification parameters obtained under the first preset measurement parameter conditions and the first preset measurement parameters required after downgrading to the second target level are combined for prediction. In other words, the specific prediction method is to make predictions in combination with the test methods (i.e., preset test parameters) before and after the downgrading.

[0076] The above solution does not directly measure the silicon wafer under the second preset measurement parameters to obtain the specification parameters and then determine whether it meets the second target level. Instead, the specification parameters obtained under the first preset measurement parameters are used to predict the simulated specification parameters obtained under the second preset measurement parameters after degradation. The principle is as follows:

[0077] As mentioned above, the test requirements (i.e., preset test parameters) for silicon wafers of different grades will be different. The higher the grade, the stricter the test requirements. However, there are certain correlations and rules between the specification requirements of different grades. Generally speaking, the lower the grade, the smaller the specification parameters of the silicon wafer. For example, according to the processing principle of silicon wafers, the edge quality of silicon wafers is generally worse than the center of the silicon wafer. Therefore, the more the edge of the silicon wafer is removed during measurement, the better the specification parameters obtained by measurement.

[0078] Taking the GBIR tested by Wafersight as an example, the test requirement for silicon wafers before degradation is EE3 (remove 3mm from the edge) test method, and the test requirement for silicon wafers after degradation is EE2 (remove 2mm from the edge). According to Wafer manufacturing experience, from EE3 to EE2, GBIR generally increases by 15nm to 50nm. From EE2 to EE1, GBIR generally increases by 80nm to 200nm. Therefore, based on the preset test parameters before and after degradation, the corresponding difference can be added to the specification parameters measured before degradation to obtain the predicted specification parameters, so as to judge whether the specification parameters of the silicon wafer after degradation meet the requirements after degradation based on the predicted specification parameters.

[0079] Exemplarily, the method further includes:

[0080] Step S05: If the prediction result is that the predicted specification parameter reaches the second target threshold, pre-degradation processing is performed on the silicon wafer, and a corresponding post-degradation simulation test is performed on the silicon wafer.

[0081] By adopting the above scheme, when it is predicted that the silicon wafer can be downgraded to the second target level according to the preset test parameters before and after downgrading, the silicon wafer does not need to be subjected to the post-downgrading processing and testing procedures first, but can be subjected to corresponding post-downgrading simulation tests.

[0082] Exemplarily, the above step S05 specifically includes:

[0083] Step S051, storing specification parameters of all silicon wafers;

[0084] Step S052: based on the identification code of the silicon wafer, retrieve the specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers;

[0085] Step S053, using the retrieved specification parameters as data to be tested;

[0086] Step S054, performing a simulation test on the data to be tested through a silicon wafer analysis system to determine the level;

[0087] Step S055: if the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determine that the silicon wafer belongs to the second target grade;

[0088] Step S056: If the result of the grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

[0089] In the above scheme, a wafer measurement device (WaferSight) is used to measure the wafer. The wafer measurement device will output the measurement results as a WNT (Wafersight NT wafer) file, which includes all the specification parameter information of the wafer. The wafer test equipment can analyze the specification parameter signal of the wafer through the wafer analysis device. Therefore, according to the WNT file, a simulation test can be performed in combination with the preset measurement parameters, and then reported to the wafer analysis device for grading and analysis, thereby improving the production capacity of the wafer measurement device.

[0090] It should be noted that the silicon wafer analysis device can be implemented through OASYS software. The data obtained by OASYS software from analyzing various parameters of silicon wafers, and the difference between the data of actual test meet the industry standards, can be used as OQC (Outgoing Quality Control) data. OASYS software can include retrieval module, transfer module, MES module, etc.

[0091] Therefore, in the above scheme, for silicon wafers whose prediction results can meet the downgrade requirements, the WNT file of silicon wafer measurement can be retrieved based on the silicon wafer identification code (wafer ID) through the retrieval module of the OASYS software (because there are cases where the equipment is retested due to special reasons, the latest WNT file is retrieved here), and the transfer module of the OASYS software transfers the retrieved WNT file to the area to be tested to use these WNT files as the data to be tested. The OASYS software clips the data to be tested from the area to be tested for testing, and reports the data to the MES module. The MES module judges and analyzes the data to be tested.

[0092] If the grading result is that the specification parameters meet the second target level, the subsequent processing flow will continue according to the downgraded processing procedures and testing procedures until sorting, packaging and shipment; if the grading result is that the specification parameters do not meet the second target level, these specification parameters will be reworked or scrapped.

[0093] Specifically, if the GBIR parameter does not meet the requirements (NG), rework (DSP) processing is performed; if the Bow parameter does not meet the requirements (NG), scrapping is performed.

[0094] In summary, the silicon wafer testing method provided in the embodiment of the present disclosure, when the silicon wafer does not meet the first target level requirement when measured under the condition of the first preset measurement parameters, can predict whether the silicon wafer meets the requirement after downgrading based on the specification parameters measured under the condition of the first preset measurement parameters, combined with the data before downgrading and the second preset measurement parameters after downgrading, instead of directly reworking, scrapping or downgrading the silicon wafers that do not meet the requirements. This can reduce the problem of low equipment utilization rate caused by low rework rescue rate, repeated testing and other problems, and can improve the effective utilization rate of the equipment.

[0095] Furthermore, in a further embodiment, the above prediction process and the simulation test after degradation can be performed through software simulation testing, which does not occupy equipment production capacity and can output real data.

[0096] In a second aspect, the present disclosure also provides a silicon wafer testing system, including:

[0097] A silicon wafer measuring device, used to measure the silicon wafer based on preset measurement parameters for different target levels of the silicon wafer to obtain specification parameters of the silicon wafer;

[0098] Silicon wafer simulation analysis device for:

[0099] Based on the specification parameter, determining whether the specification parameter reaches a first target threshold corresponding to the first target level;

[0100] If the determination result is that the specification parameter does not reach the first target threshold, performing a simulation test on the silicon wafer to predict whether the specification parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the first target level;

[0101] If the prediction result is that the predicted specification parameter does not reach the second target threshold, a first analysis result indicating that the silicon wafer should be reworked or scrapped is generated.

[0102] Obviously, the silicon wafer testing system provided by the embodiment of the present disclosure also has the beneficial effects brought by the silicon wafer testing method provided by the embodiment of the present disclosure, which will not be described in detail here.

[0103] Exemplarily, the silicon chip simulation analysis device is specifically used for:

[0104] Pre-storing the correspondence between preset measurement parameters and target thresholds for different target levels;

[0105] According to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level;

[0106] The simulation specification parameter is compared with the second target threshold to obtain the prediction result.

[0107] Exemplarily, the silicon chip simulation analysis device is further used for:

[0108] If the prediction result is that the predicted specification parameter reaches the second target threshold, the silicon wafer is pre-degraded and a corresponding post-degradation simulation test is performed on the silicon wafer.

[0109] Exemplarily, the silicon chip simulation analysis device is further used for:

[0110] Store all silicon wafer specifications;

[0111] Based on the identification code of the silicon wafer, retrieving specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers;

[0112] Using the retrieved specification parameters as data to be tested;

[0113] Performing simulation test on the data to be tested through a silicon wafer analysis system to make a grade determination;

[0114] If the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determining that the silicon wafer belongs to the second target grade;

[0115] If the result of performing grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

[0116] In addition, an embodiment of the present disclosure further provides a computing device, which includes: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the silicon wafer testing method as described above.

[0117] The computing device in the present application may include one or more of the following components: a processor and a memory.

[0118] Optionally, the processor utilizes various interfaces and lines to connect various parts within the entire computing device, and performs various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory, and calling data stored in the memory.

[0119] Optionally, the processor may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA).

[0120] The processor may integrate one or a combination of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processor (NPU), and a baseband chip. Among them, the CPU mainly processes the operating system, user interface, and application programs; the GPU is responsible for rendering and drawing the content to be displayed on the touch screen; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communications. It is understandable that the above-mentioned baseband chip may not be integrated into the processor 910, but may be implemented by a single chip.

[0121] The memory may include a random access memory (RAM) or a read-only memory (ROM). Optionally, the memory includes a non-transitory computer-readable storage medium. The memory may be used to store instructions, programs, codes, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playback function, an image playback function, etc.), instructions for implementing the following various method embodiments, etc.; the data storage area may store data created according to the use of the computing device, etc.

[0122] In addition, those skilled in the art will appreciate that the structure of the computing device shown in the above figures does not constitute a limitation on the computing device, and the computing device may include more or fewer components than shown, or combine certain components, or arrange the components differently. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and other components, which will not be described in detail here.

[0123] In addition, an embodiment of the present disclosure further provides a computer storage medium, wherein the storage medium stores at least one instruction, and the at least one instruction is used to be executed by a processor to implement the silicon wafer testing method as described above.

[0124] An embodiment of the present application also provides a computer program product, which includes computer instructions, which are stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computing device executes the method for identifying wafer edge defect types provided in various optional implementations of the above aspects.

[0125] Those skilled in the art should be aware that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented with hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein the communication media include any media that facilitates the transmission of a computer program from one place to another. The storage medium can be any available medium that a general or special-purpose computer can access.

[0126] In addition, the present disclosure also provides a silicon wafer processing method, the method comprising:

[0127] Processing the silicon wafer by a predetermined method to obtain a plurality of silicon wafers;

[0128] For each of the plurality of silicon wafers, a grade test and determination is performed using the silicon wafer testing method as described above.

[0129] There are a few points to note:

[0130] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0131] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0132] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0133] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A silicon wafer testing method, characterized in that: include: Based on the first preset measurement parameter, the silicon wafers are measured one by one to obtain specification parameters of the silicon wafers, wherein the specification parameters include at least one of particle contamination, edge integrity, surface flatness, nano-morphology and silicon wafer thickness; determining whether the specification parameter reaches a first target threshold corresponding to a first target level; If the judgment result is that the specification parameter does not reach the first target threshold, a simulation test is performed on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the first target level; If the prediction result is that the predicted specification parameter does not reach the second target threshold, the silicon wafer is reworked or scrapped.

2. The silicon wafer testing method according to claim 1, characterized in that: If the judgment result is that the specification parameter does not reach the first target threshold, a simulation test is performed on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches the second target threshold corresponding to the second target level, specifically including: Pre-storing the correspondence between preset measurement parameters and target thresholds for different target levels; According to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level; The simulation specification parameter is compared with the second target threshold to obtain the prediction result.

3. The silicon wafer testing method according to claim 1, characterized in that: The method further comprises: If the prediction result is that the predicted specification parameter reaches the second target threshold, the silicon wafer is pre-degraded and a corresponding post-degradation simulation test is performed on the silicon wafer.

4. The silicon wafer testing method according to claim 3, characterized in that: The pre-degradation process of the silicon wafer and the corresponding post-degradation simulation test of the silicon wafer specifically include: Store all silicon wafer specifications; Based on the identification code of the silicon wafer, retrieving specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers; Using the retrieved specification parameters as data to be tested; Performing simulation test on the data to be tested through a silicon wafer analysis system to make a grade determination; If the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determining that the silicon wafer belongs to the second target grade; If the result of performing grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

5. A silicon wafer testing system, characterized in that: include: A silicon wafer measuring device, used to measure the silicon wafer based on preset measurement parameters for different target levels of the silicon wafer to obtain specification parameters of the silicon wafer; Silicon wafer simulation analysis device for: Based on the specification parameter, determining whether the specification parameter reaches a first target threshold corresponding to a first target level; If the judgment result is that the specification parameter does not reach the first target threshold, if the judgment result is that the specification parameter does not reach the first target threshold, performing a simulation test on the silicon wafer based on the specification parameter to predict whether the predicted specification parameter corresponding to the silicon wafer under the second preset measurement parameter reaches a second target threshold corresponding to a second target level, wherein the second target level is lower than the level of the first target level; If the prediction result is that the predicted specification parameter does not reach the second target threshold, a first analysis result indicating that the silicon wafer should be reworked or scrapped is generated.

6. The silicon wafer testing system according to claim 5, characterized in that: The silicon wafer simulation analysis device is specifically used for: Pre-storing the correspondence between preset measurement parameters and target thresholds for different target levels; According to the corresponding relationship, based on the specification parameter, the first preset measurement parameter, and the second preset measurement parameter corresponding to the test of the silicon wafer being downgraded to the second target level, obtaining the simulation specification parameter after the silicon wafer is downgraded to the second target level; The simulation specification parameter is compared with the second target threshold to obtain the prediction result.

7. The silicon wafer testing system according to claim 5, characterized in that: The silicon wafer simulation analysis device is also specifically used for: If the prediction result is that the predicted specification parameter reaches the second target threshold, the silicon wafer is pre-degraded and a corresponding post-degradation simulation test is performed on the silicon wafer.

8. The silicon wafer testing system according to claim 5, characterized in that: The silicon wafer simulation analysis device is also specifically used for: Store all silicon wafer specifications; Based on the identification code of the silicon wafer, retrieving specification parameters corresponding to the silicon wafer from the specification data of all silicon wafers; Using the retrieved specification parameters as data to be tested; Performing simulation test on the data to be tested through a silicon wafer analysis system to make a grade determination; If the result of performing the grade determination on the data to be tested is that the grade of the silicon wafer reaches the second target grade, determining that the silicon wafer belongs to the second target grade; If the result of performing grade determination on the data to be tested is that the grade of the silicon wafer does not reach the second target grade, the silicon wafer is reworked or scrapped.

9. A computing device, characterized in that The computing device comprises: a processor and a memory; the processor is used to execute instructions stored in the memory to implement the silicon wafer testing method as claimed in any one of claims 1 to 4.

10. A silicon wafer processing method, characterized in that: The method comprises: Processing the silicon wafer by a predetermined method to obtain a plurality of silicon wafers; For each of the plurality of silicon wafers, a grade test and determination is performed using the silicon wafer testing method according to any one of claims 1 to 4.

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