Adjustable current and voltage suppression thick film integrated circuit

Abstract

The invention provides an adjustable current and voltage suppression thick film integrated circuit. Comprising an impact current suppression unit and a surge voltage suppression unit, the input end of the impact current suppression unit is connected with an input power supply, the output end of the impact current suppression unit is connected with the surge voltage suppression unit, and the output end of the surge voltage suppression unit is connected with a DC / DC power supply module. The impulse current suppression unit and the surge voltage suppression unit are arranged on the ceramic substrate. According to the thick film integration technology, all electronic components of the 28V power supply processing circuit are fully integrated on the ceramic substrate and are packaged to form a hybrid integrated circuit, and the size and the weight of the power supply processing circuit can be reduced to the maximum extent.

Description

Technical Field

[0001] The present invention relates to an adjustable current and voltage suppression thick film integrated circuit. Background Art

[0002] In recent years, with the continuous advancement of thick film technology, the thick film integrated circuit industry has continued to grow and develop. Thick film integrated circuits have very broad prospects because of their high stability, high reliability, high integration and other characteristics, and are widely used in various fields. At present, with the severe situation of scientific and technological development and national defense, the development process of military aircraft and unmanned aerial vehicles has accelerated, and the development trend of miniaturization, lightweight, integration, intelligence and localization has become more and more obvious. Therefore, the demand for miniaturization, lightweight, integration, intelligence and localization of aircraft power distribution systems has followed. Traditional 28V power supply processing circuits are composed of various electronic components, with a large number of selected devices, and are welded on printed circuit boards. This method is large in size and has poor reliability. The present invention integrates thick film integration technology into the 28V power supply processing circuit. Due to its flexibility in structure and design, it is applied in the aviation field. It has the characteristics of miniaturization, lightweight, high reliability, high stability, impact resistance and vibration resistance, which meet the current aviation development needs. For example, a robot charging device and charging pile disclosed in CN211063396U has a peak voltage suppression and impact current suppression unit in the charger to process the input AC power so that the converted DC power is within the rated range. However, the peak voltage and impact current of the input AC power are suppressed by the reactance component, and the reactance component can only process AC power. Summary of the invention

[0003] In order to solve the above technical problems, the present invention provides an adjustable current and voltage suppression thick film integrated circuit.

[0004] The present invention is achieved through the following technical solutions.

[0005] The present invention provides an adjustable current and voltage suppression thick film integrated circuit; it comprises an impact current suppression unit and a surge voltage suppression unit, wherein the impact current suppression unit input end is connected to an input power supply, the impact current suppression unit output end is connected to the surge voltage suppression unit, the surge voltage suppression unit output end is connected to a DC / DC power supply module, and the impact current suppression unit and the surge voltage suppression unit are both arranged on a ceramic substrate.

[0006] The inrush current suppression unit includes a MOS tube Q1, a gate of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, one end of the capacitor C1 and a positive electrode of a diode D1 in sequence, a source of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, the other end of the capacitor C1 and a negative electrode of the diode D1 in sequence, a positive electrode of the diode D1 is also connected to the resistor R1, and the other end of the resistor R1 is grounded; a drain of the MOS tube Q1 is connected to the surge voltage suppression unit.

[0007] A resistor R4 and a resistor R5 are connected in parallel between the source and the drain of the MOS tube Q1.

[0008] The surge voltage suppression unit includes a transistor Q2 and a transistor Q3, the base of the transistor Q2 is connected to the resistor R8, and the emitter is connected to one end of the resistor R7 and the resistor R6 in sequence; the other ends of the resistors R8 and R7 are connected in parallel to the collector of the transistor Q3, the other end of the resistor R6 is respectively connected to the cathode of the diode D2, the cathode of the diode D3, and the base of the transistor Q3, the anode of the diode D2 is grounded, the emitter of the transistor Q3 is connected to the anode of the diode D3, the emitter of the transistor Q2 is also connected to the drain of the MOS tube Q1, and the collector of the transistor Q2 and the emitter of the transistor Q3 are commonly connected to the DC / DC power supply module.

[0009] The transistor Q2 and the transistor Q3 are of NPN type and PNP type respectively.

[0010] The resistance of the resistor R4 and the resistor R5 is 100Ω.

[0011] The surge voltage suppression unit suppresses the output voltage at 33V.

[0012] The inrush current suppression unit suppresses the input inrush current within 10 times the current of the product.

[0013] The beneficial effect of the present invention is that the thick film integration technology fully integrates the electronic components of the 28V power processing circuit on the ceramic substrate, and packages them to form a hybrid integrated circuit, which can minimize the volume and weight of the power processing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the system principle of the present invention;

[0015] Figure 2 It is a schematic diagram of the principle of the impulse current suppression circuit of the present invention;

[0016] Figure 3 It is a schematic diagram of the voltage suppression circuit principle of the present invention;

[0017] Figure 4 It is a schematic diagram of the interface principle of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described below, but the scope of protection claimed is not limited to the description.

[0019] An adjustable current and voltage suppression thick film integrated circuit; comprising an impulse current suppression unit and a surge voltage suppression unit, wherein the input end of the impulse current suppression unit is connected to an input power supply, the output end of the impulse current suppression unit is connected to the surge voltage suppression unit, the output end of the surge voltage suppression unit is connected to a DC / DC power supply module, and the impulse current suppression unit and the surge voltage suppression unit are both arranged on a ceramic substrate.

[0020] The inrush current suppression unit includes a MOS tube Q1, a gate of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, one end of the capacitor C1 and a positive electrode of a diode D1 in sequence, a source of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, the other end of the capacitor C1 and a negative electrode of the diode D1 in sequence, a positive electrode of the diode D1 is also connected to the resistor R1, and the other end of the resistor R1 is grounded; a drain of the MOS tube Q1 is connected to the surge voltage suppression unit.

[0021] A resistor R4 and a resistor R5 are connected in parallel between the source and the drain of the MOS tube Q1.

[0022] The surge voltage suppression unit includes a transistor Q2 and a transistor Q3, the base of the transistor Q2 is connected to the resistor R8, and the emitter is connected to one end of the resistor R7 and the resistor R6 in sequence; the other ends of the resistors R8 and R7 are connected in parallel to the collector of the transistor Q3, the other end of the resistor R6 is respectively connected to the cathode of the diode D2, the cathode of the diode D3, and the base of the transistor Q3, the anode of the diode D2 is grounded, the emitter of the transistor Q3 is connected to the anode of the diode D3, the emitter of the transistor Q2 is also connected to the drain of the MOS tube Q1, and the collector of the transistor Q2 and the emitter of the transistor Q3 are commonly connected to the DC / DC power supply module.

[0023] The transistor Q2 and the transistor Q3 are of NPN type and PNP type respectively.

[0024] The resistance of the resistor R4 and the resistor R5 is 100Ω.

[0025] The surge voltage suppression unit suppresses the output voltage at 33V.

[0026] The inrush current suppression unit suppresses the input inrush current within 10 times the current of the product.

[0027] like Figure 1As shown, the invention is mainly composed of an impact current suppression unit, a surge voltage suppression unit and a ceramic substrate. The impact current suppression unit is mainly used to suppress the impact current on the 28V power supply at the moment of powering on the product, and is implemented by building a circuit using a MOS tube and peripheral current limiting resistors and capacitors. The surge voltage suppression circuit is mainly used to suppress overvoltage surges of 50V / 12.5ms, and is implemented by forming a circuit with two NPN and PNP transistors and accompanying devices. The present invention integrates the components of the above units on a ceramic substrate through thick film technology and encapsulates them.

[0028] Figure 2 This is the circuit diagram of the impact current suppression unit. The soft start impact current suppression circuit is composed of MOSFET and current limiting resistor. When the power is on, the impact current is limited by the starting resistor. When the startup process is over, the MOS shorts the starting resistor and the soft start circuit no longer works. Since the switching speed of the MOS tube Q1 depends on the discharge speed of the input capacitor, when the 28V power supply is input to the impact current suppression unit, the MOS tube Q1 is in the off state, and the subsequent capacitor is charged through the resistor R4 and the resistor R5. At the same time, the gate capacitor of the MOS tube Q1 and the capacitor C1 and the capacitor C2 are charged through the resistor R1 and the resistor R2. After the capacitor is fully charged, the MOS tube Q1 is turned on, and the current flows into the subsequent circuit through the MOS tube Q1. The voltage regulator diode D1 is used to suppress the gate voltage of the MOS tube to ensure that the MOS tube will not be damaged. The MOS of this circuit is placed in the loop of the circuit. The maximum surge current after suppression depends on the resistance of the parallel resistors R4 and R5 and the capacitance of the capacitors C1 and C2 in the circuit. Therefore, as long as the resistance and capacitance values ​​are adjusted appropriately, the maximum impact current value can be adjusted. The power and resistance of the current limiting resistor can be selected according to the actual engineering situation.

[0029] In order to make the technical solution of the surge current suppression circuit clearer, a specific implementation case of the circuit is given. When the power consumption of a product is 20W at a voltage of 28V, the steady-state current under normal operation is 20W / 28V=714.2mA. The rated current of the product is 100mA, and the surge current is required to be no more than 10 times the rated current. The current limiting resistor designed in the circuit should not be less than 28V / 714.2mA / 5 times=7.84Ω. Two 100Ω resistors can be selected in parallel as current limiting resistors. The resistance value after parallel connection is 50Ω, which can limit the first surge current to 28V / 50Ω=560mA, which is less than the specified 10 times rated current value. In extreme cases, if the input of 28V input is 7V, the system may still be in the power supply state. At this time, the working condition requires that the Vgs of the soft-start MOS be kept at about 5V, that is, when the input voltage is at a low limit value, the MOS can still work reliably in the switching area to avoid overheating and burning in the linear area. Assuming Vgsth = 2.5V, the soft start time is 24ms, when the system switches from zero input state to 28V input state, the Vgs voltage relationship should be: Vgs = Vin*(e^(-t / rc)); the capacitance value can be calculated from this formula. In this example, C = 2uF, and two 1uF / 100V capacitors can be selected.

[0030] Figure 3 The circuit diagram of the surge voltage suppression unit is shown in Figure 1. When the input voltage of 28V changes to 31.5V or below, the voltage stabilizing diode D2 will not break down, and the transistor Q3 is fully turned on. When the input voltage changes from 28V to 33V and reaches 35V, the voltage stabilizing diode D2 first clamps the base voltage of the NPN transistor Q3 at 33V, and the base voltage of the transistor Q2 cannot change suddenly, and it is still 35V. At this time, the BE of the transistor Q3 is reverse biased, and the base current becomes smaller. Because the VCE of the transistor Q2 increases, the BE and CE of the transistor Q3 are both forward biased, and the transistor Q3 is turned on. The system reaches a stable state, and the output voltage is stabilized at 32.3V. The whole process is a negative feedback process, which makes the transistors Q2 and Q3 work in the amplification area. The diode D3 in the circuit clamps the reverse voltage between the BE of the transistor Q3 at about 1V, which plays a protective role. The surge voltage suppression circuit can ensure that when the input is 50V, the output is 33V after voltage reduction.

[0031] Figure 4 The interface design schematic diagram of the invention is as follows. The adjustable current and voltage suppression circuit is divided into corresponding functional component diagrams, and the planar layout method is used to convert it into a circuit layout diagram that can be implemented on a ceramic substrate, and then a thick film network adjustable current and voltage suppression thick film integrated circuit is produced according to the photographic method; Figure 2 and Figure 3The electronic components in the circuit are integrated on the ceramic substrate. For resistors, thick film resistors are made of resistor paste on the ceramic substrate. According to the different resistance values, different materials are usually used. The resistance value of the resistor is achieved by laser resistance adjustment technology. The requirements for thick film resistors are mainly high precision, small resistance temperature coefficient, and good stability. For capacitors, chip capacitors are installed on the ceramic substrate by bonding or soldering. Attention should be paid to the connection reliability during installation. For diodes, triodes, MOS tubes and other devices, their bare chips are integrated on the ceramic substrate by gold wire ball bonding. The bonding quality is mainly affected by the shape of the gold wire ball. The higher the purity of the gold wire, the better the quality of the gold wire ball. However, the excessive purity of the gold ball affects the bonding strength. The bonding strength can be improved by adding a small amount of trace elements while ensuring the high purity of the gold wire. The ceramic substrate with integrated electronic components is packaged to form an integrated circuit. The current limiting resistor can be adjusted through the reserved interface to meet different suppression requirements.

Claims

1. An adjustable current and voltage suppression thick film integrated circuit, characterized in that: It includes an impact current suppression unit and a surge voltage suppression unit, wherein the impact current suppression unit input end is connected to the input power supply, the impact current suppression unit output end is connected to the surge voltage suppression unit, the surge voltage suppression unit output end is connected to the DC / DC power supply module, and the impact current suppression unit and the surge voltage suppression unit are both arranged on a ceramic substrate.

2. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 1, characterized in that: The inrush current suppression unit includes a MOS tube Q1, a gate of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, one end of the capacitor C1 and a positive electrode of a diode D1 in sequence, a source of the MOS tube Q1 is connected to a resistor R3, a capacitor C2, the other end of the capacitor C1 and a negative electrode of the diode D1 in sequence, a positive electrode of the diode D1 is also connected to the resistor R1, and the other end of the resistor R1 is grounded; a drain of the MOS tube Q1 is connected to the surge voltage suppression unit.

3. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 2, characterized in that: A resistor R4 and a resistor R5 are connected in parallel between the source and the drain of the MOS tube Q1.

4. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 1, characterized in that: The surge voltage suppression unit includes a transistor Q2 and a transistor Q3, the base of the transistor Q2 is connected to the resistor R8, and the emitter is connected to one end of the resistor R7 and the resistor R6 in sequence; the other ends of the resistors R8 and R7 are connected in parallel to the collector of the transistor Q3, the other end of the resistor R6 is respectively connected to the cathode of the diode D2, the cathode of the diode D3, and the base of the transistor Q3, the anode of the diode D2 is grounded, the emitter of the transistor Q3 is connected to the anode of the diode D3, the emitter of the transistor Q2 is also connected to the drain of the MOS tube Q1, and the collector of the transistor Q2 and the emitter of the transistor Q3 are commonly connected to the DC / DC power supply module.

5. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 4, characterized in that: The transistor Q2 and the transistor Q3 are of NPN type and PNP type respectively.

6. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 1, characterized in that: The resistance of the resistor R4 and the resistor R5 is 100Ω.

7. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 1, characterized in that: The surge voltage suppression unit suppresses the output voltage at 33V.

8. The adjustable current and voltage suppression thick film integrated circuit as claimed in claim 1, characterized in that: The inrush current suppression unit suppresses the input inrush current within 10 times the current of the product.

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