Converter control system and synchronous control method thereof

Abstract

The synchronous control method of the converter control system is characterized by comprising the following steps: S1, creating a centralized console comprising a parallel operation board and an instruction end, connecting the instruction end with the parallel operation board through UART-based optical fiber communication, and connecting the parallel operation board with a plurality of converters through UART-based optical fiber communication; s2, performing initialization verification on the parallel operation board and the converter to obtain an execution carrier wave peak value of the parallel operation board; s3, the centralized console sends a start / stop instruction of the converter to the parallel operation board through the instruction end; s4, the parallel operation board receives the start / stop instruction to generate a synchronizing signal, and transmits the synchronizing signal to the converter; and S5, the converter generates carrier waves based on the synchronizing signal, carrier wave synchronization is realized, and synchronous starting / stopping is carried out according to the synchronizing signal. The invention aims to improve the control precision and certainty of the converter control system and improve the reliability of synchronous control of the plurality of converters in the converter control system. The invention also provides a converter control system.

Description

Technical Field

[0001] The present invention relates to a synchronous control method of a converter control system, which is used for the coordinated control of multiple converters. The present invention also relates to a converter control system. Background Art

[0002] Converter control systems are widely used in engineering fields such as wind power, ships, and vehicles. For example, the converter control system of electric vehicles or new energy vehicles includes multiple four-quadrant DC / DC converters. The coordinated and efficient operation of multiple converters can realize the bidirectional flow of electric energy and improve charging efficiency and flexibility. The converters in the converter control system have the same structure and belong to an asynchronous clock system. In practical applications, the synchronization of the start and stop times of each converter will directly affect the control performance and response speed of the entire converter control system, and thus affect the effectiveness of the control algorithm. Inside a single four-quadrant DC / DC converter, the DSP generates a modulation wave, the FPGA generates a carrier, and the carrier is compared with the modulation wave to generate a PWM pulse. Each converter is asynchronous with respect to another converter, which causes the PWM of each converter to be asynchronous with respect to each other, which will affect the rapid response and convergence of the entire system. Synchronous control measures need to be taken to improve the control accuracy and certainty of the converter control system. The existing control system for multiple converters working together is to divide multiple converters into master controllers and slave controllers. The master controller and the slave controllers are connected through communication lines, and then the master controller generates a dedicated synchronization signal and transmits it to each slave controller for periodic synchronization. The existing synchronous control measures have the following problems: 1. In actual applications, if the control architecture adopts the master-slave mode, each converter is divided into a master controller and a slave controller, and signal transmission needs to add master-slave allocation logic, which will increase system complexity and reduce reliability.

[0003] 2. It is impossible to meet the time difference requirements for start-stop synchronization and carrier synchronization of multiple converters, and it is difficult to control the start-stop synchronization time difference of multiple converters at the 100ns level.

[0004] 3. The distance between the centralized control console and the converter is different, and the communication line communication is difficult to adapt to the requirements of different distances and different transmission rates.

[0005] 4. In actual application, if the main controller works abnormally, the entire system is at risk of paralysis. Summary of the invention

[0006] The synchronous control method of the converter control system provided by the present invention meets the time difference requirements for realizing start-stop synchronization and carrier synchronization of multiple converters, improves the control accuracy and certainty of the converter control system, uses UART-based optical fiber as an interconnection line to adapt to requirements of different distances and different transmission rates, expands application scenarios, and improves the reliability of synchronous control of multiple converters in the converter control system. The present invention also provides a converter control system.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is: The synchronous control method of the converter control system is characterized by comprising the following steps: S1: Create a centralized control console including a parallel board and a command terminal, connect the command terminal to the parallel board through UART-based optical fiber communication, and connect the parallel board to multiple converters through UART-based optical fiber communication; S2: The parallel board and the converter perform initialization verification to obtain the peak value of the execution carrier of the parallel board; S3: The centralized control console sends the start / stop command of the converter to the parallel board through the command terminal; S4: The parallel board receives the start / stop command to generate a synchronization signal, and transmits the synchronization signal to the converter; S5: The converter generates a carrier based on the synchronization signal, realizes carrier synchronization, and performs synchronous start / stop according to the synchronization signal.

[0008] Preferably, the multiple converters are numbered 1#, 2#, ..., N# in sequence, the signal transmission from the parallel board to the converter is set as downlink transmission, and the signal transmission from the converter to the parallel board is set as uplink transmission; Step S2 specifically refers to: S21: power on to control the converter chip initialization; S22: Each converter sends a carrier peak value to the parallel board through uplink transmission; S23: in the parallel board, the peak value of the carrier sent by the converter with the first number and operating normally to the parallel board is set as the execution carrier value peak value, and the parallel board feeds back the set execution carrier value to each converter through downlink transmission to perform carrier peak value verification; S24: If the verification is passed, each converter uses the execution carrier peak value set by the parallel board. If the verification fails due to exceeding the time limit, the fault is reported to the centralized control console. If the verification fails within the time limit, S23 is repeated.

[0009] Preferably, when step S2 is completed, the downlink transmission is switched so that the parallel board transmits only the synchronization signal to the converter.

[0010] Preferably, the method for generating the synchronization signal in the parallel board is: When the parallel board receives the start command, it generates a synchronization signal according to the execution carrier peak value obtained in step S2. When the carrier passes through zero, the synchronization signal is high level, and when the carrier peak value is reached, the synchronization signal is pulled low; When the parallel board receives a shutdown command, it generates a synchronization signal that is always pulled low.

[0011] Preferably, the main control board inside the converter uses an FPGA plus DSP architecture, and the FPGA and DSP are connected via hard-wired GPIO signals; The specific process of the converter starting / stopping synchronously according to the instruction of the synchronization signal is as follows: the FPGA in the converter parses the data frame of the synchronization signal to restore the synchronization signal and sends it to the DSP through the hard-wired GPIO, and the DSP starts or stops according to the synchronization signal.

[0012] Preferably, "DSP starts or stops according to the synchronization signal" means that when the DSP detects the rising edge of the synchronization signal, it starts to start, executes the control logic, and generates a modulation wave. After starting, if the DSP does not detect the flip of the synchronization signal within the set time, it stops.

[0013] Preferably, the converter generates a carrier based on the synchronization signal, and the specific process of realizing carrier synchronization is: the FPGA uses a high-frequency clock to parse the data frame of the synchronization signal to recover the synchronization signal, and when the FPGA detects the rising edge of the synchronization signal, it starts to generate a carrier to realize carrier synchronization.

[0014] Preferably, a redundant parallel board is provided in the centralized control console and is connected to the parallel board, the command end and the converter respectively through UART-based optical fiber communication. The command end synchronously sends the start / stop command of the converter to the parallel board and the redundant parallel board. When the parallel board works normally, the redundant parallel board does not participate in the control and only monitors the FPGA life signal of the parallel board. When the FPGA life signal of the parallel board is detected to be abnormal, the redundant parallel board reports the fault to the centralized control console and transmits a takeover mark to the converter. After the converter recognizes the takeover mark, it uses the synchronization signal transmitted by the redundant parallel board as the control command.

[0015] A converter control system adopting the above-mentioned converter control system synchronous control method includes a centralized control console and multiple converters, and is characterized in that: the centralized control console includes a parallel board and a command end, the command end is connected to the parallel board through UART-based optical fiber communication, and the parallel board is connected to the multiple converters through UART-based optical fiber communication.

[0016] Preferably, the centralized control console further comprises a redundant parallel board, and the redundant parallel board is connected to the parallel board, the command end and the converter respectively via UART-based optical fiber communication.

[0017] The beneficial effects of the present invention are: The synchronous control method of the converter control system of the present invention is that the centralized control console sends instructions to the parallel board through the instruction end, the parallel board receives the instructions, generates corresponding synchronization signals and transmits them to the converter, uses the parallel board as a unified reference to send synchronization signals to the converter, and the converter starts / stops synchronously according to the instructions of the synchronization signal to ensure the synchronous start and stop of multiple converters. The converter generates a carrier based on the synchronization signal to achieve carrier synchronization, thereby ensuring the synchronization of the PWM pulses of each converter and achieving efficient response and convergence of the converter system.

[0018] The converters are not divided into master and slave, which simplifies the signal transmission path, reduces the number of signal transmission times, shortens the time difference between multiple converters to achieve start-stop synchronization and carrier synchronization, meets the time difference requirements for multiple converters to achieve start-stop synchronization and carrier synchronization, and improves the control accuracy and certainty of the converter control system.

[0019] The command end and the parallel board, as well as the parallel board and the converter are all connected via UART-based optical fiber communication. The UART-based optical fiber is used as the interconnection line to adapt to the requirements of different distances and different transmission rates and expand the application scenarios.

[0020] A redundant parallel board is set in the centralized control console. When the parallel board is working normally, the redundant parallel board does not participate in the control, but only monitors the FPGA life signal of the parallel board. When the FPGA life signal of the parallel board is detected to be abnormal, the redundant parallel board reports the fault to the centralized control console and transmits the takeover mark to the converter. After the converter recognizes the takeover mark, it uses the synchronization signal transmitted by the redundant parallel board as the control instruction. The redundant design is adopted, and redundant parallel boards are added to avoid the paralysis of the entire control system when the parallel board works abnormally, and improve the reliability of synchronous control of multiple converters in the converter control system. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of the converter control system of the present invention.

[0022] Figure 2 Schematic diagram of the process of initializing and checking the parallel board and the converter.

[0023] Figure 3 The figure is a schematic diagram of generating a synchronization signal based on the peak value of the execution carrier in the parallel board. DETAILED DESCRIPTION

[0024] Combine the following Figures 1 to 3 The embodiments of the present invention are described in detail.

[0025] The synchronous control method of the converter control system is characterized by comprising the following steps: S1: Create a centralized control console including a parallel board and a command terminal, connect the command terminal to the parallel board through UART-based optical fiber communication, and connect the parallel board to multiple converters through UART-based optical fiber communication; S2: The parallel board and the converter perform initialization verification to obtain the peak value of the execution carrier of the parallel board; S3: The centralized control console sends the start / stop command of the converter to the parallel board through the command terminal; S4: The parallel board receives the start / stop command to generate a synchronization signal, and transmits the synchronization signal to the converter; S5: The converter generates a carrier based on the synchronization signal, realizes carrier synchronization, and performs synchronous start / stop according to the synchronization signal.

[0026] In the above-mentioned synchronous control method of the converter control system, the centralized control console sends instructions to the parallel board through the instruction end, the parallel board receives the instructions, generates corresponding synchronization signals and transmits them to the converter, uses the parallel board as a unified reference to send synchronization signals to the converter, and the converter starts / stops synchronously according to the instructions of the synchronization signal to ensure the synchronous start and stop of multiple converters. The converter generates a carrier based on the synchronization signal to achieve carrier synchronization, thereby ensuring the synchronization of the PWM pulses of each converter and achieving efficient response and convergence of the converter system. The converter does not distinguish between master and slave, simplifies the signal transmission path, reduces the number of signal transmissions, shortens the time difference between multiple converters to achieve start and stop synchronization and carrier synchronization, meets the time difference requirements for multiple converters to achieve start and stop synchronization and carrier synchronization, and improves the control accuracy and certainty of the converter control system. The instruction end and the parallel board, and the parallel board and the converter are all connected through optical fiber communication based on UART, and optical fiber based on UART is used as an interconnection line to adapt to the requirements of different distances and different transmission rates and expand application scenarios.

[0027] The multiple converters are numbered 1#, 2#, ..., N# in sequence, the signal transmission from the parallel board to the converter is set as downlink transmission, and the signal transmission from the converter to the parallel board is set as uplink transmission; Step S2 specifically refers to: S21: power on to control the converter chip initialization; S22: Each converter sends a carrier peak value to the parallel board through uplink transmission; S23: in the parallel board, the peak value of the carrier sent by the converter with the first number and operating normally to the parallel board is set as the execution carrier value peak value, and the parallel board feeds back the set execution carrier value to each converter through downlink transmission to perform carrier peak value verification; S24: If the verification is passed, each converter uses the execution carrier peak value set by the parallel board. If the verification fails due to exceeding the time limit, the fault is reported to the centralized control console. If the verification fails within the time limit, S23 is repeated.

[0028] Set the signal transmission from the parallel board to the converter as downlink transmission, and set the signal transmission from the converter to the parallel board as uplink transmission. Downlink transmission is mainly used to transmit synchronization signals, which are used to control the synchronous start and stop of the converter. Uplink transmission is used for the converter to send the carrier peak value to the parallel board. Each converter will send carrier peak data to the parallel board. The carrier peak value sent by the first converter to the parallel board is set as the execution carrier peak value of the parallel board. When the parallel board determines that the first converter has failed, the carrier peak value sent by the second converter to the parallel board is set as the execution carrier peak value of the parallel board, and so on. The numbering order of the converters is determined when the converter and the parallel board form a fiber optic communication connection. During the initialization verification process between the parallel board and the converter, the downlink transmission will feed back the set execution carrier value to each converter for carrier peak verification. After the verification, the converters all use the execution carrier peak value set by the parallel board, so that multiple converters all use the same carrier peak value, ensuring that multiple converters generate carriers based on the synchronization signal to achieve carrier synchronization.

[0029] When step S2 is completed, the downlink transmission is switched to the parallel board transmitting only the synchronization signal to the converter. After the parallel board and the converter complete the initialization verification, the downlink transmission only transmits the synchronization signal to ensure the validity and reliability of the signal transmission.

[0030] Among them, the method of generating synchronization signals in the parallel board is: When the parallel board receives the start command, it generates a synchronization signal according to the execution carrier peak value obtained in step S2. When the carrier passes through zero, the synchronization signal is high level, and when the carrier peak value is reached, the synchronization signal is pulled low; When the parallel board receives a shutdown command, it generates a synchronization signal that is always pulled low.

[0031] When the parallel board receives the start command, it generates a synchronization signal according to the peak value of the execution carrier obtained in step S2. Taking the triangular carrier as an example, when the carrier passes through zero, the synchronization signal becomes high level, and when the carrier reaches the peak value, the synchronization signal is pulled low, such as Figure 3 As shown in the figure. When the parallel board recognizes the stop command, the synchronization signal is pulled low. The synchronization signal generated in the parallel board is sent to the converter through downstream transmission.

[0032] The main control board inside the converter uses an FPGA plus DSP architecture, and the FPGA and DSP are connected via hard-wired GPIO signals; The specific process of the converter starting / stopping synchronously according to the instruction of the synchronization signal is as follows: the FPGA in the converter parses the data frame of the synchronization signal to restore the synchronization signal and sends it to the DSP through the hard-wired GPIO, and the DSP starts or stops according to the synchronization signal.

[0033] The main control board inside the converter uses an FPGA plus DSP architecture. The FPGA is responsible for driving the UART and generating the carrier wave. The PWM pulse is generated by comparing the modulation wave with the carrier wave. The DSP is responsible for current control and sends the modulation wave to the FPGA. The PWM pulse is generated by comparing the modulation wave with the carrier wave. Inside the converter, the FPGA uses a high-frequency clock to parse the data frame containing the synchronization signal and restore the synchronization signal according to the protocol. The FPGA will send the synchronization signal to the DSP through the hard-wired GPIO, and the DSP will start or stop according to the synchronization signal.

[0034] Among them, "DSP starts or stops according to the synchronization signal" means that when the DSP detects the rising edge of the synchronization signal, it starts to start, executes the control logic, and generates the modulation wave. After starting, if the DSP does not detect the flip of the synchronization signal within the set time, it stops. Under the parallel management of the parallel board, multiple converters receive the same synchronization signal. The FPGA in each converter uses a high-frequency clock to detect the start bit of the data frame. For example, the FPGA uses a clock with a frequency of 200M to detect the start bit. Since the clocks of each converter are asynchronous, although the synchronization signal is the same, the theoretical time difference between each converter receiving the synchronization signal is one clock cycle, which is about 5ns. The FPGA and DSP use a hard-wired GPIO connection to transmit the synchronization signal. The GPIO is used to trigger the external hardware interrupt of the DSP. After the external interrupt is triggered, the DSP starts to execute the conversion control. The external hardware interrupt of the DSP has the highest priority, and the delay of the DSP detecting the synchronization signal between each converter is basically the same. Therefore, considering the error of FPGA detecting synchronization signal and the error of DSP triggering hardware interrupt, the start-stop synchronization time difference of multiple converters can be controlled at 100ns level, shortening the time difference of multiple converters to achieve start-stop synchronization and meeting the time difference requirement of multiple converters to achieve start-stop synchronization.

[0035] Among them, the converter generates a carrier based on the synchronization signal, and the specific process of realizing carrier synchronization is: FPGA uses a high-frequency clock to parse the data frame of the synchronization signal to recover the synchronization signal. When the FPGA detects the rising edge of the synchronization signal, it starts to generate a carrier to achieve carrier synchronization. Under the parallel management of the parallel board, multiple converters receive the same synchronization signal. Inside the converter, the FPGA uses a high-frequency clock to parse the data frame of the synchronization signal and recover the synchronization signal according to the protocol. For example, the frequency of the high-frequency clock used to parse the data frame of the synchronization signal in the FPGA is 200M, and the high-frequency clock with a frequency of 200M is used to detect the rising edge of the synchronization signal. Then, the theoretical time difference of the carrier synchronization between each converter is two clock cycles, that is, about 10ns, which can effectively shorten the time difference of multiple converters to achieve carrier synchronization, meet the time difference requirements of multiple converters to achieve carrier synchronization, and achieve carrier synchronization, thereby ensuring the synchronization of the PWM pulses of each converter.

[0036] Among them, a redundant parallel board is set in the centralized control console, which is connected to the parallel board, the command end and the converter through UART-based optical fiber communication. The command end sends the start / stop command of the converter to the parallel board and the redundant parallel board synchronously. When the parallel board works normally, the redundant parallel board does not participate in the control, and only monitors the FPGA life signal of the parallel board. When the FPGA life signal of the parallel board is detected to be abnormal, the redundant parallel board reports the fault to the centralized control console and transmits the takeover mark to the converter; after the converter recognizes the takeover mark, the synchronous signal transmitted by the redundant parallel board is used as the control command. The redundant design is adopted to increase the redundant parallel board to avoid the paralysis of the entire control system when the parallel board works abnormally, and improve the reliability of the synchronous control of multiple converters in the converter control system.

[0037] The present invention also protects a converter control system that adopts the synchronous control method of the converter control system described above, including a centralized control console and multiple converters, characterized in that: the centralized control console includes a parallel board and a command end, the command end is connected to the parallel board through a UART-based optical fiber communication, and the parallel board is connected to the multiple converters through a UART-based optical fiber communication.

[0038] In the above-mentioned multiple converter start-up synchronization and carrier synchronization management system, the converters are not divided into master and slave, which simplifies the signal transmission path, reduces the number of signal transmissions, shortens the time difference between multiple converters to achieve start-stop synchronization and carrier synchronization, meets the time difference requirements for multiple converters to achieve start-stop synchronization and carrier synchronization, and improves the control accuracy and certainty of the converter control system. The command end and the parallel board, the parallel board and the converter are connected through UART-based optical fiber communication, and the UART-based optical fiber is used as the interconnection line to adapt to the requirements of different distances and different transmission rates, and expand the application scenarios.

[0039] Wherein, the centralized control console also includes a redundant parallel board, and the redundant parallel board is connected to the parallel board, the command end and the converter respectively through UART-based optical fiber communication. When the parallel board is working normally, the redundant parallel board does not participate in the control, and only monitors the FPGA life signal of the parallel board. When the FPGA life signal of the parallel board is detected to be abnormal, the redundant parallel board reports the fault to the centralized control console and transmits the takeover mark to the converter; after the converter recognizes the takeover mark, the synchronization signal transmitted by the redundant parallel board is used as the control command. The redundant design is adopted to add redundant parallel boards to avoid the paralysis of the entire control system when the parallel board works abnormally, and improve the reliability of synchronous control of multiple converters in the converter control system.

[0040] The above is a complete description of the technical solutions of the embodiments of the present invention in conjunction with the accompanying drawings. It should be noted that the described embodiments are only part of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

Claims

1. A synchronous control method for a converter control system, characterized in that: The following steps are involved: S1: Create a centralized control console including a parallel board and a command terminal, connect the command terminal to the parallel board through UART-based optical fiber communication, and connect the parallel board to multiple converters through UART-based optical fiber communication; S2: The parallel board and the converter perform initialization verification to obtain the peak value of the execution carrier of the parallel board; S3: The centralized control console sends the start / stop command of the converter to the parallel board through the command terminal; S4: The parallel board receives the start / stop command to generate a synchronization signal, and transmits the synchronization signal to the converter; S5: The converter generates a carrier based on the synchronization signal, realizes carrier synchronization, and performs synchronous start / stop according to the synchronization signal.

2. The synchronous control method of a converter control system according to claim 1, characterized in that: The multiple converters are numbered 1#, 2#, ..., N# in sequence, and the signal transmission from the parallel board to the converter is set as downlink transmission, and the signal transmission from the converter to the parallel board is set as uplink transmission; Step S2 specifically refers to: S21: power on to control the converter chip initialization; S22: Each converter sends a carrier peak value to the parallel board through uplink transmission; S23: in the parallel board, the peak value of the carrier sent by the converter with the first number and operating normally to the parallel board is set as the execution carrier value peak value, and the parallel board feeds back the set execution carrier value to each converter through downlink transmission to perform carrier peak value verification; S24: If the verification is passed, each converter uses the execution carrier peak value set by the parallel board. If the verification fails due to exceeding the time limit, the fault is reported to the centralized control console. If the verification fails within the time limit, S23 is repeated.

3. The synchronous control method of the converter control system according to claim 2, characterized in that: When step S2 is completed, the downlink transmission is switched so that the parallel board transmits only the synchronization signal to the converter.

4. The synchronous control method of a converter control system according to claim 1, characterized in that: The method to generate synchronization signal in the parallel board is: When the parallel board receives the start command, it generates a synchronization signal according to the execution carrier peak value obtained in step S2. When the carrier passes through zero, the synchronization signal is high level, and when the carrier peak value is reached, the synchronization signal is pulled low; When the parallel board receives a shutdown command, it generates a synchronization signal that is always pulled low.

5. The synchronous control method of the converter control system according to claim 4, characterized in that: The main control board inside the converter uses an FPGA plus DSP architecture, and the FPGA and DSP are connected via hard-wired GPIO signals; The specific process of the converter starting / stopping synchronously according to the instruction of the synchronization signal is as follows: the FPGA in the converter parses the data frame of the synchronization signal to restore the synchronization signal and sends it to the DSP through the hard-wired GPIO, and the DSP starts or stops according to the synchronization signal.

6. The synchronous control method of a converter control system according to claim 5, characterized in that: "DSP starts or stops according to the synchronization signal" means that when the DSP detects the rising edge of the synchronization signal, it starts to start, executes the control logic, and generates the modulation wave. After starting, if the DSP does not detect the flip of the synchronization signal within the set time, it stops.

7. The synchronous control method of a converter control system according to claim 6, characterized in that: The converter generates a carrier based on the synchronization signal. The specific process of realizing carrier synchronization is: FPGA uses a high-frequency clock to parse the data frame of the synchronization signal to recover the synchronization signal. When FPGA detects the rising edge of the synchronization signal, it starts to generate a carrier to realize carrier synchronization.

8. The synchronous control method of a converter control system according to claim 1, characterized in that: A redundant parallel board is set in the centralized control console, which is connected to the parallel board, the command end and the converter through UART-based optical fiber communication respectively. The command end sends the start / stop command of the converter to the parallel board and the redundant parallel board synchronously. When the parallel board works normally, the redundant parallel board does not participate in the control, but only monitors the FPGA life signal of the parallel board. When the FPGA life signal of the parallel board is detected to be abnormal, the redundant parallel board reports the fault to the centralized control console and transmits a takeover mark to the converter; after the converter recognizes the takeover mark, it uses the synchronization signal transmitted by the redundant parallel board as the control command.

9. A converter control system using the synchronous control method of a converter control system according to any one of claims 1 to 8, comprising a centralized control console and a plurality of converters, characterized in that: The centralized control console includes a parallel board and a command end. The command end is connected to the parallel board through optical fiber communication based on UART, and the parallel board is connected to multiple converters through optical fiber communication based on UART.

10. The converter control system according to claim 9, characterized in that: The centralized control console further comprises a redundant parallel board, and the redundant parallel board is connected to the parallel board, the command end and the converter respectively through optical fiber communication based on UART.

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