Time measuring circuit and time measuring method

Abstract

The invention discloses a time measuring circuit and a time measuring method. The time measurement circuit comprises an oscillation module used for outputting an oscillation signal within the first level duration of a signal to be measured; the counting control module is used for measuring the number of complete cycles of the oscillation signal; the output signal is overturned at the first rising edge and the last rising edge of the oscillation signal; the logic module is used for outputting to-be-accurately-measured pulses when the to-be-measured signals and the output signals of the counting control module are different in height; the to-be-accurately-measured pulse comprises a first to-be-accurately-measured pulse corresponding to the ending moment of the first level of the to-be-measured signal; the delay module is used for delaying the pulse to be accurately measured into two paths of measurement signals; the state judgment module is used for judging the edge relative positions of the two paths of measurement signals; and the control module is used for determining the time of the pulse to be accurately measured according to the delay value of the control delay module. According to the invention, the time measurement precision can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of time measurement, and in particular to a time measurement circuit and a time measurement method. Background Art

[0002] As modern electronic technology places increasingly higher demands on precision, the time measurement of various signals in electronic technology becomes particularly important. For example, in digital circuits, the requirements for time measurement are becoming increasingly higher, and high-precision time measurement technology plays a very important role in the chip and semiconductor industries. Among them, time measurement refers to measuring the pulse width, rising edge time, falling edge time or duty cycle of the signal.

[0003] In the related art, a Vernier (vernier) delay line solution or a tap delay line solution can be used. For FPGA (Field Programmable Gate Array), a phase-locked loop, a cascade chain or a carry chain are often used for measurement. However, the above solutions occupy more FPGA resources and the measurement error is also large. Summary of the invention

[0004] The invention provides a time measurement circuit and a time measurement method, so as to improve the accuracy of time measurement.

[0005] According to one aspect of the present invention, there is provided a time measurement circuit, comprising:

[0006] An oscillation module, wherein an input terminal of the oscillation module inputs a signal to be tested, and the oscillation module is used to output an oscillation signal within a first level duration of the signal to be tested;

[0007] A counting control module is electrically connected to the output end of the oscillation module, and is used to measure the number of complete cycles of the oscillation signal within the first level time of the signal to be measured; and is also used to flip the output signal at the first rising edge and the last rising edge of the oscillation signal within the same cycle of the signal to be measured;

[0008] A logic module, electrically connected to the output end of the counting control module, for outputting a pulse to be precisely measured when the signal to be measured and the output signal of the counting control module are different in level; wherein the pulse to be precisely measured includes a first pulse to be precisely measured corresponding to the end time of the first level of the signal to be measured;

[0009] A delay module, the input end of which is electrically connected to the output end of the logic module, and the delay module is used to delay the pulse to be precisely measured into two measurement signals;

[0010] A state determination module, used for determining the relative positions of the edges of the two measurement signals;

[0011] The control module is electrically connected to the delay module and the state determination module, and is used to control the delay value of the delay module according to the relative positions of the edges of the two measurement signals, and determine the time of the pulse to be precisely measured according to the delay value.

[0012] Optionally, the time measurement circuit is implemented based on FPGA, and the delay module includes at least one of the following: an input-output delay device IODELAY, a dedicated delay chip, and a delay circuit constructed by a DAC and a comparator.

[0013] Optionally, the pulse to be precisely measured also includes a second pulse to be precisely measured corresponding to the starting moment of the first level of the signal to be measured; and / or, the control module is also used to determine the coarse measurement time of the first level of the signal to be measured based on the number of complete cycles of the oscillation signal measured by the counting control module.

[0014] Optionally, the delay module includes a first delay unit and a second delay unit, and the state determination module includes a first D flip-flop;

[0015] The input end of the first delay unit and the input end of the second delay unit are both electrically connected to the output end of the logic module;

[0016] The D terminal of the first D flip-flop is electrically connected to the output terminal of the first delay unit, and the clock terminal of the first D flip-flop is electrically connected to the output terminal of the second delay unit;

[0017] The control module is used to fix the delay of the first delay unit and adjust the delay of the second delay unit. When the rising edge of the measurement signal of the pulse to be precisely measured after being delayed by the second delay unit is aligned with the rising edge of the measurement signal of the pulse to be precisely measured after being delayed by the first delay unit, the first delay value of the second delay unit is recorded; when the rising edge of the measurement signal of the pulse to be precisely measured after being delayed by the second delay unit is aligned with the falling edge of the measurement signal of the pulse to be precisely measured after being delayed by the first delay unit, the second delay value of the second delay unit is recorded; and the time of the pulse to be precisely measured is determined according to the first delay value and the second delay value.

[0018] Optionally, the delay module is an input-output delay device IODELAY, the first delay unit is configured as a time mode TIME, and the second delay unit is configured as a count mode COUNT.

[0019] Optionally, the oscillation module includes a second logic function module and a third delay unit;

[0020] The first input end of the second logic function module is connected to the signal to be tested, the output end of the second logic function module serves as the output end of the oscillation module, the output end of the second logic function module is electrically connected to the input end of the third delay unit, and the output end of the third delay unit is electrically connected to the second input end of the second logic function module; the second logic function module is used to invert the input signal of its second input end and output it from its output end when the first input end thereof inputs a first level; and output the second level from its output end when the first input end thereof inputs a second level; wherein the first level and the second level are different in level.

[0021] Optionally, the oscillation module includes: a first logic function module, a first inverter, a second inverter, a third inverter, a fourth inverter, a second D flip-flop and a third D flip-flop, a fourth delay unit and a fifth delay unit;

[0022] The first input terminal of the first logic function module is connected to the signal to be tested, and the first logic function module is used to output the first level if the level polarities of the second input terminal and the third input terminal are the same when the first level is input to the first input terminal; and output the second level if the level polarities of the second input terminal and the third input terminal are different; wherein the first level and the second level are different in level; and the first logic function module is also used to output the second level when the second level is input to the first input terminal;

[0023] The output end of the first logic function module is electrically connected to the input end of the fourth delay unit and the input end of the fifth delay unit; the output end of the first logic function module serves as the output end of the oscillation module;

[0024] The output end of the fourth delay unit is electrically connected to the clock end of the second D flip-flop, the Q end of the second D flip-flop is electrically connected to the D end of the second D flip-flop through the first inverter, and the Q end of the second D flip-flop is electrically connected to the second input end of the first logic function module;

[0025] The output end of the fifth delay unit is electrically connected to the clock end of the third D flip-flop through the second inverter; the Q end of the third D flip-flop is electrically connected to the D end of the third D flip-flop through the third inverter, and the Q end of the third D flip-flop is electrically connected to the third input end of the first logic function module;

[0026] The first input terminal of the first logic function module is electrically connected to the reset terminal of the second D flip-flop and the reset terminal of the third D flip-flop through the fourth inverter.

[0027] According to another aspect of the present invention, there is provided a time measurement method, which is performed by the time measurement circuit as described above, and the time measurement method comprises:

[0028] In the rough measurement stage, the number of complete cycles of the oscillation signal within the first level time of the signal to be measured is measured;

[0029] In the pulse generation stage to be precisely measured, the counting control module is controlled to flip the output signal of the counting control module at the first and last rising edges of the oscillation signal within the same cycle of the signal to be measured; the logic module is controlled to output the pulse to be precisely measured when the signal to be measured and the output signal of the counting control module are different in level; wherein the pulse generation stage to be precisely measured includes a first pulse generation stage to be precisely measured, and the generated pulse to be precisely measured includes a first pulse to be precisely measured with the same starting time as the time of the last rising edge of the oscillation signal;

[0030] In the precise measurement stage, according to the relative position of the edge of the measurement signal determined by the state determination module, the delay value of the delay module is controlled, and the time of the pulse to be precisely measured is determined according to the delay value;

[0031] In the calculation stage, the coarse measurement time of the first level of the signal to be measured is determined according to the number of complete cycles of the oscillation signal, and the time of the first level of the signal to be measured is determined according to the coarse measurement time and the time of the pulse to be precisely measured.

[0032] Optionally, the pulse to be precisely measured generation stage further includes a second pulse to be precisely measured generation stage, and the generated pulse to be precisely measured includes a second pulse to be precisely measured having a start time that is the same as the time when the signal to be measured jumps to the first level;

[0033] Determining the time of the first level of the signal to be measured according to the coarse measurement time and the time of the pulse to be precisely measured comprises:

[0034] The sum of the time of the second pulse to be precisely measured, the time of the first pulse to be precisely measured, and the coarse measurement time is used as the time of the first level of the signal to be measured.

[0035] Optionally, the delay module includes a first delay unit and a second delay unit, and the state determination module includes a first D flip-flop;

[0036] In the precise measurement stage, according to the relative position of the edge of the measurement signal determined by the state determination module, the delay value of the delay module is controlled, and according to the delay value, the time of the pulse to be precisely measured is determined, including:

[0037] Control the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to be aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit, and record the first delay value of the second delay unit;

[0038] Adjust the delay value of the second delay unit, and record the second delay value of the second delay unit when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the falling edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit;

[0039] The time of the pulse to be precisely measured is determined according to the first delay value and the second delay value.

[0040] Optionally, controlling the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to be aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit comprises:

[0041] Configuring a delay value of the first delay unit so that the delay value of the first delay unit is greater than the delay value of the second delay unit;

[0042] Fixing the delay value of the first delay unit;

[0043] Increase the delay value of the second delay unit, and when the output of the first D trigger jumps, confirm that the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit is aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit.

[0044] Optionally, the time measurement method further includes:

[0045] The first delay unit is configured as a time mode TIME, and the second delay unit is configured as a count mode COUNT, wherein the delay module includes an input-output delay device IODELAY;

[0046] Determining the time of the pulse to be precisely measured according to the first delay value and the second delay value comprises:

[0047] Obtaining the resolution of the first delay unit and the second delay unit by using the self-correction function of the first delay unit;

[0048] The time of the pulse to be precisely measured is obtained by multiplying the difference between the second delay value and the first delay value by the resolution of the second delay unit.

[0049] The technical solution of the embodiment of the present invention adopts a time measurement circuit to achieve accurate time measurement. The oscillation signal generated by the oscillation module has a strong correlation with the signal to be measured. Compared with the use of an oscillation module that is not related to the signal to be measured, the delay between the jump of the signal to be measured to a high level and the first rising edge of the oscillation signal in this embodiment can be measured in advance, which can greatly save the time required for measuring the signal to be measured. In addition, when the application adopts an FPGA-based time measurement circuit, the delay module adopts an input and output delay device, and more specifically, an input delay device can be used. Compared with the phase-locked loop, cascade chain and carry chain used in the prior art to achieve the solution, the influence of nonlinear error on measurement accuracy is reduced, and the uneven distribution of delay of the delay chain and the influence of temperature and voltage changes on the measurement results are avoided. The time measurement circuit of the present application occupies fewer FPGA resources, and the time measurement circuit of this embodiment can also improve the utilization rate of FPGA internal resources.

[0050] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0052] Figure 1 A schematic diagram of the circuit structure of a time measurement circuit provided by an embodiment of the present invention;

[0053] Figure 2 A measurement principle diagram of a time measurement circuit provided by an embodiment of the present invention;

[0054] Figure 3 This is the principle diagram of time measurement of the pulse to be precisely measured;

[0055] Figure 4 A schematic diagram of the circuit structure of another time measurement circuit provided by an embodiment of the present invention;

[0056] Figure 5 for Figure 4 Timing diagram of the oscillator module;

[0057] Figure 6 A flow chart of a time measurement method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0059] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0060] Figure 1 A schematic diagram of a circuit structure of a time measurement circuit provided by an embodiment of the present invention, referring to Figure 1The time measurement circuit includes: an oscillation module 11, a counting control module 12, a logic module 13, a delay module 14, a state determination module 15 and a control module 70. An input end of the oscillation module 11 inputs the test signal TMU_DIN, and the oscillation module 11 is used to output the oscillation signal CLK within the first level duration of the test signal TMU_DIN; the counting control module 12 is electrically connected to the output end of the oscillation module 11, and is used to measure the number of complete cycles of the oscillation signal CLK within the first level time of the test signal TMU_DIN; the counting control module 12 is also used to flip the output signal at the first rising edge and the last rising edge of the oscillation signal CLK within the same cycle of the test signal TMU_DIN; the logic module 13 is electrically connected to the output end of the counting control module 12, and is used to The signal TMU_DIN and the output signal of the counting control module 11 are different in high and low, and the pulse to be precisely measured is outputted at the same time, wherein the pulse to be precisely measured includes a first pulse to be precisely measured corresponding to the end time of the first level of the signal to be measured; the input end of the delay module 14 is electrically connected to the output end of the logic module 13, and the delay module 14 is used to delay the pulse to be precisely measured into two measurement signals; the state determination module 15 is used to determine the relative position of the edges of the two measurement signals; the control module 70 is electrically connected to the delay module 14 and the state determination module 15, and is used to control the delay value of the delay module according to the relative position of the edges of the two measurement signals, and determine the time of the pulse to be precisely measured according to the delay value.

[0061] Specifically, Figure 2 The measurement principle diagram of the time measurement circuit provided by the embodiment of the present invention is shown in FIG. Figure 1 and Figure 2 . The signal to be tested TMU_DIN is a signal whose time needs to be measured. The signal to be tested TMU_DIN is a periodic signal, and each period has a first level and a second level. The first level and the second level are different in level. For example, the first level is a high level and the second level is a low level; of course, the first level can also be a low level and the second level is a high level. In this embodiment, the first level is a high level and the second level is a low level as an example. The measurement of the time of the signal to be tested TMU_DIN is also the measurement of the duration of the first level in the signal to be tested TMU_DIN.

[0062] The oscillation module 11 is used to generate an oscillation signal CLK according to the signal to be measured TMU_DIN. The oscillation module 11 starts to generate the oscillation signal CLK when the signal to be measured TMU_DIN jumps to the first level. When the signal to be measured TMU_DIN jumps to the second level, the output of the oscillation module 11 also remains at the second level. In other words, the oscillation module 11 will only generate an oscillation signal (or understand it as generating a periodic signal) during the high level duration of the signal to be measured TMU_DIN. After the signal to be measured TMU_DIN becomes a low level, the oscillation module 11 keeps outputting a low level. The oscillation signal CLK generated by the oscillation module 11 has a strong correlation with the signal to be measured TMU_DIN. The delay from the time when the test signal TMU_DIN jumps to a high level to the first rising edge of the oscillation signal CLK (defined as the second pulse T1 to be measured in this embodiment) is the inherent delay of the oscillation module 11, and the delay is a fixed value each time the test signal is measured. Compared with using an oscillation module that is not related to the test signal (that is, the oscillation signal generated by the oscillation module is irrelevant to the test signal), the delay from the time when the test signal TMU_DIN jumps to a high level to the first rising edge of the oscillation signal CLK in this embodiment can be measured in advance, which can greatly save the time required for measuring the test signal.

[0063] The counting control module 12 may include registers and controllers inside the FPGA. The counting control module 12 mainly has two functions. The first function is to measure the number of complete cycles of the oscillation signal CLK in each cycle of the signal to be tested TMU_DIN. The number of complete cycles can be measured, for example, the number of rising edges of the oscillation signal CLK in each cycle of the signal to be tested TMU_DIN. The number of rising edges minus one is the number of cycles of the complete oscillation signal contained in the signal to be tested TMU_DIN. For example, Figure 2As shown, during the high level time of the signal to be measured TMU_DIN, there are 6 rising edges of the oscillation signal CLK, and the first 5 rising edges correspond to a complete cycle, while the high level time corresponding to the last rising edge may not be the same as the high level time corresponding to the previous rising edge, that is to say, the time from the last rising edge to the falling edge of the signal to be measured TMU_DIN may be less than the cycle of the oscillation signal CLK. Therefore, if the number of rising edges multiplied by the cycle of the oscillation signal CLK is directly used as the time of the first level of the signal to be measured, there will be a large error. In this embodiment, the counting control module 12 measures the number of rising edges of the signal to be measured TMU_DIN, and subsequently the number can be subtracted by one and then multiplied by the cycle of the oscillation signal CLK, and the time is used as the rough measurement time of the signal to be measured. It should be noted that the above process of calculating the rough measurement time can be performed by the counting control module or by the control module. The second function of the counting control module 12 is to flip the output signal at the first rising edge and the last rising edge of the oscillation signal in the same cycle of the signal to be measured; in other words, the counting control module 12 generates a pulse signal whose starting time is aligned with the first rising edge of the oscillation signal CLK and whose ending time is aligned with the last rising edge of the oscillation signal CLK in each cycle of the signal to be measured, and the pulse signal is defined as the intermediate pulse DQ. The intermediate pulse DQ is also the output signal of the counting control module 12.

[0064] From the above analysis, it can be known that the duration of the intermediate pulse DQ is the same as the rough measurement time of the first level of the signal to be measured CLK. The first level of the signal to be measured CLK also includes the second pulse to be precisely measured T1 and the first pulse to be precisely measured T2. Among them, the time corresponding to the first pulse to be precisely measured T2 is also the time from the last rising edge of the oscillation signal CLK to the falling edge of the signal to be measured TMU_DIN. One input end of the logic module 13 is connected to the signal to be measured TMU_DIN, and the other input end is connected to the intermediate pulse DQ. Through the action of the logic module 13, the second pulse to be precisely measured T1 and the first pulse to be precisely measured T2 are generated. Among them, the counting control module 12 can control the enable end of the logic module 13 to control the output of the logic module 13; for example, the counting control module 12 does not enable the logic module 13 after the first rising edge of the oscillation signal CLK, then the output of the logic module 13 only includes the second pulse to be precisely measured T1; and the counting control module 12 does not enable the logic module before the first rising edge of the oscillation signal CLK arrives, then the output of the logic module 13 only includes the first pulse to be precisely measured T2.

[0065] After the first pulse T2 to be precisely measured is generated, the time of the first pulse T2 to be precisely measured can be calculated by using the delay module 14, the state determination module 15 and the control module 70. Among them, when the rising edge of the input second measurement signal is aligned with the rising edge of the first measurement signal, the state determination module 15 becomes a metastable state, and its output will flip, for example, the output flips to a high level; and when the rising edge of the input second measurement signal is aligned with the falling edge of the first measurement signal, the state determination module will also enter a metastable state, and its output will also flip, for example, the output flips to a low level. The time measurement of the first pulse T2 to be precisely measured specifically includes: firstly aligning the rising edge of the second measurement signal with the rising edge of the first measurement signal according to the output of the state determination module 15; then adjusting the delay value of the delay module so that the second measurement signal moves backward, when the rising edge of the second measurement signal is aligned with the falling edge of the first measurement signal, it means that the time of the delay value adjustment is the same as the time of the first pulse T2 to be precisely measured. Therefore, the time of the first pulse T2 to be precisely measured can be determined by the delay value of the delay module. Finally, the control module adds the first pulse to be precisely measured T2 , the second pulse to be precisely measured T1 , and the coarse measurement time to obtain the time of the first level of the signal to be measured TMU_DIN.

[0066] Of course, it should be noted that in some cases where the accuracy requirement is relatively low, the second pulse to be precisely measured T1 may not be considered.

[0067] Each module in the circuit provided in this application can be constructed in digital, analog, mixed or other forms. For the delay module, it can include at least one of the following: an input-output delay device IODELAY, a dedicated delay chip, and a delay circuit constructed by a DAC and a comparator.

[0068] As a preferred manner, the present application is a time measurement circuit based on FPGA, the delay module may include an input-output delay device IODELAY, the oscillation module includes a logic function module, and the logic function module may include a lookup table.

[0069] In addition, in the present embodiment, the delay module 14 uses an input-output delay device IODELAY, and more specifically, an input delay device IDELAY. Compared with the use of a lookup table, such as a logic function module, to realize delay, the input delay device IDELAY has higher precision; and the delay module 14 uses a smaller number of input delay devices (such as two) to meet the total delay length reaching the period of the oscillation signal, while the use of a lookup table requires occupying more resources of the FPGA. Therefore, the time measurement circuit occupies fewer FPGA resources, and because the input delay device IDELAY is a hard-core resource of the FPGA, it can only be idle if not used and cannot be used for other purposes. Therefore, the time measurement circuit of the present embodiment can also improve the utilization rate of the internal resources of the FPGA. Compared with the prior art, the FPGA is mostly measured by a phase-locked loop, a cascade chain or a carry chain,

[0070] The technical solution of this embodiment adopts a time measurement circuit, which can realize accurate time measurement. The oscillation signal generated by the oscillation module has a strong correlation with the signal to be measured. Compared with using an oscillation module that is not related to the signal to be measured, the delay between the jump of the signal to be measured to the high level and the first rising edge of the oscillation signal in this embodiment can be measured in advance, which can greatly save the time required for measuring the signal to be measured. In addition, the delay module adopts an input and output delay device, and more specifically, an input delay device can be used. The time measurement circuit occupies fewer FPGA resources, and the time measurement circuit of this embodiment can also improve the utilization rate of FPGA internal resources.

[0071] It should be noted that the time measurement circuits in this embodiment are all composed of modules inside the FPGA, which has the advantages of simple circuit structure and less occupation of FPGA resources.

[0072] Optionally, in some embodiments, the pulse to be precisely measured further includes a second pulse to be precisely measured corresponding to the start time of the first level of the signal to be measured. The time of the second pulse to be precisely measured can be pre-determined and stored in the time measurement circuit. The time measurement method of the second pulse to be precisely measured is the same as the time measurement method of the first pulse to be precisely measured.

[0073] Optionally, the control module determines the coarse measurement time of the first level of the signal to be measured TMU_DIN according to the number of complete cycles of the oscillation signal measured by the counting control module.

[0074] Specifically, a register is provided in the counting control module 12 to store the number of rising edges of the oscillation signal. And an output end of the counting control module 12 is electrically connected to the control module to send the number of rising edges or the rough measurement time to the control module. In this embodiment, taking the control module calculating the rough measurement time as an example, the counting control module 12 sends the number of complete cycles to the control module. Or the number of rising edges is sent to the control module, and the control module subtracts one from the number of rising edges and then multiplies it by the period of the oscillation signal CLK to obtain the rough measurement time. It should be noted that the period of the oscillation signal CLK is a known quantity. When the structure of the oscillation module 11 is fixed, its period is a fixed value and remains unchanged during the measurement process.

[0075] Optionally, continue to refer to Figure 1 The delay module 14 includes a first delay unit 141 and a second delay unit 142, and the state determination module 15 includes a first D trigger 151; the input end of the first delay unit 141 and the input end of the second delay unit 142 are both electrically connected to the output end of the logic module 13; the D end of the first D trigger 151 is electrically connected to the output end of the first delay unit 141, and the clock end CLK of the first D trigger is electrically connected to the output end of the second delay unit 142; the control module is used to fix the delay of the first delay unit 141 and adjust the second delay unit 142. The delay of unit 142 is to record the first delay value of the second delay unit 142 when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit 142 is aligned with the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit 141; the second delay value of the second delay unit is to be recorded when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the falling edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit; the time of the pulse to be precisely measured is determined according to the first delay value and the second delay value.

[0076] Specifically, Figure 3 This is the time measurement principle diagram of the pulse to be precisely measured, combined with Figure 1 and Figure 3 The time of the first pulse T2 to be precisely measured or the second pulse T1 to be precisely measured can be measured within multiple cycles of the signal TMU_DIN to be measured. In this embodiment, the time of the first pulse T2 to be precisely measured is measured as an example. The specific measurement method is as follows: First, the control module outputs the measurement signal (the first measurement signal, Figure 3 The measurement signal (the second measurement signal, Figure 3Specifically, the two rising edges of the first D flip-flop 151 (indicated by the timing CLK) are aligned. Specifically, the Q-end output state of the first D flip-flop 151 is obtained, and the delay of the second delay unit 142 is continuously adjusted. When the Q-end output of the first D flip-flop 151 is flipped for the first time, such as when it is flipped to a high level, it indicates that the first D flip-flop 151 is in a metastable state, and the rising edges of the first measurement signal and the second measurement signal are aligned. At this time, the delay value of the second delay unit 142 is recorded as TAP1. That is, Figure 3 In the first cycle A1 of the signal to be measured, the rising edges of the first measurement signal and the second measurement signal are aligned. Among them, t0 represents the delay time of the first delay unit 141, and t1 represents the delay time of the second delay unit 142. Then continue to adjust the delay value of the second delay unit 142, such as continuously increasing the delay value of the second delay unit 142 in the second cycle A2 and the third cycle A3 of the signal to be measured, so that the delay time t1 corresponding to the delay value of the second delay unit 142 gradually increases. In the third cycle A3, the Q end of the first D trigger 151 flips, such as flipping to a low level, thereby indicating that the first D trigger 151 enters a metastable state, that is, the rising edge of the second measurement signal is aligned with the falling edge of the first measurement signal, and the delay value of the second delay unit 142 at this time is recorded as TAP2. Then, TAP2-TAP1 is the delay value corresponding to the first pulse T2 to be precisely measured. The time of the first pulse T2 to be precisely measured is obtained by multiplying the delay value by the resolution corresponding to the delay value (ie, the time of the first delay value).

[0077] Optionally, in the above embodiment, controlling the rising edge of the pulse to be precisely measured output by the first delay unit to be aligned with the rising edge of the pulse to be precisely measured output by the second delay unit comprises:

[0078] Configuring a delay value of the first delay unit so that the delay value of the first delay unit is greater than the delay value of the second delay unit;

[0079] Specifically, the delay value of the first delay unit 141 can be configured as a larger initial value to ensure that the delay value of the first delay unit is greater than the delay value of the second delay unit in the initial state. When the delay value of the second delay unit is subsequently adjusted, it only needs to be adjusted in the direction of increasing the delay value. Exemplarily, the first delay unit and the second delay unit each include two input delay devices IDELAY, and the delay of the first delay unit can be set to 200ps, and the delay of one input delay device IDELAY can be 0ps, and the delay of the other input delay device IDELAY can be 200ps.

[0080] Fix the delay value of the first delay unit and increase the delay value of the second delay unit. When the output of the first D trigger jumps, confirm that the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit is aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit.

[0081] Optionally, the first delay unit is configured as a time TIME mode. With this configuration, on the one hand, the first delay unit can be used to calculate the resolution of the delay value TAP in the first delay unit and the second delay unit. The resolution of the delay value can be calculated as follows: first, the two input delay devices IDELAY in the first delay unit 141 are controlled to work in the TIME mode. Of course, the IDELAYCTRL module can also be instantiated, which will automatically perform correction to ensure that the delay values ​​of the two IDELAY modules are stable and reliable. One input delay device IDELAY is configured with a delay of 0ps, and the other input delay device is configured with a delay of 200ps. The corresponding input and output delay devices IODELAY output TAP0 and TAP200 respectively, wherein TAP0 is the insertion delay of the input delay device IDELAY itself, and no matter how much the configuration delay value is, there is a fixed insertion delay; TAP200 is the TAP value corresponding to the insertion delay + 200ps, so the difference between the two delay values ​​is the delay value corresponding to 200ps, and the resolution of the input delay device is 200ps / (TAP200-TAP0). When the temperature or voltage changes, TAP0 and TAP200 will also change in real time, so the resolution of the input delay device can be obtained in real time in this embodiment, reducing the influence of environmental factors and having higher measurement accuracy. On the other hand, the first delay unit 141 is configured to work in TIME mode, and the output of the first delay unit 141 can also be fixed, so that the measurement signal output by the second delay unit 142 can be aligned with the edge of the measurement signal output by the first delay unit 141.

[0082] Optionally, the second delay unit is configured to work in a counting COUNT mode, so that the delay value of the second delay unit can be dynamically configured.

[0083] Exemplarily, the specific working process of the time measurement circuit in this embodiment may include a coarse measurement phase, a pulse generation phase to be measured accurately, a fine measurement phase and a calculation phase. The coarse measurement phase and the pulse generation phase to be measured accurately both include at least one cycle of the signal to be measured. The fine measurement phase includes at least two cycles of the signal to be measured.

[0084] In the rough measurement stage, the number of rising edges of the oscillation signal within the first level time of the signal to be measured is measured. More specifically, the rough measurement stage may include at least two cycles of the signal to be measured. If the number of rising edges of the oscillation signal in each cycle is equal, it indicates that the measurement result is reliable. At this time, the counting control module can store the number of rising edges of the oscillation signal corresponding to one cycle of the signal to be measured. The number of rising edges of the oscillation signal minus one is the number of complete cycles of the oscillation signal corresponding to one cycle of the signal to be measured.

[0085] In the stage of generating pulses to be measured accurately, the counting control module is controlled to flip the output signal of the counting control module at the first and last rising edges of the oscillation signal within the same cycle of the signal to be measured; the control logic module outputs the pulses to be measured accurately when the signal to be measured and the output signal of the counting control module are of different levels; wherein the stage of generating pulses to be measured accurately includes a first stage of generating pulses to be measured accurately, and the generated pulses to be measured accurately include a first pulse to be measured accurately whose starting moment is the same as the moment of the last rising edge of the oscillation signal.

[0086] Specifically, after the rough measurement stage, a relatively stable pulse to be measured accurately can be generated. In this embodiment, the first pulse to be measured accurately can be generated as described above. The specific generation method thereof is referred to above and will not be described here. In addition, the logic module 13 can use a lookup table, and the specific function is a logical XOR function, that is, the signals at its two input ends are XORed and then outputted from its output end.

[0087] In the precise measurement stage, the delay value of the delay module is controlled according to the relative position of the edge of the measurement signal determined by the state determination module, and the time of the pulse to be precisely measured is determined according to the delay value;

[0088] Specifically, the precision measurement stage includes at least two cycles of the signal to be measured. First, the rising edge of the second measurement signal needs to be aligned with the rising edge of the first measurement signal. The specific alignment method is as described above and will not be repeated here. Subsequently, the delay value of the delay module is increased in units of the cycle of the signal to be measured, so that the rising edge of the second measurement signal is moved back to align with the falling edge of the first measurement signal. The delay value corresponding to the pulse to be precisely measured can be determined by the delay value during the two alignments. The time of the pulse to be precisely measured can be obtained by multiplying the delay value by the resolution of the delay unit. Of course, it can be understood that the time of the first pulse to be precisely measured and the second pulse to be precisely measured can be measured using the above method.

[0089] In the calculation stage, the rough measurement time of the first level of the signal to be measured is determined according to the number of complete cycles of the oscillation signal, and the time of the first level of the signal to be measured is determined according to the rough measurement time and the time of the pulse to be precisely measured.

[0090] Specifically, the number of complete cycles of the oscillation signal multiplied by the cycle of the oscillation signal is the rough measurement time, and the rough measurement time plus the time of the first pulse to be precisely measured is the time of the first level of the signal to be measured. The above calculation process can be executed by the control module.

[0091] Optionally, in some embodiments, the pulse generation stage for precise measurement further includes a second pulse generation stage for precise measurement, and the pulse generated in the second pulse generation stage for precise measurement includes a second pulse for precise measurement whose starting time is the same as the time when the signal to be measured changes to the first level. The second pulse generation stage for precise measurement can be executed before the rough measurement stage, and a precise measurement stage is set before the rough measurement stage and after the second pulse generation stage for precise measurement to control the delay value of the delay module according to the relative position of the edge of the measurement signal determined by the state determination module, and determine the time of the second pulse for precise measurement according to the delay value, and the specific measurement method is the same as the measurement method of the first pulse for precise measurement. Finally, determining the time of the first level of the signal to be measured according to the rough measurement time and the time of the pulse for precise measurement includes: taking the sum of the time of the second pulse for precise measurement, the time of the first pulse for precise measurement and the rough measurement time as the time of the first level of the signal to be measured.

[0092] Optionally, continue to refer to Figure 1 , the oscillation module 11 includes a second logic function module 111 and a third delay unit 112; the first end of the second logic function module 111 is connected to the signal to be tested TMU_DIN, the output end of the second logic function module 111 is used as the output end of the oscillation module 11, the output end of the second logic function module 111 is electrically connected to the input end of the third delay unit 112, and the output end of the third delay unit 112 is electrically connected to the second input end of the second logic function module 111; the second logic function module 111 is used to invert the input signal of its second input end and output it from its output end when the first level is input to its first input end; when the second level is input to its first input end, the second level is output from its output end; wherein, the first level and the second level are different in height. The above-mentioned second logic function module may specifically include a second lookup table.

[0093] Specifically, in the initial state, the first input end of the second logic function module 111 is at the second level (i.e., low level), so its output end, that is, the oscillation signal CLK is at a low level, and the delay signal output by the third delay unit 112 is also at a low level. When the signal to be measured TMU_DIN jumps to a high level, after the inherent delay of the second logic function module 111, the oscillation signal CLK jumps to a high level, and after the delay of the third delay unit 112, the high level signal makes the second input end of the second logic function module 111 a high level. Subsequently, after the inherent delay of the second logic function module 111, the oscillation signal CLK jumps to a low level, and oscillates in a cycle, so that the oscillation signal CLK has a certain period. Among them, by adjusting the delay value of the third delay unit 112, the period of the oscillation signal CLK can be adjusted. In this embodiment, the structure of the oscillation module is relatively simple, and the resources of the FPGA occupied are less.

[0094] Alternatively, in some other embodiments, Figure 4 A schematic diagram of a circuit structure of another time measurement circuit provided by an embodiment of the present invention, Figure 5 for Figure 4 For the timing diagram of the oscillator module, refer to Figure 4 and Figure 5The oscillation module 11 includes: a first logic function module 113, a first inverter 114, a second inverter 115, a third inverter 116, a fourth inverter 117, a first D flip-flop DQ1 and a second D flip-flop DQ2, a fourth delay unit 118 and a fifth delay unit 119; the first input terminal of the first logic function module 113 inputs the test signal TMU_DIN. The first logic function module is used to output a second level when a first level is input to the first input terminal, if the level polarity of the second input terminal and the third input terminal is the same; wherein the first level and the second level are different in level; the first logic function module 113 is also used to output the second level when the second level is input to the first input terminal; the output terminal of the first logic function module 113 is electrically connected to the input terminal of the fourth delay unit 118 and the input terminal of the fifth delay unit 119; the output terminal of the first logic function module 113 serves as the output terminal of the oscillation module; the output terminal of the fourth delay unit 118 is electrically connected to the clock terminal CLK of the first D flip-flop DQ1, and the Q terminal of the first D flip-flop DQ1 is connected to the clock terminal CLK of the first D flip-flop DQ1 through the first inverter 11 4 is electrically connected to the D terminal of the first D flip-flop DQ1, and the Q terminal of the first D flip-flop DQ1 is electrically connected to the second input terminal of the first logic function module 113; the output terminal of the fifth delay unit 119 is electrically connected to the clock terminal CLK of the second D flip-flop DQ2 through the second inverter 115, the Q terminal of the second flip-flop DQ2 is electrically connected to the D terminal of the second D flip-flop DQ2 through the third inverter 116, and the Q terminal of the second D flip-flop DQ2 is electrically connected to the third input terminal of the first logic function module 113; the first input terminal of the first logic function module 113 is electrically connected to the reset terminal CLR of the first D flip-flop DQ1 and the reset terminal CLR of the second D flip-flop DQ2 through the fourth inverter 117. Optionally, the first logic function module 113 can be a first lookup table.

[0095] Specifically, the output of the fourth delay unit 118 is the first delayed output signal D1, the output of the fifth delay unit 119 is the second delayed output signal D2, the output of the first D flip-flop DQ1 is the first trigger output signal DQ11, and the output of the second D flip-flop DQ2 is the second trigger output signal DQ21. Figure 5 The oscillation principle of the oscillation module 11 in this embodiment is: in the initial state, the test signal TMU_DIN, the oscillation signal CLK, the first delayed output signal D1, the second delayed output signal D2, the first trigger output signal DQ11 and the second trigger output signal DQ21 are all low level.

[0096] When the signal to be tested TMU_DIN jumps to a high level, after the inherent delay of the first logic function module 113 , the oscillation signal CLK output by the first logic function module 113 jumps to a high level. Wherein, B0 is the inherent delay of the first logic function module 113 .

[0097] After the oscillation signal CLK is delayed by the fourth delay unit 118, the first delayed output signal D1 is at a high level. After the oscillation signal CLK is delayed by the fifth delay unit 119, the second delayed output signal D2 is at a high level. Wherein, B1 is the delay of the fourth delay unit 118.

[0098] Since the output of the first D flip-flop DQ1 is low level in the initial state, the D terminal is high level after passing through the first inverter 114. When the first delayed output signal D1 jumps to high level, the clock terminal CLK of the first D flip-flop DQ1 forms a rising edge. Therefore, after the inherent delay time B2 of the first D flip-flop DQ1 (the inherent delay time B0+B1+B2 is also the time of the second pulse T1 to be precisely measured), the first trigger output signal DQ11 of the first D flip-flop DQ1 jumps to high level. In this stage, since the second delayed output signal D2 is input to the clock terminal of the second D flip-flop DQ2 after passing through the second inverter 115, the clock terminal of the second D flip-flop DQ2 inputs a low level, and the output of the second D flip-flop DQ2 remains low level.

[0099] At this time, the first trigger output signal DQ11 is at a high level, and the second trigger output signal DQ21 is at a low level. Since the signal to be tested TMU_DIN is at a high level, after the total delay B3 of the wiring delay between the output of the first D flip-flop DQ1 and the input of the first logic function module 113 and the inherent delay of the first logic function module 113, the oscillation signal CLK jumps to a low level. Then, after the delay time B4 of the fifth delay unit 119, the second delay output signal D2 jumps to a low level, and then, after the delay time B5 of the second D flip-flop DQ2, the second trigger output signal DQ21 flips to a high level. At this time, the first trigger output signal DQ11 is at a high level, the second trigger output signal DQ21 is at a high level, and the signal to be tested TMU_DIN is at a high level. Therefore, after the total delay B6 of the wiring delay between the output of the second D flip-flop DQ2 and the input of the first logic function module 113 and the inherent delay of the first logic function module 113, the oscillation signal CLK jumps to a high level. Thus, a complete cycle of the oscillation signal CLK is completed, and the subsequent generation principle of the oscillation signal CLK is the same as described above, which will not be repeated here. Among them, B1 can also be understood as the delay of the primitive module of the fourth delay unit, and B4 can also be understood as the delay of the primitive module of the fifth delay unit.

[0100] It should be noted that one cycle of the oscillation signal CLK B = B1 + B2 + B3 + B4 + B5 + B6, where B2, B3, B5, and B6 are all delays of the FPGA internal devices themselves or routing delays. After the FPGA compilation is completed, these delay values ​​are fixed. Only B1 and B4 can be dynamically configured. By dynamically configuring the values ​​of B1 and B4, the cycle of the oscillation signal CLK can be changed and the cycle of the oscillation signal CLK can be adjusted.

[0101] In addition, the third delay unit, the fourth delay unit and the fifth delay unit may all use an input-output delay device IODELAY, preferably an input delay device IDELAY, and optionally an output delay device ODELAY.

[0102] The present invention also provides a time measurement method, which is performed by the time measurement circuit provided by any embodiment of the present invention. Figure 6 As shown, Figure 6 A flow chart of a time measurement method provided by an embodiment of the present invention, the time measurement method comprising:

[0103] Step S101, in the rough measurement stage, the number of complete cycles of the oscillation signal within the first level time of the signal to be measured is measured. More specifically, the rough measurement stage may include at least two cycles of the signal to be measured. If the number of rising edges of the oscillation signal in each cycle is equal, it indicates that the measurement result is reliable. At this time, the counting control module can store the number of rising edges of the oscillation signal corresponding to one cycle of the signal to be measured. The number of rising edges of the oscillation signal minus one is the number of complete cycles of the oscillation signal corresponding to one cycle of the signal to be measured.

[0104] Step S102, in the stage of generating pulses to be measured accurately, controlling the counting control module to flip the output signal of the counting control module at the first and last rising edges of the oscillation signal within the same cycle of the signal to be measured; controlling the logic module to output the pulses to be measured accurately when the signal to be measured and the output signal of the counting control module are at different levels; wherein the stage of generating pulses to be measured accurately includes a first stage of generating pulses to be measured accurately, and the generated pulses to be measured accurately include a first pulse to be measured accurately whose starting moment is the same as the moment of the last rising edge of the oscillation signal.

[0105] Specifically, after the rough measurement stage, a relatively stable first pulse to be measured accurately can be generated. In this embodiment, the first pulse to be measured accurately can be generated. The specific generation method is referred to above and will not be repeated here. In addition, the logic module 13 can use a lookup table, and the specific function is a logical XOR function, that is, the signals at its two input ends are XORed and then outputted from its output end.

[0106] Step S103, in the precise measurement stage, according to the relative position of the edge of the measurement signal determined by the state determination module, the delay value of the delay module is controlled, and the time of the pulse to be precisely measured is determined according to the delay value;

[0107] Specifically, the precision measurement stage includes at least two cycles of the signal to be measured. First, the rising edge of the second measurement signal needs to be aligned with the rising edge of the first measurement signal. The specific alignment method is as above and will not be repeated here. Subsequently, the delay value of the delay module is increased in units of the cycle of the signal to be measured, so that the rising edge of the second measurement signal is moved back to align with the falling edge of the first measurement signal. The delay value corresponding to the first pulse to be precisely measured can be determined by the delay value during the two alignments. The time of the first pulse to be precisely measured can be obtained by multiplying the delay value by the resolution of the delay unit. Of course, it can be understood that the time of both the first pulse to be precisely measured and the second pulse to be precisely measured can be measured using the above method.

[0108] Step S104, in the calculation stage, the coarse measurement time of the first level of the signal to be measured is determined according to the number of complete cycles of the oscillation signal, and the time of the first level of the signal to be measured is determined according to the coarse measurement time and the time of the pulse to be precisely measured.

[0109] Specifically, the number of complete cycles is obtained by subtracting one from the number of rising edges of the oscillation signal, and then multiplying it by the cycle of the oscillation signal to obtain the rough measurement time. The rough measurement time plus the time of the first pulse to be precisely measured is the time of the first level of the signal to be measured. The above calculation process can be performed by the control module.

[0110] The time measurement method adopted in this embodiment can greatly save the time required for measuring the signal to be measured. In addition, by adopting a time measurement circuit based on FPGA, the delay module adopts an input and output delay device, and more specifically, an input delay device can be adopted. The time measurement circuit occupies fewer FPGA resources, and the time measurement circuit of this embodiment can also improve the utilization rate of the internal resources of the FPGA.

[0111] Optionally, the stage of generating a pulse to be precisely measured also includes a stage of generating a second pulse to be precisely measured, and the generated pulse to be precisely measured includes a second pulse to be precisely measured whose starting time is the same as the time when the signal to be measured jumps to the first level; determining the time of the first level of the signal to be measured according to the coarse measurement time and the time of the pulse to be precisely measured includes: taking the sum of the time of the second pulse to be precisely measured, the time of the first pulse to be precisely measured and the coarse measurement time as the time of the first level of the signal to be measured.

[0112] Optionally, the delay module includes a first delay unit and a second delay unit, and the state determination module includes a first D flip-flop;

[0113] In the precise measurement stage, according to the relative position of the edge of the measurement signal determined by the state determination module, the delay value of the delay module is controlled, and the time of the pulse to be precisely measured is determined according to the delay value, including:

[0114] Control the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to be aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit, and record the first delay value of the second delay unit;

[0115] Adjust the delay value of the second delay unit, and record the second delay value of the second delay unit when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the falling edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit;

[0116] The time of the first pulse to be precisely measured is determined according to the first delay value and the second delay value.

[0117] Specifically, the specific measurement method of the first pulse to be precisely measured can refer to the description of the present invention. Figure 3 The description of part will not be repeated here.

[0118] Optionally, controlling the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to align with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit, including: configuring the delay value of the first delay unit so that the delay value of the first delay unit is greater than the delay value of the second delay unit; fixing the delay value of the first delay unit; increasing the delay value of the second delay unit, and confirming that the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit when the output of the first D-type flip-flop jumps, is aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit. The delay value of the first delay unit 141 can be set to a larger initial value to ensure that the delay value of the first delay unit is greater than the delay value of the second delay unit in the initial state. When the delay value of the second delay unit is subsequently adjusted, it only needs to be adjusted in the direction of increasing the delay value. Exemplarily, the first delay unit and the second delay unit each include two input delay devices IDELAY, and the delay of the first delay unit can be set to 200 ps, ​​that is, the delay of one input delay device IDELAY can be 0 ps, ​​and the delay of the other input delay device IDELAY can be 200 ps.

[0119] The delay value of the second delay unit is increased, and when the output of the first D flip-flop jumps, it is confirmed that the rising edge of the measurement signal output by the second delay unit is aligned with the rising edge of the measurement signal output by the first delay unit.

[0120] Optionally, the time measurement method further includes: configuring the first delay unit to be in the time mode TIME, configuring the second delay unit to be in the count mode COUNT; determining the time of the pulse to be precisely measured according to the first delay value and the second delay value includes: obtaining the resolution of the first delay unit and the second delay unit by using the self-correction function of the first delay unit; multiplying the difference between the second delay value and the first delay value by the resolution of the second delay unit to obtain the time of the pulse to be precisely measured. The specific resolution calculation method of the delay unit can refer to the description of the time measurement circuit part of the present invention, which will not be repeated here.

[0121] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0122] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A time measurement circuit, characterized in that: include: An oscillation module, wherein an input terminal of the oscillation module inputs a signal to be tested, and the oscillation module is used to output an oscillation signal within a first level duration of the signal to be tested; A counting control module is electrically connected to the output end of the oscillation module, and is used to measure the number of complete cycles of the oscillation signal within the first level time of the signal to be measured; and is also used to flip the output signal at the first rising edge and the last rising edge of the oscillation signal within the same cycle of the signal to be measured; A logic module, electrically connected to the output end of the counting control module, for outputting a pulse to be precisely measured when the signal to be measured and the output signal of the counting control module are different in level; wherein the pulse to be precisely measured includes a first pulse to be precisely measured corresponding to the end time of the first level of the signal to be measured; A delay module, the input end of which is electrically connected to the output end of the logic module, and the delay module is used to delay the pulse to be precisely measured into two measurement signals; A state determination module, used for determining the relative positions of the edges of the two measurement signals; The control module is electrically connected to the delay module and the state determination module, and is used to control the delay value of the delay module according to the relative positions of the edges of the two measurement signals, and determine the time of the pulse to be precisely measured according to the delay value.

2. The time measurement circuit according to claim 1, characterized in that: The time measurement circuit is implemented based on FPGA, and the delay module includes at least one of the following: an input-output delay device IODELAY, a dedicated delay chip, and a delay circuit constructed by a DAC and a comparator.

3. The time measurement circuit according to claim 1 or 2, characterized in that: The pulse to be precisely measured further includes a second pulse to be precisely measured corresponding to the starting time of the first level of the signal to be measured; and / or, The control module is further configured to determine a coarse measurement time of a first level of the signal to be measured according to the number of complete cycles of the oscillation signal measured by the counting control module.

4. The time measurement circuit according to claim 2, characterized in that: The delay module includes a first delay unit and a second delay unit, and the state determination module includes a first D flip-flop; The input end of the first delay unit and the input end of the second delay unit are both electrically connected to the output end of the logic module; The D terminal of the first D flip-flop is electrically connected to the output terminal of the first delay unit, and the clock terminal of the first D flip-flop is electrically connected to the output terminal of the second delay unit; The control module is used to fix the delay of the first delay unit and adjust the delay of the second delay unit, and record the first delay value of the second delay unit when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit; When the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the falling edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit, the second delay value of the second delay unit is recorded; and the time of the pulse to be precisely measured is determined according to the first delay value and the second delay value.

5. The time measurement circuit according to claim 4, characterized in that: The delay module is an input-output delay device IODELAY, the first delay unit is configured as a time mode TIME, and the second delay unit is configured as a count mode COUNT.

6. The time measurement circuit according to claim 1, characterized in that: The oscillation module includes a second logic function module and a third delay unit; The first input end of the second logic function module is connected to the signal to be tested, the output end of the second logic function module serves as the output end of the oscillation module, the output end of the second logic function module is electrically connected to the input end of the third delay unit, and the output end of the third delay unit is electrically connected to the second input end of the second logic function module; the second logic function module is used to invert the input signal of its second input end and output it from its output end when the first input end thereof inputs a first level; and output the second level from its output end when the first input end thereof inputs a second level; wherein the first level and the second level are different in level.

7. The time measurement circuit according to claim 1, characterized in that: The oscillation module includes: a first logic function module, a first inverter, a second inverter, a third inverter, a fourth inverter, a second D flip-flop and a third D flip-flop, a fourth delay unit and a fifth delay unit; The first input terminal of the first logic function module is connected to the signal to be tested, and the first logic function module is used to output the first level if the level polarities of the second input terminal and the third input terminal are the same when the first level is input to the first input terminal; and output the second level if the level polarities of the second input terminal and the third input terminal are different; wherein the first level and the second level are different in level; and the first logic function module is also used to output the second level when the second level is input to the first input terminal; The output end of the first logic function module is electrically connected to the input end of the fourth delay unit and the input end of the fifth delay unit; the output end of the first logic function module serves as the output end of the oscillation module; The output end of the fourth delay unit is electrically connected to the clock end of the second D flip-flop, the Q end of the second D flip-flop is electrically connected to the D end of the second D flip-flop through the first inverter, and the Q end of the second D flip-flop is electrically connected to the second input end of the first logic function module; The output end of the fifth delay unit is electrically connected to the clock end of the third D flip-flop through the second inverter; the Q end of the third D flip-flop is electrically connected to the D end of the third D flip-flop through the third inverter, and the Q end of the third D flip-flop is electrically connected to the third input end of the first logic function module; The first input terminal of the first logic function module is electrically connected to the reset terminal of the second D flip-flop and the reset terminal of the third D flip-flop through the fourth inverter.

8. A time measurement method, executed by the time measurement circuit according to any one of claims 1 to 7, characterized in that: The time measurement method comprises: In the rough measurement stage, the number of complete cycles of the oscillation signal within the first level time of the signal to be measured is measured; In the pulse generation stage to be precisely measured, the counting control module is controlled to flip the output signal of the counting control module at the first and last rising edges of the oscillation signal within the same cycle of the signal to be measured; the logic module is controlled to output the pulse to be precisely measured when the signal to be measured and the output signal of the counting control module are different in level; wherein the pulse generation stage to be precisely measured includes a first pulse generation stage to be precisely measured, and the generated pulse to be precisely measured includes a first pulse to be precisely measured with the same starting time as the time of the last rising edge of the oscillation signal; In the precise measurement stage, the delay value of the delay module is controlled according to the relative position of the edge of the measurement signal determined by the state determination module, and the time of the pulse to be precisely measured is determined according to the delay value; In the calculation stage, the coarse measurement time of the first level of the signal to be measured is determined according to the number of complete cycles of the oscillation signal, and the time of the first level of the signal to be measured is determined according to the coarse measurement time and the time of the pulse to be precisely measured.

9. The time measurement method according to claim 8, characterized in that: The pulse generation stage for precise measurement further includes a second pulse generation stage for precise measurement, wherein the generated pulse for precise measurement includes a second pulse for precise measurement having the same starting time as the time when the signal for precise measurement jumps to the first level; Determining the time of the first level of the signal to be measured according to the coarse measurement time and the time of the pulse to be precisely measured comprises: The sum of the time of the second pulse to be precisely measured, the time of the first pulse to be precisely measured, and the coarse measurement time is used as the time of the first level of the signal to be measured.

10. The time measurement method according to claim 8 or 9, characterized in that: The delay module includes a first delay unit and a second delay unit, and the state determination module includes a first D flip-flop; In the precise measurement stage, according to the relative position of the edge of the measurement signal determined by the state determination module, the delay value of the delay module is controlled, and according to the delay value, the time of the pulse to be precisely measured is determined, including: Control the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to be aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit, and record the first delay value of the second delay unit; Adjust the delay value of the second delay unit, and record the second delay value of the second delay unit when the rising edge of the measurement signal after the pulse to be precisely measured is delayed by the second delay unit is aligned with the falling edge of the measurement signal after the pulse to be precisely measured is delayed by the first delay unit; The time of the pulse to be precisely measured is determined according to the first delay value and the second delay value.

11. The time measurement method according to claim 10, characterized in that: The step of controlling the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit to be aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit, comprises: Configuring a delay value of the first delay unit so that the delay value of the first delay unit is greater than the delay value of the second delay unit; Fixing the delay value of the first delay unit; Increase the delay value of the second delay unit, and when the output of the first D trigger jumps, confirm that the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the second delay unit is aligned with the rising edge of the measurement signal output after the pulse to be precisely measured is delayed by the first delay unit.

12. The time measurement method according to claim 10, characterized in that: The time measurement method further comprises: The first delay unit is configured as a time mode TIME, and the second delay unit is configured as a count mode COUNT, wherein the delay module includes an input-output delay device IODELAY; Determining the time of the pulse to be precisely measured according to the first delay value and the second delay value comprises: Obtaining the resolution of the first delay unit and the second delay unit by using the self-correction function of the first delay unit; The time of the pulse to be precisely measured is obtained by multiplying the difference between the second delay value and the first delay value by the resolution of the second delay unit.

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